Processing method and device for cyclic code, electronic equipment and storage medium

Abstract

The present disclosure provides a processing method for loop code, relates to the technical field of artificial intelligence, and particularly relates to the chip technical field and the storage technical field. A specific implementation scheme is as follows: in response to determining that a total data amount of a plurality of variables of a loop code block is greater than an available storage space capacity of a local storage unit, storing a plurality of target variables in the plurality of variables to a global storage unit, wherein the loop code block comprises a plurality of code segments; in response to determining that a first code segment in the plurality of code segments is executed, a first target variable of the first code segment in the plurality of target variables is stored in the global storage unit, and there is an idle first cache space in the local storage unit, storing the first target variable of the first code segment to the idle first cache space, so as to execute the first code segment based on the first target variable in the first cache space in the execution process of the loop code block. The present disclosure also provides an apparatus for loop code, an electronic device and a storage medium.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence technology, and more particularly to the fields of chip technology and storage technology. More specifically, this disclosure provides a method, apparatus, electronic device, and storage medium for processing loop code. Background Technology

[0002] With the development of artificial intelligence technology, the application of AI chips is constantly increasing. AI chips can include local memory units. The core of an AI chip can quickly access data in these local memory units. Summary of the Invention

[0003] This disclosure provides a method, apparatus, device, and storage medium for processing loop code.

[0004] According to one aspect of this disclosure, a method for processing loop code is provided, the method comprising: in response to determining that the total data volume of multiple variables of a loop code block is greater than the available storage space capacity of a local storage unit, storing multiple target variables among the multiple variables into a global storage unit, wherein the loop code block includes multiple code segments, and the local storage unit includes at least one first cache space; in response to determining that a first code segment among the multiple code segments is executed, a first target variable of the first code segment among the multiple target variables is stored in the global storage unit, and determining that there is a free first cache space in the local storage unit, storing the first target variable of the first code segment into the free first cache space, so as to execute the first code segment based on the first target variable in the first cache space during the execution of the loop code block.

[0005] According to another aspect of this disclosure, a processing apparatus for loop code is provided, the apparatus comprising: a first storage module, configured to, in response to determining that the total data volume of a plurality of variables of a loop code block is greater than the available storage space capacity of a local storage unit, store a plurality of target variables among the plurality of variables into a global storage unit, wherein the loop code block includes a plurality of code segments, and the local storage unit includes at least one first cache space; and a first execution module, configured to, in response to determining that a first code segment among the plurality of code segments is executed, that the first target variable of the first code segment among the plurality of target variables is stored in the global storage unit, and that there is a free first cache space in the local storage unit, store the first target variable of the first code segment into the free first cache space, so as to execute the first code segment based on the first target variable in the first cache space during the execution of the loop code block.

[0006] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method provided according to this disclosure.

[0007] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing a computer to perform the methods provided according to this disclosure.

[0008] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method provided according to this disclosure.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0010] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0011] Figure 1 This is a flowchart of a method for processing loop code according to an embodiment of the present disclosure;

[0012] Figures 2A to 2D This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present disclosure;

[0013] Figure 3 This is a block diagram of a processing apparatus for loop code according to an embodiment of the present disclosure; and

[0014] Figure 4 This is a block diagram of an electronic device to which a processing method for loop code can be applied, according to an embodiment of the present disclosure. Detailed Implementation

[0015] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0016] Local memory units have a smaller capacity than global memory. The program executed by an AI chip can be called a kernel function. Local variables within kernel functions occupy a significant amount of storage space in local memory units. If the storage space occupied by multiple local variables exceeds the available storage capacity of the local memory unit, a local memory overflow problem occurs. Overflowing data can be stored in global memory units. However, the processing unit of an AI chip cannot directly access global memory units. The processing unit of an AI chip can be the aforementioned kernel. If overflowing data needs to be used, it can be stored in local memory units outside of the available storage space. During code loops, each iteration can use a value from an array. If this data is overflowing, multiple memory accesses will occur between global and local memory units to use the array data, resulting in high memory access latency and consequently low memory access efficiency.

[0017] Therefore, in order to significantly improve memory access efficiency, this disclosure provides a method for processing loop code, which will be described below.

[0018] Figure 1 This is a flowchart of a method for processing loop code according to an embodiment of the present disclosure.

[0019] like Figure 1 As shown, the method 100 may include operations S110 to S120.

[0020] In operation S110, in response to the determination that the total amount of data of multiple variables in the loop code block is greater than the available storage space capacity of the local storage unit, multiple target variables among the multiple variables are stored in the global storage unit.

[0021] In embodiments of this disclosure, the multiple variables may include complex variables and simple variables. The multiple simple variables may include at least one of the following types: integer variables, floating-point variables, etc. Complex variables are, for example, array variables or structure variables.

[0022] In embodiments of this disclosure, the kernel function described above may include one or more loop blocks. A loop block may include multiple code segments. For example, during each iteration of the loop, one or more of the multiple code segments may use a target variable.

[0023] In embodiments of this disclosure, the target variable may include one or more data. The target variable may be a complex variable.

[0024] In this embodiment, the capacity of the available storage space may be less than the capacity of the local storage unit. If the total data volume of multiple target variables in a loop block exceeds the capacity of the available storage space, all target variables cannot be stored in the local storage unit. Therefore, all target variables can be stored in the global storage unit.

[0025] In this embodiment of the disclosure, the local storage unit includes at least one first cache space. For example, one or more storage spaces in the local storage unit can be used as one or more first cache spaces.

[0026] In operation S120, in response to determining that the first code segment among multiple code segments is executed, the first target variable of the first code segment among multiple variables is stored in the global storage unit, and determining that there is a free first cache space in the local storage unit, the first target variable of the first code segment is stored in the free first cache space so that the first code segment is executed based on the first target variable in the first cache space during the execution of the loop code block.

[0027] In this embodiment of the disclosure, the first code segment can be determined from a plurality of code segments. For example, one or more first code segments can be determined based on the number of first cache spaces. The number of first cache spaces can be the same as the number of first code segments.

[0028] In this embodiment of the disclosure, after the first target variable of the first code segment is stored in the first cache space and before the loop code block finishes execution, the first target variable of the first code segment can be continuously stored in the first cache space. After the loop code block finishes execution, the target variable of the first code segment or the processed target variable can be written to the global storage unit.

[0029] In this embodiment, complex variables are stored in the global storage unit before the loop block is executed. During the execution of the loop block, the target variable of the first code segment of the loop block is always stored in the local storage unit, reducing the memory access overhead of the target variable of the first code segment. This memory access overhead may be the overhead of moving the target variable of the first code segment between the local storage unit and the global storage unit. This can effectively reduce memory access latency and improve memory access efficiency.

[0030] As can be understood, the method of this disclosure has been described above, and the following will be combined with... Figures 2A to 2D The method disclosed herein will be further explained.

[0031] Figures 2A to 2D This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present disclosure.

[0032] like Figures 2A to 2DAs shown, chip 200 may include a local storage unit lm20 and multiple processing units. The multiple processing units may include processing unit PU201, processing unit PU202, and processing unit PU203. Local storage unit lm20 may include first cache space lm211, first cache space lm212, and first cache space lm213. Local storage unit lm20 may also include a second cache space lm221.

[0033] As shown in Figure 2, chip 200 can read data from global storage unit gm20 and write data to global storage unit gm20.

[0034] In some embodiments of operation S110 described above, in response to determining that the total data volume of multiple variables in the loop code block is greater than the available storage space capacity of the local storage unit, multiple target variables among the multiple variables are stored in the global storage unit. As shown in FIG2, the total capacity of the first cache space lm211, the first cache space lm212, and the first cache space lm213 can be used as the available storage space capacity. If the total data volume of multiple variables in the loop code block is greater than the available storage space capacity, the risk of overflow in the local storage unit is relatively high, so multiple target variables can be stored in the global storage unit first.

[0035] In some embodiments, the multiple target variables include at least one of the following types of variables: array variables and structure variables. For example, taking array variables as an example, the multiple target variables may include array variables array21, array variables array22, array variables array23, array variables array24, and array variables array25. It is understood that the target variables may also be structure variables, or the multiple target variables may include at least one array variable and at least one structure variable.

[0036] In some embodiments, storing multiple target variables into a global storage unit may include storing the multiple target variables into multiple contiguous storage spaces within the global storage unit. For example... Figure 2AAs shown, the global storage unit gm20 may include multiple contiguous storage spaces. These contiguous storage spaces may include storage spaces gm201, gm202, gm203, gm204, and gm205. Array variable array21 can be stored in storage space gm201. Array variable array22 can be stored in storage space gm202. Array variable array23 can be stored in storage space gm203. Array variable array24 can be stored in storage space gm204. Array variable array25 can be stored in storage space gm205. Through this embodiment, storing multiple target variables in multiple contiguous storage spaces allows for rapid location of the required data based on offset values, thus improving memory access efficiency.

[0037] In some embodiments of operation S120 described above, in response to determining that a first code segment among a plurality of code segments is executed, that the target variable of the first code segment is stored in a global storage unit, and that a free first cache space exists in a local storage unit, the first target variable of the first code segment is stored in the free first cache space.

[0038] For example, during the first iteration of a loop block, the first three code segments of the loop block can be considered as three first code segments. When executing the first code segment, its first target variable can be the array variable array21. The array variable array21 is stored in the global storage unit. The local storage unit lm20 includes three free first cache spaces. For example... Figure 2B As shown, the array variable array21 can be loaded from storage space gm201 to the first cache space lm211.

[0039] In some embodiments, executing a first code segment based on a first target variable in a first cache space during the execution of a loop code block may include: retrieving at least one piece of data of the target variable of the first code segment from the first cache space. For example, the processing unit PU201 may retrieve one or more pieces of data of the array variable array21 from the first cache space lm211 to perform calculations and obtain an intermediate result of the first code segment. Through the embodiments of this disclosure, during the execution of the loop code, the first target variable is stored in the first cache space of the local storage unit, which can efficiently retrieve data from the local storage unit and improve memory access efficiency. Compared with local storage units that are not set in the first cache space, the memory access overhead required for repeatedly loading the first target variable in different loop iterations is saved, which can significantly improve the execution efficiency of the loop code. For artificial intelligence chips that do not have a first-level cache (L1 cache) or a second-level cache (L2 cache), memory access overhead can be reduced more efficiently.

[0040] In some embodiments, executing the first code segment based on the first target variable in the first cache space during the execution of the loop code block may further include: replacing at least one data of the first target variable of the first code segment in the first cache space with at least one intermediate result of the loop code block. For example, an intermediate result of the first code segment can be used to replace a data in the array variable array21. Through the embodiments of this disclosure, during the execution of the loop code, the first target variable is stored in the first cache space of the local storage unit, which can efficiently write data to the array variable and effectively improve memory access efficiency. Compared with local storage units that are not set in the first cache space, the memory access overhead required for repeatedly loading the first target variable in different loop iterations is saved, which can significantly improve the execution efficiency of the loop code. For artificial intelligence chips that do not have a first-level cache (L1 cache) or a second-level cache (L2 cache), memory access overhead can be reduced more efficiently.

[0041] For example, when executing the second code snippet, the target variable of this second code snippet can be the array variable array22. The array variable array22 is stored in the global storage unit. The local storage unit lm20 includes two free first cache spaces. The array variable array22 can be loaded from storage space gm202 into the first cache space lm212. Then, the data of the array variable array22 can be retrieved from the first cache space lm212. When executing the third code snippet, the target variable of this third code snippet can be the array variable array23. The array variable array23 is stored in the global storage unit. The local storage unit lm20 includes one free first cache space. The array variable array23 can be loaded from storage space gm203 into the first cache space lm213. Then, the data of the array variable array23 can be retrieved from the first cache space lm213.

[0042] In some embodiments, in response to determining that a second code segment among a plurality of code segments is executed, that the target variable of the second code segment is stored in a global storage unit, and that there is no free first cache space in a local storage unit, the second code segment is executed based on the second target variable in the global storage unit during the execution of the loop code block.

[0043] For example, during the first iteration of a loop block, the fourth and fifth code segments of the loop block can be used as two second code segments. When executing the fourth code segment, its target variable can be the array variable array24. The array variable array24 is stored in the global storage unit. All three first cache spaces in the local storage unit lm20 are occupied. The array variable array24 can be loaded from storage space gm204 into the second cache space lm221.

[0044] In some embodiments, executing a second code segment based on a second target variable in a global storage unit during the execution of a loop code block includes: retrieving at least one piece of data of the second target variable of the second code segment from a second cache space. For example, when executing the fourth code segment, data of the array variable array24 can be retrieved from the second cache space lm221 for calculation to obtain an intermediate result of the fourth code segment. Through embodiments of this disclosure, a second cache space is set up to cache the second target variable, avoiding the second target variable from occupying the first cache space. This allows the first target variable to be continuously stored in the local storage space during the execution of the loop code block, effectively saving memory access overhead and improving overall memory access efficiency.

[0045] In some embodiments, executing a second code segment based on a second target variable in a global storage unit during the execution of a loop code block includes: replacing at least one piece of data of the second target variable of the second code segment in the global storage unit with at least one intermediate result of the loop code block. For example, the intermediate result can be used to replace the data in the array variable array24 to obtain the array variable array24_1.

[0046] In some embodiments, executing a second code segment based on a second target variable in a global storage unit during the execution of a loop code block includes: in response to determining that the second code segment is being executed and determining that at least one second cache space is occupied, releasing at least one occupied second cache space to obtain the released second cache space. For example... Figure 2C As shown, during the first iteration of the loop block, when the fifth code segment is executed, the target variable of this fifth code segment can be the array variable array25. The array variable array25 is stored in the global storage unit. All three first cache spaces in the local storage unit lm20 are occupied. The second cache space lm221 is also occupied. The array variable array24_1 can be loaded from the second cache space lm221 to the storage space gm204 to release the second cache space lm221. As mentioned above, compared to the array variable array24, one piece of data in the array variable array24_1 is replaced with the intermediate result of the fourth code segment. After loading the array variable array24 after the first replacement into the storage space gm204, the data in the second target variable of the second code segment in the global storage unit can be replaced.

[0047] In some embodiments, executing a second code segment based on a second target variable in a global storage unit during the execution of a loop code block includes: loading the target variable of the second code segment from the global storage unit into a released second cache space, so as to obtain at least one piece of data of the target variable of the second code segment from the released second cache space. For example... Figure 2D As shown, after releasing the second cache space lm221, the array variable array25 can be loaded from the storage space gm205 into the second cache space lm221. Next, when executing the fifth code snippet, at least one piece of data for the array variable array25 can be retrieved from the second cache space lm221.

[0048] For example, after the first iteration of the loop block is completed, the second iteration can be executed. During the second iteration, when executing the first code snippet, the array variable data can be retrieved from the first cache space lm211. When executing the second code snippet, the array variable data can be retrieved from the first cache space lm212. When executing the third code snippet, the array variable data can be retrieved from the first cache space lm212.

[0049] For example, during the second iteration of the loop and while executing the fourth code snippet, the array variable `array25` can be moved from the second cache space `lm221` to the storage space `gm205` to free up the second cache space `lm221`. Next, the array variable `array24_1` can be loaded from the storage space `gm204` into the second cache space `lm221`. During the second iteration of the loop and while executing the fourth code snippet, the data of the array variable `array24_1` can be retrieved from the second cache space `lm221` for calculation, obtaining another intermediate result for the fourth code snippet. This intermediate result can then be used to replace the data in the array variable `array24_1`, resulting in an array variable after two replacements.

[0050] Next, the way the fifth code snippet of the second loop is executed is the same as or similar to the way the fifth code snippet of the first loop is executed, and will not be repeated here.

[0051] It is understood that the way the third loop is executed to the last loop is the same as or similar to the way the second loop is executed, and this disclosure will not repeat it here.

[0052] In some embodiments, the method may further include: in response to determining that the loop code block has completed execution, writing the processed target variable of the first code segment into a global storage unit. For example, after the loop termination condition is met, the three array variables in the first cache space lm211, the first cache space lm212, and the first cache space lm213 can be written as processed array variables into storage spaces gm201, gm202, and gm203, respectively. The loop termination condition can be: the number of loop iterations equals a preset threshold number. Through the embodiments of this disclosure, during the execution of the loop code block, the first target variable can be stored in a local storage unit. After the loop code block has completed execution, the first target variable is then written into the global storage unit. This can effectively reduce memory access overhead and improve memory access efficiency.

[0053] It is understood that the method of this disclosure has been described above, and the apparatus of this disclosure will be described below.

[0054] Figure 3This is a block diagram of a processing apparatus for loop code according to an embodiment of the present disclosure.

[0055] like Figure 3 As shown, the device 300 may include a first processing module 310 and a first execution module 320.

[0056] The first storage module 310 is configured to store multiple target variables from the multiple variables into the global storage unit in response to determining that the total data volume of the multiple variables in the loop code block is greater than the available storage space capacity of the local storage unit. The loop code block includes multiple code segments, and the local storage unit includes at least one first cache space.

[0057] The first execution module 320 is configured to, in response to determining that a first code segment among a plurality of code segments is executed, that the first target variable of the first code segment among a plurality of target variables is stored in a global storage unit, and that there is a free first cache space in a local storage unit, store the first target variable of the first code segment in the free first cache space, so as to execute the first code segment based on the first target variable in the first cache space during the execution of the loop code block.

[0058] In some embodiments, the apparatus 300 further includes: a second execution module, configured to execute the second code segment based on the second target variable in the global storage unit during the execution of the loop code block in response to determining that a second code segment among a plurality of code segments is executed, that the second target variable of the second code segment among a plurality of target variables is stored in a global storage unit, and determining that there is no free first cache space in the local storage unit.

[0059] In some embodiments, the first processing module includes: a first processing submodule, configured to store multiple target variables into multiple consecutive storage spaces of a global storage unit.

[0060] In some embodiments, the multiple target variables include at least one of the following types of variables: array variables and structure variables.

[0061] In some embodiments, the first execution module includes at least one of the following operations: an acquisition submodule, configured to acquire at least one data of a first target variable of a first code segment from a first cache space; and a first replacement submodule, configured to replace at least one data of the first target variable of the first code segment in the first cache space using at least one intermediate result of a loop block.

[0062] In some embodiments, the apparatus 300 further includes a writing module for writing the processed target variable of the first code segment into a global storage unit in response to determining that the loop code block has completed execution.

[0063] In some embodiments, the local storage unit further includes at least one second cache space. The second execution module includes: a release submodule, configured to release at least one occupied second cache space in response to determining that the second code segment has been executed and that at least one second cache space is occupied, thereby obtaining the released second cache space; and a loading submodule, configured to load the target variable of the second code segment from the global storage unit into the released second cache space, so as to obtain at least one piece of data of the second target variable of the second code segment from the released second cache space.

[0064] In some embodiments, the second execution module includes a second replacement submodule, configured to replace at least one data of the second target variable of the second code segment in the global storage unit with at least one intermediate result of the loop code block.

[0065] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0066] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0067] Figure 4 A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0068] like Figure 4 As shown, device 400 includes a computing unit 401, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 402 or a computer program loaded from storage unit 408 into random access memory (RAM) 403. The RAM 403 may also store various programs and data required for the operation of device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via bus 404. An input / output (I / O) interface 405 is also connected to bus 404.

[0069] Multiple components in device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of monitors, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0070] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as the processing methods for loop code. For example, in some embodiments, the processing methods for loop code can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by the computing unit 401, one or more steps of the processing methods for loop code described above can be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform processing methods for loop code by any other suitable means (e.g., by means of firmware).

[0071] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard parts (ASSPs), systems-on-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0072] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0073] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory (EPROM) or flash memory, optical fiber, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0074] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a cathode ray tube (CRT) monitor or a liquid crystal display (LCD)); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0075] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0076] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0077] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for processing loop code, comprising: In response to determining that the total data volume of multiple variables in a loop code block is greater than the available storage space capacity of a local storage unit, multiple target variables among the multiple variables are stored in a global storage unit, wherein the loop code block includes multiple code segments, and the local storage unit includes at least one first cache space; In response to determining that a first code segment among a plurality of code segments is executed, that the first target variable of the first code segment among a plurality of target variables is stored in the global storage unit, and determining that there is a free first cache space in the local storage unit, the first target variable of the first code segment is stored in the free first cache space, so that the first code segment is executed based on the first target variable in the first cache space during the execution of the loop code block; In response to determining that the loop code block has completed execution, the processed target variable of the first code segment is written to the global storage unit. The execution of the first code segment based on the first target variable in the first cache space during the execution of the loop code block includes: From the first cache space, obtain at least one piece of data for the first target variable of the first code segment; At least one data point of the first target variable in the first code segment in the first cache space is replaced using at least one intermediate result of the loop code block.

2. The method according to claim 1, further comprising: In response to determining that a second code segment among a plurality of code segments is executed, that a second target variable of the second code segment among a plurality of target variables is stored in the global storage unit, and determining that there is no free first cache space in the local storage unit, the second code segment is executed based on the second target variable in the global storage unit during the execution of the loop code block.

3. The method according to claim 1, wherein, The step of storing the multiple target variables into the global storage unit includes: The target variables are stored in multiple consecutive storage spaces of the global storage unit.

4. The method according to claim 1, wherein, The target variables include at least one of the following types: array variables and structure variables.

5. The method according to claim 2, wherein, The local storage unit also includes at least one second cache space. The execution of the second code segment based on the second target variable in the global storage unit during the execution of the loop code block includes: In response to determining that the second code segment has been executed and determining that at least one of the second cache spaces is occupied, at least one occupied second cache space is released to obtain the released second cache space; The target variable of the second code segment is loaded from the global storage unit into the released second cache space to obtain at least one piece of data of the second target variable of the second code segment from the released second cache space.

6. The method according to claim 2, wherein, The execution of the second code segment based on the second target variable in the global storage unit during the execution of the loop code block includes: At least one data point of the second target variable in the second code segment in the global storage unit is replaced using at least one intermediate result of the loop code block.

7. A processing apparatus for loop code, comprising: A first storage module is configured to, in response to determining that the total data volume of multiple variables in a loop code block is greater than the available storage space capacity of a local storage unit, store multiple target variables among the multiple variables into a global storage unit, wherein the loop code block includes multiple code segments, and the local storage unit includes at least one first cache space; A first execution module is configured to, in response to determining that a first code segment among a plurality of code segments is executed, that the first target variable of the first code segment among a plurality of target variables is stored in the global storage unit, and determining that there is a free first cache space in the local storage unit, store the first target variable of the first code segment in the free first cache space, so as to execute the first code segment based on the first target variable in the first cache space during the execution of the loop code block; The write module is configured to, in response to determining that the loop code block has completed execution, write the processed target variable of the first code segment into the global storage unit. The first execution module includes: The acquisition submodule is used to acquire at least one piece of data of the first target variable of the first code segment from the first cache space; The first replacement submodule is used to replace at least one data of the first target variable of the first code segment in the first cache space with at least one intermediate result of the loop code block.

8. The apparatus according to claim 7, further comprising: The second execution module is configured to execute the second code segment based on the second target variable in the global storage unit during the execution of the loop code block in response to determining that the second code segment among the plurality of code segments is executed, the second target variable of the second code segment among the plurality of target variables is stored in the global storage unit, and determining that there is no free first cache space in the local storage unit.

9. The apparatus according to claim 7, wherein, The first storage module includes: The first processing submodule is used to store multiple target variables into multiple consecutive storage spaces of the global storage unit.

10. The apparatus according to claim 7, wherein, The target variables include at least one of the following types: array variables and structure variables.

11. The apparatus according to claim 8, wherein, The local storage unit also includes at least one second cache space. The second execution module includes: The release submodule is configured to release at least one occupied second cache space in response to determining that the second code segment has been executed and that at least one second cache space is occupied, thereby obtaining the released second cache space; A loading submodule is used to load the target variable of the second code segment from the global storage unit into the released second cache space, so as to obtain at least one piece of data of the second target variable of the second code segment from the released second cache space.

12. The apparatus according to claim 8, wherein, The second execution module includes: The second replacement submodule is used to replace at least one data of the second target variable of the second code segment in the global storage unit with at least one intermediate result of the loop code block.

13. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 6.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 6.

15. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 6.

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