Data access method, system, device and equipment, storage medium and program product

Abstract

The embodiment of the invention discloses a data access method, a storage system, a device, equipment, a storage medium and a program product, and the data access method comprises the steps: responding to a received target access request, and determining a plurality of sub access requests based on the target access request; sending the plurality of sub-memory access requests to the corresponding storage devices in batches until a target memory access response corresponding to a target sub-memory access request in the plurality of sub-memory access requests is received; and sending the target access response to a sender of the target access request. Therefore, the problem that the tail delay sharply rises due to garbage collection, read-write competition or temporary congestion of an internal storage channel and the like of single storage equipment can be improved, and the performance of a storage system is improved; a batch stepped request sending method can improve the problem of request explosive generation; on the basis of the sub-memory access requests, parallel request processing of multiple storage devices can be realized, so that the overall request processing capability of the storage system is improved.

Description

Technical Field

[0001] The present application relates to, but is not limited to, the field of cloud computing, and in particular to a data access method, system, device, equipment, storage medium, and program product. Background Art

[0002] In the related art, there is a problem that due to garbage collection of storage devices, read-write competition or temporary congestion of internal storage channels in the storage system, the tail delay of memory access requests increases sharply and the request processing performance of the storage system is poor.

[0003] By decomposing the data corresponding to the memory access request and reducing the data processing scale, and then restoring the complete data based on partial data, there is the problem of explosive generation of requests in the data recovery stage, which further reduces the overall request processing capability of the storage system. Summary of the invention

[0004] In view of this, embodiments of the present application at least provide a data access method, system, apparatus, device, storage medium, and program product.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] The present application provides a data access method, which includes:

[0007] In response to receiving the target memory access request, determining a plurality of sub-memory access requests based on the target memory access request; each sub-memory access request corresponds to a storage device in the storage system;

[0008] Sending the multiple sub-memory access requests to the corresponding storage device in batches until receiving a target memory access response corresponding to the target sub-memory access request among the multiple sub-memory access requests;

[0009] A target memory access response is sent to the sender of the target memory access request.

[0010] The embodiment of the present application provides a storage system, which includes: a storage module and a processing module; the storage module includes multiple storage devices;

[0011] A processing module is used to: in response to receiving a target memory access request, determine multiple sub-memory access requests based on the target memory access request; each sub-memory access request corresponds to a storage device; send the multiple sub-memory access requests to the corresponding storage devices in batches until a target memory access response corresponding to the target sub-memory access request among the multiple sub-memory access requests is received; and send the target memory access response to the sender of the target memory access request.

[0012] The present application provides a data access device, which includes:

[0013] A determination module, configured to determine, in response to receiving a target memory access request, a plurality of sub-memory access requests based on the target memory access request; each sub-memory access request corresponds to a storage device;

[0014] A first sending module, configured to send the plurality of sub-memory access requests to corresponding storage devices in batches until a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests is received;

[0015] The second sending module is used to send the target memory access response to the sender of the target memory access request.

[0016] An embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor can execute the computer program to implement the above-mentioned data access method.

[0017] An embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program can be executed by a processor to implement the above-mentioned data access method.

[0018] An embodiment of the present application provides a computer program, including a computer-readable code. When the computer-readable code is executed in a computer device, a processor in the computer device executes some or all of the steps for implementing the above-mentioned data access method.

[0019] An embodiment of the present application provides a computer program product, including a computer program or instructions. When the computer program or instructions are executed by a processor, some or all of the steps in the above-mentioned data access method are implemented.

[0020] According to the technical solution provided by the embodiment of the present application, multiple sub-memory access requests determined based on the target memory access request are sent to multiple storage devices in batches, and after receiving the memory access response of the target sub-memory access request, the target memory access response is sent to the sender of the target memory access request. In this way, on the one hand, the problem of a sharp increase in tail delay caused by garbage collection of a single storage device, read-write competition, or temporary congestion of the internal storage channel can be improved, and the request processing performance of the storage system can be improved; on the other hand, the batch-by-batch step-by-step request sending method can improve the problem of explosive generation of requests; on the other hand, based on the sub-memory access request, parallel processing of requests from multiple storage devices can be realized, improving the problem of decreased request processing performance of the storage system caused by garbage collection being triggered by multiple storage devices at the same time, and further improving the overall request processing capability of the storage system.

[0021] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of an implementation flow of a data access method provided in an embodiment of the present application;

[0023] Figure 2A A schematic diagram of the structure of a solid state hard disk in the related art;

[0024] Figure 2B A schematic diagram of tail delay of a read request provided in an embodiment of the present application;

[0025] Figure 2C A schematic diagram of the composition structure of a storage system provided in an embodiment of the present application Figure 1 ;

[0026] Figure 2D A second schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of an implementation flow of a data reading method provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of an implementation flow of a data writing method provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a data access device provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0032] In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field to which this application belongs. The terms used herein are only for the purpose of describing this application and are not intended to limit this application. It should also be noted that, for ease of description, only the parts related to the relevant application are shown in the accompanying drawings.

[0033] The present application embodiment provides a data access method, such as Figure 1 As shown, the data access method includes the following steps S101 to S103:

[0034] Step S101 : in response to receiving a target memory access request, a plurality of sub-memory access requests are determined based on the target memory access request; each sub-memory access request corresponds to a storage device in a storage system.

[0035] In some implementations, the data access method can be applied to electronic devices, where the electronic devices may refer to devices with data processing capabilities, such as servers, laptops, tablet computers, desktop computers, smart TVs, set-top boxes, mobile devices (such as mobile phones, portable video players, personal digital assistants, dedicated messaging devices, portable gaming devices), etc.

[0036] Here, the target memory access request may include a data memory access request to a storage device in the storage system, for example, may include a target read request and / or a target write request.

[0037] For example, the target memory access request may include a read request sent by a client to a server.

[0038] As another example, the target memory access request may include a write request sent by the host to the solid state drive.

[0039] In some implementations, the sender of the target memory access request may be a source device, and the source device may be an electronic device.

[0040] The sub-memory access request corresponds to the target memory access request. For example, the sub-memory access request corresponding to the target read request may be a sub-read request; and the sub-memory access request corresponding to the target write request may be a sub-write request.

[0041] In some implementations, the target memory access request and the sub-memory access request may have the same request data, but different destination device addresses of the requests, where the destination device may include a receiving device of the memory access request.

[0042] Exemplarily, the destination device address of the target memory access request may include a device address corresponding to the storage system, and the destination device address of the sub-memory access request may include a device address corresponding to each storage device.

[0043] The storage system may include but is not limited to at least one of physical and / or virtual devices, systems, and services with storage functions. For example, the storage system may include but is not limited to electronic devices, virtual servers, distributed storage services, etc.; the storage devices in the storage system may include one or more.

[0044] In some embodiments, the storage device may include a physical device and / or a virtual unit for storing data, for example, may include but is not limited to at least one of a hard disk (HDD), a solid state disk (SSD), an optical disk, a portable storage device, a storage volume in a cloud server, etc.; wherein the portable storage device may include but is not limited to a U disk (Universal Serial Bus, USB), a mobile hard disk, a memory card, etc.

[0045] In some implementations, the storage device may be integrated into the electronic device or may be externally connected to the electronic device.

[0046] In some implementations, after receiving the target memory access request, the legality of the target memory access request can be determined; if the target memory access request is legal, subsequent processing can be performed. The legality represents that the values ​​of the parameters corresponding to the memory access request are all within the value range of each parameter; the parameters corresponding to the memory access request can include the name of the target device, the address of the target device, the storage space of the target device, etc.

[0047] Step S102: Send the multiple sub-memory access requests to the corresponding storage device in batches until a target memory access response corresponding to a target sub-memory access request among the multiple sub-memory access requests is received.

[0048] Here, the target sub-memory access request may include a sub-memory access request that can represent the target memory access request among the multiple sub-memory access requests.

[0049] For example, the target sub-memory access request may include the sub-memory access request corresponding to any first received memory access response, that is, receiving a response to any sub-memory access request is deemed to be receiving a response to the target memory access request. It is understandable that, in the case where the data contents corresponding to multiple sub-memory access requests are the same, the completion response of any sub-memory access request can be deemed to be the completion response of the target memory access request corresponding to the sub-memory access request.

[0050] For another example, the target sub-memory access request may include a sub-memory access request sent to a target storage device in the storage system, that is, the response to the target memory access request is considered completed only after receiving a response to the memory access request from a specific storage device in the storage system.

[0051] In some implementations, whether to continue sending the next batch of sub-memory access requests may be determined based on the response results of the sub-memory access requests sent to the corresponding storage device in the current batch.

[0052] Step S103: Send the target memory access response to the sender of the target memory access request.

[0053] Here, since the target sub-memory access request can represent the target memory access request, the response result of the target sub-memory access request can represent the response result of the target memory access request. Therefore, the target memory access response corresponding to the target sub-memory access request is sent to the sender of the target memory access request, indicating that the target memory access request has completed the response.

[0054] In an embodiment of the present application, multiple sub-memory access requests determined based on a target memory access request are sent to multiple storage devices in batches, and after receiving the memory access response of the target sub-memory access request, the target memory access response is sent to the sender of the target memory access request. In this way, on the one hand, the problem of a sharp increase in tail delay caused by garbage collection of a single storage device, read-write competition, or temporary congestion of an internal storage channel can be improved, and the request processing performance of the storage system can be improved; on the other hand, the batch-by-batch step-by-step request sending method can improve the problem of explosive generation of requests; on the other hand, based on the sub-memory access request, parallel processing of requests from multiple storage devices can be realized, improving the problem of a decrease in the request processing performance of the storage system caused by garbage collection being triggered by multiple storage devices at the same time, and further improving the overall request processing capability of the storage system.

[0055] In some embodiments, the step S101 of determining a plurality of sub-memory access requests based on the target memory access request may include the following step S111:

[0056] Step S111: for each storage device in the storage system, update the destination device information carried in the target memory access request to the device information of the storage device, and obtain a sub-memory access request corresponding to the storage device.

[0057] Here, the destination device information may include device information corresponding to the recipient of the target memory access request, for example, may include but is not limited to the device name and device address of the recipient device.

[0058] In some implementations, the destination device information corresponding to the target memory access request may include virtual device information corresponding to the storage system. The destination device information corresponding to the sub-memory access request may include device information corresponding to each storage device.

[0059] In the embodiment of the present application, after receiving the target memory access request, the destination device information carried in the target memory access request is updated to the device information of the storage device, and the sub-memory access request corresponding to each storage device is obtained. In this way, on the one hand, based on the device information in each sub-memory access request, the accuracy of sending each sub-memory access request to the corresponding storage device can be improved; on the other hand, the sender does not need to make requests to multiple storage devices, but only needs to send a target memory access request corresponding to the storage system, thereby reducing the complexity of memory access.

[0060] In some embodiments, the target memory access request includes a target read request, the sub-memory access request includes a sub-read request, and the above step S102 may include the following steps S121 to S122:

[0061] Step S121 : selecting sub-read requests of a current batch from a plurality of sub-read requests, and sending the sub-read requests of the current batch to corresponding storage devices respectively.

[0062] Step S122: In response to receiving a read response corresponding to any sub-read request, determining the read response as a target memory access response, and stopping sending the next batch of sub-read requests.

[0063] In some implementations, the number of sub-read requests in the current batch may be determined based on the total number of sub-read requests. For example, one third of the total number of sub-read requests may be determined as the number of sub-read requests in each batch.

[0064] In some implementations, the number of sub-read requests in the current batch may be determined based on a processing performance parameter of the electronic device. For example, the number of parallel processing requests supported by the electronic device may be determined as the number of sub-read requests in each batch.

[0065] In some implementations, the number of sub-read requests in the current batch may be determined based on the types of storage devices in the storage system. For example, the number of types of all storage devices in the storage system may be determined as the number of sub-read requests in the current batch, and one sub-read request may be sent to each storage device in the current batch.

[0066] The current batch may include the first batch in which the sub-read request is sent, or may include any batch.

[0067] For example, after sending the first batch of sub-read requests and receiving a read response corresponding to any sub-read request in the first batch, the read response can be determined as the target memory access response, and sending the second batch and subsequent batches of sub-read requests can be stopped to determine that the response to the target read request has been completed.

[0068] For example, after sending multiple batches of sub-read requests and receiving a read response corresponding to any sub-read request in the multiple batches of requests for the first time, the read response can be determined as the target memory access response, and sending other sub-read requests that have not yet been sent can be stopped to determine that the response to the target read request has been completed.

[0069] For example, after sending the sub-read requests of the current batch and receiving the read responses of the sub-read requests of the target storage device, the read responses can be determined as the target memory access responses, and sending other sub-read requests that have not yet been sent can be stopped to determine that the responses to the target read requests have been completed.

[0070] In an embodiment of the present application, the sub-read requests of the current batch selected from the multiple sub-read requests are sent to the corresponding storage devices respectively, and in response to receiving the read response corresponding to any sub-read request, the read response is determined as the target memory access response, and the sending of the next batch of sub-read requests is stopped. In this way, on the one hand, by sending sub-read requests in batches and returning the read result to the sender of the target read request based on the first returned read response, the response speed to the target read request can be improved, and the sender's memory access experience can be improved; on the other hand, after receiving any read response, stopping sending other sub-memory access requests can reduce resource waste.

[0071] In some embodiments, the above step S102 may further include the following step S123:

[0072] Step S123 , in response to not receiving a read response within the target time after sending the sub-read requests of the current batch, selecting the sub-read requests of the next batch from the multiple sub-read requests, and sending the sub-read requests of the next batch to the corresponding storage devices respectively.

[0073] Here, the target duration may include a preset duration range.

[0074] In some implementations, the target duration may be determined based on an average latency of the storage system for read requests.

[0075] For example, the target duration may include, but is not limited to: a value corresponding to the delay performance of a storage device in a normal non-blocking state in the storage system, 50% of the value corresponding to the delay performance in a normal non-blocking state, and the like.

[0076] In the embodiment of the present application, if no read response is received within the target time after sending the sub-read requests of the current batch, the sub-read requests of the next batch are selected from the multiple sub-read requests and sent to the corresponding electronic device. In this way, based on the target time, on the one hand, the sending interval of the sub-requests can be controlled to improve the explosive generation of requests; on the other hand, on the basis of sending the read requests in batches, the overall read request response time is reduced, further improving the reading efficiency.

[0077] In some embodiments, the target memory access request includes a target write request, the sub-memory access request includes a sub-write request, and the above step S102 may include the following steps S131 to S132:

[0078] Step S131 : selecting sub-write requests of a current batch from a plurality of sub-write requests, and sending the sub-write requests of the current batch to corresponding storage devices respectively.

[0079] Step S132: In response to receiving a write response corresponding to any sub-write request, determine the write response as a target memory access response.

[0080] In some implementations, the number of sub-write requests in the current batch may be determined based on the total number of sub-write requests. For example, one third of the total number of sub-write requests may be determined as the number of sub-write requests in each batch.

[0081] In some implementations, the number of sub-write requests in the current batch may be determined based on a processing performance parameter of the electronic device. For example, the number of parallel processing requests supported by the electronic device may be determined as the number of sub-write requests in each batch.

[0082] In some implementations, the number of sub-write requests in the current batch may be determined based on the types of storage devices in the storage system. For example, the number of types of all storage devices in the storage system may be determined as the number of sub-write requests in the current batch, and one sub-write request may be sent to each storage device in the current batch.

[0083] The current batch may include the first batch in which the sub-write request is sent, or may include any batch.

[0084] For example, after sending the first batch of sub-write requests and receiving a write response corresponding to any sub-write request in the first batch, the write response can be determined as the target memory access response to determine that the response to the target write request has been completed.

[0085] For another example, after sending multiple batches of sub-write requests and first receiving a write response corresponding to any sub-write request in the multiple batches of requests, the write response may be determined as a target memory access response to determine that the response to the target write request has been completed.

[0086] For another example, after sending the sub-write requests of the current batch and receiving the write responses of the sub-write requests of the target storage device, the write responses can be determined as the target memory access responses to determine that the responses to the target write requests have been completed.

[0087] In the embodiment of the present application, the sub-write requests of the current batch selected from the multiple sub-write requests are sent to the corresponding storage devices respectively, and in response to receiving the write response corresponding to any sub-write request, the write response is determined as the target memory access response, and the sending of the next batch of sub-write requests is stopped. In this way, on the one hand, after receiving the response to any sub-write request, a response can be returned to the sender of the target write request, thereby improving the write response speed; on the other hand, by writing in batches, it is possible to avoid multiple storage devices from triggering garbage collection or other internal operations that affect delays at the same time without affecting the write performance, thereby improving the stability of the tail delay of the storage system.

[0088] In some embodiments, after the above step S103, the above data access method may further include the following step S141:

[0089] Step S141: Send the sub-write requests that have not been sent to the corresponding storage devices among the multiple sub-write requests to their corresponding storage devices.

[0090] Here, after the target memory access response is sent to the sender of the target memory access request, if there are unsent sub-write requests, the unsent sub-write requests are sent to their respective corresponding storage devices until all storage devices are written, so that the data of the storage devices in the storage system can be kept consistent.

[0091] In some implementations, after sending the sub-write requests of the current batch, the sub-write requests of the next batch may be sent at an interval of a target time.

[0092] For example, after sending the sub-write requests of the current batch, the sub-write requests of the next batch may be sent every 10 microseconds until all the sub-write requests are sent.

[0093] In the embodiment of the present application, the sub-write requests that have not been sent to the corresponding storage device among the multiple sub-write requests are sent to the corresponding storage devices. In this way, the data consistency of the storage devices in the storage system can be improved without affecting the response speed of the target write request.

[0094] In some embodiments, the first batch of sub-write requests selected from the plurality of sub-write requests include target sub-write requests corresponding to the target storage device, and the above step S132 may include the following steps S151:

[0095] Step S151: In response to receiving a write response corresponding to a target sub-write request, determine the write response as a target memory access response.

[0096] Here, due to an unexpected crash of the storage system or damage to one or more storage devices in the storage system, data on different storage devices may be inconsistent due to incomplete write requests. By setting the target storage device in advance and taking the target sub-write request corresponding to the target storage device as the basis, the data of other storage devices in the storage system can be synchronized based on the data written in the target storage device, thereby improving the stability of the data in the storage system.

[0097] In an embodiment of the present application, by introducing a target storage device and using the write response of the target sub-write request as the target memory access response sent to the sender of the target write request, when the write status of some storage devices in the storage system is abnormal, the data written in the target storage device can be synchronized to the storage device with the abnormal write status according to the target memory access response, thereby improving the stability of the data in the storage system.

[0098] In some embodiments, the starting sector of the target storage device includes a target identifier, and the above data access method may further include the following steps S161 to S162:

[0099] Step S161: When the data stored in any two storage devices are inconsistent, a target storage device is determined from all storage devices based on the target identifier.

[0100] Here, the target identifier may include an identifier that is identifiable by the storage system and unique to the target storage device. For example, the target identifier may include a binary tag.

[0101] Step S162: Synchronize the data in each storage device with the data in the target storage device.

[0102] In the embodiment of the present application, when the data stored in any two storage devices are inconsistent, the data in each storage device is synchronized with the data in the target storage device determined based on the target identifier. In this way, the consistency of the data in each storage device in the storage system can be achieved.

[0103] It can be understood that by executing steps S161 to S162 before writing data, the initialization of the storage device in the storage system can be completed; by executing steps S161 to S162 at any stage after writing data to the target storage device, data consistency recovery can be achieved when the storage system status is abnormal.

[0104] In some embodiments, the above data access method may be applied to a processing module, the processing module may include a first processing module, and the first processing module may include a plurality of first working threads;

[0105] Determining a plurality of sub-memory access requests based on the target memory access request in the above step S101 may include the following steps S171 to S172:

[0106] Step S171: Add the target memory access request to the request queue of the first target working thread through the first processing module; the first target working thread includes the first working thread with the least number of memory access requests to be processed.

[0107] Step S172: Using the first processing module and the first target working thread, read the target memory access request from the request queue of the first target working thread, and determine a plurality of sub-memory access requests based on the target memory access request.

[0108] In some embodiments, the first processing module can utilize the first target working thread to determine multiple sub-memory access requests based on the target memory access request, apply for multiple blocks of temporary memory, and set the memory buffer pointer parameters of the sub-memory access requests to the memory pointers corresponding to the multiple blocks of temporary memory respectively; each sub-memory access request corresponds to a block of temporary memory.

[0109] In the embodiment of the present application, a first processing module including multiple first working threads is used to add a target memory access request to the first working thread with the least number of memory access requests to be processed, that is, the request queue of the first target working thread; and the target memory access request is read from the request queue of the first target working thread, and multiple sub-memory access requests are determined based on the target memory access request. In this way, on the one hand, the processing efficiency of the target memory access request can be improved based on the first target working thread with the least number of memory access requests to be processed through the first processing module; on the other hand, multiple memory access requests can be processed in parallel through the first processing module, thereby improving the overall parallel request processing capability of the storage system.

[0110] In some embodiments, the processing module may further include a second processing module, and the second processing module may include a group of second working threads corresponding to each storage device;

[0111] The above step S102 may include the following steps S181 to S182:

[0112] Step S181, through the second processing module, add multiple sub-memory access requests in batches to the request queue of the second target working thread of the corresponding storage device; the second target working thread of the storage device includes the second working thread with the least number of memory access requests to be processed among the second working threads corresponding to the storage device.

[0113] In some implementations, the plurality of sub-memory access requests may be sent to the second processing module through the first processing module.

[0114] In some implementations, each storage device may correspond to a group of thread pools, and each thread pool may include a plurality of second working threads.

[0115] Step S182: In response to receiving the target memory access response, the target memory access response is sent to the first processing module through the second processing module.

[0116] The above step S103 may include the following step S183:

[0117] Step S183: Send the target memory access response to the sender of the target memory access request through the first processing module.

[0118] In an embodiment of the present application, a plurality of sub-memory access requests are added in batches to the request queue of the second working thread of the storage device corresponding to each other and having the least number of memory access requests to be processed, that is, the second target working thread, through the second processing module; and upon receiving the target memory access response, the target memory access response is sent to the first processing module through the second processing module; and then the target memory access response is sent to the sender of the target memory access request through the first processing module. In this way, on the one hand, the processing efficiency of the sub-memory access request can be improved by using the second target working thread with the least number of memory access requests to be processed through the second processing module; on the other hand, the sending of the sub-memory access request to the storage device is completed based on the second processing module, and the interaction between the sub-memory access request and the target memory access response is completed based on the first processing module and the second processing module, so as to further improve the overall parallel request processing capability.

[0119] In the related art, a solid state drive uses a flash memory (NAND) medium for data storage.

[0120] like Figure 2A As shown, the front end 20 of the solid-state drive 10 mainly includes a host interface 21, a hard disk controller 22 and a dynamic random access memory (DRAM) 23, wherein the hard disk controller 22 may include multiple channel controllers for controlling the back-end flash memory channels, such as a channel controller 24 and a channel controller 25; the back end 30 of the solid-state drive 10 usually includes multiple flash memory channels, such as a channel 31 and a channel 32, which can transmit and process input / output (IO) transactions in parallel, and each channel is connected to one or more flash memory media, such as channel 31 is connected to flash memory chip 33 and flash memory chip 34, and channel 32 is connected to flash memory chip 35 and flash memory chip 36.

[0121] Since flash media cannot directly overwrite existing data, new data can only be written to the same location after the old data has been erased. SSDs read and write at the page level and erase data at the flash block level. Therefore, an address mapping manager (Flash Translation Layer, FTL) is required inside the SSD controller to map the logical block address requested by the host to the physical block address of the flash memory.

[0122] Based on the above structure, SSD has a tail delay problem that is difficult to solve. The reasons that lead to increased tail delay include but are not limited to: SSD garbage collection (GC) mechanism; wear leveling mechanism; controller competition; flash channel competition; IO task scheduling mechanism, etc.

[0123] For the GC mechanism of SSD, when writing new data to a block storing invalid data in a solid-state drive, the block storing invalid data needs to be deleted before writing can be completed. GC refers to re-transferring the existing data in the current flash memory location to other flash memory locations and completely deleting the invalid data. In addition, garbage collection will be performed when there is a write request.

[0124] The GC operation migrates data inside the SSD, which blocks the data read and write IO of external users until the GC completes the FTL record and returns to the read and write IO. Therefore, GC latency has a greater impact on the latency of read and write IO, especially on the high percentiles of tail latency, such as 99%, 99.9%, etc.

[0125] For mechanisms such as wear leveling and IO task scheduling, similar to garbage collection, these internal operations involve the migration of data within the SSD. The data migration process will occupy key resources within the SSD, for example, occupying flash channel resources, generating FTL conflicts, or occupying SSD computing resources, resulting in a serious decline in the quality of user request services.

[0126] like Figure 2B As shown in the figure, when processing read and write requests in parallel, the tail delay distributions of read requests of different sizes (e.g., 8KB, 16KB, 32KB, 64KB, 128KB, etc.) are different. The x-axis is the duration of the tail delay in milliseconds, and the y-axis is the percentage of requests. It can be seen that the tail delays of read requests of different sizes will be greatly affected when reading and writing are concurrent.

[0127] Therefore, SSDs are difficult to be widely used in scenarios that are sensitive to latency and Quality of Service (QoS). For example, in the storage of metadata, if the performance of accessing metadata decreases, the overall data access performance will be greatly reduced.

[0128] In the related art, the high tail latency problem of SSD is solved by optimizing the internal or external operations of SSD. For example, by redesigning or optimizing the behaviors inside the SSD device that cause the increased tail latency, such as garbage collection and wear leveling, or by optimizing the host software or SSD load behavior, adding new components outside the SSD, etc.

[0129] However, since multiple complex mechanisms inside the SSD jointly lead to increased tail latency, optimizing only a single or partial internal operation cannot completely solve the SSD tail latency problem. In addition, the redesigned or optimized SSD requires modification of the corresponding hardware controller and / or flash media, which is highly targeted and has poor application flexibility.

[0130] As for the method of setting up cache outside the SSD, due to the limited cache capacity, it is still impossible to avoid the tail delay problem. For example, when the cache space is missing, it is inevitable that the read request to the SSD will still be interfered by the internal operation of the SSD when all data cannot be read. Therefore, this kind of method cannot effectively reduce the tail delay.

[0131] On this basis, the present application embodiment provides a storage system, such as Figure 2C As shown, the storage system 200 includes: a storage module 210 and a processing module 220. The storage module 210 may include multiple storage devices;

[0132] The processing module 220 can be used to: in response to receiving a target memory access request, determine multiple sub-memory access requests based on the target memory access request; each of the sub-memory access requests corresponds to one of the storage devices; send the multiple sub-memory access requests to the corresponding storage devices in batches until a target memory access response corresponding to the target sub-memory access request among the multiple sub-memory access requests is received; and send the target memory access response to the sender of the target memory access request.

[0133] In some embodiments, the processing module can also be used to: for each storage device in the storage system, update the destination device information carried in the target memory access request to the device information of the storage device, and obtain the sub-memory access request corresponding to the storage device.

[0134] In some embodiments, the target memory access request includes a target read request, and the sub-memory access request includes a sub-read request. The processing module can also be used to: select a current batch of sub-read requests from a plurality of the sub-read requests, and send the current batch of sub-read requests to corresponding storage devices respectively; in response to receiving a read response corresponding to any of the sub-read requests, determine the read response as the target memory access response, and stop sending the next batch of sub-read requests.

[0135] In some embodiments, the processing module can also be used to: in response to not receiving a read response within a target time length after sending the current batch of sub-read requests, select a next batch of sub-read requests from multiple sub-read requests, and send the next batch of sub-read requests to corresponding storage devices respectively.

[0136] In some embodiments, the target memory access request includes a target write request, and the sub-memory access request includes a sub-write request. The processing module can also be used to: select a current batch of sub-write requests from a plurality of the sub-write requests, and send the current batch of sub-write requests to corresponding storage devices respectively; in response to receiving a write response corresponding to any of the sub-write requests, determine the write response as the target memory access response.

[0137] In some embodiments, the processing module may also be used to: send sub-write requests that have not been sent to corresponding storage devices among the plurality of sub-write requests to their respective corresponding storage devices.

[0138] In some embodiments, a first batch of sub-write requests selected from the multiple sub-write requests include target sub-write requests corresponding to a target storage device, and the processing module can also be used to: in response to receiving a write response corresponding to the target sub-write request, determine the write response as the target memory access response.

[0139] In some embodiments, the starting sector of the target storage device includes a target identifier, and the processing module can also be used to: when the data stored in any two of the storage devices are inconsistent, determine the target storage device from all the storage devices based on the target identifier; and synchronize the data in each of the storage devices with the data in the target storage device.

[0140] In some embodiments, the processing module includes a first processing module, the first processing module includes multiple first working threads, and the first processing module can be used to: add the target memory access request to the request queue of the first target working thread; the first target working thread includes the first working thread with the least number of memory access requests to be processed; use the first target working thread to read the target memory access request from the request queue of the first target working thread, and determine multiple sub-memory access requests based on the target memory access request.

[0141] In some embodiments, the processing module further includes a second processing module, the second processing module includes a group of second working threads corresponding to each of the storage devices, and the second processing module can be used to: add the plurality of sub-memory access requests to the request queue of the second target working thread of the storage device corresponding to each of the storage devices in batches; the second target working thread of the storage device includes the second working thread with the least number of memory access requests to be processed among the second working threads corresponding to the storage device; in response to receiving the target memory access response, send the target memory access response to the first processing module;

[0142] The first processing module may also be configured to: send the target memory access response to a sender of the target memory access request.

[0143] For example, Figure 2D As shown, the storage system 200 may further include a bitmap module 230 and a data consistency recovery module 240. The storage module 210 may include multiple storage devices, such as storage device 1, storage device 2 to storage device N; the processing module 220 may include a first request processing module 221 and a second request processing module 222, which respectively correspond to the first processing module and the second processing module in the above-mentioned data access method, the first request processing module 221 and the second request processing module 222 may include multiple working threads, and the processing module 220 may be a request parallel processing module; the bitmap module 230 is used to determine whether a data block of the storage device is being written; the data consistency recovery module 240 is used to perform consistency recovery of data stored in the storage device in the storage system.

[0144] In some implementations, multiple solid-state hard disks of the same model may be used as storage devices in the storage module.

[0145] In some implementations, each storage device may contain an identical copy of the data.

[0146] In some implementations, the storage module may be initialized before the storage module is applied, for example, full initialization or partial initialization may be performed.

[0147] For example, for full initialization, the existing data in all storage devices may be abandoned, and an empty storage module without any data may be constructed, that is, the data stored in all storage devices in the storage module are empty. For example, all available spaces of all hard disks may be filled with 0, and a completion result may be returned after the filling is completed.

[0148] Exemplarily, for partial initialization, at least one storage device among all storage devices may be designated as an initial storage device, all existing data in the initial storage device is retained, and a storage module containing only the existing data in the initial storage device is constructed.

[0149] For example, the used space information and unused space information of the initial storage device can be obtained; according to the used space information of the initial storage device, data is read from the initial storage device, and the read data is overwritten to the corresponding positions of all other storage devices in the storage module; according to the unused space information of the initial storage device, the corresponding positions of all storage devices including the initial storage device are set to 0; and the completion result is returned after completion. Among them, the used space information may include the storage offset and storage length information of the used data, the storage offset of the used data may include the storage position of the used data in the hard disk, the storage length of the used data may include the data size of the used data, and the unused space information may include the unused storage offset and storage length information in the initial storage device.

[0150] In some embodiments, after the storage module is initialized, a storage device can be randomly designated as the target storage device in the storage module, and a target identifier can be written in the starting sector of the target storage device; the available capacity of the target storage device is used as the total capacity of the storage module, and the total capacity of the storage module and the virtual device name of the storage module are reported to upper-level applications, such as a file system, a database application, etc., wherein the virtual device name may include a device name that is different from the storage device name and is used to indicate the storage module.

[0151] During implementation, the first request processing module may include a thread pool including a plurality of first working threads. The number of first working threads may be determined based on the processing performance of the electronic device and / or user requirements, for example, the number of first working threads may be 128. Each first working thread is assigned a first request queue, and the first working thread processes all requests in the first request queue sequentially and independently.

[0152] In implementation, the second request processing module may include multiple groups of thread pools, each storage device may correspond to a group of thread pools, and each group of thread pools may include multiple second working threads. The number of second working threads may be determined based on the processing performance of the electronic device and / or user requirements, for example, the number of second working threads may be 4. Each second working thread is assigned a second request queue, and the second working thread processes all requests in the second request queue in sequence and independently.

[0153] During implementation, the bitmap module may include multiple bitmap instances, each of which corresponds to a storage device in the storage module. The bitmap instance may be used to save the write status of all data blocks in the storage device during operation in bits. For example, when a data block of a storage device is being written, the bit corresponding to the bitmap instance of the storage device may be set to 1; after the writing of the data block is completed, the bit corresponding to the bitmap instance of the storage device may be set to 0.

[0154] In some implementations, the bit corresponding to the data block may be determined by the offset of the data block in the storage device.

[0155] For example, the position of the data block in the bitmap may correspond to the position where the ratio between the offset of the data block and the size of the data block is located.

[0156] Combination Figure 2D The storage system 200 in the present application provides a data reading method for processing a read request from a client to the storage system. The storage system includes a storage module for storing user data in multiple SSDs of the same model, managing key data such as virtual storage device information and storage system capacity; a processing module for processing data read requests and / or write requests, performing multiple read operations and parallel IO request access; a bitmap module for recording the write status of the runtime data of the SSD in the storage module, avoiding multiple read operations from returning erroneous data or old data, and keeping the multiple read operations stable and available; a data consistency recovery module for recovering the data in the storage module to keep the data consistent when the storage system crashes unexpectedly or one or more SSDs are damaged; the client can correspond to the sender in the above data access method, and the client's read request can correspond to the target read request in the above data access method.

[0157] Exemplarily, a read request may be represented as Q r .

[0158] like Figure 3 As shown, the method includes the following steps S301 to S309:

[0159] Step S301: Check the legitimacy of the read request.

[0160] Here, it can correspond to checking the legality of the memory access request in the above data memory access method.

[0161] The read request may be an IO structure including key parameters such as the destination device, access offset, access length, and memory buffer pointer, wherein the access offset corresponds to the storage offset of the accessed destination device, and the access length corresponds to the storage length of the accessed destination device.

[0162] In some implementations, after the sender sends the target read request, the validity of the target read request may be checked by the request scheduler.

[0163] If the read request is legal, step S302 is executed; otherwise, the read request returns failure.

[0164] Step S302: The first request processing module allocates a first working thread for the read request.

[0165] In implementation, after receiving the read request, the first request processing module may determine a first working thread T in its thread pool that has the least number of requests to be processed. f , and read the request Q r Join the first worker thread T f The corresponding first request queue.

[0166] Step S303: The first working thread copies the read request and generates N sub-requests.

[0167] In implementation, the first worker thread T f The read request Q can be obtained and copied from the first request queue r After that, N sub-requests Q are generated rc1 -Q rcN , and modify the destination device information of all sub-requests to the device names of N SSDs in the storage system; apply for N new temporary memory blocks, and the size of each temporary memory block is the same as the read request Q r The access length of sub-request Q is equal to that of N new memory pointers. rc1 -Q rcN It may correspond to the sub-read request in the above data access method.

[0168] Step S304: Select K sub-requests from all sub-requests, send them to the second request processing module, and count the time.

[0169] In implementation, subrequests may be chosen randomly.

[0170] During implementation, K may be greater than or equal to 2 and less than or equal to N. For example, K may be N / 3.

[0171] In implementation, K sub-requests can be sent to the second request processing module at the same time, waiting for the sub-requests to return responses and timing; if no sub-request returns a response after the timing exceeds the average delay threshold, K sub-requests that have not been sent can be selected and sent to the second request processing module, and the timing can be restarted; if the number of sub-requests that have not been sent is less than K, all the remaining sub-requests are sent. The average delay threshold can correspond to the target duration in the above data access method.

[0172] During implementation, if all subrequests have been sent, you can stop sending and wait for any subrequest to complete.

[0173] Step S305: The second request processing module schedules the sub-requests to different thread pool groups.

[0174] During implementation, the second request processing module may receive the sub-request Q rcAfterwards, the sub-requests are assigned to thread pool groups corresponding to different SSDs according to the destination device information of each sub-request. rc , determine the second worker thread T with the least number of pending requests in the thread pool s , the sub-request Q rc Join thread T s The corresponding second request queue.

[0175] Step S306: query the bitmap module to determine whether there is any unfinished writing.

[0176] In implementation, the second worker thread T s Get a subrequest Q from the queue rc First, according to Q rc The IO parameters included in the sub-request query the bitmap instance corresponding to the SSD to determine whether there is an unfinished write operation on the data block of the SSD corresponding to the sub-request. If there is an unfinished write operation, for example, the bit of the bitmap is 1, wait for the write operation to be completed; if there is no unfinished write operation, for example, the bit of the bitmap is 0, execute step S307.

[0177] Step S307: read the SSD and return a response to the first request processing module.

[0178] In implementation, the second worker thread T s According to the sub-request Q rc The IO parameters contained in the data are read from the corresponding SSD and Q is filled after the reading is completed. rc The corresponding temporary memory buffer is sent to the first worker thread T f Returns the response.

[0179] Step S308: Determine whether any sub-request has been completed.

[0180] In implementation, the first worker thread T f After any sub-request is processed, Q rc The content in the corresponding temporary memory buffer is copied to the read request Q r The sub-request is sent to the provided memory buffer and the response is returned to the sender. For example, the sub-request with the fastest response can be selected.

[0181] Step S309: Return a response to the sender.

[0182] In implementation, the first worker thread T f You can wait for all sub-requests to complete the response, destroy the N blocks of temporary memory requested, continue to process other memory access requests in the queue, or enter the idle state.

[0183] In the embodiment of the present application, when the user reads data, a read request is sent to multiple SSDs in a step-by-step manner, that is, a round of read requests is first sent to some SSDs and timed, and after the timeout, other SSDs are selected to send the next round, until the first SSD reads data and returns success to the user. In this way, the problem of a sharp increase in read latency caused by garbage collection of a single SSD, read-write competition, or temporary congestion of the internal flash channel can be improved, and the request processing performance of the storage system can be improved; on the other hand, the step-by-step request sending method can also improve the problem of explosive generation of IO traffic; on the other hand, there is no need to modify the internal software or hardware components of the SSD, and the application flexibility is strong.

[0184] Combination Figure 2D The storage system 200 in the present application provides a data writing method for processing a write request from a client to the storage system. The storage system includes multiple SSDs, and the write request from the client can correspond to the target write request in the above data access method.

[0185] Exemplarily, a write request may be represented as Q w .

[0186] like Figure 4 As shown, the method includes the following steps S401 to S410:

[0187] Step S401: Check the legitimacy of the write request.

[0188] Here, it can correspond to checking the legality of the memory access request in the above data memory access method.

[0189] The write request can be an IO structure containing key parameters such as the destination device, access offset, access length, and memory buffer pointer.

[0190] In some implementations, after the sender sends the target write request, the validity of the target write request may be checked by the request scheduler.

[0191] If the write request is legal, step S402 is executed; otherwise, the write request returns failure.

[0192] Step S402: The first request processing module allocates a first working thread for the write request.

[0193] In implementation, after receiving the write request, the first request processing module may determine a first working thread T in its thread pool that has the least number of requests to be processed. f , and write request Q w Join the first worker thread T f The corresponding first request queue.

[0194] Step S403: The first working thread obtains a write request and generates N sub-requests.

[0195] In implementation, the first worker thread T f The write request Q can be obtained and copied from the first request queue w After that, N sub-requests Q are generated wc1 -Q wcN , and modify the destination device information of all sub-requests to the device names of N SSDs in the storage system. wc1 -Q wcN It may correspond to the sub-write request in the above data access method.

[0196] Step S404: Send the target sub-request corresponding to the main SSD in all sub-requests to the second request processing module, and send other sub-requests to the second request processing module according to a certain time interval.

[0197] Here, the master SSD may correspond to the target storage device in the above data access method.

[0198] In implementation, the first worker thread T f The target sub-request Q corresponding to the primary SSD can be wcm After being sent to the second request processing module, other sub-requests are sent to the second request processing module in a random order at each target interval. During this period, the target sub-request Q sent to the primary SSD is polled. wcm The target sub-request Q wcm It can correspond to the target sub-write request in the above data access method.

[0199] Step S405: The second request processing module schedules the sub-requests to different thread pool groups.

[0200] During implementation, the second request processing module may receive the sub-request Q wc Afterwards, the sub-requests are assigned to thread pool groups corresponding to different SSDs according to the destination device information of each sub-request. wc , determine the second worker thread T with the least number of pending requests in the thread pool s , the sub-request Q wc Join thread T s The corresponding second request queue.

[0201] Step S406: modify the corresponding bitmap instance in the bitmap module according to the write status.

[0202] In implementation, the second worker thread T s Get a subrequest Q from the queue wc First, according to Qwc The included IO parameters set the bit corresponding to the bitmap instance corresponding to the SSD to 1, and write the request to the SSD; after the write is successful, the bit corresponding to the bitmap instance is set to 0, and a response is returned to the first request processing module.

[0203] Step S407: Return a response to the first request processing module.

[0204] Here, the second request processing module may return a response to the first request processing module after the target sub-request completes the response.

[0205] Step S408: Determine whether the target sub-request corresponding to the primary SSD has completed the response.

[0206] Step S409: Return a response to the sender.

[0207] Step S410: Determine whether all sub-requests have completed the response.

[0208] In implementation, the first worker thread T f The target subrequest Q wcm After completing the response, it returns the response to the sender and polls the completion status of other sub-requests. After waiting for all sub-requests to complete the response, it continues to process other memory access requests in the queue or enters the idle state.

[0209] In the embodiment of the present application, when the user writes data, the data is first written to the main SSD, and after the request is successfully written, a response is first returned to the sender, and then write requests are sent to the remaining SSDs in a random order in the background, and the data synchronization status is recorded using a bitmap. In this way, on the one hand, the asynchronous writing method can disrupt the writing order of multiple SSDs, improve the problem of multiple SSDs triggering garbage collection at the same time, and further improve the delay stability of read requests in the read-write parallel scenario; on the other hand, there is no need to modify the internal software or hardware components of the SSD, and the application flexibility is strong.

[0210] It can be understood that the above-mentioned data reading method and data writing method receive user requests through the first request processing module, generate sub-requests and asynchronously transmit them to the second request processing module; through the second request processing module, the SSD is read and written in parallel according to the sub-requests, which can effectively improve the overall parallel request processing capability of the storage system.

[0211] In some embodiments, during the implementation of the above-mentioned data reading method and data writing method, when the data of different SSDs in the storage module are inconsistent, the starting sectors of all SSDs in the storage module can be scanned, and the main SSD containing the target identifier can be determined; the SSD data except the main SSD is compared with the data of the main SSD, and if the data are different, the main SSD data overwrites the data of other SSDs.

[0212] The present application embodiment provides a data access device, such as Figure 5 As shown, the data access device 500 includes:

[0213] A determination module 510 is used to determine, in response to receiving a target memory access request, a plurality of sub-memory access requests based on the target memory access request; each sub-memory access request corresponds to a storage device in the storage system;

[0214] A first sending module 520, configured to send the plurality of sub-memory access requests to corresponding storage devices in batches until a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests is received;

[0215] The second sending module 530 is used to send the target memory access response to the sender of the target memory access request.

[0216] In some implementations, the first sending module may correspond to the second processing module in the above-mentioned data access method.

[0217] In some implementations, the second sending module may correspond to the first processing module in the above-mentioned data access method.

[0218] In some embodiments, the determination module may also be used to: for each storage device in the storage system, update the destination device information carried in the target memory access request to the device information of the storage device, and obtain a sub-memory access request corresponding to the storage device.

[0219] In some embodiments, the target memory access request includes a target read request, the sub-memory access request includes a sub-read request, and the first sending module can also be used to: select a current batch of sub-read requests from multiple sub-read requests, and send the current batch of sub-read requests to corresponding storage devices respectively; in response to receiving a read response corresponding to any sub-read request, determine the read response as a target memory access response, and stop sending the next batch of sub-read requests.

[0220] In some embodiments, the first sending module can also be used to: in response to not receiving a read response within a target time length after sending a current batch of sub-read requests, select a next batch of sub-read requests from multiple sub-read requests, and send the next batch of sub-read requests to corresponding storage devices respectively.

[0221] In some embodiments, the target memory access request includes a target write request, the sub-memory access request includes a sub-write request, and the first sending module can also be used to: select a current batch of sub-write requests from multiple sub-write requests, and send the current batch of sub-write requests to corresponding storage devices respectively; in response to receiving a write response corresponding to any sub-write request, determine the write response as a target memory access response.

[0222] In some embodiments, after sending the target memory access response to the sender of the target memory access request, the first sending module may also be used to send sub-write requests among multiple sub-write requests that have not been sent to corresponding storage devices to their respective corresponding storage devices.

[0223] In some embodiments, a first batch of sub-write requests selected from multiple sub-write requests includes target sub-write requests corresponding to a target storage device, and the first sending module can also be used to: in response to receiving a write response corresponding to the target sub-write request, determine the write response as a target memory access response.

[0224] In some embodiments, the starting sector of the target storage device includes a target identifier, and the determination module can also be used to: when the data stored in any two storage devices are inconsistent, determine the target storage device from all storage devices based on the target identifier; and synchronize the data in each storage device with the data in the target storage device.

[0225] In some embodiments, the above-mentioned data memory access device may also include a processing module, the processing module may include a first processing module, the first processing module may include multiple first working threads, and the first processing module may be used to: add the target memory access request to the request queue of the first target working thread; the first target working thread includes the first working thread with the least number of memory access requests to be processed; using the first target working thread, read the target memory access request from the request queue of the first target working thread, and determine multiple sub-memory access requests based on the target memory access request.

[0226] In some embodiments, the processing module may further include a second processing module, the second processing module includes a group of second working threads corresponding to each storage device, and the second processing module may be used to: add multiple sub-memory access requests to the request queue of the second target working thread of the storage device corresponding to each storage device in batches; the second target working thread of the storage device includes the second working thread with the least number of memory access requests to be processed among the second working threads corresponding to the storage device; in response to receiving the target memory access response, send the target memory access response to the first processing module;

[0227] The first processing module may also be configured to: send a target memory access response to a sender of the target memory access request.

[0228] The present application embodiment provides an electronic device, including: a memory and a processor. Figure 6 As shown, the electronic device 600 includes:

[0229] A memory 601, for storing a computer program executable on the processor 602;

[0230] The processor 602 is used to execute the program stored in the memory 601 to implement the above-mentioned data access method applied to the data access device.

[0231] An embodiment of the present application provides a computer program, including a computer-readable code. When the computer-readable code is executed in a computer device, a processor in the computer device executes some or all of the steps for implementing the above-mentioned data access method.

[0232] An embodiment of the present application provides a computer program product, including a computer program or instructions, which, when executed by a processor, implements some or all of the steps in the above-mentioned data access method.

[0233] An embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program can be executed by a processor to implement the above-mentioned data access method.

[0234] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatuses, and devices according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0235] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0236] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0237] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application.

[0238] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0239] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0240] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0241] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0242] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0243] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0244] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0245] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0246] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A data access method, characterized in that: The method comprises: In response to receiving a target memory access request, determining a plurality of sub-memory access requests based on the target memory access request; each of the sub-memory access requests corresponds to a storage device in the storage system; Sending the plurality of sub-memory access requests to the corresponding storage device in batches until receiving a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests; The target memory access response is sent to the sender of the target memory access request.

2. The method according to claim 1, characterized in that The determining, based on the target memory access request, a plurality of sub-memory access requests comprises: For each of the storage devices in the storage system, the destination device information carried in the target memory access request is updated with the device information of the storage device, so as to obtain the sub-memory access request corresponding to the storage device.

3. The method according to claim 1, characterized in that The target memory access request includes a target read request, and the sub-memory access request includes a sub-read request; The sending the plurality of sub-memory access requests to the corresponding storage device in batches until receiving a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests includes: Selecting sub-read requests of a current batch from the plurality of sub-read requests, and sending the sub-read requests of the current batch to corresponding storage devices respectively; In response to receiving a read response corresponding to any of the sub-read requests, determining the read response as the target memory access response, and stopping sending the next batch of sub-read requests.

4. The method according to claim 3, characterized in that: The sending of the plurality of sub-memory access requests to the corresponding storage device in batches until receiving a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests further includes: In response to not receiving a read response within a target time period after sending the sub-read requests of the current batch, selecting a next batch of sub-read requests from the multiple sub-read requests, and sending the next batch of sub-read requests to corresponding storage devices respectively.

5. The method according to claim 1, characterized in that The target memory access request includes a target write request, and the sub-memory access request includes a sub-write request; The sending the plurality of sub-memory access requests to the corresponding storage device in batches until receiving a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests includes: Selecting sub-write requests of a current batch from the plurality of sub-write requests, and sending the sub-write requests of the current batch to corresponding storage devices respectively; In response to receiving a write response corresponding to any of the sub-write requests, determining the write response as the target memory access response.

6. The method according to claim 5, characterized in that After sending the target memory access response to the sender of the target memory access request, the method further includes: Sub-write requests that have not been sent to corresponding storage devices among the plurality of sub-write requests are sent to their corresponding storage devices.

7. The method according to claim 5, characterized in that A first batch of sub-write requests selected from the plurality of sub-write requests includes target sub-write requests corresponding to a target storage device; In response to receiving a write response corresponding to any of the sub-write requests, determining the write response as the target memory access response includes: In response to receiving a write response corresponding to the target sub-write request, determining the write response as the target memory access response.

8. The method according to claim 7, characterized in that The starting sector of the target storage device includes a target identifier, and the method further includes: In the case where the data stored in any two of the storage devices are inconsistent, determining the target storage device from all the storage devices based on the target identifier; The data in each of the storage devices is synchronized with the data in the target storage device.

9. The method according to any one of claims 1 to 8, characterized in that Applied to a processing module, the processing module includes a first processing module, and the first processing module includes a plurality of first working threads; The determining, based on the target memory access request, a plurality of sub-memory access requests comprises: By means of the first processing module, the target memory access request is added to a request queue of a first target working thread; the first target working thread comprises a first working thread having the least number of memory access requests to be processed; The target memory access request is read from the request queue of the first target working thread by the first processing module, and a plurality of the sub-memory access requests are determined based on the target memory access request.

10. The method according to claim 9, characterized in that The processing module further includes a second processing module, wherein the second processing module includes a group of second working threads corresponding to each of the storage devices; The sending the plurality of sub-memory access requests to the corresponding storage device in batches until receiving a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests includes: By means of the second processing module, the plurality of sub-memory access requests are added in batches to the request queue of the second target working thread of the storage device corresponding to each of them; the second target working thread of the storage device includes the second working thread with the least number of memory access requests to be processed among the second working threads corresponding to the storage device; In response to receiving the target memory access response, sending the target memory access response to the first processing module through the second processing module; The step of sending the target memory access response to the sender of the target memory access request includes: The target memory access response is sent to a sender of the target memory access request through the first processing module.

11. A storage system, characterized in that: include: Storage module and processing module; The storage module includes a plurality of storage devices; The processing module is used to: in response to receiving a target memory access request, determine a plurality of sub-memory access requests based on the target memory access request; each of the sub-memory access requests corresponds to one of the storage devices; Sending the plurality of sub-memory access requests to the corresponding storage device in batches until receiving a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests; The target memory access response is sent to the sender of the target memory access request.

12. A data access device, characterized in that: include: A determination module, configured to determine, in response to receiving a target memory access request, a plurality of sub-memory access requests based on the target memory access request; Each of the sub-memory access requests corresponds to a storage device in the storage system; A first sending module, configured to send the plurality of sub-memory access requests to the corresponding storage device in batches until a target memory access response corresponding to a target sub-memory access request among the plurality of sub-memory access requests is received; The second sending module is used to send the target memory access response to the sender of the target memory access request.

13. An electronic device, characterized in that: include: A memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, the steps in the method according to any one of claims 1 to 10 are implemented.

14. A computer-readable storage medium, characterized in that: A computer program is stored, and the computer program can be executed by a processor to implement the method according to any one of claims 1 to 10.

15. A computer program product, characterized in that The method comprises a computer program or an instruction, which, when executed by a processor, implements the method according to any one of claims 1 to 10.

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