Satellite-borne aircraft fault processing method and system, computer equipment and readable storage medium

Abstract

The invention discloses a spaceborne aircraft fault processing method and system, computer equipment and a readable storage medium, a hardware reconstruction program allows in-orbit reconstruction, errors caused by a single event can be corrected, the in-orbit operation fault tolerance rate is improved, and the self-repairing capability of the system is enhanced. The method comprises the following steps: in response to a reconstruction instruction, loading a plurality of pre-configured reconstruction programs into a target memory based on the program processing system part; a target reconstruction program is determined, the program processing system part and / or the programmable logic part are / is reconstructed based on the target reconstruction program, and the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction; detecting an output signal of the programmable logic part, wherein the output signal is a state signal output by the programmable logic part; when it is detected that the output signal is higher than a preset value, reconstruction of the spaceborne computer is completed.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, system, computer device and readable storage medium for handling satellite-borne aircraft faults. Background Art

[0002] With the advancement of aerospace technology, micro-satellites need to achieve diversified tasks, which requires their onboard aircraft, that is, onboard computers, to be more flexible and able to match functions to tasks. They must also be scalable and able to expand the system to meet changing mission requirements. At the same time, considering that the onboard aircraft is in a high-radiation environment, single-particle radiation effects may occur, causing device anomalies or even damage, which requires onboard computers to have error detection and fault tolerance capabilities.

[0003] In related technologies, satellite-borne aircraft generally adopt a redundant backup architecture design that includes multiple devices. This multi-device redundant backup strategy can effectively reduce the risk of single point failures, thereby ensuring that the satellite-borne aircraft can still maintain its normal function under extreme conditions such as vacuum, radiation, temperature fluctuations, etc. in space.

[0004] In the process of implementing this application, the applicant found that the related technology has at least the following problems:

[0005] Although multi-device redundant backup improves reliability, it also increases system complexity and cost. Moreover, due to the increase in the number of components, the weight and power consumption of the system also increase. In addition, when faced with some unexpected failure modes, the multi-device redundant backup architecture cannot completely prevent the failure of the onboard aircraft system, which may cause the onboard aircraft system to be unable to continue to perform its mission. Summary of the invention

[0006] In view of this, the present application provides a satellite-borne aircraft fault handling method, system, computer device and readable storage medium, the main purpose of which is to solve the problem that the current multi-device redundant backup increases the complexity and cost of the system. At the same time, due to the increase in the number of components, the weight and power consumption of the system also increase. In addition, when faced with some unexpected failure modes, the multi-device redundant backup architecture cannot completely avoid the failure of the satellite-borne aircraft system, resulting in the problem that the satellite-borne aircraft system cannot continue to perform the mission.

[0007] According to a first aspect of the present application, a method for handling faults of a satellite-borne machine is provided. The method is applicable to an embedded system chip of a satellite-borne computer. The embedded system chip includes a program processing system part and a programmable logic part. The method includes:

[0008] In response to the reconstruction instruction, based on the program processing system part, multiple pre-configured reconstruction programs are loaded into the target memory, and the reconstruction instruction is generated by the monitoring module of the onboard computer according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal;

[0009] Determine a target reconstruction program, and reconstruct the program processing system part and / or the programmable logic part based on the target reconstruction program, wherein the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part;

[0010] Detecting an output signal of the programmable logic part, where the output signal is a state signal DONE signal output by the programmable logic part;

[0011] When it is detected that the output signal is higher than a preset value, the reconstruction of the onboard computer is completed.

[0012] Optionally, based on the program processing system part, a plurality of pre-configured reconstruction programs are loaded into the target memory, including:

[0013] Based on the reconstruction task scheduling module, the program processing system part of the embedded system chip is controlled to call multiple reconstruction programs stored in the off-chip program memory Flash;

[0014] Perform data verification on the reconstructed program based on the program processing system part and generate verification results;

[0015] When the verification result indicates that the verification is passed, multiple reconstruction programs are loaded into the target memory based on the program processing system part, wherein the program processing system part includes a reconstruction task scheduling module, an ARM task reconstruction module and a remote reconstruction module.

[0016] Optionally, after performing data verification on the reconstructed program based on the program processing system part and generating a verification result, the method further includes:

[0017] When the verification result indicates that the verification is abnormal, a remote reconstruction request is initiated to the ground control terminal, and a reconstruction program transmitted by the ground control terminal is received based on the remote reconstruction module, and the reconstruction program is transmitted by the ground control terminal through Ethernet;

[0018] Based on the remote reconstruction module, the reconstruction program is stored in the Flash using a triple-module redundant storage method.

[0019] Optionally, in response to the reconstruction instruction, based on the program processing system part, before loading a plurality of pre-configured reconstruction programs into the target memory, the method further comprises:

[0020] constructing a top-level module for the programmable logic portion, and constructing at least one reconfiguration module for the programmable logic portion according to at least one running task, each reconfiguration module being associated with one running task;

[0021] Determine a first hardware description language associated with the top-level module and a second hardware description language associated with each reconstruction module, perform syntax detection and rule detection on the first hardware description language and each second hardware description language, and generate syntax detection results and rule detection results, wherein the first hardware description language and each second hardware description language are both written based on the Verilog module;

[0022] When both the syntax detection result and the rule detection result indicate that the detection is passed, setting physical constraints for the programmable logic part, the physical constraints include but are not limited to clock constraints and pin constraints;

[0023] Compile and solidify the programmable logic part, and initialize the embedded system chip when it is powered on. The initialization is to read the global reconstruction program solidified in the Flash to the target memory, initialize the program processing system part of the embedded system chip by running the global reconstruction program in the target memory, and initialize the programmable logic part by configuring the storage address and data size associated with the global reconstruction program of the target memory to the programmable logic part of the embedded system chip.

[0024] Optionally, compiling and curing the programmable logic part includes:

[0025] Divide the programmable logic part into at least one reconfigurable area, determine the area range of each reconfigurable area, and perform layout and routing on the top module and each reconfigurable module;

[0026] Determine a global reconstruction program based on the first hardware description language, and determine a reconstruction program corresponding to each reconstruction module based on each second hardware description language;

[0027] The global reconstruction program is solidified in the off-chip program memory Flash, and each reconstruction program is stored in the off-chip program memory Flash and / or in the SD card memory as a pre-configured reconstruction program.

[0028] Optionally, determining an area range of each reconfigurable area includes:

[0029] For any reconfigurable area, determining at least one operating task executed by the reconfigurable area, and determining a reconfiguration module corresponding to each operating task;

[0030] Determine a target reconstruction module with the largest resource demand in at least one reconstruction module, and determine a target resource demand corresponding to the target reconstruction module;

[0031] Determine the area range that matches the target resource demand, and configure the reconfigurable area according to the area range.

[0032] Optionally, reconfiguring the programmable logic portion based on the target reconfiguration program includes:

[0033] The storage address and data size associated with the hardware reconstruction program in the target memory are configured to the programmable logic part of the embedded system chip through the hardware interface standard AXIDMA bus of data transmission and the PCAP interface, so that the programmable logic part executes the hardware reconstruction program for reconstruction.

[0034] According to a second aspect of the present application, a satellite-borne aircraft fault handling system is provided, the system comprising: an embedded system chip, a monitoring module, and a target memory;

[0035] An embedded system chip, used for responding to a reconstruction instruction, loading a plurality of pre-configured reconstruction programs into a target memory, and determining a target reconstruction program, and reconstructing a program processing system part and / or a programmable logic part based on the target reconstruction program, wherein the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring a storage address and a data size associated with the hardware reconstruction program to the programmable logic part, and detecting an output signal of the programmable logic part, and when it is detected that the output signal is higher than a preset value, the reconstruction of the onboard computer is completed, and the output signal is a state signal DONE signal output by the programmable logic part;

[0036] A monitoring module, used for generating a reconstruction instruction according to fault information associated with the embedded system chip or according to task conversion information uploaded by the ground control terminal and transmitting the reconstruction instruction to the embedded system chip;

[0037] The target memory is used to store a plurality of pre-configured reconstruction programs.

[0038] Optionally, the embedded system chip is used to control the program processing system part to call multiple reconstruction programs stored in the off-chip program memory Flash based on the reconstruction task scheduling module; perform data verification on the reconstruction program based on the program processing system part to generate a verification result; when the verification result indicates that the verification is passed, the multiple reconstruction programs are loaded into the target memory based on the program processing system part, wherein the program processing system part includes a reconstruction task scheduling module, an ARM task reconstruction module and a remote reconstruction module.

[0039] Optionally, the embedded system chip is also used to initiate a remote reconstruction request to the ground control terminal when the verification result indicates a verification abnormality, and receive a reconstruction program transmitted by the ground control terminal based on the remote reconstruction module, and the reconstruction program is transmitted by the ground control terminal via Ethernet; based on the remote reconstruction module, the reconstruction program is stored in the Flash using a triple-module redundant storage method.

[0040] Optionally, an embedded system chip is used to construct a top-level module for a programmable logic part, and to construct at least one reconstruction module for the programmable logic part according to at least one running task, each reconstruction module being associated with one running task; determining a first hardware description language associated with the top-level module and a second hardware description language associated with each reconstruction module, performing syntax detection and rule detection on the first hardware description language and each second hardware description language, and generating syntax detection results and rule detection results, wherein the first hardware description language and each second hardware description language are both written based on the Verilog module; when both the syntax detection results and the rule detection results indicate that the detection has passed, setting physical constraints for the programmable logic part, the physical constraints including but not limited to clock constraints and pin constraints; compiling and solidifying the programmable logic part, and initializing the embedded system chip when the embedded system chip is powered on, the initialization is to read the global reconstruction program solidified in the Flash to the target memory, initialize the program processing system part of the embedded system chip by running the global reconstruction program in the target memory, and initialize the programmable logic part by configuring the storage address and data size associated with the global reconstruction program of the target memory to the programmable logic part of the embedded system chip.

[0041] Optionally, an embedded system chip is used to divide the programmable logic part into at least one reconfigurable area, determine the area range of each reconfigurable area, and layout and route the top-level module and each reconstruction module; determine a global reconstruction program based on a first hardware description language, and determine a reconstruction program corresponding to each reconstruction module based on each second hardware description language; solidify the global reconstruction program in an off-chip program memory Flash, and store each reconstruction program as a pre-configured reconstruction program in an off-chip program memory Flash and / or an SD card memory.

[0042] Optionally, the embedded system chip is used to determine, for any reconfigurable area, at least one operating task performed by the reconfigurable area, and determine a reconstruction module corresponding to each operating task; determine a target reconstruction module with the largest resource demand in at least one reconstruction module, and determine a target resource demand corresponding to the target reconstruction module; determine an area range that matches the target resource demand, and configure the reconfigurable area according to the area range.

[0043] Optionally, the embedded system chip is used to configure the storage address and data size associated with the hardware reconstruction program in the target memory to the programmable logic part of the embedded system chip through the hardware interface standard AXIDMA bus for data transmission and the PCAP interface, so that the programmable logic part executes the hardware reconstruction program for reconstruction.

[0044] According to a third aspect of the present application, a computer device is provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the methods described in the first aspect when executing the computer program.

[0045] According to a fourth aspect of the present application, a readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the methods described in the first aspect are implemented.

[0046] By means of the above technical scheme, the present application provides a method, system, computer device and readable storage medium for handling faults of a satellite-borne machine. The present application is applicable to an embedded system chip of a satellite-borne computer. The embedded system chip includes a program processing system part and a programmable logic part. The embedded system chip first responds to a reconstruction instruction and loads a plurality of pre-configured reconstruction programs into a target memory based on the program processing system part. The reconstruction instruction is generated by the monitoring module of the satellite-borne computer according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal. Further, a target reconstruction program is determined, and the program processing system part and / or the programmable logic part are reconstructed based on the target reconstruction program. The target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part. Next, the output signal of the programmable logic part is detected, and the output signal is a state signal DONE signal output by the programmable logic part. Finally, when it is detected that the output signal is higher than the preset value, the reconstruction of the satellite-borne computer is completed. The embodiment of the present application uses a dynamic reconstruction mechanism based on reconstruction instructions. The onboard computer can reconstruct the program processing system part and the programmable logic part of the embedded system chip in real time according to the fault information generated by the monitoring module or the task conversion information uploaded by the ground control terminal. This dynamic reconstruction capability significantly improves the reliability and fault tolerance of the system. In addition, the hardware reconstruction program in the embodiment of the present application allows on-orbit reconstruction, which can correct errors caused by single particle events (SEU), which not only improves the on-orbit operation fault tolerance rate, but also enhances the system's self-repair ability, thereby improving the overall performance and task execution capability of the onboard computer.

[0047] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0049] Figure 1 A schematic diagram of a method for handling a satellite-borne aircraft fault provided in an embodiment of the present application is shown;

[0050] Figure 2 A schematic diagram showing the overall architecture of a software system of a method for handling a satellite-borne aircraft fault provided in an embodiment of the present application is shown;

[0051] Figure 3 A schematic diagram of a system reconstruction development framework of a method for handling a satellite-borne aircraft fault provided in an embodiment of the present application is shown;

[0052] Figure 4 A schematic diagram of a method for handling a satellite-borne aircraft fault provided in an embodiment of the present application is shown;

[0053] Figure 5 A schematic diagram of the structure of a satellite-borne aircraft fault handling device provided in an embodiment of the present application is shown;

[0054] Figure 6 A schematic diagram of the device structure of a computer device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0055] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0056] With the advancement of aerospace technology, micro-satellites need to achieve diversified tasks, which requires their onboard aircraft, that is, onboard computers, to be more flexible and able to match functions to tasks. And it has scalability and can expand the system for changing mission requirements. At the same time, considering that the onboard aircraft is in a high-radiation environment, single-particle radiation effects will occur, causing device abnormalities or even damage, which requires the onboard computer to have error detection and fault tolerance capabilities. At present, onboard aircraft generally adopt a redundant backup architecture design containing multiple devices. Through this multi-device redundant backup strategy, the risk of single point failure can be effectively reduced, thereby ensuring that the onboard aircraft can still maintain the normal execution of its functions under extreme environments, such as vacuum, radiation, temperature fluctuations and other harsh conditions in space. However, the applicant recognizes that although multi-device redundant backup improves reliability, it also increases the complexity and cost of the system. At the same time, due to the increase in the number of devices, the weight and power consumption of the system also increase. In addition, in the face of some unexpected failure modes, the multi-device redundant backup architecture cannot completely avoid the failure of the onboard aircraft system, resulting in the inability of the onboard aircraft system to continue to perform the mission. Therefore, the present application provides a method for handling faults of a satellite-borne machine, which is applicable to an embedded system chip of a satellite-borne computer, wherein the embedded system chip includes a program processing system part and a programmable logic part, and the embedded system chip first responds to a reconstruction instruction, and based on the program processing system part, loads a plurality of pre-configured reconstruction programs into a target memory. Wherein, the reconstruction instruction is generated by the monitoring module of the satellite-borne computer according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal. Further, a target reconstruction program is determined, and the program processing system part and / or the programmable logic part are reconstructed based on the target reconstruction program, and the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part. Next, the output signal of the programmable logic part is detected, and the output signal is a state signal DONE signal output by the programmable logic part. Finally, when it is detected that the output signal is higher than the preset value, the reconstruction of the satellite-borne computer is completed. The embodiment of the present application uses a dynamic reconstruction mechanism based on reconstruction instructions. The onboard computer can reconstruct the program processing system part and the programmable logic part of the embedded system chip in real time according to the fault information generated by the monitoring module or the task conversion information uploaded by the ground control terminal. This dynamic reconstruction capability significantly improves the reliability and fault tolerance of the system. In addition, the hardware reconstruction program in the embodiment of the present application allows on-orbit reconstruction, which can correct errors caused by single particle events (SEU), which not only improves the on-orbit operation fault tolerance rate, but also enhances the system's self-repair ability, thereby improving the overall performance and task execution capability of the onboard computer.

[0057] The present application embodiment provides a method for handling a satellite-borne aircraft failure, such as Figure 1 As shown, the method includes:

[0058] S10. In response to a reconstruction instruction, based on the program processing system part, multiple pre-configured reconstruction programs are loaded into the target memory, and the reconstruction instruction is generated by the monitoring module of the onboard computer according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal.

[0059] Onboard computers are embedded systems that are usually composed of microprocessors, storage, communication, acquisition, instructions, power distribution and other modules. Onboard computers are the "central nervous system" of satellites, and are mainly responsible for managing onboard data, communications, energy, attitude and orbit control, payloads, etc. In recent years, the space missions of microsatellites have become increasingly complex, and the requirements for the performance and reliability of onboard computers have become increasingly high.

[0060] Microsatellites have been widely used in important fields such as scientific research, observation, and military. Microsatellites have the advantages of low cost, fast launch speed, and high integration, but the traditional design method of onboard computer systems has the following limitations. First, after the system is completed, the function is limited, the functional mode is single, and it is difficult to repair damage. Secondly, the system is a tightly coupled architecture between software and hardware. The hardware logic cannot be changed, and the software is difficult to update based on fixed hardware. Finally, to increase the life of the system, it is necessary to use a multi-mode redundant mode or use expensive aerospace-grade components. Although this can improve the reliability of the system, the cost is very high.

[0061] In the embodiment of the present application, a general scheme for developing a reconfigurable onboard computer software system is provided. The overall architecture of the software system is as follows: Figure 2 As shown, it includes the operating system layer (device layer) as the bottom support, the intermediate adaptation driver layer and framework library layer (middle layer), and the top application layer. The main functions of the software system are reconstruction software development and embedded system development and transplantation. Among them, the embedded system realizes the efficient utilization of satellite system resources and reconstruction task scheduling by transplanting embedded operating systems and designing corresponding driver functions. Reconstruction software development is based on ARM's software reconfiguration and dynamic reconstruction based on programmable hardware logic resources, providing solutions and technical support for on-orbit fault repair and on-orbit software updates of satellite-borne aircraft. Reconstruction software development, that is, the reconstruction development framework of the satellite-borne aircraft fault handling system is as shown Figure 3As shown in the figure, the onboard fault handling system is based on the ZYNQ embedded system chip, monitoring module, off-chip program memory Flash and target memory DDR. The full name of ZYNQ is Zynq-7000 All Programmable SoC (System on Chip). ZYNQ integrates the ARM Cortex-A9 dual-core processor, that is, the PS (Processing System) part and a programmable logic PL (Programmable Logic) part. The programmable logic part is implemented based on FPGA (Field-Programmable Gate Array) technology. The monitoring module controls the reconstruction enable, and the PS part of ZYNQ performs the reconstruction operation through the reconstruction task scheduling module. When reconstructing, the PS part calls the reconstruction program stored in the off-chip program memory Flash, and after data verification, the program is loaded into the DDR. During software reconstruction, the program in the DDR can be directly loaded and run. During hardware reconstruction, the program in the DDR needs to be read out and configured to the PL part through the AXIDMA bus and PCAP interface. The remote reconstruction process uses Ethernet communication to transfer the program from the ground to the onboard computer. ZYNQ stores the program in off-chip Flash through triple-mode redundancy in preparation for reconstruction calls.

[0062] In the specific implementation process, the reconstruction instruction indicates the reconstruction type and the corresponding reconstruction program. The reconstruction type includes software reconstruction, that is, the reconstruction of the PS part, and hardware reconstruction, that is, the reconstruction of the PL part. In the actual operation process, the monitoring module can generate a reconstruction instruction based on the fault information associated with the embedded system chip or based on the task conversion information uploaded by the ground control terminal. Specifically, it can be used as

[0063] The monitoring module of the onboard computer is generated according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal. That is to say, the monitoring module continuously monitors the operating status of the onboard computer. Once the fault information is received, it will immediately analyze the fault point and determine the area to be reconstructed that needs to be reconstructed. The area to be reconstructed is associated with at least one operating task. For each operating task, the reconstruction program associated with the operating task is determined, and the reconstruction instruction is generated according to at least one reconstruction program, reconstruction type and / or area to be reconstructed. The monitoring module quickly responds to the fault information by monitoring the operating status of the onboard computer in real time, and realizes the precise positioning of the fault point. This instant response mechanism improves the reliability and fault recovery speed of the system. Similarly, when the onboard computer receives the on-orbit task switching instruction through Ethernet, the monitoring module reads the task conversion information in these instructions, and determines the operating task to be reconstructed and the reconstruction program corresponding to the operating task according to this information, and determines the corresponding area to be reconstructed, and generates the reconstruction instruction according to the reconstruction program, reconstruction type and area to be reconstructed. In this way, the monitoring module can flexibly adjust the task configuration of the onboard computer to adapt to different task requirements, thereby enhancing the versatility and task adaptability of the onboard computer.

[0064] Further, in response to the reconstruction instruction, the embedded system chip ZYNQ will start its internal program processing system part, which includes a reconstruction task scheduling module, an ARM task reconstruction module and a remote reconstruction module. The reconstruction task scheduling module of the program processing system calls multiple reconstruction programs pre-stored in the off-chip program memory Flash. After calling the reconstruction program, the program processing system part will perform a data verification process. This process involves checking the data integrity of the reconstruction program to ensure that the program is complete and correct before being loaded into the system. After the verification is completed, the system will generate a verification result. If the verification result shows that the reconstruction program has passed the data verification, the program processing system part will perform the next step, that is, load these reconstruction programs into the target memory. On the contrary, if the verification result shows that there is a verification anomaly, that is, a problem with the reconstruction program is found during the data verification process, such as damage. Then the program processing system part will initiate a remote reconstruction request to the ground control terminal, requesting the ground control terminal to provide assistance. After receiving the request, the ground control terminal will transmit the correct reconstruction program to the embedded system via Ethernet. Once these programs are received, the remote reconstruction module will be responsible for receiving and processing these data. Finally, the remote reconstruction module will use a triple-module redundant storage method to safely store the received reconstruction program in the Flash to ensure the stability and reliability of the system. The triple-module redundant storage method means that key data or programs will be copied to three independent storage modules to ensure data integrity and consistency and reduce the risk of data damage or loss.

[0065] S20. Determine a target reconstruction program, and reconstruct the program processing system part and / or the programmable logic part based on the target reconstruction program, wherein the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by a reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part.

[0066] In this step, the target reconstruction program indicated by the reconstruction instruction is read, wherein the target reconstruction program may be one or more, and the category of the reconstruction program may be a software reconstruction program and / or a hardware reconstruction program. It should be noted that the software reconstruction program is a bitstream configuration file for reconstructing the PS part, and the hardware reconstruction program is a bitstream configuration file for reconstructing the reconfigurable area of ​​the PL. The reconstruction of the PS part can be performed by directly running the software reconstruction program stored in the target memory DDR. For the reconstruction of the PL part, it is necessary to configure the storage address and data size associated with the hardware reconstruction program to the programmable logic part through the hardware interface standard AXIDMA bus for data transmission and the PCAP interface to realize the reconstruction of the programmable logic part.

[0067] S30, detecting an output signal of the programmable logic part, where the output signal is a state signal DONE signal output by the programmable logic part.

[0068] S40: When it is detected that the output signal is higher than a preset value, the onboard computer is reconfigured.

[0069] In steps S30 and S40, in order to determine whether the reconstruction process is successfully completed, it is necessary to detect the output signal of the programmable logic part, that is, the state signal DONE signal. Determine the level value of the output signal and compare the level value with the preset value. When it is detected that the level value is higher than the preset value, it means that the reconstruction process has ended. At this time, the reconstructed running task can be tested to determine the reconstruction result. At the same time, when it is detected that the level value is not higher than the preset value, it means that the reconstruction process is not over. At this time, the level value of the output signal can be continuously detected until the detection time reaches the preset duration, and then a fault information is generated to the monitoring module so that the monitoring module regenerates the reconstruction instruction according to the fault information. The fault information indicates the reconstruction type, reconstruction program and / or reconstruction area. This process is a key step in the automated detection process, which ensures that the onboard computer can be quickly and accurately reconstructed when necessary, thereby ensuring the smooth progress of the entire space mission.

[0070] Further, as a refinement and expansion of the specific implementation of the above embodiment, in order to fully illustrate the implementation process of this embodiment, a method for handling a satellite-borne aircraft failure is provided, such as Figure 4 As shown, the method includes:

[0071] Before waiting for the reconstruction instruction, the programmable logic part inside the embedded system chip is dynamically reconfigured. First, in the logic design stage, a top-level TOP module is built for the programmable logic part. The top-level module includes static logic and dynamic logic. Among them, the static module corresponding to the static logic remains unchanged and is responsible for the overall logic control and state preservation. During the operation of the dynamic logic, according to the actual task requirements, a corresponding reconfigurable module (Reconfigurable Module, RM) is designed for each running task. Each RM will generate a corresponding partial reconstruction configuration file, and reconstruction can be achieved by loading the partial reconstruction configuration file. The first hardware description language associated with the top-level module and the second hardware description language associated with each reconstruction module are written based on the Verilog module.

[0072] Next, during the compilation and curing stage, the first hardware description language and each second hardware description language are subjected to syntax detection and rule detection, and syntax detection results and rule detection results are generated. When both the syntax detection results and the rule detection results indicate that the detection is passed, physical constraints are set for the programmable logic part, wherein the physical constraints include but are not limited to clock constraints and pin constraints. Next, the programmable logic part is compiled and cured, and at least one reconfigurable area is divided for the programmable logic part, and the area range of each reconfigurable area is determined. After the area is dynamically reconfigured, its size, internal resources, and location will not change with operation. For any reconfigurable area, at least one operation task executed by the reconfigurable area is determined, and the reconstruction module corresponding to each operation task is determined. The target reconstruction module with the largest resource demand is determined in at least one reconstruction module, and the target resource demand corresponding to the target reconstruction module is determined. The area range that matches the target resource demand is determined, and the reconfigurable area is configured according to the area range. The range must be delimited according to the RM of the maximum resource required for the area, otherwise the reconstruction will fail due to insufficient resources. Further, the top module and each reconstruction module are placed and routed. In the reconfigurable design process of onboard computers, layout and routing of the top-level module and each reconfiguration module is a crucial step, which involves mapping the logic units in the design to the physical location of the FPGA chip (layout) and determining the electrical connection paths between these units (wiring). The goal of this process is to optimize the physical layout of the logic units to reduce signal delays and improve performance. At the same time, routing needs to find the shortest path to connect the logic units on the basis of meeting the electrical characteristics and signal integrity requirements, reduce signal delays and crossovers, and avoid signal interference and reflection. Through layout and routing, the system's operating speed can be improved, resource utilization efficiency can be increased, signal integrity can be ensured, power consumption can be reduced, and design errors can be reduced. These technical effects together ensure the high performance, high reliability and adaptability of onboard computers in the space environment, enabling them to flexibly adapt to different mission requirements and achieve fault recovery and performance optimization.

[0073] Furthermore, in the initialization configuration stage, when the embedded system chip is powered on, the embedded system chip is initialized, and the initialization is to read the global reconstruction program solidified in the Flash to the target memory, and the program processing system part of the embedded system chip is initialized by running the global reconstruction program in the target memory, and the programmable logic part is initialized by configuring the storage address and data size associated with the global reconstruction program of the target memory to the programmable logic part of the embedded system chip. The global reconstruction program is determined based on the first hardware description language, and the reconstruction program corresponding to each reconstruction module is determined based on each second hardware description language. The global reconstruction program is solidified in the off-chip program memory Flash, and each reconstruction program is stored as a pre-configured reconstruction program in the off-chip program memory Flash and / or in the SD card memory so that it can be read and configured when needed.

[0074] The method provided in the embodiment of the present application is applicable to the embedded system chip of the onboard computer. The embedded system chip includes a program processing system part and a programmable logic part. The embedded system chip first responds to the reconstruction instruction and loads a plurality of pre-configured reconstruction programs into the target memory based on the program processing system part. The reconstruction instruction is generated by the monitoring module of the onboard computer according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal. Further, the target reconstruction program is determined, and the program processing system part and / or the programmable logic part are reconstructed based on the target reconstruction program. The target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the reconstruction of the program processing system part is realized by running the software reconstruction program, and the reconstruction of the programmable logic part is realized by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part. Next, the output signal of the programmable logic part is detected, and the output signal is a state signal DONE signal output by the programmable logic part. Finally, when it is detected that the output signal is higher than the preset value, the reconstruction of the onboard computer is completed. The embodiment of the present application uses a dynamic reconstruction mechanism based on reconstruction instructions. The onboard computer can reconstruct the program processing system part and the programmable logic part of the embedded system chip in real time according to the fault information generated by the monitoring module or the task conversion information uploaded by the ground control terminal. This dynamic reconstruction capability significantly improves the reliability and fault tolerance of the system. In addition, the hardware reconstruction program in the embodiment of the present application allows on-orbit reconstruction, which can correct errors caused by single particle events (SEU), which not only improves the on-orbit operation fault tolerance rate, but also enhances the system's self-repair ability, thereby improving the overall performance and task execution capability of the onboard computer.

[0075] Further, as Figure 1In a specific implementation of the method, the present application provides a satellite-borne aircraft fault processing system, such as Figure 5 As shown, the system includes: an embedded system chip 501, a monitoring module 502, and a target memory 503;

[0076] The embedded system chip 501 is used to load a plurality of pre-configured reconstruction programs into a target memory in response to a reconstruction instruction, and to determine a target reconstruction program, and to reconstruct a program processing system part and / or a programmable logic part based on the target reconstruction program, wherein the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring a storage address and a data size associated with the hardware reconstruction program to the programmable logic part, and an output signal of the programmable logic part is detected, and when it is detected that the output signal is higher than a preset value, the reconstruction of the onboard computer is completed, and the output signal is a state signal DONE signal output by the programmable logic part;

[0077] The monitoring module 502 is used to generate a reconstruction instruction according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal and transmit it to the embedded system chip;

[0078] The target memory 503 is used to store a plurality of pre-configured reconstruction programs.

[0079] Optionally, the embedded system chip 501 is used to control the program processing system part to call multiple reconstruction programs stored in the off-chip program memory Flash based on the reconstruction task scheduling module; perform data verification on the reconstruction program based on the program processing system part to generate a verification result; when the verification result indicates that the verification is passed, the multiple reconstruction programs are loaded into the target memory based on the program processing system part, wherein the program processing system part includes a reconstruction task scheduling module, an ARM task reconstruction module and a remote reconstruction module.

[0080] Optionally, the embedded system chip 501 is also used to initiate a remote reconstruction request to the ground control terminal when the verification result indicates a verification abnormality, and receive a reconstruction program transmitted by the ground control terminal based on the remote reconstruction module, and the reconstruction program is transmitted by the ground control terminal via Ethernet; based on the remote reconstruction module, a triple-module redundant storage method is used to store the reconstruction program in Flash.

[0081] Optionally, the embedded system chip 501 is used to construct a top-level module for the programmable logic part, and to construct at least one reconstruction module for the programmable logic part according to at least one running task, each reconstruction module being associated with one running task; determining a first hardware description language associated with the top-level module and a second hardware description language associated with each reconstruction module, performing syntax detection and rule detection on the first hardware description language and each second hardware description language, and generating syntax detection results and rule detection results, wherein the first hardware description language and each second hardware description language are both written based on the Verilog module; when the syntax detection results and the rule detection results both indicate that the detection has passed, setting physical constraints for the programmable logic part, the physical constraints including but not limited to clock constraints and pin constraints; compiling and solidifying the programmable logic part, and initializing the embedded system chip when the embedded system chip is powered on, the initialization is to read the global reconstruction program solidified in the Flash to the target memory, initialize the program processing system part of the embedded system chip by running the global reconstruction program in the target memory, and initialize the programmable logic part by configuring the storage address and data size associated with the global reconstruction program of the target memory to the programmable logic part of the embedded system chip.

[0082] Optionally, the embedded system chip 501 is used to divide the programmable logic part into at least one reconfigurable area, determine the area range of each reconfigurable area, and layout and route the top-level module and each reconstruction module; determine a global reconstruction program based on a first hardware description language, and determine a reconstruction program corresponding to each reconstruction module based on each second hardware description language; solidify the global reconstruction program in an off-chip program memory Flash, and store each reconstruction program as a pre-configured reconstruction program in an off-chip program memory Flash and / or an SD card memory.

[0083] Optionally, the embedded system chip 501 is used to determine, for any reconfigurable area, at least one operating task performed by the reconfigurable area, and determine a reconstruction module corresponding to each operating task; determine a target reconstruction module with the largest resource demand in at least one reconstruction module, and determine a target resource demand corresponding to the target reconstruction module; determine an area range that matches the target resource demand, and configure the reconfigurable area according to the area range.

[0084] Optionally, the embedded system chip 501 is used to configure the storage address and data size associated with the hardware reconstruction program in the target memory to the programmable logic part of the embedded system chip through the hardware interface standard AXIDMA bus for data transmission and the PCAP interface, so that the programmable logic part executes the hardware reconstruction program for reconstruction.

[0085] The device provided in the embodiment of the present application is applicable to the embedded system chip of the onboard computer. The embedded system chip includes a program processing system part and a programmable logic part. The embedded system chip first responds to the reconstruction instruction and loads a plurality of pre-configured reconstruction programs into the target memory based on the program processing system part. The reconstruction instruction is generated by the monitoring module of the onboard computer according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal. Further, the target reconstruction program is determined, and the program processing system part and / or the programmable logic part are reconstructed based on the target reconstruction program. The target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part. Next, the output signal of the programmable logic part is detected, and the output signal is a state signal DONE signal output by the programmable logic part. Finally, when it is detected that the output signal is higher than the preset value, the reconstruction of the onboard computer is completed. The embodiment of the present application uses a dynamic reconstruction mechanism based on reconstruction instructions. The onboard computer can reconstruct the program processing system part and the programmable logic part of the embedded system chip in real time according to the fault information generated by the monitoring module or the task conversion information uploaded by the ground control terminal. This dynamic reconstruction capability significantly improves the reliability and fault tolerance of the system. In addition, the hardware reconstruction program in the embodiment of the present application allows on-orbit reconstruction, which can correct errors caused by single particle events (SEU), which not only improves the on-orbit operation fault tolerance rate, but also enhances the system's self-repair ability, thereby improving the overall performance and task execution capability of the onboard computer.

[0086] It should be noted that for other corresponding descriptions of the functional units involved in the onboard aircraft fault handling device provided in the embodiment of the present application, reference can be made to Figure 1 and Figure 4 The corresponding description in will not be repeated here.

[0087] In an exemplary embodiment, see Figure 6 , and also provides a device, which includes a communication bus, a processor, a memory and a communication interface, and may also include an input and output interface and a display device, wherein each functional unit can communicate with each other through the bus. The memory stores a computer program, and the processor is used to execute the program stored in the memory and execute the satellite-borne aircraft fault handling method in the above embodiment.

[0088] A computer-readable storage medium stores a computer program, which implements the steps of the onboard aircraft fault handling method when executed by a processor.

[0089] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by hardware, or by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each implementation scenario of the present application.

[0090] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of a preferred implementation scenario, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present application.

[0091] Those skilled in the art will appreciate that the modules in the device in the implementation scenario can be distributed in the device in the implementation scenario according to the implementation scenario description, or can be changed accordingly and located in one or more devices different from the implementation scenario. The modules in the above implementation scenario can be combined into one module, or can be further split into multiple sub-modules.

[0092] The above application serial numbers are for description only and do not represent the advantages or disadvantages of the implementation scenarios.

[0093] The above disclosure only discloses several specific implementation scenarios of the present application. However, the present application is not limited thereto, and any changes that can be conceived by technicians in this field should fall within the scope of protection of the present application.

Claims

1. A method for handling a satellite-borne aircraft fault, characterized in that: The method is applicable to an embedded system chip of a satellite-borne computer, wherein the embedded system chip comprises a program processing system part and a programmable logic part, including: In response to a reconstruction instruction, based on the program processing system part, a plurality of pre-configured reconstruction programs are loaded into the target memory, wherein the reconstruction instruction is generated by the monitoring module of the onboard computer according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal; Determine a target reconstruction program, and reconstruct the program processing system part and / or the programmable logic part based on the target reconstruction program, wherein the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part; Detecting an output signal of the programmable logic part, wherein the output signal is a state signal DONE signal output by the programmable logic part; When it is detected that the output signal is higher than a preset value, the reconstruction of the onboard computer is completed.

2. The method according to claim 1, characterized in that The method of loading a plurality of pre-configured reconstruction programs into a target memory based on the program processing system part includes: Based on the reconstruction task scheduling module, the program processing system part of the embedded system chip is controlled to call the multiple reconstruction programs stored in the off-chip program memory Flash; Performing data verification on the reconstructed program based on the program processing system part to generate a verification result; When the verification result indicates that the verification is passed, the multiple reconstruction programs are loaded into the target memory based on the program processing system part, wherein the program processing system part includes the reconstruction task scheduling module, the ARM task reconstruction module and the remote reconstruction module.

3. The method according to claim 2, characterized in that After performing data verification on the reconstructed program based on the program processing system part and generating a verification result, the method further includes: When the verification result indicates a verification abnormality, a remote reconstruction request is initiated to the ground control terminal, and a reconstruction program transmitted by the ground control terminal is received based on the remote reconstruction module, where the reconstruction program is transmitted by the ground control terminal via Ethernet; Based on the remote reconstruction module, the reconstruction program is stored in the Flash using a triple-module redundant storage method.

4. The method according to claim 1, characterized in that: In response to the reconstruction instruction, based on the program processing system part, before loading a plurality of pre-configured reconstruction programs into the target memory, the method further comprises: Constructing a top-level module for the programmable logic part, and constructing at least one reconfiguration module for the programmable logic part according to at least one running task, each of the reconfiguration modules being associated with one running task; Determine a first hardware description language associated with the top-level module and a second hardware description language associated with each of the reconstruction modules, perform syntax detection and rule detection on the first hardware description language and each of the second hardware description languages, and generate syntax detection results and rule detection results, wherein the first hardware description language and each of the second hardware description languages ​​are both written based on the Verilog module; When both the syntax detection result and the rule detection result indicate that the detection is passed, setting physical constraints for the programmable logic part, wherein the physical constraints include but are not limited to clock constraints and pin constraints; The programmable logic part is compiled and solidified, and the embedded system chip is initialized when the embedded system chip is powered on. The initialization is to read the global reconstruction program solidified in the Flash to the target memory, initialize the program processing system part of the embedded system chip by running the global reconstruction program in the target memory, and initialize the programmable logic part by configuring the storage address and data size associated with the global reconstruction program of the target memory to the programmable logic part of the embedded system chip.

5. The method according to claim 1, characterized in that The compiling and curing operations on the programmable logic part include: Divide the programmable logic part into at least one reconfigurable area, determine the area range of each reconfigurable area, and perform layout and routing on the top-level module and each reconfigurable module; Determine a global reconstruction program based on the first hardware description language, and determine a reconstruction program corresponding to each reconstruction module based on each of the second hardware description languages; The global reconstruction program is solidified in the off-chip program memory Flash, and each of the reconstruction programs is stored in the off-chip program memory Flash and / or in the SD card memory as the pre-configured reconstruction program.

6. The method according to claim 5, characterized in that The determining the area range of each of the reconfigurable areas comprises: For any reconfigurable area, determining at least one operating task executed by the reconfigurable area, and determining a reconfiguration module corresponding to each operating task; Determine a target reconstruction module with the largest resource demand in at least one of the reconstruction modules, and determine a target resource demand corresponding to the target reconstruction module; An area range matching the target resource demand is determined, and the reconfigurable area is configured according to the area range.

7. The method according to claim 1, characterized in that The reconstructing the programmable logic part based on the target reconstructing program comprises: The storage address and data size associated with the hardware reconstruction program in the target memory are configured to the programmable logic part of the embedded system chip through the hardware interface standard AXIDMA bus for data transmission and the PCAP interface, so that the programmable logic part executes the hardware reconstruction program for reconstruction.

8. A satellite-borne aircraft fault handling system, characterized in that: include: Embedded system chip, monitoring module, target memory; The embedded system chip is used to load a plurality of pre-configured reconstruction programs into the target memory in response to a reconstruction instruction, and determine a target reconstruction program, and reconstruct the program processing system part and / or the programmable logic part based on the target reconstruction program, wherein the target reconstruction program is a software reconstruction program and / or a hardware reconstruction program indicated by the reconstruction instruction, wherein the program processing system part is reconstructed by running the software reconstruction program, and the programmable logic part is reconstructed by configuring the storage address and data size associated with the hardware reconstruction program to the programmable logic part, and the output signal of the programmable logic part is detected, and when it is detected that the output signal is higher than a preset value, the reconstruction of the onboard computer is completed, and the output signal is a state signal DONE signal output by the programmable logic part; The monitoring module is used to generate a reconstruction instruction according to the fault information associated with the embedded system chip or according to the task conversion information uploaded by the ground control terminal and transmit it to the embedded system chip; The target memory is used to store the pre-configured multiple reconstruction programs.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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