Method and system for reducing efficiency calculation time

Abstract

The invention provides a method and a system for reducing performance calculation time, which are used for converting a waveform record file of a bus framework into performance analysis data so as to carry out transmission performance analysis. The method for reducing the performance calculation time comprises the following steps of: reading a waveform record file, wherein the waveform record file comprises a plurality of pieces of waveform signal information; capturing part of waveform signal information from the waveform recording file; the partial waveform signal information is mapped to a plurality of pieces of transmission signal information of the connection port to generate a mapped waveform recording file. A plurality of time stamps for each of the connection ports are defined according to a specified voltage level of the transmission signal information. And integrating the mapped waveform recording file with the time stamp to generate performance analysis data. Therefore, the amount of data required to be calculated in the performance analysis process is reduced, and the calculation time is further shortened.

Description

Technical Field

[0001] The present invention relates to a method and system for reducing computing time, and more particularly to a method and system for reducing performance computing time. Background Art

[0002] As the performance and functions of current System On a Chip (SOC) are improved, the circuit complexity is also increased, and data transmission across nodes and different buses is becoming more and more common. Conventional performance analysis methods access waveform record files for performance analysis. However, waveform record files record the waveforms and signal changes of all nodes in the SOC, and the amount of data is very large. Therefore, reading the waveform signal of each node from the waveform record file and obtaining the amount of data transmitted between nodes, transmission time, transmission start time and transmission end time requires a lot of computing time and a processor with better performance to perform calculations in order to calculate the transmission performance.

[0003] It can be seen that there is currently a lack of a method and system in the market that can reduce the amount of computing data and shorten the performance computing time, so relevant industry players are all looking for solutions. Summary of the invention

[0004] Therefore, the purpose of the present invention is to provide a method and system for reducing performance calculation time, which captures waveform signal information corresponding to a specified list in a waveform record file, maps the aforementioned waveform signal information, and obtains the timestamp of the connection port to perform performance calculation.

[0005] According to an embodiment of the method aspect of the present invention, a method for reducing performance calculation time is provided, which is used to convert a waveform record file of a bus architecture into performance analysis data to perform a transmission performance analysis of a transmission instruction. The method for reducing performance calculation time includes: reading a waveform record file in a database by a processor, wherein the waveform record file includes a plurality of waveform signal information corresponding to the bus architecture. Extracting a portion of these waveform signal information corresponding to a specified list from the waveform record file by the processor, wherein the specified list corresponds to a plurality of nodes of the bus architecture. Mapping a portion of these waveform signal information to a plurality of transmission signal information of a plurality of connection ports by the processor to generate a mapped waveform record file, wherein any one of these connection ports is used to connect two of these nodes. Defining a plurality of time stamps of each of these connection ports according to a specified voltage level of each of these transmission signal information by the processor. Integrating the mapped waveform record file with these time stamps by the processor to generate performance analysis data.

[0006] Thus, the method for reducing performance calculation time of the present invention can precisely calculate the state of each time stamp during data transmission, thereby finding out the section with abnormal transmission speed and effectively eliminating the abnormal problem.

[0007] Other examples of the aforementioned implementation are as follows: the aforementioned waveform record file may include one of an IEEE 1364 standard waveform (Value Change Dump; VCD) file, a Fast Signal Data Base (FSDB) file, and a signal change (SignalValue) file.

[0008] Other embodiments of the aforementioned implementation are as follows: When one of the aforementioned nodes initiates data transmission to another of the aforementioned nodes, the timestamps of one of the connection ports between the one of the aforementioned nodes and the other of the aforementioned nodes may include a first timestamp, a second timestamp, a third timestamp, a fourth timestamp, and a fifth timestamp. The first timestamp corresponds to a time point when the one of the aforementioned nodes initiates an address communication request. The second timestamp corresponds to a time point when the other of the aforementioned nodes replies to the address communication request. The third timestamp corresponds to a time point when the one of the aforementioned nodes transmits a piece of data. The fourth timestamp corresponds to a time point when the other of the aforementioned nodes receives the piece of data. The fifth timestamp corresponds to a time point when the data transmission is completed.

[0009] Other embodiments of the aforementioned implementation are as follows: the aforementioned timestamps may further include a sixth timestamp and a seventh timestamp. The sixth timestamp corresponds to a time point when another of the nodes requests to establish a reply channel. The seventh timestamp corresponds to a time point when one of the nodes receives a request to complete the establishment of the reply channel.

[0010] Other embodiments of the aforementioned implementation are as follows: the aforementioned method for reducing performance calculation time may further include calculating, by a processor, a transmission performance of the nodes of the bus architecture according to the timestamps of each of the connection ports.

[0011] Other examples of the aforementioned implementation are as follows: The aforementioned method for reducing performance calculation time may further include generating a performance abnormality warning message by a processor when the transmission performance does not meet a preset value.

[0012] Other embodiments of the aforementioned implementation are as follows: The aforementioned method for reducing performance calculation time may further include: converting the performance analysis data into a transmission record table by a processor, wherein the transmission record table includes a connection port code, a time value, one of the time stamps, a destination node, and a transmission data volume corresponding to each of the plurality of data transmission behaviors between the plurality of nodes. The processor stores the plurality of data transmission behaviors into a plurality of queues according to the time stamps corresponding to each data transmission behavior, and takes out one of the partial data transmission behaviors in each queue in a first-in-first-out order, combines the partial data transmission behaviors in each queue into a data stream, and further combines the plurality of data transmission behaviors in the plurality of queues into a plurality of data streams. The processor compares the plurality of connection port codes, the plurality of time values, the plurality of destination nodes, and the plurality of transmission data volumes of each data stream with a sending port, a sending time, a receiving port, and a data volume of a transmission instruction to determine whether each data stream corresponds to one of the connection port codes, wherein the data is transmitted along a transmission path to the receiving port at the sending time by the transmission instruction to control the sending port. A processor stores a portion of the data streams corresponding to the connection port codes in a register, and calculates the transmission efficiency of the transmission instruction according to the portion of the data streams.

[0013] According to an embodiment of the system aspect of the present invention, a system for reducing performance calculation time is provided, which is used to convert a waveform record file of a bus architecture into a performance analysis data to perform a transmission performance analysis of a transmission instruction. The system for reducing performance calculation time includes a database and a processor. The database is connected to the bus architecture and includes a waveform record file and a specified list. The waveform record file includes a plurality of waveform signal information corresponding to the bus architecture. The specified list corresponds to a plurality of nodes of the bus architecture and corresponds to a portion of these waveform signal information. The processor is connected to the database and is configured to implement an operation including the following steps: Read the waveform record file. Extract a portion of these waveform signal information corresponding to the specified list from the waveform record file. Map a portion of these waveform signal information to a plurality of transmission signal information of a plurality of connection ports of the bus architecture to generate a mapped waveform record file. Any of these connection ports is used to connect two of these nodes. Multiple time stamps of each of these connection ports are defined according to a specified voltage level of each of these transmission signal information. Integrate the mapped waveform record file with these time stamps to generate a performance analysis data.

[0014] Thus, the system for reducing performance calculation time of the present invention captures a portion of waveform signal information and does not need to calculate all waveform signal information in the waveform record file, thereby reducing the amount of data required for calculation during performance analysis, thereby shortening the calculation time of performance analysis and improving the calculation speed.

[0015] Other examples of the aforementioned implementation are as follows: the aforementioned waveform record file may include one of an IEEE 1364 standard waveform file, a FSDB file, and a signal change file.

[0016] Other embodiments of the aforementioned implementation are as follows: When one of the aforementioned nodes initiates data transmission to another of the aforementioned nodes, the timestamps of one of the connection ports between the one of the aforementioned nodes and the other of the aforementioned nodes may include a first timestamp, a second timestamp, a third timestamp, a fourth timestamp, and a fifth timestamp. The first timestamp corresponds to a time point when the one of the aforementioned nodes initiates an address communication request. The second timestamp corresponds to a time point when the other of the aforementioned nodes replies to the address communication request. The third timestamp corresponds to a time point when the one of the aforementioned nodes transmits a piece of data. The fourth timestamp corresponds to a time point when the other of the aforementioned nodes receives the piece of data. The fifth timestamp corresponds to a time point when the data transmission is completed.

[0017] Other embodiments of the aforementioned implementation are as follows: The aforementioned timestamp may further include a sixth timestamp and a seventh timestamp. The sixth timestamp corresponds to a time point when another of the nodes requests to establish a reply channel. The seventh timestamp corresponds to a time point when one of the nodes receives a request to complete the establishment of the reply channel.

[0018] Other embodiments of the aforementioned implementation are as follows: the aforementioned processor may further include an operation configured to implement the following steps: calculating a transmission performance of the nodes of the bus architecture according to the timestamps of each of the connection ports.

[0019] Other embodiments of the aforementioned implementation are as follows: the aforementioned processor may further include an operation configured to implement the following steps: generating a performance abnormality warning message by the processor when the transmission performance does not meet a preset value.

[0020] Other embodiments of the aforementioned implementation are as follows: The aforementioned processor may further include an operation configured to implement the following steps: converting the performance analysis data into a transmission record table, wherein the transmission record table includes a connection port code, a time value, one of the time stamps, a destination node, and a transmission data volume corresponding to each of the plurality of data transmission behaviors between the plurality of nodes. According to the time stamps corresponding to each data transmission behavior, these data transmission behaviors are stored in a plurality of queues, and one of the partial data transmission behaviors in each queue is taken out in a first-in-first-out order, and the partial data transmission behaviors in each queue are combined into a data stream, and then these data transmission behaviors in these queues are combined into a plurality of data streams. The plurality of connection port codes, the plurality of time values, the plurality of destination nodes, and the plurality of transmission data volumes of each data stream are compared with a sending port, a sending time, a receiving port, and a data volume of a transmission instruction to determine whether each data stream corresponds to one of the connection port codes, wherein the data is transmitted along a transmission path to the receiving port at the sending time controlled by the transmission instruction. A portion of the data streams corresponding to the connection port codes is stored in a register, and the transmission performance of the transmission instruction is calculated according to the portion of the data streams. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram of a system for reducing performance computing time according to a first embodiment of the present invention;

[0022] Figure 2 is a flow chart illustrating a method for reducing performance calculation time according to a second embodiment of the present invention;

[0023] Figure 3 It is shown according to Figure 2 A flowchart of the steps of a method for reducing performance calculation time;

[0024] Figure 4 It is shown according to Figure 2 A schematic diagram of a mapping operation interface of a method for reducing performance calculation time;

[0025] Figure 5 It is shown according to Figure 2 A flowchart of the steps of a method for reducing performance calculation time;

[0026] Figure 6 It is shown according to Figure 2 A schematic diagram of transmitting signal information of a method for reducing performance calculation time;

[0027] Figure 7 is a flow chart illustrating a method for reducing performance calculation time according to a third embodiment of the present invention;

[0028] Fig. 8A is a flowchart illustrating some steps of a method for reducing performance calculation time according to a fourth embodiment of the present invention;

[0029] Figure 8B is a flowchart illustrating another part of the steps of the method for reducing performance calculation time according to the fourth embodiment of the present invention;

[0030] Fig. 9 It is shown according to Fig. 8A , Figure 8B A schematic diagram of a method for reducing performance computing time applied to an Advanced Microcontroller Bus Architecture (AMBA);

[0031] Fig.10 It is shown according to Fig. 8A , Figure 8B A flowchart of the steps of a method for reducing performance calculation time;

[0032] Fig.11 It is shown according to Fig. 8A , Figure 8B A schematic diagram of a queue of a method for reducing performance calculation time;

[0033] Fig.12 It is shown according to Fig. 8A , Figure 8B A schematic diagram of the steps of a method for reducing performance computing time; and

[0034] Fig.13 It is shown according to Fig. 8A , Figure 8B Schematic diagram of the transmission performance of the method of reducing the performance calculation time.

[0035]

Explanation of symbols

[0036] 10: Bus architecture

[0037] 100: System for reducing performance computing time

[0038] 120: Database

[0039] 130: Processor

[0040] 200,200a,300: Methods to reduce performance calculation time

[0041] ACLK, ARADDR, ARVALID, ARREADY: Transmission signal information

[0042] CLK1, CLK2, CLK3, CLK4, CLK5: Clock

[0043] DT1,DT2,DT3,DT4,DT5,DT6,DT7,DT8,DT9,DT10,DT11,DT12,DT13,DTN,DTN-1,DTN-2,DTN-3: Data transmission behavior

[0044] FT: Transmission end time

[0045] I1: Mapping operation interface

[0046] L1: Designated list

[0047] n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18: nodes

[0048] P1,P2,P3,P4,P5,P6,P11,P12,P21,P22: Connection port code

[0049] PF: Waveform Recording File

[0050] Q1,Q2,Q3,Q4,Q5,Q6,Q7: Queues

[0051] R1, R2: Transmission path

[0052] S1: Waveform signal information

[0053] S01,S011,S012,S013,S014,S02,S03,S031,S032,S033,S04,S041,S042,S043,S044,S045,S046,S05,S06,S11,S12,S13,S14,S15,S16,S17,S171,S172,S173,S174,S175a,S175b,S175c,S176a,S176b,S176c,S18,S181a,S181b,S185,S187,S19: Steps

[0054] S182a, S182b: First judgment step

[0055] S183a, S183b: Second judgment step

[0056] S184: First temporary storage step

[0057] S186: Second temporary storage step

[0058] ST: Transmission start time

[0059] T2: Second timestamp

[0060] VH: High voltage level

[0061] VL: Low voltage level DETAILED DESCRIPTION

[0062] The following will describe multiple embodiments of the present invention with reference to the accompanying drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings; and repeated elements may be represented by the same number.

[0063] In addition, in this article, when a certain element (or unit or module, etc.) is "connected" to another element, it may refer to that the element is directly connected to another element, or it may refer to that a certain element is indirectly connected to another element, that is, there are other elements between the element and the other element. When it is explicitly stated that a certain element is "directly connected" to another element, it means that there are no other elements between the element and the other element. The terms first, second, third, etc. are only used to describe different elements, and there is no restriction on the elements themselves. Therefore, the first element can also be renamed as the second element. Moreover, the combination of elements / units / circuits in this article is not a generally known, conventional or conventional combination in this field. Whether the elements / units / circuits themselves are conventional cannot be used to determine whether their combination relationship is easy to be easily completed by ordinary knowledgeable people in the technical field.

[0064] See also Figure 1 and Figure 2 , Figure 1 is a block diagram of a system 100 for reducing performance computing time according to a first embodiment of the present invention; and Figure 2 1 is a flow chart of a method 200 for reducing performance calculation time according to a second embodiment of the present invention. The system 100 for reducing performance calculation time includes a database 120 and a processor 130. The system 100 for reducing performance calculation time is used to convert a waveform record file PF of a bus architecture 10 into performance analysis data to perform a transmission performance analysis of a transmission instruction. The bus architecture 10 includes a plurality of nodes and a plurality of connection ports. Any of these connection ports is used to connect two of these nodes. The database 120 is connected to the bus architecture 10 and includes a waveform record file PF and a designated list L1. The waveform record file PF includes a plurality of waveform signal information S1 corresponding to the bus architecture 10. The designated list L1 corresponds to these nodes and corresponds to a portion of these waveform signal information S1. The processor 130 is connected to the database 120 and is configured to implement the method 200 for reducing performance calculation time.

[0065] Specifically, the bus architecture 10 may be an advanced microcontroller bus architecture in an Advanced RISC Machine (ARM) or other system-on-chip. The database 120 includes a random access memory (RAM) or other type of dynamic storage device that can store information and instructions for execution by the processor 130. The processor 130 may include any type of processor or microprocessor, but the present invention is not limited thereto. The waveform record file PF records the waveform signal information S1 in the bus architecture 10. The waveform signal information S1 includes the signal code, voltage value and corresponding time interval of each signal of each node. The waveform record file PF may include one of the IEEE 1364 standard waveform file, the NOVAS customized FSDB file and other signal change files in any format, but the present invention is not limited thereto.

[0066] The method 200 for reducing performance calculation time is used to convert a waveform record file PF of a bus architecture 10 into performance analysis data to perform transmission performance analysis of a transmission instruction. The method 200 for reducing performance calculation time includes steps S01, S02, S03, S04, and S05. Step S01 reads the waveform record file PF in the database 120 through the processor 130, wherein the waveform record file PF includes a plurality of waveform signal information S1 corresponding to the bus architecture 10. Step S02 extracts a portion of these waveform signal information S1 corresponding to a specified list L1 from the waveform record file PF through the processor 130, wherein the specified list L1 corresponds to a plurality of nodes of the bus architecture 10. Step S03 maps a portion of these waveform signal information S1 to a plurality of transmission signal information of a plurality of connection ports through the processor 130 to generate a mapped waveform record file, wherein any one of these connection ports is used to connect two of these nodes. In step S04, the processor 130 defines multiple time stamps of each of the connection ports according to a specified voltage level of each of the transmission signal information. In step S05, the processor 130 integrates the mapped waveform record file with the time stamps to generate performance analysis data. In this way, the system 100 for reducing performance calculation time of the present invention captures a part of the waveform signal information S1, and does not need to calculate all the waveform signal information S1 in the waveform record file PF, thereby reducing the amount of data required for calculation during performance analysis, thereby shortening the calculation time of performance analysis and improving the calculation speed.

[0067] In detail, step S01 is to read the waveform record file PF of the bus architecture 10 stored in the database 120. Step S02 is to extract the waveform signal information S1 listed in the specified list L1 in the waveform record file PF, wherein the specified list L1 can be as shown in Table 1. For example, the bus architecture 10 includes M nodes (i.e., node 1, node 2 to node M), wherein node 1 includes 6 waveform signal information S1, node 2 includes 7 waveform signal information S1, and node M includes 8 waveform signal information S1. The specified list L1 lists the signal names of the waveform signals that will generate high and low level changes when nodes 1, 2 to M perform data transmission. Step S02 is to extract 3 waveform signal information S1 of node 1, 5 waveform signal information S1 of node 2, and 3 waveform signal information S1 of node M corresponding to the specified list L1, and so on, which will not be repeated.

[0068] Table 1

[0069]

[0070] Two adjacent nodes in the bus architecture 10 are connected through a connection port and transmit data. Step S03 is to correspond the waveform signal information S1 of each node recorded in the waveform record file PF with the transmission signal information of the connection port, and generate a mapped waveform record file. The following will explain the operation of steps S01, S02, and S03 through a more detailed embodiment.

[0071] Please refer to Figures 1 to 4 ,in Figure 3 It is shown according to Figure 2 A flowchart of steps S01, S02, and S03 of a method 200 for reducing performance calculation time; and Figure 4 It is shown according to Figure 2 Schematic diagram of the mapping operation interface I1 of the method 200 for reducing the performance calculation time. Step S01 may include steps S011, S012, S013 and S014. Step S03 may include steps S031, S032 and S033. Step S011 is to load the waveform record file PF, which may correspond to Figure 4 In the "Load File" field in the mapping operation interface I1, step S012 is to split the waveform record file PF into signal definitions and waveform signal information S1, and execute step S013 for the waveform signal information S1. Specifically, step S012 extracts the waveform signal information S1 of each signal in the waveform record file PF. The waveform signal information S1 includes time information, voltage level changes and signal names. Step S013 is to review all waveform signal information S1, and step S014 is to select the node to be analyzed for performance and review all signals of the aforementioned node. Steps S013 and S014 may correspond to Figure 4The "Select Node" field and the "Search Signal" field in the bus architecture 10 are selected. The "Select Node" field lists all nodes in the bus architecture 10, and the "Search Signal" field lists all signals in one of the nodes. Step S02 may include extracting the waveform signal information S1 corresponding to the specified list L1. Step S031 is to map the aforementioned waveform signal information S1 to the transmission signal information of the connection port, which may correspond to the "Mapping" field. Step S031 is to select the protocol type of the connection port currently to be mapped (such as the Advanced High-performance Bus (AHB) protocol, the Advanced PeripheralBus (APB) protocol, or the Advanced eXtensible Interface (AXI) protocol), and map the waveform signal information S1 selected in step S02 with the signal name of the transmission signal information in the connection port. Step S032 is to determine whether the transmission signal information of all connection ports has been mapped. If so, execute step S033; if not, execute step S013. Step S033 is to combine the definition of the signal and the transmission signal information and generate a waveform record file after mapping. In addition, the “Search All Signals” column allows the user to search for the desired waveform signal information S1 from the bus architecture 10 according to the signal name.

[0072] Please refer to Figure 1 , Figure 2 and Figure 5 ,in Figure 5 It is shown according to Figure 2 Flow chart of step S04 of method 200 for reducing performance calculation time. Step S04 may include steps S041, S042, S043, S044, S045 and S046. Step S041 is to input the mapped waveform record file. Step S042 is to disassemble all signals and add the time information in the waveform record file PF. Step S043 is to determine whether the combination of the current signals of the same connection port meets the voltage level condition of the specified timestamp. If so, execute step S044; if not, execute step S045. Step S044 is to mark the timestamp on the clock that meets the specified voltage level. Step S045 is to check the voltage level of the next clock. Step S046 is to determine whether all timestamps have been marked.

[0073] In detail, when one of the nodes initiates a data transmission to another of the nodes, and the data transmission is for reading data, the number of time stamps of the connection port between the one of the nodes and the other of the nodes is five, which may include a first time stamp, a second time stamp, a third time stamp, a fourth time stamp, and a fifth time stamp. The first time stamp corresponds to a time point when the one of the nodes initiates an address communication request. The second time stamp corresponds to a time point when the other of the nodes replies to the address communication request. The third time stamp corresponds to a time point when the one of the nodes transmits a piece of data. The fourth time stamp corresponds to a time point when the other of the nodes receives the piece of data. The fifth time stamp corresponds to a time point when the data transmission is completed. When a piece of data transmission is for writing data, the number of time stamps is seven, which may further include a sixth time stamp and a seventh time stamp. The sixth time stamp corresponds to a time point when the other of the nodes requests to establish a reply channel. The seventh time stamp corresponds to a time point when the one of the nodes receives a request for completion of reply channel establishment.

[0074] Please refer to Figure 1 , Figure 2 , Figure 5 and Figure 6 ,in Figure 6 It is shown according to Figure 2 Schematic diagram of the transmission signal information ACLK, ARADDR, ARVALID, ARREADY of the method 200 for reducing the performance calculation time. Figure 6 , the voltage levels of the transmission signal information ACLK, ARADDR, ARVALID, ARREADY of the connection port corresponding to the node 2 at the first clock CLK1, the second clock CLK2, the third clock CLK3, the fourth clock CLK4, and the fifth clock CLK5 are shown, and the transmission signal information ACLK, ARADDR, ARVALID, ARREADY varies between the high voltage level VH and the low voltage level VL. In the second embodiment, all time stamps have voltage level conditions, and when the specified voltage level of the transmission signal information ACLK, ARADDR, ARVALID, ARREADY meets the conditions, it can be marked as one of the time stamps. For example, when node 2 is transmitting data, the condition of the second time stamp T2 is that the transmission signal information ARVALID is at a high voltage level VH, and the transmission signal information ARREADY is at a high voltage level VH. Therefore, at the fourth clock CLK4, the transmission signal information ARVALID and ARREADY are both at a high voltage level VH, so the second time stamp T2 is marked at the fourth clock CLK4. In other embodiments of the present invention, the voltage level condition of the time stamp of each connection port can be adjusted and set according to requirements, but the present invention is not limited thereto.

[0075] Please refer to Figure 1 , Figure 2 and Figure 7 , Figure 7 2 is a flow chart of a method 200a for reducing performance calculation time according to a third embodiment of the present invention. The method 200a for reducing performance calculation time includes steps S01, S02, S03, S04, S05 and S06. In the third embodiment, steps S01, S02, S03, S04, S05 may be the same as steps S01, S02, S03, S04, S05 of the method 200 for reducing performance calculation time according to the second embodiment, and are not described in detail. In particular, the method 200a for reducing performance calculation time may further include step S06. Step S06 calculates a transmission performance of these nodes of the bus architecture 10 according to these timestamps (i.e., the first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the fifth timestamp, the sixth timestamp and the seventh timestamp) of each of these connection ports by the processor 130. Specifically, after obtaining the timestamps of all connection ports, the mapped waveform record file PF and the timestamps can be integrated to generate performance analysis data, and the transmission performance can be calculated based on the timestamps in the performance analysis data. In this way, the method 200a of reducing performance calculation time of the present invention can accurately calculate the state of each timestamp during data transmission, and then find out the section with abnormal transmission speed, effectively eliminating the abnormal problem.

[0076] In other embodiments of the present invention, the method for reducing performance calculation time can also generate a performance abnormality warning message when the transmission performance does not meet a preset value. In detail, the method for reducing performance calculation time can compare the time period between all time stamps with the preset value of the time stamp in the historical transmission information. When the time period between two adjacent time stamps is much greater than the preset value, it indicates that this time period may have an abnormal problem, thereby generating a performance abnormality warning message.

[0077] See also Figure 1 , Fig. 8A , Figure 8B and Fig. 9 , Fig. 8A and Figure 8B 1 and 2 are flowcharts of partial steps of a method 300 for reducing performance calculation time according to a fourth embodiment of the present invention, and Figure 8B The steps are continued in Fig. 8A after the steps; and Fig. 9 It is shown according to Fig. 8A , Figure 8BSchematic diagram of the method 300 for reducing performance computing time applied to an advanced microcontroller bus architecture. The method 300 for reducing performance computing time includes steps S11, S12, S13, S14, S15, S16, S17, S18, and S19. In the fourth embodiment, steps S11, S12, S13, S14, and S15 in the method 300 for reducing performance computing time may be the same as steps S01, S02, S03, S04, and S05 of the method 200 for reducing performance computing time in the second embodiment, and will not be repeated. In particular, the method 300 for reducing performance computing time may further include steps S16, S17, S18, and S19.

[0078] For example, in Fig. 9In the embodiment, the bus architecture 10 may be an advanced microcontroller bus architecture, which may include nodes n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18 (n1-n18), and the nodes n1-n18 are connected via connection ports, and the connection ports correspond to connection port codes P1, P2, P3, P4, P5, P6, P11, P12, P21, P22. The transmission path R1 includes multiple connection port codes P4, P5, P11, P12, P21, P22, and the transmission path R2 includes connection port codes P1 and P6. The nodes n1-n18 are used to represent the AXI bus, AHB bus, APB bus and Minimal Instruction Set Computer (MISC) in the advanced microcontroller bus architecture and the interconnection interfaces in the aforementioned buses, but the present invention is not limited thereto. Node n1 corresponds to the first central processing unit, node n2 corresponds to the SI to AXI signal conversion interface, node n3 corresponds to the Deep Learning Processor (DLP) IP, node n4 corresponds to the AXI interconnection interface, node n5 corresponds to the AXI interface converter (AXI wrapper), node n6 corresponds to the Double Data Rate (DDR) memory module, node n7 corresponds to the AHB bridge, node n8 corresponds to the AHB interconnection interface, node n9 corresponds to the system memory, node n10 corresponds to the APB bridge, node n11 corresponds to the General Purpose Input / Output group 0 (GPIO set 0), node n12 corresponds to the PAD module (Pin and Device model), node n13 corresponds to the second central processing unit, node n14 corresponds to the SI to AXI 2 signal conversion interface, node n15 corresponds to the AHB master module, node n16 corresponds to the AHB slave module, node n17 corresponds to the General Purpose Input / Output group 1 (GPIOset1), and node n18 corresponds to the PAD module. The DLP IP and the AXI interconnect interface are connected via connection port codes P2 and P3.Data is transmitted between nodes n13 and n18 via multiple connection port codes P4, P5, P11, P12, P21, and P22. For example, when a transmission instruction is issued, the control node n13 transmits a piece of data to the node n18. At this time, the node n13 is the sending port in the transmission instruction, and the node n18 is the receiving port in the transmission instruction. During the transmission of this data, the node n13 cannot directly transmit the data to the node n18, and it needs to pass through other nodes n14, n4, n7, n8, n10, and n17 to transmit the data to the node n18 via the connection port codes P4, P5, P11, P12, P21, and P22.

[0079] exist Fig. 8A In the step S11, S12, S13, S14, and S15, the waveform record file PF of the nodes n1 to n18 in the advanced microcontroller bus architecture is read, and the waveform signal information S1 required for computing performance analysis is extracted from the waveform record file PF, and mapped to the connection port codes P1, P2, P3, P4, P5, P6, P11, P12, P21, and P22 of the connection ports between the nodes n1 to n18 and their transmission signal information to generate a mapped waveform record file. The time stamps of these connection ports are defined to generate performance analysis data.

[0080] exist Figure 8B In the embodiment, step S16 converts the performance analysis data into a transmission record table by the processor 130, wherein the transmission record table includes a connection port code, a time value, one of the timestamps, a destination node, and a transmission data volume corresponding to each of the multiple data transmission behaviors between the nodes n1-n18. Step S17 stores the data transmission behaviors into multiple queues Q1, Q2, Q3, Q4, Q5, Q6, and Q7 (see FIG. 1 ) according to the timestamps corresponding to each data transmission behavior by the processor 130. Fig.11), and take out one of these data transmission behaviors in each queue Q1-Q7 in a first-in-first-out order, combine this part of these data transmission behaviors in each queue Q1-Q7 into a data stream, and then combine these data transmission behaviors in these queues Q1-Q7 into multiple data streams. Step S18 is to compare the multiple connection port codes P4, P5, P11, P12, P21, P22, multiple time values, multiple destination nodes and multiple transmission data volumes of each data stream with a sending port, a sending time, a receiving port and a data volume of a transmission instruction by the processor 130 to determine whether each data stream corresponds to one of these connection port codes P4, P5, P11, P12, P21, P22, wherein the data is controlled by the transmission instruction to control the sending port to transmit the data to the receiving port along a transmission path R1, R2 at the sending time. In step S19, the processor 130 stores a portion of the data streams corresponding to the connection port codes P4, P5, P11, P12, P21, and P22 in a register, and calculates the transmission efficiency of the transmission instruction according to the portion of the data streams.

[0081] Specifically, the transmission record table may be shown in Table 2. The transmission record table may be a data statistics file generated by a C++ language program code, but the present invention is not limited thereto.

[0082] Table 2

[0083]

[0084]

[0085] Please refer to Table 2, which lists the data transmission behaviors DT1, DT2, DT3, DT4, DT5, DT6, DT7, DT8, DT9, DT10, DT11, DT12, DT13 to DTN-3, DTN-2, DTN-1, and DTN after the time value starts from 0. Taking the data transmission behavior DT1 as an example, the signal change of the connection port code P4 at the time value of 100ns and the specified voltage level of the first time stamp, the time value 100ns is marked as the first time stamp, and the address of the destination node of the data transmission behavior DT1 is "2689597440". It can be seen from the other data transmission behaviors DT2 to DTN in Table 2 that the time values ​​of the signal change of the connection port code P5 are all close to the connection port code P4, and the time value of its marked time stamp is close to the connection port code P4, so the destination node in the data transmission behavior DT1 corresponds to the connection port code P5, and "2689597440" is the address corresponding to the connection port code P5.

[0086] In the fourth embodiment, if the connection port code P4 needs to read a piece of data from the connection port code P5, all operations of reading the first time stamp, the second time stamp, the third time stamp, the fourth time stamp and the fifth time stamp corresponding to the data must be performed completely.

[0087] Please refer to Figure 1 , FIG. 8A to FIG. 11 , Fig.10 It is shown according to Fig. 8A , Figure 8B Flow chart of step S17 of the method 300 for reducing performance calculation time; Fig.11 It is shown according to Fig. 8A , Figure 8BSchematic diagram of queues Q1-Q7 of method 300 for reducing performance calculation time. Step S17 may include steps S171, S172, S173, S174, S175a, S175b, S175c, S176a, S176b, S176c. For example, step S171 is to obtain the transmission record table of data transmission behaviors DT1-DTN corresponding to all nodes n1-n18. Steps S172 and S173 are to obtain node n14 and obtain all data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, DTN-1 corresponding to connection port code P4. Step S174 is to determine whether the current data transmission behavior DT1, DT3, DT5, DT7, DT9, DTN-3, DTN-1 is one of reading data and writing data according to the timestamps of the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, DTN-1. When the data transmission behavior DT1, DT3, DT5, DT7, DT9, DTN-3, DTN-1 is reading data, step S175a is executed; when the data transmission behavior DT1, DT3, DT5, DT7, DT9, DTN-3, DTN-1 is writing data, step S176a is executed. Since the maximum value of the timestamp corresponding to the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, DTN-1 corresponding to the connection port code P4 is 7, it can be known that the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, DTN-1 corresponding to the connection port code P4 are writing data. Step S176a is to take out the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, and DTN-1 from the queues Q1 to Q7 according to the first-in-first-out rule. Step S176b is to determine whether the number of the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, and DTN-1 taken out is seven, that is, to determine whether all the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, and DTN-1 corresponding to the current connection port code P4 have been taken out. Step S176c is to combine the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, and DTN-1 taken out from all the queues Q1 to Q7 into one data stream. In addition, when the data transmission behaviors DT1, DT3, DT5, DT7, and DT9 are for reading data, step S175a is to take out the data transmission behaviors DT1, DT3, DT5, DT7, and DT9 from the queues Q1 to Q5 respectively according to the first-in-first-out rule.Step S175b is to determine whether the number of the data transmission behaviors DT1, DT3, DT5, DT7, and DT9 taken out is five, that is, to determine whether all the data transmission behaviors DT1, DT3, DT5, DT7, and DT9 corresponding to the current connection port code P4 have been taken out. Step S175c is to combine the data transmission behaviors DT1, DT3, DT5, DT7, and DT9 taken out from all queues Q1 to Q5 into one data stream.

[0088] In other words, step S17 takes out the data transmission behaviors DT1, DT3, DT5, DT7, DT9, DTN-3, and DTN-1 corresponding to the connection port code P4 from queues Q1 to Q7 and combines them into one data stream, and then takes out the data transmission behaviors DT2, DT4, DT6, DT8, DT10, DTN-2, and DTN corresponding to the connection port code P5 from queues Q1 to Q7 and combines them into another data stream.

[0089] Please refer to Figure 1 , FIG. 8A to FIG. 12 , Fig.12 It is shown according to Fig. 8A , Figure 8B Schematic diagram of step S18 of the method 300 for reducing performance computing time. Step S18 may include a first judgment step S182a and a second judgment step S183a. The first judgment step S182a is to determine by the processor 130 whether the connection port codes P4, P5, P11, P12, P21, P22 of one of the data streams and at least one of the destination nodes are the same as at least one of the sending port and the receiving port of the transmission instruction, and whether the transmission start time of the one of the data streams is later than or equal to the sending time of the transmission instruction to generate a first judgment result. The second judgment step S183a includes determining by the processor 130 whether the transmission data volume of the one of the data streams is equal to the data volume of the transmission instruction to generate a second judgment result. When the first judgment result is yes and the second judgment result is yes, the one of the data streams is one of the connection port codes P4, P5, P11, P12, P21, P22.

[0090] When the first judgment result is yes and the second judgment result is no, the comparison step S18 may further include a first temporary storage step S184, a step S185, a second temporary storage step S186 and a step S187. The first temporary storage step S184 includes storing one of the data streams in a temporary storage by the processor 130. Step S185 includes executing the first judgment step S182b and the second judgment step S183b on the other of the data streams by the processor 130. The second temporary storage step S186 includes storing the other of the data streams in the temporary storage by the processor 130 when the first judgment result corresponding to the other of the data streams is yes and the second judgment result is no. Step S187 includes calculating a sum of the amounts of the transmission data in the temporary storage by the processor 130 and determining whether the sum is equal to the amount of data. When the sum is equal to the amount of data, one and the other of these data streams are both this of these connection port codes P4, P5, P11, P12, P21, P22.

[0091] In detail, step S18 may further include steps S181a and S181b. Step S181a is to obtain a data stream. The first judgment step S182a is to judge whether at least one of the connection port code P4 and the destination node (i.e., the connection port code P5) corresponding to the data transmission behavior DT1, DT3, DT5, DT7, DT9, DTN-3, and DTN-1 in the current data stream is the same as the sending port (i.e., the connection port code P4) and the receiving port (i.e., the connection port code P12) of the transmission instruction, and whether the transmission start time (i.e., 100ns) of the current data stream is later than the sending time of the transmission instruction. If none of the nodes n1 to n18 and the destination node of the current data stream is the same as any of the sending port and the receiving port of the transmission instruction, it means that the current data stream may not be one of the connection port codes P4, P5, P11, P12, P21, and P22 in the transmission path R1 of the transmission instruction. If the nodes n1~n18 and the destination node of the current data flow match the sending port and receiving port of the transmission instruction, but the transmission start time of the current data flow is earlier than the sending time of the transmission instruction, it means that the current data flow is a data transmission behavior that occurred before the transmission instruction was sent, so the current data flow is not one of the connection port codes P4, P5, P11, P12, P21, P22 in the transmission path R1 of the transmission instruction.

[0092] When the first judgment result of the first judgment step S182a is no, step S181a is repeated to obtain another data stream. When the first judgment result is yes, the second judgment step S183a is executed. When the data amount of the transmission instruction is 8 bytes, and the transmission data amount of the current data stream is also 8 bytes, the second judgment result is yes, and the current data stream is judged to be one of the connection port codes P4, P5, P11, P12, P21, and P22. When the data amount of the transmission instruction is 8 bytes, and the transmission data amount of the current data stream is 4 bytes, the second judgment result is no, and the first temporary storage step S184 is executed. The first temporary storage step S184 stores the current data stream in a temporary register and executes step S185. Step S185 includes executing step S181b, the first judgment step S182b, and the second judgment step S183b. Step S181b is to obtain another data stream and perform a first judgment step S182b on the other data stream. When the first judgment result of the first judgment step S182b is no, step S181b is performed to obtain other data streams. When the first judgment result is yes, a second judgment step S183b is performed on the other data stream. When the data amount of the transmission instruction is 8 bytes and the transmission data amount of the other data stream is also 8 bytes, the second judgment result is yes, and the other data stream is judged to be one of the connection port codes P4, P5, P11, P12, P21, and P22. When the data amount of the transmission instruction is 8 bytes and the transmission data amount of the other data stream is 4 bytes, the second judgment result is no, and the second temporary storage step S186 is performed to store the other data stream in the temporary register. Step S187 calculates the sum of the transmission data amounts of all data streams in the temporary register and determines whether the sum is equal to the data amount. When the transmission data volume of the current data stream and the other data stream are both 4 bytes, their sum is equal to the data volume, and the data of the current data stream and the other data stream are stored in the same node at consecutive addresses, it means that an 8-byte transmission instruction is split into two groups of 4-byte data for transmission during transmission, so the current data stream and the other data stream both correspond to one of the connection port codes P4, P5, P11, P12, P21, and P22. In detail, when the data of the current data stream is stored at addresses 100-103 in the connection port code P5, and the data of the other data stream is stored at addresses 104-107 in the connection port code P5, it means that the data of the current data stream and the other data stream are stored in the same connection port code P5 at consecutive addresses. In this way, the method 300 of reducing performance calculation time of the present invention can calculate the data transmission efficiency across different buses.

[0093] See also Figure 1 , Fig. 8A , Figure 8B and Fig.13 ,in Fig.13 It is shown according to Fig. 8A , Figure 8B A schematic diagram of the transmission performance of the method 300 for reducing the performance calculation time. Fig.13 In the figure, a transfer instruction is shown to transfer a piece of data from the AXI-1 bus to the APB bus, crossing the AXI-2 bus and the AHB bus in the middle, and the transmission start time ST and transmission end time FT of the data stream corresponding to each bus. The transmission start time ST of the AXI-1 bus is 129020ns, and it is transmitted to the AXI-2 bus after 50ns. The transmission start time ST of the AXI-2 bus is 129070ns, and it is transmitted to the AHB bus after 970ns. The transmission start time ST of the AHB bus is 130040ns, and it is transmitted to the APB bus after 460ns. The APB bus then transmits the transmission completion response back to the AXI-1 bus in the aforementioned order, and the transmission end time FT when the AXI-1 bus receives the transmission completion response is 131570ns. The total time consumed by the transfer instruction is 2550ns.

[0094] It can be seen from the above implementation that the method and system for reducing performance calculation time of the present invention have the following advantages. First, by extracting a part of the waveform signal information, it is not necessary to calculate all the waveform signal information in the waveform record file, thereby reducing the amount of data required for calculation during performance analysis, thereby shortening the calculation time of performance analysis and improving the calculation speed; second, the state of each timestamp during data transmission can be accurately calculated, thereby finding the section with abnormal transmission speed and effectively eliminating the abnormal problem; third, the data transmission efficiency across different buses can be calculated.

[0095] Although the present invention has been disclosed as above in the form of implementation modes, it is not intended to limit the present invention. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the attached claims.

Claims

1. A method for reducing performance calculation time, for converting a waveform record file of a bus architecture into performance analysis data to perform a transmission performance analysis of a transmission instruction, characterized in that: The method for reducing performance calculation time includes: Reading the waveform record file in a database through a processor, wherein the waveform record file includes a plurality of waveform signal information corresponding to the bus architecture; Retrieving, by the processor, a portion of the plurality of waveform signal information corresponding to a designated list from the waveform record file, wherein the designated list corresponds to a plurality of nodes of the bus architecture; Mapping part of the plurality of waveform signal information to a plurality of transmission signal information of a plurality of connection ports by the processor to generate a mapped waveform record file, wherein any one of the plurality of connection ports is used to connect two of the plurality of nodes; defining, by the processor, a plurality of time stamps for each of the plurality of connection ports according to a specified voltage level of each of the plurality of transmission signal information; as well as The processor integrates the mapped waveform record file with the multiple time stamps to generate the performance analysis data.

2. The method for reducing performance calculation time as claimed in claim 1, characterized in that: The waveform record file includes one of an IEEE 1364 standard waveform (Value Change Dump; VCD) file, a Fast Signal Data Base (FSDB) file, and a signal change (SignalValue) file.

3. The method for reducing performance calculation time as claimed in claim 1, characterized in that: When one of the plurality of nodes initiates data transmission to another of the plurality of nodes, the plurality of timestamps of one of the plurality of connection ports between the one of the plurality of nodes and the other of the plurality of nodes include: a first timestamp corresponding to a time point at which the one of the plurality of nodes initiates an address communication request; a second timestamp corresponding to a time point at which the other one of the plurality of nodes responds to the address communication request; a third timestamp corresponding to a time point at which the one of the plurality of nodes transmits a piece of data; a fourth timestamp corresponding to a time point at which the other one of the plurality of nodes receives the data; and A fifth timestamp corresponds to a time point when the data transmission is completed.

4. The method for reducing performance calculation time as claimed in claim 3, characterized in that: The multiple time stamps also include: a sixth timestamp corresponding to a time point at which the other one of the plurality of nodes requests to establish a reply channel; and A seventh timestamp corresponds to a time point when the one of the plurality of nodes receives the reply channel establishment completion request.

5. The method for reducing performance calculation time as claimed in claim 1, characterized in that: Also includes: A transmission performance of the plurality of nodes of the bus architecture is calculated by the processor according to the plurality of time stamps of each of the plurality of connection ports.

6. The method for reducing performance calculation time as claimed in claim 5, characterized in that: Also includes: The processor generates a performance abnormality warning message when the transmission performance does not meet a preset value.

7. The method for reducing performance calculation time as claimed in claim 1, characterized in that: Also includes: Converting the performance analysis data into a transmission record table by the processor, wherein the transmission record table includes a connection port code, a time value, one of the timestamps, a destination node, and a transmission data volume corresponding to each of the multiple data transmission behaviors between the multiple nodes; The processor stores the plurality of data transmission behaviors into a plurality of queues according to the plurality of time stamps corresponding to the plurality of data transmission behaviors, and takes out one of the plurality of data transmission behaviors in each queue in a first-in-first-out order, combines the plurality of data transmission behaviors in each queue into a data stream, and further combines the plurality of data transmission behaviors in the plurality of queues into a plurality of the data streams; By comparing the plurality of connection port codes, the plurality of time values, the plurality of destination nodes and the plurality of transmission data volumes of each data stream with a sending port, a sending time, a receiving port and a data volume of a data of a transmission instruction, through the processor, to determine whether each data stream corresponds to one of the plurality of connection port codes, wherein the data is transmitted along a transmission path to the receiving port at the sending time by controlling the sending port by the transmission instruction; and The processor stores a portion of the plurality of data streams corresponding to the plurality of connection port codes in a register, and calculates a transmission efficiency of the transmission instruction according to the portion of the plurality of data streams.

8. A system for reducing performance calculation time, for converting a waveform record file of a bus architecture into performance analysis data to perform a transmission performance analysis of a transmission instruction, characterized in that: The system for reducing performance computing time includes: A database is signal-connected to the bus architecture and includes: The waveform record file includes a plurality of waveform signal information corresponding to the bus architecture; and a designated list corresponding to a plurality of nodes of the bus architecture and corresponding to a portion of the plurality of waveform signal information; as well as A processor is signal-connected to the database and is configured to perform operations comprising the following steps: Read the waveform record file; Extracting the plurality of waveform signal information corresponding to the portion of the designated list from the waveform record file; Mapping part of the plurality of waveform signal information to a plurality of transmission signal information of a plurality of connection ports of the bus architecture to generate a mapped waveform record file, wherein any one of the plurality of connection ports is used to connect two of the plurality of nodes; defining a plurality of time stamps for each of the plurality of connection ports according to a specified voltage level of each of the plurality of transmission signal information; and The mapped waveform record file is integrated with the multiple time stamps to generate performance analysis data.

9. The system for reducing performance computing time as claimed in claim 8, characterized in that: The waveform record file includes one of an IEEE 1364 standard waveform file, an FSDB file, and a signal change file.

10. The system for reducing performance computing time as claimed in claim 8, characterized in that: When one of the plurality of nodes initiates data transmission to another of the plurality of nodes, the plurality of timestamps of one of the plurality of connection ports between the one of the plurality of nodes and the other of the plurality of nodes include: a first timestamp corresponding to a time point at which the one of the plurality of nodes initiates an address communication request; a second timestamp corresponding to a time point at which the other one of the plurality of nodes responds to the address communication request; a third timestamp corresponding to a time point at which the one of the plurality of nodes transmits a piece of data; a fourth timestamp corresponding to a time point at which the other one of the plurality of nodes receives the data; and A fifth timestamp corresponds to a time point when the data transmission is completed.

11. The system for reducing performance computing time as claimed in claim 10, characterized in that: The multiple time stamps also include: a sixth timestamp corresponding to a time point at which the other one of the plurality of nodes requests to establish a reply channel; and A seventh timestamp corresponds to a time point when the one of the plurality of nodes receives the reply channel establishment completion request.

12. The system for reducing performance computing time as claimed in claim 8, characterized in that: The processor also includes operations configured to perform the following steps: A transmission performance of the plurality of nodes of the bus architecture is calculated according to the plurality of time stamps of each of the plurality of connection ports.

13. The system for reducing performance computing time as claimed in claim 12, characterized in that: The processor also includes operations configured to perform the following steps: The processor generates a performance abnormality warning message when the transmission performance does not meet a preset value.

14. The system for reducing performance computing time as claimed in claim 8, characterized in that: The processor also includes operations configured to perform the following steps: Converting the performance analysis data into a transmission record table, wherein the transmission record table includes a connection port code, a time value, one of the timestamps, a destination node, and a transmission data volume corresponding to each of the multiple data transmission behaviors between the multiple nodes; storing the plurality of data transmission behaviors into a plurality of queues according to the plurality of time stamps corresponding to the plurality of data transmission behaviors, taking out one of the plurality of data transmission behaviors in each queue in a first-in-first-out order, combining the plurality of data transmission behaviors in each queue into a data stream, and further combining the plurality of data transmission behaviors in the plurality of queues into a plurality of the data streams; Comparing the plurality of connection port codes, the plurality of time values, the plurality of destination nodes and the plurality of transmission data volumes of each of the data streams with a sending port, a sending time, a receiving port and a data volume of a data of a transmission instruction, so as to determine whether each of the data streams corresponds to one of the plurality of connection port codes, wherein the data is transmitted along a transmission path to the receiving port at the sending time by controlling the sending port by the transmission instruction; and A portion of the plurality of data streams corresponding to the plurality of connection port codes is stored in a register, and a transmission performance of the transmission instruction is calculated according to the portion of the plurality of data streams.

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