Link conversion method and system in universal serial bus equipment

Abstract

A method for link conversion in a USB device includes transmitting, by a first transmitter, a plurality of first RS-FEC blocks, receiving, by a receiver, a UNBOND set, waking up, by a LASM, a second transmitter when the receiver receives the UNBOND set, transmitting, by the second transmitter, a training sequence, transmitting, by the second transmitter, a specific pattern sequence, and determining whether the current RS-FEC block transmitted by the first transmitter is a DESKEW block, if the current RS-FEC block is determined to be the DESKEW block, stopping transmitting the specific mode sequence, and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter.

Description

Technical Field

[0001] The present application generally relates to the field of universal serial bus, and more specifically, to a method and system for link conversion in a Universal Serial Bus (USB) device. Background Art

[0002] Universal Serial Bus (USB) is an industrial standard that specifies the physical interface and protocol for connection, data transfer, and power supply between hosts (such as personal computers, peripheral devices (such as keyboards and mobile devices), and intermediate hubs. USB aims to standardize the connection of peripherals to computers, replacing various interfaces such as serial ports, parallel ports, game ports, and Android Debug Bridge (ADB) ports. It has become a universal standard for various devices, such as keyboards, mice, cameras, printers, scanners, flash drives, smartphones, game consoles, and mobile power banks. As of 2023, USB includes four generations of specifications: USB 1.x, USB 2.0, USB 3.x, and USB4.

[0003] USB4 (sometimes referred to as USB 4.0) is a new generation of Universal Serial Bus (USB) standard released by the USB Implementers Form (USB-IF) in 2019. It is based on the Thunderbolt 3 protocol specification, but also supports multiple data and display protocols, such as DisplayPort and PCI Express (PCIe). The USB4 structure can dynamically share a single high-speed link with multiple hardware endpoints to best provide each transfer service by data type and application. USB4 includes enhanced data transmission and power supply capabilities, as well as a connection-oriented channel architecture designed to combine multiple protocols onto a single physical interface in order to dynamically share the total speed and performance of the USB4 Fabric.

[0004] Key features of USB4 include dual-lane operation using existing USB Type-C cables as well as up to 80Gbps operation via 80Gbps certified cables, multiple data and display protocols to efficiently share the maximum aggregate bandwidth on the bus, and backward compatibility with all previous versions of USB.

[0005] USB4 itself does not provide any general data transfer mechanisms or device classes (like USB 3.x), but is primarily used as a way to tunnel other protocols such as USB 3.2, DisplayPort, and optionally PCIe. According to the USB4 1.0 specification, when the host and device do not support the optional PCIe tunnel, the non-display bandwidth will be limited to the mandatory 10Gbit / s described by USB 3.2, but includes optional support for 20Gbit / s. The USB42.0 specification introduces optional support for the new USB3 Gen T tunnel, which extends the USB3 protocol to be able to use the maximum available bandwidth. USB4 2.0 specifies USB 3.2 ("Enhanced SuperSpeed") tunnels, DisplayPort 2.1-based tunnels, and PCIe-based tunnels.

[0006] The USB4 specification describes specific steps that a USB4 interface should follow when transitioning to a symmetrical link. The key steps are:

[0007] The new transmitter shall send consecutive DESKEW.0 ordered sets or data sets and wait for the existing transmitter (Tx0) to add it to the link; and

[0008] When Tx1 is sending a DESKEW.0 ordered set or data set, at the start of an RS-FEC block (either the start of the first RS-FEC block or the start of any subsequent RS-FEC block while Tx1 is sending a DESKEW.0 ordered set or data set), the USB4 interface shall transmit a timing correction block (De-skew block) on both transmitters (Tx0 and Tx1).

[0009] However, the specification lacks details on how the designer can implement these steps. Therefore, it is necessary to propose an implementation scheme for converting to a symmetrical link. Summary of the invention

[0010] An embodiment provides a method for link conversion in a Universal Serial Bus (USB) device, including sending multiple first RS-FEC blocks by a first transmitter, receiving an UNBOND set by a receiver, waking up a second transmitter through a lane adapter state machine (LASM) when the receiver receives the UNBOND set, sending a training sequence by the second transmitter, sending a specific mode sequence by the second transmitter after sending the training sequence, determining whether the current RS-FEC block to be sent by the first transmitter is a DESKEW block, if it is determined that the current RS-FEC block is a DESKEW block, stopping sending the specific mode sequence, and sending multiple second RS-FEC blocks by the first transmitter and the second transmitter.

[0011] An embodiment provides a universal serial bus (USB) device, including a receiver, a first transmitter, a second transmitter, and a controller coupled to the receiver, the first transmitter, and the second transmitter. The receiver is used to receive an UNBOND set. The first transmitter is used to transmit multiple first RS-FEC blocks and multiple second RS-FEC blocks. The second transmitter is used to send a training sequence, a specific mode sequence, and multiple second RS-FEC blocks. The controller is used to implement a lane adapter state machine (LASM) and wake up the second transmitter through LASM when the receiver receives an UNBOND set. The first transmitter determines whether the current RS-FEC block to be sent by the first transmitter is a DESKEW block.

[0012] These and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments illustrated in the various drawings and figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A USB system according to an embodiment of the present invention is shown.

[0014] Figure 2 Shown by Figure 1 Flowchart of a link conversion method implemented by a USB system.

[0015] Figure 3 Show Figure 1 An embodiment of a USB system converted from one transmitter to two transmitters.

[0016] Figure 4 A schematic diagram showing a USB system according to another embodiment of the present invention.

[0017] Figure 5Shown by Figure 4 Flowchart of a link conversion method implemented by a USB system.

[0018] Figure 6 Conceptually show Figure 4 An embodiment of a USB system converted from one transmitter to two transmitters. DETAILED DESCRIPTION

[0019] For terms and technologies not specifically described, reference may be made to wireless communication standard documents (eg, USB specifications) issued prior to this specification.

[0020] In this specification, technical features described separately in one drawing may be implemented separately or simultaneously.

[0021] USB4 is similar to earlier versions of USB in that it is a cable bus that supports data exchange between a host computer and multiple, simultaneously accessible peripherals. However, USB4 also allows the host to set up data exchange between compatible peripherals. Connected peripherals share bandwidth configured by the host. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are running.

[0022] When configured through the USB Type-C connector interface, USB4 functionally replaces USB 3.2 while retaining the USB 2.0 bus running in parallel. Enhanced SuperSpeed ​​USB defined in the USB 3.2 specification remains the basic architecture for USB data transfer on the USB4 fabric. USB4 differs from USB 3.2 in that USB4 is a connection-oriented channel architecture designed to combine multiple protocols onto a single physical interface in order to dynamically share the total speed and performance of the USB4 fabric. USB4 allows USB data transfer to run in parallel with other independent protocols specific to display, load / store, and host-to-host interfaces. In addition, USB4 extends performance from 20Gbps (Gen 2×2) of USB 3.2 to 80Gbps (Gen 4×2) on the same dual-channel, dual-simplex architecture.

[0023] Figure 1The USB system 100 of the embodiment is shown. The USB system 100 has a controller 150 coupled to four links. For the purpose of illustration, two links can be configured as transmitters 110 and 120, and the other two links can be configured as receivers 130 and 140. The first transmitter 110 is used to send a plurality of first RS-FEC blocks to the USB device 150. The second transmitter 120 is used to send a training sequence and a specific pattern sequence to the USB device 150. The controller 130 is used to determine the number of sets in the first RS-FEC block sent by the first transmitter when the first transmitter 120 sends the training sequence and the specific pattern sequence. The second transmitter completes the sending of the training sequence, and generates a specific pattern sequence according to the number of sets in the first RS-FEC block sent by the first transmitter and the total number of sets in the first RS-FEC block. The controller 130 can implement a channel adapter state machine (LASM) 140 to determine the current state (e.g., CL0 state) of the transmitters 110 and 120.

[0024] However, the number of transmitters and receivers is not limited thereto. One of the transmitters 110 or 120 may be configured as a receiver, so that the USB system 100 will have three receivers and one transmitter. On the other hand, one of the receivers 130 or 140 may be configured as a transmitter, so that the USB system 100 will have three transmitters and one receiver. Therefore, according to the USB4 specification, there are 4 links in total, and the number of transmitters may be 1, 2, or 3; the number of receivers may also be 1, 2, or 3.

[0025] In some embodiments, the first transmitter 110 and the second transmitter 120 may each include an ordered set (OS) generator and a training sequence (TS) generator. The OS generator may generate the first RS-FEC block and the second RS-FEC block, and the TS generator may generate the training sequence.

[0026] The USB4 specification specifies that the logical layer adopts Reed-Solomon forward error-correction code (RS-FEC), and that the adapter should support RS-FEC at all speeds. The RS-FEC block is an error correction code block that can improve the reliability and performance of USB data transmission. It works by adding additional bits to the data stream for error detection and correction. RS-FEC blocks are implemented in the USB 3.2 and USB 4.0 standards, and they can reduce the bit error rate and increase the effective throughput of the USB system. The RS-FEC block is particularly useful for high-speed and long-distance USB connections, where noise and interference may cause data corruption.

[0027] USB link training is the process that occurs when a USB device is first connected to a USB host. The purpose of link training is to establish a high-speed connection between the device and the host. It may involve a series of steps, including device discovery, link negotiation, and link training. Device discovery is the process where the host and device exchange information to identify each other. Link negotiation is the process where the host and device agree on the highest possible link speed that they can both support. Link training is the process where the host and device exchange data to ensure that they can communicate at the agreed-upon link speed.

[0028] In the USB4 specification, a training sequence for link training is implemented to establish communication between a transmitter and a receiver, and more specifically, to negotiate link parameters (e.g., optimal link speed, lane count, and encoding scheme) and establish a connection. The training sequence is sent by the transmitter and used by the receiver to determine the channel characteristics and adjust its parameters accordingly. The training sequence is typically a known pattern that is repeated multiple times during the link training process.

[0029] The Lane Adapter State Machine (LASM) is used in the context of USB4 link initialization. It describes the behavior of the logical link layer during the connection sequence. The sequence includes the following steps: the link partner makes the initial connection during CLd state entry (channel initialization), followed by channel configuration, link training, and finally link establishment.

[0030] Figure 2 The flowchart of the link conversion method 200 implemented by the USB system 100 is shown. The method 200 is particularly suitable for the scenario where the number of transmitters increases, that is, the scenario where the receiver has switched to the second transmitter 120. The method 200 includes the following steps:

[0031] S202: The first transmitter 110 sends a first RS-FEC block;

[0032] S204: The second transmitter 120 sends a training sequence;

[0033] S206: When the second transmitter 120 completes sending the training sequence, determine the number of sets in the first RS-FEC block sent by the first transmitter 110;

[0034] S208: The second transmitter 120 generates a specific pattern sequence according to the number of sets in the first RS-FEC block sent by the first transmitter 110 and the total number of sets in the first RS-FEC block; and

[0035] S210: The second transmitter 120 sends a specific pattern sequence.

[0036] Figure 3And the following relevant paragraphs describe the specific implementation of method 200.

[0037] In some embodiments, the controller 130 may be configured to determine the number of sets in the first RS-FEC block that the first transmitter 110 has transmitted when the second transmitter 120 completes transmitting the training sequence.

[0038] In some embodiments, the specific pattern sequence that fills the blanking period can be a DESKEW.0 ordered set as specified in the USB4 specification.

[0039] Please also refer to Figure 1 and Figure 3 . Figure 3 An embodiment of the USB system 100 is shown in which one transmitter is converted to two transmitters. When sending the first RS-FEC block 310 to the USB device 150, the first transmitter 110 is in the committed link 0 (CL0) state and the second transmitter 120 is in the training state. When the LASM 140 in the controller 130 wakes up the second transmitter 120, when the transmitter 120 recovers from the idle state, the second transmitter 120 will start sending the training sequence 340 to the USB device 150. When the second transmitter 120 is synchronized with the USB device 150, a link is established.

[0040] However, according to the USB4 specification, the second transmitter 120 must send RS-FEC blocks synchronously with the first transmitter 110. Therefore, the second transmitter 120 may need to wait until the first transmitter 110 finishes sending the current first RS-FEC block 310. While the second transmitter 120 is waiting, it can send a specific pattern sequence 330 (e.g., a DESKEW.0 ordered set) to fill the blanking period. The number of sets in the specific pattern sequence 330 can be determined by subtracting the number of sets in the first RS-FEC block 310 that the first transmitter 110 has already sent from the total number of sets in the first RS-FEC block 310.

[0041] For example, each first RS-FEC block 310 may be defined as including 126 sets. When the second transmitter 120 starts to send the specific pattern sequence 330, the first transmitter 110 may currently be sending the 31st set in the first RS-FEC block 310. Then, the controller 130 may decide that the second transmitter 120 needs to send 95 (=126-31) sets of the specific pattern sequence 330 to fill the blanking period. At the end of the transmission of the specific pattern sequence 330, the second transmitter 120 enters the CL0 state (i.e., starts), and the first transmitter 110 and the second transmitter 120 will synchronously send the second RS-FEC block 320. That is, the second RS-FEC block 320 sent by the first transmitter 110 must be aligned with the second RS-FEC block 320 sent by the second transmitter 120. Therefore, the link transition is completed.

[0042] It should be noted that each second RS-FEC block 320 includes half the number of sets in each first RS-FEC block 310. In other words, when two transmitters transmit data simultaneously, each second RS-FEC block 320 includes 63 (=126 / 2) sets. Therefore, the first RS-FEC block 310 and the second RS-FEC block 320 contain substantially the same amount of data. Since these data are now transmitted by two transmitters (i.e., transmitters 110 and 120), the transmission speed can be doubled to reduce the transmission time.

[0043] In some embodiments, a third transmitter can be introduced. The same method can be applied to start the third transmitter. In this case, when the three transmitters send data simultaneously, the third RS-FEC block will include 42 (=126 / 3) sets. Compared with a single active transmitter, the transmission speed can be increased by three times.

[0044] Figure 4A USB system 400 of another embodiment is shown. The USB system 400 has a controller 450 coupled to four links. For the purpose of illustration, two links may be configured as transmitters 410 and 420, and the other two links may be configured as receivers 430 and 440. Receivers 430 and 440 may each receive an UNBOND set from a USB device 470. The first transmitter 410 is used to transmit a plurality of first RS-FEC blocks and a plurality of second RS-FEC blocks to the USB device 470. The second transmitter 420 is used to transmit a training sequence, a specific pattern sequence, and a plurality of second RS-FEC blocks. The controller 450 is used to implement a channel adapter state machine (LASM) 460, and to wake up the second transmitter 420 according to the LASM 460 when the receiver 430 receives the UNBOND set. The first transmitter 410 may determine whether the current RS-FEC block to be transmitted by the first transmitter 410 is a DESKEW block. The USB device 470 may be considered as a USB device being synchronized with the USB system 400. The training sequence is used to synchronize the second transmitter 420 with the receiver of the USB device 470 .

[0045] However, the number of transmitters and receivers is not limited thereto. One of the transmitters 410 or 420 may be configured as a receiver, so that the USB system 400 will have three receivers and one transmitter. On the other hand, one of the receivers 430 or 440 may be configured as a transmitter, so that the USB system 100 will have three transmitters and one receiver. Therefore, according to the USB4 specification, there are 4 links in total, and the number of transmitters may be 1, 2, or 3; the number of receivers may also be 1, 2, or 3.

[0046] In some embodiments, the first transmitter 410 and the second transmitter 420 each include an ordered set (OS) generator and a training sequence (TS) generator. The OS generator is used to generate a plurality of first RS-FEC blocks and a plurality of second RS-FEC blocks, and the TS generator is used to generate a training sequence.

[0047] The functions of LASM 460 are similar to those of LASM 140. The description will not be repeated here.

[0048] Figure 5 The flowchart of the link conversion method 500 implemented by the USB system 400 is shown. The method 500 is particularly suitable for the scenario where the number of transmitters increases, that is, the scenario where the receiver has switched to the second transmitter 420. The method 500 includes the following steps:

[0049] S502: The first transmitter 410 sends a plurality of first RS-FEC blocks;

[0050] S504: The receiver 430 receives the UNBOND set;

[0051] S506: When the receiver 430 receives the UNBOND set, the controller 450 wakes up the second transmitter 420 according to the LASM 460;

[0052] S508: The second transmitter 420 sends a training sequence;

[0053] S510: After completing the sending of the training sequence, the second transmitter 420 sends a specific pattern sequence;

[0054] S512: Determine whether the current RS-FEC block sent by the first transmitter 410 is a DESKEW block; if it is a DESKEW block, proceed to S514; if not, return to S510;

[0055] S514: The second transmitter 420 stops sending the specific pattern sequence; and

[0056] S516: The first transmitter 410 and the second transmitter 420 send multiple second RS-FEC blocks.

[0057] Figure 6 The following related paragraphs describe specific implementations of method 500.

[0058] In some embodiments, whether the current RS-FEC block to be transmitted by the first transmitter 410 is a DESKEW block may be determined by the first transmitter 410 according to the boundary of the current RS-FEC block.

[0059] Please also refer to Figure 4 and Figure 6 . Figure 6An embodiment in which the USB system 400 is converted from one transmitter to two transmitters is shown. When the first transmitter 410 sends the first RS-FEC block 610 in the CL0 state, the receiver 430 receives the UNBOND set. The UNBOND set is a signal for LASM 460 to wake up the second transmitter 420. Once the second transmitter 420 wakes up and enters the training state according to LASM 460, the second transmitter 420 will start sending the training sequence 640. When the second transmitter 420 is synchronized with the receiver of the USB device 470, the second transmitter 420 completes sending the training sequence 640 and starts sending the specific mode sequence 630 (e.g., DESKEW.0 ordered set). At this point, the first transmitter 410 can prepare to send the second RS-FEC block 620. At the same time, the first transmitter 410 can actively monitor and detect the boundary of the first block (i.e., DESKEW block) in the second RS-FEC block 620 sent by the first transmitter 410. It should be noted that the DESKEW block is different from the DESKEW.0 ordered set in the USB4 specification. In this embodiment, DESKEW is the name of the packet of the first block in the second RS-FEC block 620. In contrast, RS-FEC describes the encoding scheme of the blocks in transit.

[0060] When the boundary of the DESKEW block is detected in the queue of the first transmitter 410, the second transmitter 420 will enter the CL0 state and send the DESKEW block synchronously with the first transmitter 410. That is, the boundary blocks of the DESKEW block are aligned. In other words, the first transmitter 410 and the second transmitter 420 will synchronously send the DESKEW block and the subsequent second RS-FEC block 620. At this point, the link conversion is completed.

[0061] In some embodiments, the first transmitter 410 may use the index number of the RS-FEC block to determine whether the next RS-FEC block to be transmitted is a DESKEW block. However, other determination methods are also included, and the present invention is not limited thereto.

[0062] In some embodiments, when only a single transmitter transmits data, the first RS-FEC block 610 may be defined to include 126 sets. When two transmitters transmit data simultaneously, the second RS-FEC block 620 may include 63 (=126 / 2) sets.

[0063] In some embodiments, a third transmitter may be introduced. The same method as above may be applied to start the third transmitter. In this case, when the three transmitters send data simultaneously, the third RS-FEC block will include 42 (=126 / 3) sets. Compared with a single active transmitter, the transmission speed can be increased three times.

[0064] The various illustrative elements, logic, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the implementation disclosed herein may be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. The interchangeability of hardware, firmware, and software has been generally described in terms of functionality, and is shown in the various illustrative elements, blocks, modules, circuits, and processes described above. Whether such functions are implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the entire system.

[0065] The hardware and data processing devices used to implement the various illustrative elements, logic, logic blocks, modules and circuits described in conjunction with the aspects disclosed herein can be implemented or executed with a general-purpose single-chip processor or multiple chips. Processors, digital signal processors (digital signal processors, referred to as DSP), application specific integrated circuits (application specific integrated circuits, referred to as ASIC), field programmable gate arrays (field programmable gate arrays, referred to as FPGA) or other programmable logic devices (programmable logic devices, referred to as PLD), discrete gates or transistor logic, discrete hardware elements or any combination thereof are intended to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processing, operations and methods can be performed by circuits specific to a given function.

[0066] The terms used in the description of the various embodiments described herein are only for the purpose of describing a specific embodiment and are not intended to be limiting. As used in the description of the various described embodiments and the appended claims, the singular forms "one", "an" and "the" are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more related listed items. It should also be understood that the terms "include", "comprise", "comprises" and / or "comprising" when used in this specification specify the existence of stated features, integers, steps, operations, elements and / or elements, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, elements and / or combinations thereof.

[0067] In addition, in the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still collaborate or interact with each other.

[0068] As mentioned above, in some aspects, the realization of the subject matter described in this specification can be implemented as software.For example, the various functions of the elements disclosed herein or the various blocks or steps of the methods, operations, processes or algorithms disclosed herein can be implemented as one or more modules of one or more computer programs.Such a computer program may include non-transitory processor executable or computer executable instructions encoded on one or more tangible processor-readable or computer-readable storage media, for executing or controlling its operation by the data processing device of the elements including the equipment described herein.As an example and not limitation, such storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that can be used to store program code in the form of instructions or data structures.The above combination should also be included in the scope of storage media.

[0069] Various modifications to the embodiments described in this disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Therefore, the claims are not intended to be limited to the embodiments shown herein, but should be consistent with the broadest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0070] In addition, various features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually in multiple implementations or in any suitable sub-combination. Thus, while features may be described above as functioning in a particular combination, and even initially claimed, one or more features from the claimed combination may be deleted from the claimed combination in some cases, and the claimed combination may be directed to a sub-combination or variants of a sub-combination.

[0071] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in a continuous order, or performing all the operations shown, to achieve the desired result. In addition, the accompanying drawings may schematically depict another example process in the form of a flow chart. However, other operations not depicted may be incorporated into the schematically illustrated example process. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. In certain cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system elements in the described implementation should not be understood as requiring such separation in all implementations, and it should be understood that the described program elements and systems can generally be integrated together in a single software product or packaged into multiple software products. In addition, other embodiments are also within the appended claims. In some cases, the actions recorded in the claims may be performed in different orders and still achieve the desired result.

[0072] Those skilled in the art will readily observe that various modifications and changes can be made to the apparatus and method while retaining the teachings of the present invention.Therefore, the above disclosure should be interpreted as being limited only by the scope and limits of the claims.

Claims

1. A link conversion method in a universal serial bus device, comprising: Sending a plurality of first Reed-Solomon forward error correction code blocks by a first transmitter; receiving a start signal via a receiver; When the receiver receives the start signal, starting the second transmitter according to the channel adapter state machine; The second transmitter sends a training sequence; After sending the training sequence, the second transmitter sends a specific pattern sequence; determining whether a current Reed-Solomon forward error correction code block sent by the first transmitter is a timing correction block; If it is determined that the current Reed-Solomon forward error correction code block is the DESKEW block, stopping sending the specific pattern sequence; and A plurality of second Reed-Solomon forward error correction code blocks are transmitted by the first transmitter and the second transmitter.

2. The link conversion method in a universal serial bus device according to claim 1, characterized in that: Determining whether the current Reed-Solomon FEC code block sent by the first transmitter is the timing correction block is performed by detecting the boundary of the current Reed-Solomon FEC code block.

3. The link conversion method in a universal serial bus device according to claim 1, characterized in that: The plurality of second Reed-Solomon forward error correction code blocks are simultaneously transmitted by the first transmitter and the second transmitter.

4. The link conversion method in a universal serial bus device according to claim 1, characterized in that: The plurality of first Reed-Solomon forward error correction code blocks are sent when the first transmitter is in the committed link 0 state, and the plurality of second Reed-Solomon forward error correction code blocks are sent when the first transmitter and the second transmitter are in the committed link 0 state.

5. The link conversion method in a universal serial bus device according to claim 1, characterized in that: The training sequence is sent when the second transmitter is in a training state.

6. The link conversion method in a universal serial bus device according to claim 1, characterized in that: The first block in the sequence of the plurality of second Reed-Solomon forward error correction code blocks is the DESKEW block.

7. The link conversion method in a universal serial bus device according to claim 1, characterized in that: When the second transmitter wakes up from an idle state, the second transmitter starts transmitting the training sequence.

8. The link conversion method in a universal serial bus device according to claim 1, characterized in that: The training sequence synchronizes the second transmitter with a receiver of another universal serial bus device.

9. The link conversion method in a universal serial bus device according to claim 1, characterized in that: Each of the first transmitter and the second transmitter comprises: an ordered set generator configured to generate the plurality of first Reed-Solomon forward error correction code blocks and the plurality of second Reed-Solomon forward error correction code blocks; and The training sequence generator is configured to generate the training sequence.

10. The link conversion method in a universal serial bus device according to claim 1, characterized in that: The first transmitter and the second transmitter are guided by the channel adapter state machine to change states.

11. A universal serial bus device, comprising: A receiver configured to receive a start signal; A first transmitter configured to transmit a plurality of first Reed-Solomon forward error correction code blocks and a plurality of second Reed-Solomon forward error correction code blocks; a second transmitter configured to transmit a training sequence, a specific pattern sequence, and a plurality of second Reed-Solomon forward error correction code blocks; as well as a controller coupled to the receiver, the first transmitter and the second transmitter, and configured to: Implement the channel adapter state machine; as well as When the receiver receives the start signal, the channel adapter state machine wakes up the second transmitter; The first transmitter determines whether a current Reed-Solomon forward error correction code block sent by the first transmitter is a timing correction block.

12. The universal serial bus device according to claim 11, characterized in that Determining whether the current Reed-Solomon FEC code block sent by the first transmitter is the timing correction block is performed by detecting the boundary of the current Reed-Solomon FEC code block.

13. The universal serial bus device according to claim 11, characterized in that: The plurality of second Reed-Solomon forward error correction code blocks are simultaneously transmitted by the first transmitter and the second transmitter.

14. The universal serial bus device according to claim 11, characterized in that: The plurality of first Reed-Solomon forward error correction code blocks are sent when the first transmitter is in the committed link 0 state, and the plurality of second Reed-Solomon forward error correction code blocks are sent when the first transmitter and the second transmitter are in the committed link 0 state.

15. The universal serial bus device according to claim 11, characterized in that: The training sequence is sent when the second transmitter is in a training state.

16. The universal serial bus device according to claim 11, characterized in that: A first block in the sequence of the plurality of second Reed-Solomon forward error correction code blocks is the timing correction block.

17. The universal serial bus device according to claim 11, characterized in that: When the second transmitter wakes up from an idle state, the second transmitter starts transmitting the training sequence.

18. The universal serial bus device according to claim 11, characterized in that: The training sequence synchronizes the second transmitter with a receiver of another universal serial bus device.

19. The universal serial bus device according to claim 11, characterized in that: Each of the first transmitter and the second transmitter comprises: an ordered set generator configured to generate the plurality of first Reed-Solomon forward error correction code blocks and the plurality of second Reed-Solomon forward error correction code blocks; and The training sequence generator is configured to generate the training sequence.

20. The universal serial bus device according to claim 11, characterized in that The first transmitter and the second transmitter are directed by the channel adapter state machine to change states.

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