Radar signal modulation mode identification method and device, electronic equipment and storage medium

Abstract

The invention relates to a radar signal modulation mode identification method and device, electronic equipment and a storage medium, and the method comprises the steps: converting a radar signal into a two-dimensional time-frequency graph; extracting local features in the two-dimensional time-frequency graph, and extracting different features in the two-dimensional time-frequency graph; compressing the local features and the different features into a target range; obtaining a result meeting a preset integration condition, and mapping elements in the input feature vector into probability distribution; integrating the local features, the different features, the sampling feature map, the result and the probability distribution, and generating a classification result of the features according to a decision result; and based on the written RTL code, integrating the classification result to the target CNN network, so as to identify a CNN algorithm-based radar signal modulation mode on a hardware platform by using the comparison data of the radar signal. Therefore, the problems that the optimal performance and resource utilization rate are difficult to obtain, the delay of each level is difficult to deeply optimize and the performance bottleneck exists in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the technical field of signal recognition based on artificial neural networks and its hardware acceleration, and in particular to a radar signal modulation mode recognition method, device, electronic device and storage medium. Background Art

[0002] Radar modulation signal recognition has broad application prospects in many fields such as military, communication, aerospace, unmanned driving, meteorological monitoring, and medical imaging. Its main functions include enhancing the anti-interference ability of radar systems, improving the accuracy of target detection and classification, ensuring the security of communication and spectrum management, and providing real-time environmental perception and response capabilities for automated systems. These applications not only promote the development of radar technology, but also provide technical support for the modernization process of many industries. In the recognition of the modulation mode of radar signals, traditional methods are usually based on manual feature extraction and classification through classical classifiers, which has high computational complexity and limited recognition accuracy. Since the convolutional neural network (CNN) was proposed, it has performed well in image classification, target detection, semantic segmentation and other tasks based on its ability to process two-dimensional image data. Radar signals can generate time-frequency images through short-time Fourier transform (STFT) or wavelet transform, which are similar to two-dimensional images. Therefore, CNN can extract complex features from these time-frequency images to identify different modulation modes.

[0003] In the actual application of radar signal processing, modulation recognition needs to respond as quickly as possible, especially in scenarios such as electronic warfare, drone control, and spectrum management that require real-time analysis and decision-making, where fast processing is crucial. Compared with the traditional method of implementing CNN through software programming languages ​​on a central processing unit (CPU) or graphics processing unit (GPU), hardware methods such as field-programmable gate arrays (FPGA) have advantages in implementing convolutional neural networks. By processing operations such as convolution, pooling, and fully connected layers in parallel, the inference speed of CNN is greatly improved; it has low power consumption characteristics and is very suitable for deployment in embedded systems or edge computing devices.

[0004] In the related technology, there are two ways to implement CNN through FPGA. One way is to convert C++ or python code into hardware implementation through high-level synthesis (HLS) tools; the other way is to use hardware description languages ​​​​such as Verilog HDL to directly control the hardware at the register transfer level (RTL) to implement network design.

[0005] However, related technologies have limited optimization and control over hardware resources, making it difficult to achieve optimal performance and resource utilization. In addition, the hardware design generated by the HLS tool is usually difficult to deeply optimize to each level of latency due to its high level of abstraction. Especially in applications with high real-time requirements, there may be performance bottlenecks. The hardware description language allows developers to design low-latency hardware circuits, but it is only suitable for radar signal processing scenarios that are sensitive to latency, which urgently needs to be improved. Summary of the invention

[0006] The present application provides a radar signal modulation mode identification method, device, electronic device and storage medium to solve the problem that the optimization and control of hardware resources in related technologies are relatively limited, it is difficult to obtain the optimal performance and resource utilization, it is difficult to deeply optimize the delay at each level, and there is a performance bottleneck.

[0007] The first aspect of the present application provides a radar signal modulation mode recognition method, which is applied to a convolutional neural network model. The method includes the following steps: adding Gaussian white noise to a one-dimensional radar signal to generate a radar signal that meets a preset noise condition, and converting the radar signal into a two-dimensional time-frequency diagram; extracting local features in the two-dimensional time-frequency diagram, and extracting different features in the two-dimensional time-frequency diagram; compressing the local features and the different features into a target range to downsample the output feature map to obtain a sampled feature map that meets the preset dimensional condition; obtaining a result that meets the preset integration condition, and mapping the elements in the input feature vector into a probability distribution; integrating the local features, the different features, the sampled feature map, the results and the probability distribution to generate a decision result, and generating a feature classification result based on the decision result; based on the written RTL code, integrating the classification result into the target CNN network to use the comparison data of the radar signal to identify the radar signal modulation mode based on the CNN algorithm on the hardware platform.

[0008] Optionally, in one embodiment of the present application, the extracting of local features in the two-dimensional time-frequency graph and extracting different features of the two-dimensional time-frequency graph include: comparing resource occupancy rates and calculation accuracy under different bit floating-point numbers to determine a floating-point number bit width that meets preset suitable conditions, and using the floating-point number bit width that meets preset suitable conditions to determine the local features in the two-dimensional time-frequency graph; extracting a local area corresponding to a convolution kernel sliding window, and calculating the convolution of the convolution kernel and the two-dimensional time-frequency graph in the local area to determine the different features based on the convolution.

[0009] Optionally, in one embodiment of the present application, before comparing the resource occupancy rate and calculation accuracy of floating-point numbers of different bits, it also includes: obtaining the sign bit, exponent bit and mantissa bit of the floating-point number, and determining whether the sign bit is opposite and whether the exponent bit and mantissa bit are equal; if the sign bit is opposite and the exponent bit and mantissa bit are equal, outputting a zero value, otherwise comparing whether the exponent satisfies a preset exponent same condition; if the exponent satisfies the preset exponent same condition, determining whether the sign of the floating-point number satisfies the preset sign same condition, otherwise performing a right shift of the mantissa to align the exponent; if the sign satisfies the preset sign same condition, performing a mantissa addition action of the floating-point number, otherwise performing a mantissa subtraction action of the floating-point number, left-shifting the mantissa and adjusting the exponent until a preset normalization standard condition is met.

[0010] Optionally, in one embodiment of the present application, before comparing the resource utilization and calculation accuracy under different bit floating-point numbers, it also includes: respectively determining whether the sign bit, the exponent bit and the mantissa bit have the zero value; if the sign bit, the exponent bit and the mantissa bit have the zero value, outputting the zero value, otherwise performing an XOR operation on the sign bit of the floating-point number, performing an exponential addition operation on the floating-point number, and performing a mantissa multiplication operation on the floating-point number, shifting the mantissa left and adjusting the exponent until a preset normalization standard condition is met.

[0011] Optionally, in one embodiment of the present application, the calculation formula for mapping the elements in the input feature vector to the probability distribution is:

[0012]

[0013] Among them, x i is the i-th value of the input feature, S(x i ) is the Softmax output of the i-th value, and N is the length of the input vector.

[0014] Optionally, in one embodiment of the present application, before using the comparison data to identify the modulation mode of the radar signal, it also includes: training a convolutional neural network model using training samples to determine a trained convolutional neural network model; comparing the trained convolutional neural network model with a target model to generate the comparison data.

[0015] The second aspect of the present application provides a radar signal modulation mode identification device, which is applied to a convolutional neural network model, and the device includes: a conversion module, which is used to add Gaussian white noise to a one-dimensional radar signal to generate a radar signal that meets a preset noise condition, and convert the radar signal into a two-dimensional time-frequency diagram; an extraction module, which is used to extract different features in the two-dimensional time-frequency diagram; an acquisition module, which is used to compress the local features and the different features into a target range to downsample the output feature map to obtain a sampled feature map that meets the preset dimensional condition; a mapping module, which is used to obtain a result that meets the preset integration condition and maps the elements in the input feature vector to a probability distribution; a generation module, which is used to integrate the local features, the different features, the sampled feature map, the results and the probability distribution to generate a decision result, and generate a feature classification result based on the decision result; an identification module, which is used to integrate the classification result into a target CNN network based on a written RTL code, so as to use the comparison data of the radar signal to identify the radar signal modulation mode based on the CNN algorithm on the hardware platform.

[0016] Optionally, in one embodiment of the present application, the conversion module includes: a comparison unit, used to compare resource occupancy rates and calculation accuracy under different bit floating-point numbers to determine the floating-point bit width of the convolution layer that meets preset suitable conditions, and use the floating-point bit width that meets the preset suitable conditions to determine the local features in the two-dimensional time-frequency graph; a determination unit, used to extract the local area corresponding to the convolution kernel sliding window, and calculate the convolution of the convolution kernel and the two-dimensional time-frequency graph in the local area to determine the different features according to the convolution.

[0017] Optionally, in one embodiment of the present application, it also includes: a first judgment module, used to obtain the sign bit, exponent bit and mantissa bit of the floating-point number, and judge whether the sign bit is opposite and whether the exponent bit and mantissa bit are equal; an output module, used to output a zero value when the sign bit is opposite and the exponent bit and mantissa bit are equal, otherwise compare whether the exponent satisfies a preset exponent same condition; a second judgment module, used to judge whether the sign of the floating-point number satisfies a preset sign same condition when the exponent satisfies the preset exponent same condition, otherwise execute a right shift of the mantissa to align the exponent; a first execution module, used to execute a mantissa addition action of the floating-point number when the sign satisfies the preset sign same condition, otherwise execute a mantissa subtraction action of the floating-point number, left-shift the mantissa and adjust the exponent until a preset normalization standard condition is met.

[0018] Optionally, in one embodiment of the present application, it also includes: a third judgment module, used to respectively judge whether the sign bit, the exponent bit and the mantissa bit have the zero value; a second execution module, used to output the zero value when the sign bit, the exponent bit and the mantissa bit have the zero value, otherwise perform an XOR operation on the sign bit of the floating-point number, perform an exponent addition operation on the floating-point number, and perform a mantissa multiplication operation on the floating-point number, left-shift the mantissa and adjust the exponent until the preset normalization standard condition is met.

[0019] Optionally, in one embodiment of the present application, the calculation formula for mapping the elements in the input feature vector to the probability distribution is:

[0020]

[0021] Among them, x i is the i-th value of the input feature, S(x i ) is the Softmax output of the i-th value, and N is the length of the input vector.

[0022] Optionally, in one embodiment of the present application, it also includes: a training module, used to train a convolutional neural network model using training samples before using comparison data to identify the modulation mode of the radar signal to determine the trained convolutional neural network model; a comparison module, used to compare the trained convolutional neural network model with the target model to generate the comparison data.

[0023] A third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the radar signal modulation mode identification method as described in the above embodiment.

[0024] The fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program. When the program is executed by a processor, it implements the above radar signal modulation mode identification method.

[0025] The fifth aspect of the present application provides a computer program product, which stores a computer program that, when executed by a processor, implements the above radar signal modulation mode identification method.

[0026] The embodiment of the present application can convert a one-dimensional radar signal into two-dimensional image data that can be processed by a convolutional neural network, and is designed by processing feature extraction through a convolutional layer, controlling the output range through an activation function, reducing the dimension through a pooling layer, generating probability distribution through a Softmax layer, and performing classification through a fully connected layer. Floating-point operation optimization, approximate calculation of activation functions, and division operation optimization of the SoftMax layer are added to the algorithm design. The system performance is further improved through parallel processing and pipeline design. The modular design of each part enables the system to be reused, which is suitable for implementation on a resource-constrained hardware platform such as FPGA, and has advantages in accuracy and delay time. Thus, the problem that the optimization and control of hardware resources by related technologies are relatively limited, it is difficult to obtain the optimal performance and resource utilization, it is difficult to deeply optimize the delay at each level, and there is a performance bottleneck is solved.

[0027] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A flowchart of a radar signal modulation mode identification method provided according to an embodiment of the present application;

[0030] Figure 2 A design flow chart according to an embodiment of the present application;

[0031] Figure 3 A diagram showing a time-frequency conversion result according to an embodiment of the present application;

[0032] Figure 4 A schematic diagram of a convolution operation according to an embodiment of the present application;

[0033] Figure 5 Schematic diagram of a convolution calculation module according to one embodiment of the present application;

[0034] Figure 6 is a flow chart of an adder according to an embodiment of the present application;

[0035] Figure 7 is a flow chart of a multiplier according to an embodiment of the present application;

[0036] Figure 8 is a schematic diagram of a pooling unit according to an embodiment of the present application;

[0037] Figure 9(a)-Figure 9(e) This is a test result diagram according to an embodiment of the present application;

[0038] Fig.10 is a block diagram of a convolutional neural network according to an embodiment of the present application;

[0039] Fig.11 A design flow chart according to an embodiment of the present application;

[0040] Fig.12 A schematic diagram of the structure of a radar signal modulation mode identification device provided according to an embodiment of the present application;

[0041] Fig.13 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0043] The radar signal modulation mode identification method, device, electronic device and storage medium of the embodiment of the present application are described below with reference to the accompanying drawings. In view of the limited optimization and control of hardware resources by the related technologies mentioned in the above background technology, it is difficult to obtain the optimal performance and resource utilization, it is difficult to deeply optimize the delay at each level, and there is a performance bottleneck problem, the present application provides a radar signal modulation mode identification method, in which a one-dimensional radar signal can be converted into two-dimensional image data for processing by a convolutional neural network, and the design is carried out by processing feature extraction through a convolutional layer, controlling the output range through an activation function, reducing the dimension through a pooling layer, generating a probability distribution through a Softmax layer, and performing classification through a fully connected layer, etc., floating point operation optimization, approximate calculation of an activation function, and optimization of division operations of a SoftMax layer are added to the algorithm design, and the system performance is further improved through parallel processing and pipeline design, and the modular design of each part enables the system to be reused, which is suitable for implementation on a resource-limited hardware platform such as FPGA, and has advantages in accuracy and delay time. Thus, the problems that the optimization and control of hardware resources by the related technologies are limited, it is difficult to obtain the optimal performance and resource utilization, it is difficult to deeply optimize the delay at each level, and there is a performance bottleneck are solved.

[0044] Specifically, Figure 1 A schematic flow chart of a radar signal modulation mode identification method provided in an embodiment of the present application.

[0045] like Figure 1 As shown, the radar signal modulation mode identification method includes the following steps:

[0046] In step S101, Gaussian white noise is added to a one-dimensional radar signal to generate a radar signal that meets a preset noise condition, and the radar signal is converted into a two-dimensional time-frequency diagram.

[0047] It can be understood that in order to simulate the interference situation in the actual signal receiving environment, such as Figure 2 As shown, in the embodiment of the present application, Gaussian white noise can be added to the generation of radar signals, and the time-frequency conversion is performed into a two-dimensional time-frequency graph as the input of CNN. Gaussian white noise is a random signal with zero mean and variance σ 2 By adjusting σ, the noise intensity reaches the set SNR value. The noisy signal is transformed from the time domain to the time-frequency domain by short-time Fourier transform (STFT).

[0048] The embodiment of the present application defines three common signals (LFM, Costas, FMCW) and adds Gaussian noise, and generates a time-frequency diagram for each signal through STFT. In the embodiment, the starting frequency of the LFM signal is defined as 0Hz and the duration is 10ms; the Costas signal is defined as 5 frequency steps, the starting frequency is 0Hz, the duration is 10ms, the bandwidth is 100kHz, and the sequence [1 2 4 5 3] represents 5 different frequency steps, stepping in the range of 0 to 20kHz; the starting frequency of the FMCW signal is 10kHz, the bandwidth is 100kHz, and the duration of each chirp (linear frequency modulation signal) is 1 millisecond. At the same time, the standard deviation of the input Gaussian noise is defined as 0.2.

[0049] Perform STFT on each noisy signal and generate a time-frequency graph. The time-frequency graph of each signal displays the relationship between frequency and time in a two-dimensional image. The results are Figure 3 It means that the time-frequency diagram can intuitively show the changes of the three signal frequencies over time.

[0050] Furthermore, the modulation mode of the radar signal in the embodiment of the present application determines its changing characteristics in the time domain and the frequency domain. Different modulation modes usually show different time-frequency characteristics. The modulation modes are respectively normal signal (NS), linear frequency modulation (LFM), two-phase coding (BPSK), nonlinear frequency modulation (NLFM), frequency coding (FSK), four-phase coding (QPSK), frequency modulated continuous wave (FMCW), two-frequency coding, four-frequency coding and Costas coding. Through short-time Fourier transform (STFT), the radar signal can be converted from the time domain to the frequency domain, and a two-dimensional time-frequency diagram can be generated to provide data for the subsequent radar signal modulation mode recognition convolutional neural network.

[0051] The radar signal can be expressed as follows after LFM modulation:

[0052] S(t)=A·sin(2πf C t+Kπt 2 ),

[0053] Where A is the amplitude of the signal, f C is the carrier frequency, K is the modulation rate (the linear change speed of the control frequency), and t is the time variable. The signal is transformed by STFT from the time domain to the time-frequency domain, and the signal is expressed as:

[0054]

[0055] Among them, ω(t-τ) is a sliding window function, which is used to localize the Fourier transform and extract the local characteristics of the signal in time and frequency. In the research and application of radar signal modulation recognition, in order to simulate the interference in the actual signal receiving environment, this application adds Gaussian white noise to the generation of radar signals. Gaussian white noise is a random signal with zero mean and variance σ 2 The signal with added noise is expressed as:

[0056] S N (t) = S (t) + N (t),

[0057] Among them, the noise N(t)~N(0,σ 2 ), the noise intensity can be controlled by setting the standard deviation σ. The signal-to-noise ratio (SNR) of the signal can be controlled by adjusting the noise intensity σ. The signal-to-noise ratio is defined as:

[0058]

[0059] By adjusting σ, the noise intensity reaches the set SNR value. The noisy signal is transformed from the time domain to the time-frequency domain by short-time Fourier transform (STFT), and the linear frequency modulated signal with Gaussian white noise is obtained as follows:

[0060]

[0061] In step S102, local features in the two-dimensional time-frequency graph are extracted, and different features in the two-dimensional time-frequency graph are extracted.

[0062] It is understandable that the input data is convolved to achieve feature extraction. Compared with 32-bit floating point numbers, 16-bit floating point numbers require significantly fewer hardware resources, and 16-bit floating point numbers have higher precision and are suitable for feature extraction of radar modulation mode recognition. Therefore, in the embodiment, 16-bit floating point numbers are used to represent the convolution kernel.

[0063] The multi-convolutional layer module adopts a parallel and modular design, and the processing of each convolution kernel is encapsulated separately in a single convolutional layer module. Parallel operation is achieved by instantiating two single convolutional layer modules. The input is the image data and the 16-bit floating point data of the six convolution kernels. The six convolution kernels are grouped in groups of two and input into the single convolution layer three times in a cycle, that is, the convolution of two convolution kernels with the image is performed each time. Figure 4 Schematic diagram of a convolution operation in one cycle.

[0064] Specifically, in the convolutional neural network of the embodiment of the present application, the convolution layer is responsible for extracting local features in the input time-frequency graph data. Each convolution kernel extracts different features. The convolution layer adopts the idea of ​​modular design and realizes multi-level convolution operations by instantiating a single-layer convolution module.

[0065] The embodiment of the present application adopts a modular design to enable system reuse, which is suitable for implementation on a resource-constrained hardware platform such as FPGA, and has advantages in terms of accuracy and delay time.

[0066] Optionally, in one embodiment of the present application, local features in the two-dimensional time-frequency graph are extracted, and different features of the two-dimensional time-frequency graph are extracted, including: comparing resource occupancy rates and calculation accuracy under different bit floating-point numbers to determine a floating-point number bit width that meets preset suitable conditions, and using the floating-point number bit width that meets preset suitable conditions to determine the local features in the two-dimensional time-frequency graph; extracting a local area corresponding to a convolution kernel sliding window, and calculating the convolution of the convolution kernel and the two-dimensional time-frequency graph in the local area to determine different features according to the convolution.

[0067] It is understandable that when the convolution kernel is designed in the embodiment of the present application, the appropriate floating point bit width of the convolution layer is selected by comparing the resource occupancy rate and calculation accuracy under different bit floating point numbers. In order to achieve higher calculation accuracy and reduce resource occupancy, 32-bit or 16-bit numbers are selected to represent the weights and input data in the convolution layer.

[0068] The multi-convolutional layer module instantiates multiple single-convolutional layer modules, processes multiple convolution kernels simultaneously through parallel design, and generates multiple feature maps through loop operations. The single-convolutional layer module instantiates multiple convolutional unit modules, and uses the region selection module (RF) to extract the local area corresponding to the convolution kernel sliding window, calculates the convolution of a convolution kernel and an image, and outputs the features of the complete image extracted by convolution. The convolutional unit module instantiates the convolution operation module, performs element-by-element multiplication and accumulation of the input image and the convolution kernel, thereby realizing the convolution operation.

[0069] RF(i,j)=x(i:i+M-1,j:j+N-1),

[0070] The more convolution units there are, the higher the parallelism is, but at the same time, more look-up table (LUT) resources are occupied. The number of LUTs increases exponentially in a single or multiple convolution kernel modules. Through experimental comparison, choosing to use a number of convolution calculation units equal to half the number of pixels in a single row in the output feature can achieve high computational efficiency while lowering resource usage.

[0071] The convolution unit module instantiates the convolution calculation module to perform element-by-element multiplication and accumulation of the input image and the convolution kernel to achieve the convolution operation:

[0072]

[0073] Among them, x(i,j) represents the pixel value of the input image, w(m,n) represents the weight of the convolution kernel, y(i,j) represents the pixel value of the output image, and M and N represent the size of the convolution kernel respectively.

[0074] For example, an embodiment of the present application can select a local area of ​​5×5 from the input image. These local areas are the input of the convolution operation, and multiple convolution units are instantiated using the generate statement, each of which is responsible for calculating a portion of the image output. For parallel computing, the number of convolution units is equal to half the width of the output feature map. In the embodiment, the output feature map is 28×28, so 14 convolution units are used, each of which performs a convolution operation based on the input image area and the convolution kernel, and controls the timing of the convolution operation through an internal counter.

[0075] The convolution unit is implemented by instantiating the convolution calculation module. The convolution calculation module (PE) inputs floating point numbers floatA and floatB, and outputs the result of 16-bit floating point data type through instantiating multipliers and adders. Registers are used to save intermediate results to implement pipeline operations to reduce data transmission delays. Figure 5 It is the operation process of PE.

[0076] It should be noted that the preset appropriate conditions can be set by those skilled in the art according to actual conditions and are not specifically limited here.

[0077] Optionally, in one embodiment of the present application, before comparing the resource occupancy rate and calculation accuracy of floating-point numbers of different bits, it also includes: obtaining the sign bit, exponent bit and mantissa bit of the floating-point number, and determining whether the sign bit is opposite and whether the exponent bit and the mantissa bit are equal; if the sign bit is opposite and the exponent bit and the mantissa bit are equal, outputting a zero value, otherwise comparing whether the exponent satisfies a preset exponent same condition; if the exponent satisfies the preset exponent same condition, determining whether the sign of the floating-point number satisfies the preset sign same condition, otherwise performing a right shift of the mantissa to align the exponent; if the sign satisfies the preset sign same condition, performing a mantissa addition action of the floating-point number, otherwise performing a mantissa subtraction action of the floating-point number, shifting the mantissa left and adjusting the exponent until the preset normalization standard condition is met.

[0078] It is understandable that the convolution operation unit is composed of a multiplier and an adder, and the transmission delay is reduced by a pipeline in this module. Floating-point numbers are usually divided into three parts: a sign bit, an exponent bit, and a mantissa bit. Since the exponent bits of floating-point numbers are different and cannot be directly operated, in order to maximize the numerical accuracy of each floating-point number, the present application optimizes the addition operation of floating-point numbers.

[0079] In the actual implementation process, the design steps of the floating point adder in this application are as follows:

[0080] (1) Determine special cases, such as when the input is zero or the sum of opposite numbers results in a zero output.

[0081] (2) Compare the exponents of two floating-point numbers. If they are different, align the exponents by right-shifting the mantissa.

[0082] (3) If the two floating-point numbers have the same sign, their mantissas are added directly; if the signs are different, the mantissas are subtracted, with the larger mantissa minus the smaller mantissa. Carry or borrow situations are also handled.

[0083] (4) Ensure that the result meets the normalization standard of floating-point numbers by shifting the mantissa left and adjusting the exponent.

[0084] For example, in order to correctly perform floating-point addition operations, special cases are first handled. When floatA is 0, floatB is directly returned as the result, and vice versa. If floatA and floatB are opposite numbers, the result is directly zero; then the exponent and mantissa of the floating-point number are extracted. Floating-point numbers follow the IEEE 754 format, with the exponent part stored in bits 14:10 and the mantissa part stored in bits 9:0. The mantissa part contains an implicit 1, so it needs to be added to fractionA and fractionB, that is, they are expanded to fractionA = {1'b1, floatA[9:0]}; exponent alignment is to shift the mantissa with a smaller exponent right by a certain number of bits so that the exponents of the two numbers are the same. For example, when exponentB>exponentA: shift fractionA right so that fractionA and fractionB are aligned; in the mantissa calculation, if the signs are the same, the two mantissas are directly added. If the addition result produces a carry, the result needs to be shifted right by one bit and the exponent increased. When two floating-point numbers have opposite signs, the mantissas need to be subtracted. If the result of the subtraction is negative, it needs to be negated and adjusted; after the mantissas are subtracted, a denormalized number may appear, that is, the highest bit of the mantissa is not 1. Therefore, it is necessary to ensure that the result is renormalized by shifting the mantissa left and reducing the exponent at the same time; the sign bit, the normalized exponent, and the mantissa are concatenated to form the final 16-bit floating-point product. If the exponent value is negative (that is, underflow occurs), the result is set to 0, indicating that the value of the product is too small to be represented. Figure 6 This is the adder operation flow chart.

[0085] It should be noted that the preset index same condition, the preset sign same condition and the preset normalization standard condition can be set by those skilled in the art according to actual conditions and are not specifically limited here.

[0086] Optionally, in one embodiment of the present application, before comparing the resource utilization and calculation accuracy of floating-point numbers of different bits, it also includes: determining whether the sign bit, exponent bit and mantissa bit have zero values ​​respectively; if the sign bit, exponent bit and mantissa bit have zero values, outputting zero values, otherwise performing an XOR operation on the sign bit of the floating-point number, performing an exponential addition operation on the floating-point number, and performing a mantissa multiplication operation on the floating-point number, shifting the mantissa left and adjusting the exponent until the preset normalization standard conditions are met.

[0087] It can be understood that the present application optimizes the multiplication operation of floating-point numbers.

[0088] In the actual implementation process, the design steps of the floating-point multiplier in this application are as follows:

[0089] (1) Determine special cases, such as when the input is zero, the output is zero.

[0090] (2) The sign bit of the result is determined by performing an XOR operation on the sign bits (highest bit) of the two floating-point numbers.

[0091] (3) Add the exponents of the two floating-point numbers. Since the exponent is represented by a bias in floating-point representation, it is necessary to adjust the bias to obtain the correct exponent value.

[0092] (4) In floating-point representation, the mantissa is an implicit normalized number, so the implicit 1 is first added, and the product of the two mantissas is calculated to obtain a larger mantissa for subsequent normalization processing.

[0093] (5) Ensure that the result meets the normalization standard of floating-point numbers by shifting the mantissa left and adjusting the exponent.

[0094] For example, in the implementation of the multiplier, special cases are first handled. If floatA or floatB is 0, the result is directly 0. The sign bit in the multiplier is calculated by the input sign bit XOR: sign = floatA

[15] ^floatB

[15] . The exponents of floatA and floatB are added, and a bias value of 15 is subtracted to ensure that the exponent of the floating-point number remains within the representable range of the IEEE 754 standard, and an additional correction value of 2 is added for precision adjustment. The mantissas of the two floating-point numbers are extracted and an implicit 1 is added to them respectively to form fractionA and fractionB. The two mantissas are then multiplied to obtain a 22-bit mantissa product fraction. The mantissa product is normalized and the highest bit of the result is ensured to be 1 by shifting to the left. The exponent value is adjusted accordingly according to the number of shifts. The sign bit, the normalized exponent, and the mantissa are concatenated to form the final 16-bit floating-point product. Figure 7 This is the multiplier operation flow chart.

[0095] It should be noted that the preset normalization standard conditions can be set by those skilled in the art according to actual conditions and are not specifically limited here.

[0096] In step S103, the local features and different features are compressed into a target range to downsample the output feature map to obtain a sampled feature map that meets a preset dimensionality condition.

[0097] In the actual execution process, the embodiment of the present application can activate the data obtained in the above steps. The activation layer can control the output within a certain range to prevent numerical overflow. The Tanh activation function can compress the input value into the range of [-1,1], which is suitable for processing radar signal modulation recognition, such as a scenario with a large input value range. The output is expressed as:

[0098]

[0099] In order to calculate the index value, the activation function in this application is optimized by an approximate algorithm, and the Tanh activation function result is obtained by using the Taylor expansion approximate calculation method.

[0100]

[0101] The pooling layer downsamples the feature map by average pooling to reduce the data dimension. The pooling operation implemented in this application is fully parallel, that is, the pooling operation of the input data and multiple pooling units is performed simultaneously, which reduces the waiting time of each operation.

[0102] The pooling unit calculates the average value of pixels in the window through optimized floating-point operations.

[0103]

[0104] Among them, P(i,j) is the output after pooling, and Y(i,j) is the feature map data before pooling. In order to optimize resource utilization, pipeline operations are added to the pooling unit module.

[0105] For example, the activation layer is implemented by instantiating an activation function calculation module. At the beginning of the calculation, the absolute value of the input value is checked first. If the absolute value is greater than π / 2, the saturation value ±1 of tanh is directly output; if the input value is equal to π / 2, its exact value is directly output. In the embodiment, the first 4 terms of Taylor expansion are used to approximate the tanh value, and each term is added to the previous cumulative result to form a new cumulative result.

[0106] The pooling layer uses full parallel computing, instantiating 14 pooling units to implement average pooling operations. In the embodiment, each 2×2 area of ​​the input image is traversed for processing through a nested for loop. The size of the input image is 28×28, and the size of the output image after pooling is reduced to 14×14.

[0107] The pooling unit takes the sum of four numbers floatA, floatB, floatC, and floatD as input, adds them up in sequence, and then multiplies the sum by 0.25 to get the average of the four numbers. Registers are inserted in the middle of the calculation to achieve pipeline operation. The calculation process of the pooling unit is as follows: Figure 8 shown.

[0108] The embodiment of the present application includes a three-layer convolution structure, each layer of convolution is followed by an activation function Tanh to introduce nonlinearity, and downsampling is performed through a pooling operation. The reset signal of each layer is controlled by a counter to ensure that each stage is carried out in a predetermined time sequence.

[0109] In step S104, results satisfying preset integration conditions are obtained, and elements in the input feature vector are mapped into probability distribution.

[0110] It can be understood that the Softmax layer in the embodiment of the present application needs to instantiate an exponential calculation module, an adder module, and a reciprocal calculation module for calculation.

[0111] In the actual implementation process, the embodiment of the present application can integrate the convolution layer, activation layer and pooling layer obtained in the above steps into a convolution module to generate a result. The module includes a three-layer convolution structure, each layer of convolution is followed by an activation function Tanh to introduce nonlinearity, and downsampling is performed through a pooling operation. The control of the reset signal of each layer is realized by a counter to ensure that each stage is carried out in a predetermined time sequence.

[0112] In one embodiment of the present application, the function of the Softmax layer is to map the elements in a vector into a probability distribution, and the calculation formula is:

[0113]

[0114] Among them, x i is the i-th value of the input feature, S(x i ) is the Softmax output of the i-th value, and N is the length of the input vector, that is, how many categories there are. The Softmax layer needs to instantiate the exponential calculation module, adder module, and reciprocal calculation module for calculation.

[0115] In the index calculation module, this application uses Taylor expansion to approximate the index value:

[0116]

[0117] The floating-point divider calculation in hardware is relatively slow. In order to speed up the division operation, the Newton-Raphson iteration method is used in this application to calculate the reciprocal:

[0118] x n+1 =x n ·(2-a·x n ),

[0119] Among them, x n is the approximate value of the inverse at the nth iteration; x n+1 It is the new approximate value obtained after the n+1th iteration. First, input the floating point number and extract the mantissa. Use constants P1 and P2 to initialize the first iteration value x1==P1+P2·a. Use the iteration formula to perform iterative calculations to determine whether it converges (x n+1 = = x n ), output the result if convergence occurs, otherwise continue iterating.

[0120] For example, the embodiments of the present application can integrate the above functions into a convolution module to obtain the result. Convolution kernels of different depths are used to perform convolution operations on the input image, and the size of the convolution kernels of each layer is 5×5. The first convolution layer receives a 32×32 input image, uses a convolution kernel with a depth of 6 for convolution, and outputs 6 28×28 feature maps. After the first activation layer Tanh1, the output is 28×28×6, and the output of the first layer average pooling is 14×14×6. The number of convolution kernels in the second layer is 16×6, and 16 10×1 feature maps are output. After the activation layer Tanh2, the output is 10×10×16; the output of the second layer average pooling is 5×5×1. The number of convolution kernels in the third layer is 120×16, and the output is 1×1×120. After the activation layer Tanh3, the output is 1×1×120.

[0121] It should be noted that, in order to ensure the timing, a counter is used to manage the startup time of each layer of modules. The count value of each stage controls the reset signal of each module to ensure that each layer starts running at the appropriate time point.

[0122] After the data is processed through multiple layers, higher precision is required to maintain the accuracy of the classification or regression task. Therefore, in the embodiment, each layer in the fully connected module selects 32-bit floating point numbers for calculation.

[0123] The Softmax layer mainly includes four modules: exponent calculation module (exponent), adder module (floatAdd), multiplier module (floatMult), and reciprocal calculation module (floatReciprocal). First, use multiple parallel exponents to calculate the exponents of all input values. Use floatAdd to gradually add the exponents and calculate the exponential sum. Since parallel calculation may result in different calculation times for different exponents, it is managed by a counter. After each addition, the counter increments until all exponential values ​​are added. After the exponential sum is calculated, start floatReciprocal to calculate the reciprocal. By instantiating floatMult, each exponential value is multiplied by the reciprocal to obtain the final output Softmax value.

[0124] Taylor series is used for approximation in exponent, and the first 7 items are used for approximate calculation in the embodiment.

[0125] The Newton-Raphson iteration method is used to calculate the reciprocal of a floating-point number. The entire process is divided into three stages: initialization, iterative calculation, and convergence judgment. First, the iteration is started by setting the initial value, and then the iteration value is updated in each clock cycle until the convergence condition is met, and finally the result is output.

[0126] (1) Use the enable signal enable to control whether to start the calculation. When enable is low, the module remains in standby mode and is ready to accept new inputs. Reset the acknowledgement signal ack, indicating that the calculation has not yet been completed.

[0127] (2) Extract the mantissa of the input floating point number and use it as a variable in the iterative calculation. Set constants P1 and P2 to and They are used for the initial calculation of the Newton-Raphson iteration method.

[0128] (3) First iteration calculation: calculated by floatMult Calculated by floatAdd module Get the initial approximation X i , calculate X by floatMult i ×Ddash (indicates the current approximation multiplied by the mantissa of the input floating point number). Finally, we get X i+1 =X i +X i ×(1-X i ×Ddash) to update the iteration value.

[0129] (4) After each iteration, the current iteration result mux is determined to be consistent with the new iteration result X. i+1 If they are equal, it means convergence. Setting ack to high can end the iteration and output the result. If they are not converged, mux is updated to the new iteration value X. i+1 , and continue iterating.

[0130] In step S105, local features, different features, sampling feature maps, results and probability distributions are integrated to generate a decision result, and a classification result of the feature is generated based on the decision result.

[0131] It is understandable that the embodiment of the present application can design a fully connected module. The fully connected module is mainly used to integrate the features extracted by the previous layers and make decisions, that is, to perform final inference and classification based on these extracted features. The feature maps of the first few layers are flattened by the designed fully connected layer, and the Tanh activation layer and the Softmax layer are connected respectively. The matrix multiplication operation of the fully connected layer usually requires higher precision. Especially in the last few layers of the network, after the data has been processed by multiple layers, higher precision is required to maintain the accuracy of the classification or regression task.

[0132] The core operation of the fully connected layer is the product of the input vector and the weight matrix. The input vector and the weight matrix are matrix multiplied to obtain the output vector. The matrix multiplication is expressed as follows:

[0133]

[0134] Among them, x j is the input feature vector, W i,j is the element of the weight matrix, b i is the bias, y i is the i-th element of the output vector. Similar to the optimization of floating-point operations in the convolutional layer, the multipliers and adders in the fully connected layer use optimized floating-point operations.

[0135] To improve computational efficiency, the fully connected layer is accelerated by parallelizing matrix multiplication. Multiple multipliers process different input data simultaneously and accumulate the results in a pipelined manner. The calculation of each output node can be completed in a separate accumulator, maximizing the efficiency of parallel processing.

[0136] The output of the fully connected layer is passed to the activation function layer. The activation layer uses the Tanh activation function. The last layer of the fully connected layer is the Softmax layer obtained in the above steps, which converts the output into a probability distribution. The overall process is based on the clock signal for timing control to ensure the correct output of the module.

[0137] In the embodiment of the present application, the matrix multiplication operation of the fully connected layer usually requires higher precision, and 32-bit floating point numbers can be used for calculation. The fully connected layer is accelerated by parallelizing matrix multiplication, and multiple multipliers process different input data at the same time and accumulate the results in a pipeline manner. The calculation of each output node can be completed in a separate accumulator, maximizing the efficiency of parallel processing.

[0138] It should be noted that the fully connected module consists of 2 fully connected layers (FC layers), 1 Tanh activation layer, and 1 Softmax activation layer.

[0139] The input of the FC layer is the feature map and weight matrix (weights) processed by the convolution module. The product of the input and weights is calculated by looping through multiple parallel processing units (PE32) and outputting the calculation result. The traversal method is to process the data from the last input node step by step until the data of the first input node. The PE32 module is similar to the PE module in the convolution layer, and 32-bit floating-point operations are used instead of 16-bit floating-point operations.

[0140] In the embodiment, the number of FC1 input neurons is 3840 / 32=120, the number of output neurons is 2688 / 32=84; after the Tanh activation layer, the number of output neurons is 84; the number of FC2 input neurons is 2688 / 32=84, the number of output neurons is 320 / 32=10; after the Softmax layer, the number of output neurons is 10. Enable each submodule in a fixed clock cycle sequence, ensure that the data flow is correctly transmitted between modules, and output the final reasoning result.

[0141] In the embodiment, Xilinx XC7Z020 of Xilinx's Zynq-7000 series is used, and Vivado 2020.2 suite is used for hardware development and simulation. Write verification code, simulate the convolution layer, pooling layer, activation function and fully connected layer one by one in the simulation environment, and verify the correctness and function of each module. In the embodiment, the Vivado simulation tool is used to test the logical function of the Verilog code. The code of the target function is written in C++ and run in an external script. Use random samples for testing, compare the running results of the two groups of codes implemented in different languages, check whether these results are consistent with expectations, ensure the correctness of the implementation, and the simulation results are as follows: Figure 9(a)-9(e) shown.

[0142] The designed Verilog code is synthesized using a synthesis tool (Xilinx Vivados), and the timing and resource utilization are optimized to ensure that the FPGA's logic units, DSP, and on-chip memory can be reasonably utilized.

[0143] In order to make reasonable resource utilization, in an embodiment, the input image data and weight data are stored in BRAM, where the weight data includes the convolution kernel in the convolution layer and the weight matrix of the fully connected layer. In the operation of the convolutional neural network, the weight matrix and the input data volume are large, and the convolution layer and the fully connected layer need to frequently access the input image data and the convolution kernel weight. Using BRAM to store data, the access delay will be significantly reduced, which is very important for applications with high real-time computing requirements. FIFO is used as the storage space for intermediate feature maps in CNN. The feature maps output by the convolution layer, pooling layer, and fully connected layer are stored in FIFO, and data is read directly from FIFO when the next layer needs it.

[0144] In step S106, based on the written RTL code, the classification result is integrated into the target CNN network to use the comparative data of the radar signal to identify the radar signal modulation mode based on the CNN algorithm on the hardware platform.

[0145] It is understandable that the present application can write verification code and use the Vivado simulation tool to test the modules such as the convolution layer, pooling layer, activation function and fully connected layer in the above steps one by one. At the same time, use C++ to write the target function and pass the random sample test to ensure the correctness of the function and logic of each module. Use the Vivado synthesis tool to synthesize the Verilog code to ensure the rational use of resources such as hardware logic units, DSP and on-chip memory BRAM.

[0146] In the actual implementation process, Fig.10 For the overall CNN network structure, the embodiment of the present application can integrate the results of the convolution module and the classification results into the complete CNN network to ensure smooth data transmission between layers and reduce system bottlenecks. And improve processing efficiency to ensure efficient operation of the system in a resource-constrained environment. Based on the target CNN network, the modulation mode of the radar signal is identified by using the comparison data of the radar signal.

[0147] The embodiment of the present application uses CNN to identify the radar signal modulation mode and uses FPGA to implement the CNN algorithm, which can improve the radar signal recognition speed. By writing RTL code, the method can be implemented on a hardware platform.

[0148] Optionally, in one embodiment of the present application, before using comparison data to identify the modulation mode of the radar signal, it also includes: adding Gaussian white noise to the radar signal to generate training samples, and using the training samples to train a convolutional neural network model to determine the trained convolutional neural network model; comparing the trained convolutional neural network model with the target model to generate comparison data.

[0149] Specifically, in the simulation experiment, the embodiment of the present application can add different Gaussian white noise to each signal type to generate training samples and use Python language to train the model. The trained model weights are uploaded to the FPGA platform for experiments. Use the test samples to perform performance tests: compare the accuracy and performance with other reference models, generate comparison data, and verify the hardware acceleration effect by comparing the test delays on the FPGA, CPU, and GPU platforms to further improve the radar signal recognition speed.

[0150] For example, the recognition accuracy of the embodiment of the present application under different signal-to-noise ratios. In the simulation experiment, different Gaussian white noise is added to each signal, and the SNR ranges from 10dB to -10dB, with a step of 5dB. 1000 sets of training samples are randomly generated for each signal type at each signal-to-noise ratio, and the network model training adopts Python programming language. The trained model weights are uploaded to XC7Z020 for radar signal modulation mode recognition experiments. At the same time, 150 sets of test samples are generated for performance testing and compared with the residual network (ResNet). The test results are as follows: Fig.11 As shown, the recognition accuracy of the network model proposed by the present invention is basically equal to that of the ResNet network.

[0151] In order to verify the hardware acceleration effect, the average value of the delay time of 150 tests is taken in the embodiment to represent the single radar modulation mode recognition time. The XC7Z020 board, CPU platform and GPU platform are tested and compared respectively, and the test results are shown in Table 1. Through the experimental data, the advantage of the FPGA acceleration platform in terms of delay can be effectively proved.

[0152] Table 1

[0153] Test platform Delay time / ms XC7Z020 6.7 CPU 120.6 GPU 10.4

[0154] The embodiments of the present application can be applied to enhancing the anti-interference capability of the radar system, improving the accuracy of target detection and classification, and ensuring the security of communication and spectrum management.

[0155] According to the radar signal modulation mode identification method proposed in the embodiment of the present application, a one-dimensional radar signal can be converted into two-dimensional image data that can be processed by a convolutional neural network, and the convolution layer is used to process feature extraction, the activation function controls the output range, the pooling layer reduces the dimension, the Softmax layer generates probability distribution, and the fully connected layer is designed for classification. Floating-point operation optimization, approximate calculation of activation functions, and division operation optimization of the SoftMax layer are added to the algorithm design. The system performance is further improved through parallel processing and pipeline design. The modular design of each part enables the system to be reused, which is suitable for implementation on a resource-constrained hardware platform such as FPGA, and has advantages in accuracy and delay time. As a result, the problem that the optimization and control of hardware resources in related technologies are relatively limited, it is difficult to obtain the optimal performance and resource utilization, it is difficult to deeply optimize the delay at each level, and there is a performance bottleneck.

[0156] Next, a radar signal modulation mode identification device proposed according to an embodiment of the present application is described with reference to the accompanying drawings.

[0157] Fig.12 It is a structural diagram of a radar signal modulation mode identification device according to an embodiment of the present application.

[0158] like Fig.12 As shown, the radar signal modulation mode identification device 10 includes: a conversion module 100, an extraction module 200, an acquisition module 300, a mapping module 400, a generation module 500 and an identification module 600.

[0159] Specifically, the conversion module 100 is used to add Gaussian white noise to a one-dimensional radar signal to generate a radar signal that meets a preset noise condition, and convert the radar signal into a two-dimensional time-frequency diagram.

[0160] The extraction module 200 is used to extract local features in the two-dimensional time-frequency diagram and extract different features in the two-dimensional time-frequency diagram.

[0161] The acquisition module 300 is used to compress the local features and different features into a target range, so as to downsample the output feature map and obtain a sampled feature map that meets a preset dimensionality condition.

[0162] The mapping module 400 is used to obtain results that meet preset integration conditions and map elements in the input feature vector into probability distribution.

[0163] The generation module 500 is used to integrate local features, different features, sampling feature maps, results and probability distributions to generate decision results, and generate classification results of features based on the decision results.

[0164] The identification module 600 is used to integrate the classification results into the target CNN network based on the written RTL code, so as to use the comparison data of the radar signal to identify the radar signal modulation mode based on the CNN algorithm on the hardware platform.

[0165] Optionally, in one embodiment of the present application, the extraction module 200 includes: a comparison unit and a determination unit.

[0166] Among them, the comparison unit is used to compare the resource occupancy rate and calculation accuracy under different bit floating point numbers to determine the floating point bit width of the convolution layer that meets the preset suitable conditions, and use the floating point bit width that meets the preset suitable conditions to determine the local features in the two-dimensional time-frequency diagram.

[0167] The determination unit is used to extract the local area corresponding to the convolution kernel sliding window, and calculate the convolution of the convolution kernel and the two-dimensional time-frequency map in the local area to determine different features according to the convolution.

[0168] Optionally, in one embodiment of the present application, the radar signal modulation mode identification device 10 further includes: a first judgment module, an output module, a second judgment module and a first execution module.

[0169] The first judgment module is used to obtain the sign bit, exponent bit and mantissa bit of the floating point number, and judge whether the sign bit is opposite and whether the exponent bit and mantissa bit are equal.

[0170] The output module is used to output a zero value when the sign bits are opposite and the exponent bits and the mantissa bits are equal, otherwise the exponents are compared to see whether they meet the preset exponent same condition.

[0171] The second judgment module is used to judge whether the sign of the floating point number meets the preset sign same condition when the exponent meets the preset exponent same condition, otherwise, execute the right shift mantissa to align the exponent.

[0172] The first execution module is used to perform the mantissa addition action of the floating point number when the sign meets the preset sign same condition, otherwise perform the mantissa subtraction action of the floating point number, left-shift the mantissa and adjust the exponent until the preset normalization standard condition is met.

[0173] Optionally, in one embodiment of the present application, the radar signal modulation mode identification device 10 further includes: a third judgment module and a second execution module.

[0174] The third judgment module is used to judge whether the sign bit, the exponent bit and the mantissa bit have zero values ​​respectively.

[0175] The second execution module is used to output a zero value when the sign bit, the exponent bit and the mantissa bit have a zero value, otherwise perform an XOR operation on the sign bit of the floating-point number, perform an exponential addition operation on the floating-point number, and perform a mantissa multiplication operation on the floating-point number, shift the mantissa left and adjust the exponent until a preset normalization standard condition is met.

[0176] Optionally, in one embodiment of the present application, the calculation formula for mapping the elements in the input feature vector to the probability distribution is:

[0177]

[0178] Among them, x i is the i-th value of the input feature, S(x i ) is the Softmax output of the i-th value, and N is the length of the input vector.

[0179] Optionally, in one embodiment of the present application, the radar signal modulation mode identification device 10 further includes: a training module and a comparison module.

[0180] Among them, the training module is used to add Gaussian white noise to the radar signal to generate training samples before using comparative data to identify the modulation mode of the radar signal, and use the training samples to train the convolutional neural network model to determine the trained convolutional neural network model.

[0181] The comparison module is used to compare the trained convolutional neural network model with the target model to generate comparison data.

[0182] It should be noted that the aforementioned explanation of the embodiment of the radar signal modulation mode identification method is also applicable to the radar signal modulation mode identification device of this embodiment, and will not be repeated here.

[0183] According to the radar signal modulation mode identification device proposed in the embodiment of the present application, a one-dimensional radar signal can be converted into two-dimensional image data that can be processed by a convolutional neural network, and is designed by processing feature extraction through a convolutional layer, controlling the output range through an activation function, reducing the dimension through a pooling layer, generating probability distribution through a Softmax layer, and performing classification through a fully connected layer. Floating-point operation optimization, approximate calculation of activation functions, and division operation optimization of the SoftMax layer are added to the algorithm design. The system performance is further improved through parallel processing and pipeline design. The modular design of each part enables the system to be reused, which is suitable for implementation on a resource-constrained hardware platform such as FPGA, and has advantages in accuracy and delay time. Thus, the problem that the optimization and control of hardware resources by related technologies are relatively limited, it is difficult to obtain the optimal performance and resource utilization, it is difficult to deeply optimize the delay at each level, and there is a performance bottleneck is solved.

[0184] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0185] A memory 1301 , a processor 1302 , and a computer program stored in the memory 1301 and executable on the processor 1302 .

[0186] When the processor 1302 executes the program, the radar signal modulation mode identification method provided in the above embodiment is implemented.

[0187] Furthermore, the electronic device further comprises:

[0188] The communication interface 1303 is used for communication between the memory 1301 and the processor 1302 .

[0189] The memory 1301 is used to store computer programs that can be executed on the processor 1302 .

[0190] The memory 1301 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0191] If the memory 1301, the processor 1302 and the communication interface 1303 are implemented independently, the communication interface 1303, the memory 1301 and the processor 1302 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.13 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0192] Optionally, in a specific implementation, if the memory 1301, the processor 1302 and the communication interface 1303 are integrated on a chip, the memory 1301, the processor 1302 and the communication interface 1303 can communicate with each other through an internal interface.

[0193] The processor 1302 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0194] This embodiment also provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the above radar signal modulation mode identification method is implemented.

[0195] An embodiment of the present application also provides a computer program product, on which a computer program is stored, and when the program is executed by a processor, the above radar signal modulation mode identification method is implemented.

[0196] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0197] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0198] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0199] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or N wirings (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways as necessary and then storing it in a computer memory.

[0200] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0201] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0202] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0203] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A radar signal modulation mode identification method, characterized in that: Applied to a convolutional neural network model, wherein the method comprises the following steps: Adding Gaussian white noise to a one-dimensional radar signal to generate a radar signal that meets a preset noise condition, and converting the radar signal into a two-dimensional time-frequency graph; Extracting local features in the two-dimensional time-frequency graph, and extracting different features in the two-dimensional time-frequency graph; Compressing the local features and the different features into a target range to downsample the output feature map to obtain a sampled feature map that meets a preset dimensionality condition; Obtain results that meet the preset integration conditions and map the elements in the input feature vector to probability distribution; Integrating the local features, the different features, the sampling feature map, the results and the probability distribution to generate a decision result, and generating a classification result of the feature according to the decision result; Based on the written RTL code, the classification result is integrated into the target CNN network to use the comparison data of the radar signal to identify the radar signal modulation mode based on the CNN algorithm on the hardware platform.

2. The method according to claim 1, characterized in that: The extracting of local features in the two-dimensional time-frequency graph and extracting different features of the two-dimensional time-frequency graph includes: Comparing resource occupancy rates and calculation accuracy under different bit floating point numbers to determine a floating point number bit width that meets preset suitable conditions, and using the floating point number bit width that meets the preset suitable conditions to determine local features in the two-dimensional time-frequency diagram; A local area corresponding to the convolution kernel sliding window is extracted, and a convolution of the convolution kernel and the two-dimensional time-frequency graph is calculated in the local area to determine the different features according to the convolution.

3. The method according to claim 2, characterized in that Before comparing the resource usage and calculation accuracy of different floating-point numbers, we also include: Obtain the sign bit, exponent bit and mantissa bit of the floating point number, and determine whether the sign bit is opposite and whether the exponent bit and mantissa bit are equal; If the sign bits are opposite and the exponent bits and the mantissa bits are equal, a zero value is output; otherwise, the exponents are compared to see whether they meet a preset exponent same condition; If the exponent satisfies the preset exponent same condition, determining whether the sign of the floating point number satisfies the preset sign same condition, otherwise right-shifting the mantissa to align the exponent; If the sign satisfies the preset sign same condition, the mantissa addition action of the floating point number is performed, otherwise the mantissa subtraction action of the floating point number is performed, the mantissa is left-shifted and the exponent is adjusted until the preset normalization standard condition is met.

4. The method according to claim 3, characterized in that Before comparing the resource usage and calculation accuracy of different floating-point numbers, we also include: Determine whether the sign bit, the exponent bit, and the mantissa bit have the zero value respectively; If the sign bit, the exponent bit and the mantissa bit have the zero value, the zero value is output, otherwise an XOR operation is performed on the sign bit of the floating-point number, an exponent addition operation is performed on the floating-point number, and a mantissa multiplication operation is performed on the floating-point number, the mantissa is left-shifted and the exponent is adjusted until a preset normalization standard condition is met.

5. The method according to claim 1, characterized in that The calculation formula for mapping the elements in the input feature vector to the probability distribution is: Among them, x i is the i-th value of the input feature, S(x i ) is the Softmax output of the i-th value, and N is the length of the input vector.

6. The method according to claim 1, characterized in that Before using the comparison data to identify the modulation mode of the radar signal, the method further includes: Using the training samples to train the convolutional neural network model to determine the trained convolutional neural network model; The trained convolutional neural network model is compared with the target model to generate the comparison data.

7. A radar signal modulation mode identification device, characterized in that: Applied to a convolutional neural network model, wherein the device comprises: A conversion module, used for adding Gaussian white noise to a one-dimensional radar signal to generate a radar signal that meets a preset noise condition, and converting the radar signal into a two-dimensional time-frequency diagram; An extraction module, used to extract local features in the two-dimensional time-frequency diagram and extract different features in the two-dimensional time-frequency diagram; An acquisition module, used for compressing the local features and the different features into a target range, so as to downsample the output feature map and obtain a sampled feature map that meets a preset dimensional condition; A mapping module, used to obtain results that meet preset integration conditions and map elements in the input feature vector to probability distribution; A generation module, used for integrating the local features, the different features, the sampling feature map, the results and the probability distribution to generate a decision result, and generating a classification result of the feature according to the decision result; An identification module is used to integrate the classification result into a target CNN network to identify the modulation mode of the radar signal using the comparison data of the radar signal.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the radar signal modulation mode identification method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the radar signal modulation mode identification method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that The computer program is executed to implement the radar signal modulation mode identification method according to any one of claims 1 to 6.

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