A method and system for fast soft error rate estimation based on graph neural network

Abstract

The present invention discloses a method and system for rapidly estimating soft error rates based on a graph neural network. The method comprises converting a combinational circuit being estimated into a directed acyclic graph, where nodes represent inputs, AND gates, and output units in the estimated combinational circuit, and edges represent connections between nodes; adding feature information to the directed acyclic graph; and using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit. The pre-trained graph neural network establishes a mapping between the directed acyclic graph and the soft error rate. The present invention aims to achieve rapid and efficient estimation of the soft error rate of each unit in a combinational logic circuit, while only considering the logical shielding effect.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit electronic design automation (EDA), and in particular to a method and system for fast soft error rate estimation based on graph neural network. Background Art

[0002] Electronic design automation (EDA) refers to a design methodology that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design processes of very large-scale integrated circuits (VLSIs). Soft errors in integrated circuits are errors caused by single-event effects (SEEs). SEEs are one of the most important effects of ionizing radiation. When a SEE occurs, particles impacting different locations in the circuit can cause different phenomena and failures. These failures can be categorized into two main types based on whether they are recoverable: ① Destructive SEEs, also known as hard errors, cause irreversible damage to the circuit after occurrence, such as SEE latch-up, SEE burnout, SEE gate punch-through, SEE dielectric breakdown, and SEE bit lockup. ② Non-destructive SEEs, also known as soft errors, cause circuit system state errors but do not cause hardware damage. They can be restored to normal through hardware and software algorithms or a reset. Examples include SEE upsets, multi-cell upsets, block errors, column errors, row errors, SEE functional interruptions, single-event transients, and SEE multi-transients. When a combinational circuit unit is affected by a single-particle transient and a soft error occurs, the probability that it can propagate along the circuit direction and be successfully captured by the output end is the soft error rate.

[0003] A single-event transient (SET) is one of the most important single-event effects. Its manifestation occurs when a cell in a circuit is bombarded by a particle, generating a transient pulse. This pulse propagates backward along the circuit path. If it reaches the output and is successfully captured by a sequential cell, the transient pulse causes a soft error, impacting the normal operation of the circuit. However, the probability of a SET reaching the output is low due to three shielding effects: logical shielding, electrical shielding, and latch window shielding. Logical shielding occurs when a SET encounters a cell in the off state, preventing it from propagating further. Electrical shielding occurs when a SET passes through a cell or wire mesh, causing the pulse width and amplitude to be attenuated due to parasitic effects such as capacitance and resistance, preventing it from propagating further. Latch window shielding ensures that the SET arrives at the appropriate time within the clock cycle, meeting hold and setup time requirements, in order to be successfully captured by downstream sequential cells. Logical shielding is the most important and complex of the three shielding effects because it is dynamically dependent on the circuit's current input stimulus. With advancements in process technology and improvements in circuit performance, the effectiveness of electrical shielding has gradually diminished. Furthermore, using latch window shielding to filter single-event transient pulses has become more difficult due to shrinking clock cycles. Logical shielding is less affected by process technology, and the same analysis methods remain effective across different processes. Furthermore, the new challenges introduced by scaling have made analyzing the logic structure of circuits even more important. Considering only the logical shielding effect, how to quickly and efficiently estimate the soft error rate of each cell in a combinational logic circuit has become a critical technical challenge that needs to be addressed. Summary of the Invention

[0004] The technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, a method and system for rapid estimation of soft error rate based on graph neural network are provided. The present invention aims to quickly and efficiently estimate the soft error rate of each unit in a combinational logic circuit.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A method for fast soft error rate estimation based on graph neural network includes the following steps:

[0007] S1, converting the estimated combinational circuit into a directed acyclic graph, where the nodes in the directed acyclic graph are the inputs, AND gates, and output units in the estimated combinational circuit, and the edges are the connections between the nodes;

[0008] S2, adds feature information to the directed acyclic graph;

[0009] S3, using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit using the directed acyclic graph after adding feature information. The graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate.

[0010] Optionally, adding feature information to the directed acyclic graph in step S2 includes adding node feature information to the nodes in the directed acyclic graph, and the node feature information added to the directed acyclic graph includes part or all of the topological order of the nodes, the fan-in and fan-out numbers of the nodes, the number of associated inputs of the nodes, the number of outputs associated with the nodes, the number of paths between the nodes and the outputs, the average length of the paths between the nodes and the outputs, and the average number of inputs associated with the paths between the nodes and the outputs.

[0011] Optionally, the nodes in the directed acyclic graph in step S1 are AND gates of the combinational circuit, the edges are connection lines of the AND gates in the combinational circuit, and the NOT gates in the combinational circuit do not exist as nodes in the directed acyclic graph but are integrated on the edges of the directed acyclic graph. The use of a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit refers to using a pre-trained graph neural network to regress and predict the soft error rate of the AND gate in the combinational circuit. Adding feature information to the directed acyclic graph in step S2 includes adding edge feature information to the edges in the directed acyclic graph, and the function expression of the added edge feature information is:

[0012] ,

[0013] In the above formula, is the edge feature information; Used to indicate whether there is a NOT gate on the edge. If there is a NOT gate If there is no NOT gate, then ; Indicates the starting node position of the edge; Indicates the end node position of the edge, is the number of layers of the graph neural network.

[0014] Optionally, converting the estimated combinational circuit into a directed acyclic graph in step S1 includes:

[0015] S1.1, if the estimated combinational circuit is a combinational circuit in AIG format, jump to step S1.3, otherwise jump to step S1.2;

[0016] S1.2, if the estimated combinational circuit is a combinational circuit in bench format, convert the bench format combinational circuit to Verilog format, and then use the tool Yosys to convert the Verilog format to AIG format; if the estimated combinational circuit is a combinational circuit in Verilog format, use the tool Yosys to convert the Verilog format to AIG format; if the estimated combinational circuit is a sequential circuit, first use the tool Yosys to convert the sequential circuit to table format, then use the trigger as the main input or main output of the sub-circuit, divide the table format sequential circuit into sub-circuits based on the trigger to obtain bench format sub-circuits, convert the bench format sub-circuits to Verilog format, and use the tool Yosys to convert the Verilog format to AIG format; if converted to AIG format, jump to step S1.3, otherwise end and exit;

[0017] S1.3, read the structural information of the combinational circuit in the AIG format, and check whether the read circuit structural information meets the specification. If it meets the specification, generate a directed acyclic graph of the estimated combinational circuit according to the structural information of the combinational circuit in the AIG format, otherwise end and exit.

[0018] Optionally, step S3 also includes training a graph neural network to establish a mapping relationship between a directed acyclic graph and a soft error rate:

[0019] S101, obtaining a combinational circuit sample;

[0020] S102, converting the combinational circuit sample into a combinational circuit sample in AIG format;

[0021] S103, reading the structure information of the combinational circuit sample in AIG format, checking whether the read circuit structure information meets the specification, and discarding it if it does not meet the specification;

[0022] S104: for each combinational circuit sample in the AIG format, convert the combinational circuit sample into a directed acyclic graph, where nodes in the directed acyclic graph represent circuit units in the combinational circuit sample, and edges represent connecting lines between circuit units in the combinational circuit sample. Feature information is added to the directed acyclic graph, and soft error rates of nodes in the combinational circuit sample are used as node labels. Node label information is added to construct a circuit dataset.

[0023] S105, dividing the circuit data set into a training set and a test set;

[0024] S106, using the training set and the test set to train the graph neural network to establish a mapping relationship between the directed acyclic graph and the soft error rate.

[0025] Optionally, acquiring the soft error rate of a node in the combinational circuit sample includes:

[0026] S201, using a depth-first search method to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, and store all paths from the circuit units to the main output port;

[0027] S202, traversing and selecting a circuit unit as the current circuit unit;

[0028] S203, conveniently selecting a sensitized path from all paths of the current circuit unit, wherein the sensitized path refers to a path from which a soft error can be successfully propagated to a main output without being logically masked;

[0029] S204, adding the constraints of the sensitized path to the SAT solver;

[0030] S205, using a SAT solver to cyclically solve for a satisfiable solution for the soft error of the current circuit unit. If no satisfiable solution can be obtained, jump to step S206; otherwise, determine whether there is an undefined signal in the obtained satisfiable solution. If there is an undefined signal in the satisfiable solution, jump to step S206; if there is no undefined signal in the satisfiable solution, add additional constraints to the SAT solver to mask the current solution obtained, and jump to step S205;

[0031] S206, determine whether the sensitization path of the current circuit unit has been traversed. If the sensitization path of the current circuit unit has not been traversed, jump to step S203; otherwise, determine whether the circuit unit has been traversed. If the circuit unit has not been traversed, jump to step S202. If the circuit unit has been traversed, the soft error rate of the node in the combinational circuit sample is obtained.

[0032] Optionally, when using the depth-first search method in step S201 to obtain the set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, it includes using a dual stack to store the intermediate process of traversing the entire graph, and the dual stack includes a main stack and an auxiliary stack. The main stack is used to store a single element, and the element is used to represent a node on the current path. The auxiliary stack stores a list of adjacent nodes corresponding to the element of the main stack. The length of the auxiliary stack is always consistent with that of the main stack. During the full-graph search, the main stack and the auxiliary stack are constantly changing, so that all paths between the target starting point and the main output port are obtained during the change of the main stack and the auxiliary stack.

[0033] In addition, the present invention also provides a system for rapid estimation of soft error rate based on graph neural network, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for rapid estimation of soft error rate based on graph neural network.

[0034] In addition, the present invention also provides a computer-readable storage medium, which stores a computer program or instruction, and the computer program or instruction is programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0035] In addition, the present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0036] Compared with the prior art, the present invention mainly has the following advantages: the present invention includes converting the estimated combinational circuit into a directed acyclic graph, where the nodes in the directed acyclic graph are circuit units of the combinational circuit, and the edges are connection lines of the circuit units in the combinational circuit; adding feature information to the directed acyclic graph; using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit using the directed acyclic graph after adding feature information. The graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate. The present invention can quickly and efficiently estimate the soft error rate of each unit in the combinational logic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the basic process of rapid estimation of soft error rate in the method of an embodiment of the present invention.

[0038] Figure 2 FIG. 4 is a schematic diagram of the structure of the estimated combinational circuit in an embodiment of the present invention.

[0039] Figure 3 FIG. 4 is a schematic diagram of a directed acyclic graph of a combinational circuit being estimated in an embodiment of the present invention.

[0040] Figure 4 The figure is a schematic diagram of the process of constructing a circuit data set in an embodiment of the present invention.

[0041] Figure 5 Schematic diagram of the training process of the neural network in the figure according to an embodiment of the present invention.

[0042] Figure 6 Schematic diagram of the flow chart of the conversion format of combinational circuit samples when training a graph neural network in an embodiment of the present invention.

[0043] Figure 7 Schematic diagram of the process of training a graph neural network in an embodiment of the present invention.

[0044] Figure 8 Schematic diagram of adding AND gate constraints to MiniSAT in an embodiment of the present invention.

[0045] Figure 9FIG. 4 is a flow chart of calculating the soft error rate of a circuit unit using MiniSAT in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] like Figure 1 As shown, the method for fast estimating soft error rate based on graph neural network in this embodiment includes the following steps:

[0047] S1, converting the estimated combinational circuit into a directed acyclic graph, where the nodes in the directed acyclic graph are the inputs, AND gates, and output units in the estimated combinational circuit, and the edges are the connections between the nodes;

[0048] S2, adds feature information to the directed acyclic graph;

[0049] S3, using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit using the directed acyclic graph after adding feature information. The graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate.

[0050] In step S2 of this embodiment, adding feature information to the directed acyclic graph includes adding node feature information to the nodes in the directed acyclic graph, and the node feature information added to the directed acyclic graph includes part or all of the topological order of the nodes, the fan-in and fan-out numbers of the nodes, the number of associated inputs of the nodes, the number of outputs associated with the nodes, the number of paths between the nodes and the outputs, the average length of the paths between the nodes and the outputs, and the average number of inputs associated with the paths between the nodes and the outputs.

[0051] As an optional implementation, the nodes in the directed acyclic graph in step S1 of this embodiment are AND gates of the combinational circuit, the edges are connection lines of the AND gates in the combinational circuit, the NOT gates in the combinational circuit do not exist as nodes in the directed acyclic graph but are integrated on the edges of the directed acyclic graph, and using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit refers to using a pre-trained graph neural network to regress and predict the soft error rate of the AND gates in the combinational circuit. Figure 2 1 is a combinational circuit to be evaluated in an embodiment of the present invention, wherein 1-3 are input ports, 7 is an output port, 4-6 are AND gates, and also includes two NOT gates. Figure 3 for Figure 2 The DAG of the estimated combinational circuit is constructed, wherein two NOT gates are not nodes in the DAG but are integrated on the edges of the DAG. To indicate the position of edges in the graph and whether NOT gates exist on the edges, this embodiment uses a 32-dimensional feature to quantify this information. In step S2 of this embodiment, adding feature information to the DAG includes adding edge feature information to the edges in the DAG. The function expression for the added edge feature information is:

[0052] ,

[0053] In the above formula, is the edge feature information; Used to indicate whether there is a NOT gate on the edge. If there is a NOT gate If there is no NOT gate, then ; Indicates the starting node position of the edge; Indicates the end node position of the edge, is the number of layers of the graph neural network.

[0054] In step S1 of this embodiment, converting the estimated combinational circuit into a directed acyclic graph includes:

[0055] S1.1, if the estimated combinational circuit is a combinational circuit in AIG format, jump to step S1.3, otherwise jump to step S1.2;

[0056] S1.2, if the estimated combinational circuit is a combinational circuit in bench format, convert the bench format combinational circuit to Verilog format, and then use the tool Yosys to convert the Verilog format to AIG format; if the estimated combinational circuit is a combinational circuit in Verilog format, use the tool Yosys to convert the Verilog format to AIG format; if the estimated combinational circuit is a sequential circuit, first use the tool Yosys to convert the sequential circuit to table format, then use the trigger as the main input or main output of the sub-circuit, divide the table format sequential circuit into sub-circuits based on the trigger to obtain bench format sub-circuits, convert the bench format sub-circuits to Verilog format, and use the tool Yosys to convert the Verilog format to AIG format; if converted to AIG format, jump to step S1.3, otherwise end and exit;

[0057] S1.3, read the structural information of the combinational circuit in the AIG format, and check whether the read circuit structural information meets the specification. If it meets the specification, generate a directed acyclic graph of the estimated combinational circuit according to the structural information of the combinational circuit in the AIG format, otherwise end and exit.

[0058] like Figure 4 and Figure 5 As shown, step S3 of this embodiment also includes training a graph neural network to establish a mapping relationship between a directed acyclic graph and a soft error rate:

[0059] S101, obtaining a combinational circuit sample; As an optional implementation, such as Figure 6As shown, the combinational circuit samples in step S101 of this embodiment are from the ISCAS'85 test set, the EPFL test set and Opencores, wherein the circuits in the ISCAS'85 test set are in bench format, and the circuits in the EPFL test set and Opencores are in Verilog format.

[0060] S102: Convert the combinational circuit samples into AIG format combinational circuit samples. This embodiment utilizes the open-source tool yosys, using its built-in instructions to uniformly convert circuits from Verilog format to AIG format. Alternatively, combinational circuit samples can be obtained from other existing datasets or created independently as needed. When processing the ISCAS'85 circuit test set, all combinational circuits are in bench format. This embodiment first uses the bench_to_verilog.py script to convert bench format combinational circuits into Verilog format, and then uses the open-source tool yosys to convert Verilog format circuits into AIG format. The instruction flow in this embodiment is as follows:

[0061] yosys -import

[0062] read_verilog *

[0063] synth -flatten -auto-top

[0064] aigmap

[0065] write_aiger -ascii . / test.aag

[0066] exit

[0067] In the above instruction stream, the first line of instruction is to import the combinational circuit in Verilog format into the open source tool yosys; the second line is to read all the files of the imported combinational circuit in Verilog format in the current directory; the third line is to perform the synthesis operation, the -flatten option means to flatten the circuit hierarchy, and the -auto-top option automatically determines the top-level module; the fourth line is to map the circuit to AIG format, which is the step of preparing to output the AIG file; the fifth line is to write the AIG format circuit in ASCII encoding into a file named test.aag, and the sixth line is to exit the open source tool yosys. When processing the EPFL circuit test set, the test set contains combinational circuits in verilog format. This embodiment uses the open source tool yosys to convert this part of the circuit into AIG format. Figure 6As shown, when processing the circuits in Opencores, both combinational circuits and sequential circuits are included. For combinational circuits, this embodiment uses the open source tool yosys to convert them into the AIG format; for sequential circuits, this embodiment first uses the open source tool yosys to convert them into the table format, and then uses the table_to_bench.py ​​script to divide the sequential circuit into subcircuits based on the trigger (using the trigger as the main input or main output of the subcircuit) to obtain the bench format subcircuit, and then uses the bench_to_verilog.py script to convert it into the verilog format, and finally uses the open source tool yosys to convert it into the AIG format circuit. The purpose of using sequential circuits for subcircuit division is to expand the scale of the circuit data set;

[0068] S103, reading the structural information of the combinational circuit sample in the AIG format, checking whether the read circuit structural information complies with the specification, and discarding it if it does not comply with the specification; when reading the circuit structural information in the AIG format, the aiger_open_and_read_from_file() method provided by the AIGER And-Inverter-Graph Library code repository can be used to read the circuit structural information; the aiger_check() method provided by the AIGER And-Inverter-Graph Library code repository can be used to check whether the read circuit structural information complies with the specification;

[0069] S104, for each combinational circuit sample in the AIG format, convert the combinational circuit sample into a directed acyclic graph, where the nodes in the directed acyclic graph are the circuit units of the combinational circuit sample, and the edges are the connection lines of the circuit units in the combinational circuit sample. Feature information is added to the directed acyclic graph, and the soft error rates of the nodes in the combinational circuit sample are used as node labels to add node label information to construct a circuit data set; when adding node label information, the node label is the soft error rate data, which is the target of regression prediction using the graph neural network in this embodiment. In the training set, the label needs to be added to the node to calculate the current error and guide the direction of parameter adjustment of the model. In the test set, the label needs to be used to calculate the error between the predicted value and the standard value to test the generalization performance of the model;

[0070] S105: Divide the circuit dataset into a training set and a test set. After converting the AIG format combinational circuits into a graph data structure and adding node feature information, edge feature information, and node label information, a complete circuit dataset is constructed. The circuits in the dataset are then randomly divided into a training set and a test set according to an appropriate ratio. As an optional implementation, in this embodiment, the dataset is randomly divided into a training set and a test set at a ratio of 7:3.

[0071] S106, using the training set and the test set to train the graph neural network to establish a mapping relationship between the directed acyclic graph and the soft error rate, including: first establishing an initial graph neural network, Figure 5 In the figure, the initial graph neural network is represented as graph neural network model M1, and then the model parameters are adjusted using the training set, and the generalization is verified using the test set. The trained graph neural network is then represented as graph neural network M1'.

[0072] Graph neural networks refer to the extension of neural network methods to the field of graph data processing, extracting and discovering key features and patterns in graph structured data, and ultimately achieving target prediction. Graph neural networks can be classified according to their architecture and the way they process graph structured data, mainly including the following three categories: (1) Graph convolutional neural networks: The convolution operation in the convolutional neural network (CNN) is extended to the graph field to achieve the update of node features. (2) Graph recurrent neural networks: The structure of the recurrent neural network (RNN) is used to perform recursive calculations on the graph. This type of network is suitable for dynamic graphs or time series graphs. (3) Graph attention networks: The attention mechanism is introduced to replace the static normalization constant in the graph convolutional network, and a learnable importance weight parameter is calculated for all neighboring nodes of each node. The graph neural network can adopt the required graph neural network type as needed. For example, as an optional implementation method, this embodiment uses a graph neural network model specifically for directed acyclic graphs: the DAG Transformer model. The model is trained on the training set, and the hyperparameters used by the DAG Transformer model are continuously adjusted to achieve better performance on the test set. Save the model parameter dictionary that has the best performance on the test set, and use this model to predict the soft error rate of each unit of the new combinational circuit. Figure 7As shown, in step S106 of this embodiment, when using the training set and test set to train the graph neural network (DAG Transformer model), the following steps are included: (1) Normalizing feature data and label data: In certain calculation processes of the graph neural network, the gradient descent algorithm needs to be used. If the scale of the feature data varies greatly, it may cause numerical instability or gradient disappearance / explosion problems. Using normalization helps to avoid such numerical problems. At the same time, scaling the feature data to the same scale also helps to accelerate the convergence speed of the algorithm. (2) Optimizer adjustment: The optimizer is an algorithm used for backpropagation. It can adaptively adjust the parameters in the graph neural network model so that the graph neural network can perform better on the training set. The optimizer and the gradient descent algorithm are closely related. The gradient descent algorithm has many problems (such as falling into local optimality, oscillation, slow convergence, etc.). Different optimizers will introduce different techniques to optimize the gradient descent algorithm. Therefore, when training the graph neural network, this embodiment tries to use various different optimizers and finally selects the one with the best performance. (3) Learning rate adjustment: The learning rate is a very important hyperparameter in supervised learning. It controls the learning progress of the graph neural network and determines whether the graph neural network can succeed or how long it takes to successfully find the global optimal solution. If the learning rate is too large, the graph neural network will not converge and will hover around the optimal solution; if the learning rate is too small, the graph neural network will converge very slowly, greatly increasing the time to find the optimal solution, and may converge after finding a local extreme point, and will not be able to find the true optimal solution. Therefore, this embodiment tried a variety of different options when setting the learning rate (initial learning rate setting: ), and as the number of training rounds increases, the learning rate gradually decreases, and finally a starting learning rate with the best performance and the smallest error is selected. (4) Loss function adjustment: The role of the loss function is to express the degree of difference between the predicted value and the true value, which can measure the quality of the model prediction. For node regression type prediction tasks, the mean squared error (MSE) or mean absolute error (MAE) is generally used as the loss function. Finally, the training set is used to adjust the model parameters, and the test set is used to verify the generalization. Then, the model parameters with the best performance on the test set are saved to obtain the trained DAG Transformer model.

[0073] It should be noted that the soft error rate of the nodes in the combinational circuit sample can be obtained as needed. For each combinational circuit unit, whether a single-particle transient (SET) soft error can be propagated to the output end and captured depends on the current input state. Therefore, a method that is easy to think of is to perform a fault simulation for each input state of the combinational circuit, and finally count the number of times the soft error can be propagated to the output end and captured. The soft error rate of the combinational circuit unit is defined as: the number of times captured by the output end / the total number of input states. However, based on the fault simulation technical requirements of simulation, exhaustive simulation is required to calculate the soft error rate of each unit in the combinational circuit (2 N times, where N is the number of main inputs of the circuit). Therefore, this method has a very high time complexity and is extremely time-consuming. In addition to the simplest fault simulation technology mentioned above, another approach is to convert the soft error rate calculation problem of the combinational circuit unit into a satisfiability problem (SAT) for solution. Assuming that a soft error occurs in a unit in the combinational circuit, the soft error rate of the unit is the ratio between the number of input combinations that the error can propagate to the output end and the total number of input combinations. How to convert this problem into a satisfiability problem includes: First, a combinational circuit is equivalent to a set of constraints. Each logic gate in the circuit can be represented by a SAT constraint. For example, a SAT constraint corresponding to a gate is as follows: Figure 8 As shown, P and Q are the inputs of the AND gate, R is the output of the AND gate, and the function expression of the SAT constraint corresponding to the AND gate is: ,in" " is the NOT operation," " is the AND operation," " is an OR operation. For ease of solution, combinational circuits are usually converted to AIG format, containing only AND and NOT gates. After adding the original SAT constraints of the circuit, it is necessary to obtain all paths from the combinational circuit unit where the soft error occurs to the output terminal, independently add sensitization constraints to each path, and finally send it to a SAT solver (such as MiniSAT) to calculate the number of satisfactory solutions. The soft error rate of a combinational circuit unit is defined as: the sum of the number of satisfactory solutions for all paths divided by the total number of input states. This method is faster than simulation-based fault simulation technology to a certain extent (about 15 times), but it is still very time-consuming and, due to the number of inputs in the combinational circuit, cannot handle large-scale circuits with many main inputs. As an optional implementation method, this embodiment uses the calculation of the soft error rate of the circuit unit. For each unit in the combinational circuit, MiniSAT is used to calculate the probability that a soft error in that unit can be successfully propagated to the output terminal. Specifically, Figure 9 As shown, in this embodiment, obtaining the soft error rate of a node in a combinational circuit sample includes:

[0074] S201, using a depth-first search method to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, and store all paths from the circuit units to the main output port;

[0075] S202, traversing and selecting a circuit unit as the current circuit unit;

[0076] S203, conveniently selecting a sensitized path from all paths of the current circuit unit, wherein the sensitized path refers to a path from which a soft error can be successfully propagated to a main output without being logically masked;

[0077] S204: Add the constraints of the sensitized path to the SAT solver. As an optional implementation, the SAT solver in this embodiment uses MiniSAT as the SAT solver. Other SAT solvers may also be used as needed. For each combinational circuit, its structure information and connection relationship constitute a set of SAT constraints. Therefore, the constraints consisting of the structure information and connection relationship on the sensitized path need to be added to the MiniSAT solver.

[0078] S205, using a SAT solver to cyclically solve for a satisfiable solution for the soft error of the current circuit unit. If no satisfiable solution can be obtained, jump to step S206; otherwise, determine whether there is an undefined signal in the obtained satisfiable solution. If there is an undefined signal in the satisfiable solution, jump to step S206; if there is no undefined signal in the satisfiable solution, add additional constraints to the SAT solver to mask the current solution obtained, and jump to step S205;

[0079] S206, determine whether the sensitization path of the current circuit unit has been traversed. If the sensitization path of the current circuit unit has not been traversed, jump to step S203; otherwise, determine whether the circuit unit has been traversed. If the circuit unit has not been traversed, jump to step S202. If the circuit unit has been traversed, the soft error rate of the node in the combinational circuit sample is obtained.

[0080] When the SAT solver is used in a loop to solve in step S205, according to the solving principle of MiniSAT, only one set of satisfiable solutions can be obtained after adding the constraints. If you want to obtain all the satisfiable solutions, you need to add additional constraints to shield the solutions that have been obtained when solving to a satisfiable solution. After adding the additional constraints, if a satisfiable solution can still be obtained, continue to add constraints to shield the current solution and continue to use MiniSAT to solve. After adding the additional constraints, if a satisfiable solution (unsat) cannot be obtained, all the satisfiable solutions for this sensitized path have been obtained, and this solution is terminated. After adding the additional constraints, if a satisfiable solution can be obtained, but a signal in the satisfiable solution is undef (undefined), it means that this solution has failed (possibly caused by timeout or other reasons), and this solution can also be terminated.

[0081] The problem of using the depth-first search method to obtain the set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample is a full-graph traversal problem. As an optional implementation method, based on the depth-first search DFS, when using the depth-first search method in step S201 of this embodiment to obtain the set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, it further includes using a dual stack to store the intermediate process of the full-graph traversal. The dual stack includes a main stack and an auxiliary stack. The main stack is used to store a single element, and the element is used to represent a node on the current path. The auxiliary stack stores a list of adjacent nodes corresponding to the element in the main stack. The length of the auxiliary stack is always consistent with that of the main stack. During the full-graph search process, the main stack and the auxiliary stack are constantly changing, so that all paths between the target starting point and the main output port are obtained during the change of the main stack and the auxiliary stack.

[0082] In summary, the graph neural network-based rapid soft error rate estimation method of this embodiment can more quickly estimate the sensitivity of each unit in a combinational circuit to single-event transient (SET) soft errors. This invention includes four core components: 1) circuit format conversion; 2) calculating label data for each unit in the combinational circuit using the MiniSAT tool; 3) circuit modeling and dataset construction; and 4) training the graph neural network and verifying its generalization performance on a new circuit. This embodiment's method proposes randomly partitioning a sequential circuit into subcircuits using flip-flops as primary inputs or outputs, generating a large number of smaller-scale combinational circuits and expanding the dataset size. This embodiment's method also proposes using the open-source tool MiniSAT to calculate the soft error rate (i.e., the number of satisfied solutions) for each unit in the combinational circuit. Generally, MiniSAT only generates a set of satisfied solutions for a specific constraint. However, in this embodiment, the requirement is to obtain all satisfied solutions for a specific constraint. Therefore, a looping solution strategy is proposed, whereby existing solutions are continuously removed during the solution process until the constraint becomes unsatisfiable. This embodiment proposes a new modeling method for AIG-format combinational circuits. Given the goal of estimating the soft error rate of AND gates within a combinational circuit, this embodiment treats the input, AND gate, and output of the combinational circuit as nodes, with the connections between them as edges. Furthermore, when considering the connections, the NOT gate is skipped and quantified as a feature on the edge. Overall, this embodiment proposes a systematic technical framework for rapidly estimating the soft error rate of each unit in a combinational circuit. Compared to previous methods, both those based on simulation-based fault models and those based on Boolean satisfiability problems are significantly more time-consuming. For a completely new combinational circuit (with approximately 10,000 gates), using previous methods often requires several hours or even days to obtain accurate results. However, using this embodiment's method, an estimated result is obtained in approximately ten minutes, and the mean absolute error of the soft error rate for each AND gate in the combinational circuit is within 10%. This embodiment, targeting integrated circuit electronic design automation (EDA), can quickly and efficiently estimate the soft error rate of each unit in a combinational logic circuit, while only considering the effects of logical shielding.

[0083] In addition, this embodiment also provides a system for rapid estimation of soft error rate based on graph neural network, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the method for rapid estimation of soft error rate based on graph neural network.

[0084] In addition, this embodiment also provides a computer-readable storage medium, which stores a computer program or instructions, and the computer program or instructions are programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0085] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0086] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions described in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0087] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for fast soft error rate estimation based on graph neural network, characterized in that: The steps include: S1, converting the estimated combinational circuit into a directed acyclic graph, where the nodes in the directed acyclic graph are the inputs, AND gates, and output units in the estimated combinational circuit, and the edges are the connections between the nodes; S2, adds feature information to the directed acyclic graph; S3, using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit using the directed acyclic graph with added feature information, wherein the graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate; Adding characteristic information to the directed acyclic graph in step S2 includes adding node characteristic information to the nodes in the directed acyclic graph, and the node characteristic information added to the directed acyclic graph includes part or all of the topological order of the node, the fan-in and fan-out number of the node, the number of associated inputs of the node, the number of outputs associated with the node, the number of paths between the node and the output, the average length of the path between the node and the output, and the average number of inputs associated with the path between the node and the output; Step S3 also includes training a graph neural network to establish a mapping relationship between a directed acyclic graph and a soft error rate: S101, obtaining a combinational circuit sample; S102, converting the combinational circuit sample into a combinational circuit sample in AIG format; S103, reading the structure information of the combinational circuit sample in AIG format, checking whether the read circuit structure information meets the specification, and discarding it if it does not meet the specification; S104: for each combinational circuit sample in the AIG format, convert the combinational circuit sample into a directed acyclic graph, where nodes in the directed acyclic graph represent circuit units in the combinational circuit sample, and edges represent connecting lines between circuit units in the combinational circuit sample. Feature information is added to the directed acyclic graph, and soft error rates of nodes in the combinational circuit sample are used as node labels. Node label information is added to construct a circuit dataset. S105, dividing the circuit data set into a training set and a test set; S106, using the training set and the test set to train the graph neural network to establish a mapping relationship between the directed acyclic graph and the soft error rate.

2. The method for fast soft error rate estimation based on graph neural network according to claim 1, characterized in that: The nodes in the directed acyclic graph in step S1 are AND gates of the combinational circuit, and the edges are connection lines of the AND gates in the combinational circuit. The NOT gates in the combinational circuit do not exist as nodes in the directed acyclic graph but are integrated on the edges of the directed acyclic graph. The use of a pre-trained graph neural network to regressively predict the soft error rate of the combinational circuit refers to using a pre-trained graph neural network to regressively predict the soft error rate of the AND gate in the combinational circuit. Adding feature information to the directed acyclic graph in step S2 includes adding edge feature information to the edges in the directed acyclic graph, and the function expression of the added edge feature information is: ， In the above formula, is the edge feature information; Used to indicate whether there is a NOT gate on the edge. If there is a NOT gate If there is no NOT gate, then ; Indicates the starting node position of the edge; Indicates the end node position of the edge, is the number of layers of the graph neural network.

3. The method for fast soft error rate estimation based on graph neural network according to claim 2, characterized in that: Converting the estimated combinational circuit into a directed acyclic graph in step S1 includes: S1.1, if the estimated combinational circuit is a combinational circuit in AIG format, jump to step S1.3, otherwise jump to step S1.2; S1.2, if the estimated combinational circuit is a combinational circuit in bench format, convert the bench format combinational circuit to Verilog format, and then use the tool Yosys to convert the Verilog format to AIG format; if the estimated combinational circuit is a combinational circuit in Verilog format, use the tool Yosys to convert the Verilog format to AIG format; if the estimated combinational circuit is a sequential circuit, first use the tool Yosys to convert the sequential circuit to table format, then use the trigger as the main input or main output of the sub-circuit, divide the table format sequential circuit into sub-circuits based on the trigger to obtain bench format sub-circuits, convert the bench format sub-circuits to Verilog format, and use the tool Yosys to convert the Verilog format to AIG format; if converted to AIG format, jump to step S1.3, otherwise end and exit; S1.3, read the structural information of the combinational circuit in the AIG format, and check whether the read circuit structural information meets the specification. If it meets the specification, generate a directed acyclic graph of the estimated combinational circuit according to the structural information of the combinational circuit in the AIG format, otherwise end and exit.

4. The method for fast soft error rate estimation based on graph neural network according to claim 1, characterized in that: Acquiring the soft error rate of the node in the combinational circuit sample includes: S201, using a depth-first search method to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, and store all paths from the circuit units to the main output port; S202, traversing and selecting a circuit unit as the current circuit unit; S203, conveniently selecting a sensitized path from all paths of the current circuit unit, wherein the sensitized path refers to a path from which a soft error can be successfully propagated to a main output without being logically masked; S204, adding the constraints of the sensitized path to the SAT solver; S205, using a SAT solver to cyclically solve for a satisfiable solution for the soft error of the current circuit unit. If no satisfiable solution can be obtained, jump to step S206; otherwise, determine whether there is an undefined signal in the obtained satisfiable solution. If there is an undefined signal in the satisfiable solution, jump to step S206; if there is no undefined signal in the satisfiable solution, add additional constraints to the SAT solver to mask the current solution obtained, and jump to step S205; S206, determine whether the sensitization path of the current circuit unit has been traversed. If the sensitization path of the current circuit unit has not been traversed, jump to step S203; otherwise, determine whether the circuit unit has been traversed. If the circuit unit has not been traversed, jump to step S202. If the circuit unit has been traversed, the soft error rate of the node in the combinational circuit sample is obtained.

5. The method for fast soft error rate estimation based on graph neural network according to claim 4, characterized in that: In step S201, when using the depth-first search method to obtain the set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, it includes using a dual stack to store the intermediate process of traversing the entire graph. The dual stack includes a main stack and an auxiliary stack. The main stack is used to store a single element, and the element is used to represent a node on the current path. The auxiliary stack stores a list of adjacent nodes corresponding to the element in the main stack. The length of the auxiliary stack is always consistent with that of the main stack. During the full-graph search, the main stack and the auxiliary stack are constantly changing, so that all paths between the target starting point and the main output port are obtained during the change of the main stack and the auxiliary stack.

6. A system for fast soft error rate estimation based on graph neural network, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for fast soft error rate estimation based on graph neural network as described in any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the method for fast soft error rate estimation based on graph neural network as described in any one of claims 1 to 5 through a processor.

8. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the method for fast soft error rate estimation based on graph neural network as described in any one of claims 1 to 5 through a processor.

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