Chip module level simulation test method and system, electronic equipment and medium

Abstract

The invention discloses a chip module level simulation test method and system, electronic equipment and a medium, and relates to the technical field of chip testing, a to-be-tested chip comprises a to-be-tested module, the to-be-tested module is provided with input ports and output ports, each input port and each output port are connected with a monitoring assembly, and the monitoring assemblies are connected with the to-be-tested module. The method comprises the following steps: configuring a template document by combining information of an input port and an output port of a to-be-tested module; reading template document information, and writing the template document information into a pre-configured monitoring component template file to generate a monitoring component; and monitoring the input port transactions and / or the output port transactions by adopting a monitoring component so as to capture abnormal transactions, setting the abnormal transactions to replace the abnormal transactions into a monitoring log of the monitoring component, and outputting the monitoring log. According to the method, the correctness of the function of the test module is assisted, the time and energy spent by verification personnel on problem positioning in the simulation test are saved, the verification efficiency is improved, and the module-level verification process is accelerated.

Description

Technical Field

[0001] The present application relates to the technical field of chip testing, and in particular to a chip module-level simulation testing method, system, electronic equipment and medium. Background Art

[0002] The main goal of the chip module-level verification is to ensure that the various modules of the chip can operate normally and stably when tested individually and in combination, and meet the design specifications and performance requirements. Only after completing the function and interface tests of each module can the subsequent subsystem-level and system-level verification be carried out. Therefore, module-level verification is the basis and key to the bottom-up verification process of the chip.

[0003] In some related technologies, the functions and characteristics of each module in the chip are quite different. Different modules are divided into different operation modes. Multiple interfaces may work at the same time. The test scenarios are relatively complex. The existing reference models used for testing are difficult to cover all test scenarios. There may be scenarios where the function of the module to be tested is abnormal but no error is reported, resulting in large deviations in the test process. In the simulation test, the problem is located through the generated log file. However, in the actual test process, it is common for the generated log file to be too large and contain a certain number of errors or the simulation process to get stuck, which makes it difficult to locate the problem. Summary of the invention

[0004] In order to solve at least one of the problems mentioned in the above background technology, the present application provides a chip module-level simulation test method, system, electronic device and medium to assist in testing the correctness of module functions, save the time and energy spent by verification personnel in locating problems in simulation testing, improve verification efficiency, and speed up the module-level verification process.

[0005] The specific technical solutions provided by the embodiments of this application are as follows:

[0006] In a first aspect, a chip module-level simulation test method is provided, which is applied to a chip to be tested, wherein the chip to be tested includes a module to be tested, and the module to be tested is provided with an input port and an output port, and each of the input port and the output port is connected to a monitoring component, and the method includes:

[0007] Configuring a template document in combination with the input port and the output port information of the module to be tested;

[0008] Reading the template document information, and writing the template document information into a preconfigured monitoring component template file to generate a monitoring component;

[0009] The monitoring component is used to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, the abnormal transactions are set to be replaced in the monitoring log of the monitoring component, and the monitoring log is output.

[0010] In a specific embodiment, the template document information is read and written into a preconfigured monitoring component template file to generate a monitoring component, which specifically includes: using a preset script to read the template document information and extracting interface information and configuration information in the template document; and writing the interface information and the configuration information into the preconfigured monitoring component template file to replace the information so as to generate the monitoring component.

[0011] In a specific embodiment, the input port is connected to an input-end monitor, and the output port is connected to an output-end monitor, and the method further includes: the input-end monitor is used to capture a first transaction from the input port, and transmit the first transaction to the monitoring component; the output-end monitor is used to capture a second transaction from the output port, and transmit the second transaction to the monitoring component; the monitoring component is used to parse the first transaction and the second transaction to obtain a transaction address; according to the transaction address, the first transaction and the second transaction are respectively stored in corresponding storage queues;

[0012] Obtain the queue status in the storage queue within a first preset time. If the queue status has not changed and is not 0, obtain the last group of data transactions in the storage queue, and set the type of the last group of data transactions to data exception; or, start counting when all standby flags are pulled high, and in response to the count value being equal to the preset simulation timeout in the template document, obtain the last group of data transactions in the storage queue, and set the type of the last group of data transactions to time exception.

[0013] In a specific embodiment, after parsing the first transaction and the second transaction by the monitoring component to obtain the transaction address, the method further includes: if the transaction address is a start or reset address for controlling the module to be tested, clearing the storage queue; or, if the transaction address is a function address for controlling the module to be tested, storing the function address for controlling the module to be tested in the command queue of the storage queue; or, if the transaction address is a control data volume address, parsing the control data volume address to obtain the total amount of data transmission, and storing the total amount of data transmission in the data queue of the storage queue.

[0014] In a specific embodiment, in response to the port signal of the input port or the output port not jumping within the second preset time, the standby flag is pulled high; or, in response to the port signal of the input port or the output port jumping, the standby flag is pulled low.

[0015] In a specific embodiment, the total amount of data transmission of the module to be tested within a preset simulation time is obtained, and an average transmission performance parameter within the preset simulation time is calculated; and the average transmission performance parameter is set as the transmission performance parameter of the associated output port.

[0016] In a specific embodiment, after the setting of replacing the abnormal transaction into the monitoring log of the monitoring component, the method also includes: obtaining all the abnormal transactions in the simulation process, and dividing the abnormal transactions into the associated monitoring logs according to the transaction types of the abnormal transactions; in response to receiving that the abnormal transaction is a time abnormal transaction, updating the monitoring log and ending the simulation.

[0017] In a second aspect, a chip module-level simulation test system is provided, which is used to implement the chip module-level simulation test method as described above, and is applied to a chip to be tested, wherein the chip to be tested includes a module to be tested, and the module to be tested is provided with an input port and an output port, and each of the input port and the output port is connected to a monitoring component, and the system further includes:

[0018] A template configuration unit, configured to configure a template document in combination with the input port and the output port information of the module to be tested;

[0019] A design unit, used for reading the template document information and writing the template document information into a pre-configured monitoring component template file to generate a monitoring component;

[0020] The dynamic monitoring unit is used to use the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, set the abnormal transactions to be replaced in the monitoring log of the monitoring component, and output the monitoring log.

[0021] In a third aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0022] Step A: configuring a template document in combination with the input port and the output port information of the module to be tested;

[0023] Step B: reading the template document information, and writing the template document information into a pre-configured monitoring component template file to generate a monitoring component;

[0024] Step C: using the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, setting the abnormal transactions to be replaced in the monitoring log of the monitoring component, and outputting the monitoring log.

[0025] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0026] Step A: configuring a template document in combination with the input port and the output port information of the module to be tested;

[0027] Step B: reading the template document information, and writing the template document information into a pre-configured monitoring component template file to generate a monitoring component;

[0028] Step C: using the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, setting the abnormal transactions to be replaced in the monitoring log of the monitoring component, and outputting the monitoring log.

[0029] The embodiments of the present application have the following beneficial effects:

[0030] 1. The embodiment of the present application provides a chip module-level simulation test method, which configures monitoring components for the input port and output port of the module to be tested on the chip to be tested to obtain the performance test results of each port. It can perform simulation tests of various complex scenarios on the module to be tested, and when an abnormality occurs, it can clear and accurately confirm all abnormal situations and corresponding interface signals, command sequences and trigger conditions that occur during the simulation process from the monitoring log, thereby saving a lot of time and labor costs; by storing the simulation test results in a database and continuously improving the data in the database, it can achieve effective feedback on the location of the abnormal information, and can be applicable to module-level verification of different functions and characteristics, thereby improving the verification and test efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram of a module to be tested according to the present application is shown;

[0033] Figure 2 A schematic diagram of a test system architecture based on a module to be tested according to the present application is shown;

[0034] Figure 3 A schematic diagram of a chip module level simulation test method according to the present application is shown;

[0035] Figure 4A schematic diagram showing a specific structure of a monitoring component according to the present application is shown;

[0036] Figure 5 A schematic diagram of a chip module-level simulation test system according to the present application is shown;

[0037] Figure 6 A schematic diagram showing a computer device according to the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] The present application provides a chip module level simulation test method, which is applied to a chip to be tested, such as Figure 1 As shown, the chip to be tested includes several modules to be tested, each of which is provided with an input port and an output port, the input port is connected to an input end monitor, the output port is connected to an output end monitor, the output ends of the input end monitor and the output end monitor are connected to a monitoring component, and a first-in-first-out queue is also provided between the input end monitor and the monitoring component and between the output end monitor and the monitoring component, and the first-in-first-out queue is used for data caching.

[0040] like Figure 2 As shown, the output end monitor of the module to be tested is connected to the monitoring component, and the output end of the monitoring component is also connected to the information processing component and the monitoring database in sequence, that is, the data information captured by the monitoring component is processed by the information processing component, and the processing result and the monitored data are transmitted to the monitoring database for storage, wherein the monitoring database is interactively connected with the information processing component to realize the communication between the information processing component and the monitoring database, and the abnormal situation information appearing in this simulation will be compared with the monitoring database and written into it, so as to update the monitoring database.

[0041] Further, such as Figure 3 As shown, the method comprises the following steps:

[0042] Step 101: configure a template document in combination with the input port and the output port information of the module to be tested.

[0043] In order to implement complex simulation tests of multiple scenarios on the module to be tested in this embodiment, Figure 1As shown, the module to be tested is set to have M input ports and N output ports, where M and N are integers greater than or equal to 1, and the monitoring component is set to have M+N groups of processing units, and the M+N groups of processing units specifically include M+N signal monitoring units, M+N analysis and storage units, 1 timing unit, and N performance calculation units. This configuration architecture is used to implement simulation testing of the module to be tested.

[0044] Furthermore, the design code files are hierarchically classified and numbered according to the design documents and design architecture. The file hierarchy is mainly divided into top-level files, common files and functional files. The file path, name and hierarchy number are written into the first part of the template document according to this hierarchical classification; the module to be tested has M input ports and N output ports. The number of input ports, the number of output ports, the core configuration and the simulation timeout of the module to be tested are written into the second part of the above-mentioned template document, wherein the core configuration information includes the transaction address for starting or resetting the control module, the transaction address for the control module function and the transaction address for controlling the data volume; the simulation timeout includes the time count value when the monitoring component detects that the input signal or output signal of each port has not jumped for a long time and thus ends the simulation, wherein the template document is selected and configured in the ".txt" format.

[0045] It should be noted that in this embodiment, a reference model is also provided at the output end of the input end monitor, and a first-in-first-out queue is also provided between the output end of the input end monitor and the reference model. The first-in-first-out queue is used to cache data. The other end of the reference model is also connected to the first-in-first-out queue and the scoreboard in sequence, and the output end of the output end monitor is also connected to the scoreboard to realize simulation testing of the chip to be tested through the reference model.

[0046] Step 102: read the template document information, and write the template document information into a preconfigured monitoring component template file to generate a monitoring component.

[0047] Specifically, it includes: using a preset script to read the template document information, extracting the interface information and configuration information in the template document; and writing the interface information and the configuration information into the pre-configured monitoring component template file to replace the information, so as to generate the monitoring component.

[0048] In this embodiment, the information of the template document is read in using a written Python or Perl script. First, M+N groups of processing units are generated in the monitoring component template file according to the number of input ports M and the number of output ports N of the module to be tested in the verification platform; then, the interface signal information in the design code files with different hierarchical numbers is extracted, and the interface signal is replaced in the corresponding signal monitoring unit in the dynamic monitoring component; then, the remaining configuration information such as the transaction address, simulation timeout, etc. are written into the monitoring component template file, and the information is replaced to generate a dynamic monitoring component. Further, the simulation test system of the dynamic monitoring component is transplanted into the simulation test environment and adapted. In the top-level environment of the verification platform, the input end monitor and the output end monitor of the module to be tested are respectively connected to the monitoring component through the TLM port protocol.

[0049] Step 103: Use the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, set the abnormal transactions to be replaced in the monitoring log of the monitoring component, and output the monitoring log.

[0050] The monitoring component in this embodiment is used to monitor, analyze and dynamically store the behavior of each input port and output port, specifically including capturing a first transaction from the input port through the input end monitor and transmitting the first transaction to the monitoring component; capturing a second transaction from the output port through the output end monitor and transmitting the second transaction to the monitoring component, and analyzing the first transaction and the second transaction through the monitoring component to obtain a transaction address; storing the first transaction and the second transaction in corresponding storage queues according to the transaction addresses; obtaining a queue state in the storage queue within a first preset time, if the queue state has not changed and is not 0, obtaining the last group of data transactions in the storage queue, and setting the type of the last group of data transactions to data exception; or, starting counting when all standby flags are pulled high, in response to the count value being equal to the preset simulation timeout in the template document, obtaining the last group of data transactions in the storage queue, and setting the type of the last group of data transactions to time exception.

[0051] In a specific embodiment, after the monitoring component parses the first transaction and the second transaction to obtain the transaction address, it also includes: if the transaction address is a start or reset address for controlling the module to be tested, clearing the storage queue; or, if the transaction address is a function address for controlling the module to be tested, storing the function address for controlling the module to be tested in the command queue of the storage queue; or, if the transaction address is a control data volume address, parsing the control data volume address to obtain the total amount of data transmission, and storing the total amount of data transmission in the data queue of the storage queue.

[0052] Specifically, Figure 4 As shown, the monitoring component in this embodiment includes a signal monitoring unit, a parsing and storage unit, a timing unit and a performance calculation unit. The input-end monitor captures a first transaction, the output-end monitor captures a second transaction, and the first transaction and the second transaction are transmitted to the monitoring component so that the first transaction and the second transaction are parsed, processed and stored through the parsing and storage unit in the monitoring component.

[0053] The signal jump and signal handshake of the input port or output port in the design code are monitored by the signal monitoring unit, and the jump time and signal value of each signal are stored in the signal queue. When the signal value exceeds the expected value, for example, if an uncertain state or an unexpected value appears or the signal has not been handshaked for a long time and has been in a waiting state, the last set of simulation time and signal value in the signal queue will be put into a transaction and transmitted to the information processing component through the output port of the dynamic monitoring component, and the type of the transaction is set to "Anomaly_IF".

[0054] The transaction transmitted by each input end monitor and output end monitor is parsed by the parsing storage unit, and the address of the transaction is determined. Exemplarily, if the transaction address is the transaction address of the control module startup or reset, the storage queue inside each parsing storage unit is cleared, if the transaction address is the control module function, the transaction is stored in the command queue inside the unit, if the transaction address is the control data volume, the total data transmission obtained by parsing the transaction is stored in the data queue inside the unit; if it is other transaction addresses, the data transmission of the transaction is executed, and after each data transmission, the total data transmission corresponding to the command in the data queue is subtracted from the data transmission volume of the current transaction, until the total data transmission volume of the command is cleared to 0. If the total data transmission volume of a certain command in the data queue does not change within a period of time and is not 0, the last transaction address in the command queue of the current parsing storage unit and the last group of data transmission volume in the data queue are placed in the transaction and transmitted to the information processing component through the output port of the monitoring component, and the type of the transaction is set to "Anomaly_Data".

[0055] In a specific embodiment, it also includes pulling up a standby flag in response to no jump in the port signal of the input port or the output port within the second preset time; or pulling down the standby flag in response to a jump in the port signal of the input port or the output port.

[0056] Furthermore, the total amount of data transmission of the module to be tested within a preset simulation time is obtained, and an average transmission performance parameter within the preset simulation time is calculated; the average transmission performance parameter is set as the transmission performance parameter of the associated output port.

[0057] The timing unit is used to monitor whether each data output port has been idle for a long time during the simulation test to prevent the simulation process from being stuck. Exemplarily, when all port signals of a certain signal monitoring port have not changed within a period of time, the standby flag "wait_flag" is pulled high, and when the signal changes, the standby flag is pulled low. The standby flag in each signal monitoring unit can be sensed by the timing unit. When all the standby flags are pulled high, the timing unit starts counting internally, and each clock cycle count is increased by 1. When the count value is equal to the simulation timeout value filled in the template document, the last transaction address in the command queue of each parsing storage unit and the last group of data transmission totals in the data queue will be put into the transaction and transmitted to the information processing component through the output port of the dynamic monitoring component. The type of the transaction is set to "Anomaly_Time".

[0058] The performance calculation unit mainly calculates the bus transmission performance and bus utilization of each output port within a fixed time. The verification personnel can judge whether the current test stimulus needs to be adjusted appropriately based on the performance calculation results. For example, if the depth of the command queue in the analysis storage unit corresponding to the performance storage unit changes, a random delay is performed, and the amount of data transmitted during the current simulation time and a fixed period of time thereafter is recorded after the delay. The amount of data divided by the fixed time is the bus transmission performance of the current time. The data signal handshake time within the fixed time can be obtained from the signal monitoring unit. The data signal handshake time divided by the fixed time is the bus utilization of the current time.

[0059] During the entire simulation test process, the performance calculation unit may calculate the bus transmission performance and bus utilization multiple times, obtain the average value of the multiple bus transmission performance and bus utilization as the bus transmission performance and bus utilization of each output port, and put the bus transmission performance and bus utilization of each output port into a transaction through the output port of the monitoring component and transmit it to the information processing component. The type of the transaction is set to "Eff_Result".

[0060] The information processing component in this embodiment can receive transactions transmitted from the monitoring component, wherein the abnormal transactions in the monitoring log include types such as "Error, UVM_Error, Warning, UVM_Warning, and UVM_Fatal", wherein the abnormal transactions include simulation time, structural hierarchy, print information added by the verifier, the location where the abnormal transaction is generated in the verification platform, etc.

[0061] In a specific embodiment, the information processing component reads the simulation directory generated under the current simulation directory in real time according to predefined simulation parameters, identifies abnormal transactions, captures, counts and classifies abnormal transactions through keyword comparison, and continuously replaces abnormal transaction information into the monitoring log template according to the type to generate a monitoring log. At the same time, the corresponding code that verifies that the environment does not meet the conditions when the abnormal situation occurs is also intercepted and output to the monitoring log to realize dynamic updating of the monitoring log.

[0062] Furthermore, the monitoring log is output and stored in the monitoring database, and compared with the previous abnormal information in the monitoring database to determine whether there are completely consistent or highly similar abnormal situations, and the comparison results are output to the monitoring log. The information processing component outputs the transactions transmitted by the monitoring component to the monitoring log according to the transaction type as timeout conditions, performance monitoring results, signal abnormalities, etc. When the signal processing unit receives a transaction of the Anomaly_Time type, the simulation ends after completing the monitoring log update.

[0063] In a specific embodiment, after the setting of replacing the abnormal transaction into the monitoring log of the monitoring component, it also includes: obtaining all the abnormal transactions in the simulation process, and dividing the abnormal transactions into the associated monitoring logs according to the transaction types of the abnormal transactions; in response to receiving that the abnormal transaction is a time abnormal transaction, updating the monitoring log and ending the simulation.

[0064] It should be noted that the template of the monitoring log in this implementation is divided into multiple parts, including abnormal situation information, statistical results, interception code, comparison results, performance monitoring results, signal abnormalities, timeout conditions, etc., which can be matched and replaced according to keywords to update the information in the monitoring log.

[0065] Through the scheme in this embodiment, simulation tests of various complex scenarios can be performed on the module to be tested, and when an abnormality occurs, all abnormal situations occurring during the simulation process and the corresponding interface signals, command sequences and trigger conditions can be cleared and accurately confirmed from the monitoring log, saving a lot of time and labor costs; by storing the simulation test results in a database and continuously improving the data in the database, effective feedback on the location of the abnormal information can be achieved, and it can be applicable to module-level verification of different functions and characteristics, thereby improving the verification and testing efficiency of the chip.

[0066] Embodiment 2

[0067] Corresponding to the above embodiment, the present application provides a chip module level simulation test system, which is used to implement the chip module level simulation test method as described above, and is applied to a chip to be tested, wherein the chip to be tested includes a module to be tested, and the module to be tested is provided with an input port and an output port, and each of the input port and the output port is connected to a monitoring component, such as Figure 5 As shown, the system further includes: a template configuration unit, configured to configure a template document in combination with the input port and the output port information of the module to be tested;

[0068] A design unit, used for reading the template document information and writing the template document information into a pre-configured monitoring component template file to generate a monitoring component;

[0069] The dynamic monitoring unit is used to use the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, set the abnormal transactions to be replaced in the monitoring log of the monitoring component, and output the monitoring log.

[0070] In this embodiment, the template configuration unit is also used to read the template document information using a preset script, extract the interface information and configuration information in the template document; and write the interface information and the configuration information into the pre-configured monitoring component template file for information replacement to generate the monitoring component.

[0071] In a specific embodiment, the system also includes an input-end monitor and an output-end monitor, wherein the input-end monitor is used to capture a first transaction from the input port and transmit the first transaction to the monitoring component; the output-end monitor is used to capture a second transaction from the output port and transmit the second transaction to the monitoring component; the first transaction and the second transaction are parsed by the monitoring component to obtain a transaction address; the first transaction and the second transaction are stored in corresponding storage queues according to the transaction addresses; the queue status in the storage queue within a first preset time is obtained, if the queue status has not changed and is not 0, the last group of data transactions in the storage queue is obtained, and the type of the last group of data transactions is set to data exception; or, when all standby flags are pulled high, counting starts, in response to the count value being equal to the preset simulation timeout in the template document, the last group of data transactions in the storage queue is obtained, and the type of the last group of data transactions is set to time exception.

[0072] In a specific embodiment, the dynamic monitoring unit is also used to clear the storage queue if the transaction address is a start or reset address for controlling the module to be tested; or, if the transaction address is a function address for controlling the module to be tested, store the function address for controlling the module to be tested in the command queue of the storage queue; or, if the transaction address is a control data volume address, parse the control data volume address to obtain the total amount of data transmission, and store the total amount of data transmission in the data queue of the storage queue.

[0073] In a specific embodiment, the dynamic monitoring unit is also used to pull up the standby flag in response to the port signal of the input port or the output port not jumping within the second preset time; or, to pull down the standby flag in response to the port signal of the input port or the output port jumping.

[0074] In a specific embodiment, the dynamic monitoring unit is also used to obtain the total amount of data transmission of the module under test within a preset simulation time, and calculate the average transmission performance parameter within the preset simulation time; and set the average transmission performance parameter as the transmission performance parameter of the associated output port.

[0075] In a specific embodiment, the dynamic monitoring unit is also used to obtain all the abnormal transactions in the simulation process, and divide the abnormal transactions into the associated monitoring logs according to the transaction types of the abnormal transactions; in response to receiving that the abnormal transaction is a time abnormal transaction, the monitoring log is updated and the simulation is ended.

[0076] Embodiment 3

[0077] A computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0078] Step 201: configuring a template document in combination with the input port and the output port information of the module to be tested;

[0079] Step 202: read the template document information, and write the template document information into a pre-configured monitoring component template file to generate a monitoring component;

[0080] Step 203: Use the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, set the abnormal transactions to be replaced in the monitoring log of the monitoring component, and output the monitoring log.

[0081] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0082] The template document information is read by a preset script to extract the interface information and configuration information in the template document; and the interface information and the configuration information are written into the pre-configured monitoring component template file for information replacement to generate the monitoring component.

[0083] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0084] The input-end monitor is used to capture a first transaction from the input port and transmit the first transaction to the monitoring component; the output-end monitor is used to capture a second transaction from the output port and transmit the second transaction to the monitoring component; the first transaction and the second transaction are parsed by the monitoring component to obtain a transaction address; the first transaction and the second transaction are stored in corresponding storage queues according to the transaction addresses; the queue state in the storage queue within a first preset time is obtained, if the queue state does not change and is not 0, the last group of data transactions in the storage queue is obtained, and the type of the last group of data transactions is set to data exception; or, when all standby flags are pulled high, counting is started, in response to the count value being equal to the preset simulation timeout in the template document, the last group of data transactions in the storage queue is obtained, and the type of the last group of data transactions is set to time exception.

[0085] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0086] If the transaction address is a start or reset address for controlling the module to be tested, the storage queue is cleared; or, if the transaction address is a function address for controlling the module to be tested, the function address for controlling the module to be tested is stored in the command queue of the storage queue; or, if the transaction address is a control data volume address, the control data volume address is parsed to obtain the total amount of data transmission, and the total amount of data transmission is stored in the data queue of the storage queue.

[0087] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0088] In response to the port signal of the input port or the output port not jumping within the second preset time, the standby flag is pulled high; or, in response to the port signal of the input port or the output port jumping, the standby flag is pulled low.

[0089] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0090] The total amount of data transmission of the module to be tested within a preset simulation time is obtained, and an average transmission performance parameter within the preset simulation time is calculated; and the average transmission performance parameter is set as the transmission performance parameter of the associated output port.

[0091] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0092] All the abnormal transactions in the simulation process are obtained, and the abnormal transactions are divided into the associated monitoring logs according to the transaction types of the abnormal transactions; in response to receiving that the abnormal transaction is a time abnormal transaction, the monitoring log is updated and the simulation is ended.

[0093] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store monitoring log data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a chip module-level simulation test method is implemented.

[0094] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0095] Embodiment 4

[0096] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0097] Step 301: configure a template document in combination with the input port and the output port information of the module to be tested;

[0098] Step 302: read the template document information, and write the template document information into a pre-configured monitoring component template file to generate a monitoring component;

[0099] Step 303: Use the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, set the abnormal transactions to be replaced in the monitoring log of the monitoring component, and output the monitoring log.

[0100] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0101] The template document information is read by a preset script to extract the interface information and configuration information in the template document; and the interface information and the configuration information are written into the pre-configured monitoring component template file for information replacement to generate the monitoring component.

[0102] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0103] The input-end monitor is used to capture a first transaction from the input port and transmit the first transaction to the monitoring component; the output-end monitor is used to capture a second transaction from the output port and transmit the second transaction to the monitoring component; the first transaction and the second transaction are parsed by the monitoring component to obtain a transaction address; the first transaction and the second transaction are stored in corresponding storage queues according to the transaction addresses; the queue state in the storage queue within a first preset time is obtained, if the queue state does not change and is not 0, the last group of data transactions in the storage queue is obtained, and the type of the last group of data transactions is set to data exception; or, when all standby flags are pulled high, counting is started, in response to the count value being equal to the preset simulation timeout in the template document, the last group of data transactions in the storage queue is obtained, and the type of the last group of data transactions is set to time exception.

[0104] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0105] If the transaction address is a start or reset address for controlling the module to be tested, the storage queue is cleared; or, if the transaction address is a function address for controlling the module to be tested, the function address for controlling the module to be tested is stored in the command queue of the storage queue; or, if the transaction address is a control data volume address, the control data volume address is parsed to obtain the total amount of data transmission, and the total amount of data transmission is stored in the data queue of the storage queue.

[0106] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0107] In response to the port signal of the input port or the output port not jumping within the second preset time, the standby flag is pulled high; or, in response to the port signal of the input port or the output port jumping, the standby flag is pulled low.

[0108] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0109] The total amount of data transmission of the module to be tested within a preset simulation time is obtained, and an average transmission performance parameter within the preset simulation time is calculated; and the average transmission performance parameter is set as the transmission performance parameter of the associated output port.

[0110] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0111] All the abnormal transactions in the simulation process are obtained, and the abnormal transactions are divided into the associated monitoring logs according to the transaction types of the abnormal transactions; in response to receiving that the abnormal transaction is a time abnormal transaction, the monitoring log is updated and the simulation is ended.

[0112] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0113] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0114] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip module level simulation test method, characterized in that: Applied to a chip to be tested, the chip to be tested includes a module to be tested, the module to be tested is provided with an input port and an output port, each of the input port and the output port is connected to a monitoring component, the method includes: Configuring a template document in combination with the input port and the output port information of the module to be tested; Reading the template document information, and writing the template document information into a preconfigured monitoring component template file to generate a monitoring component; The monitoring component is used to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, the abnormal transactions are set to be replaced in the monitoring log of the monitoring component, and the monitoring log is output.

2. The chip module level simulation test method according to claim 1, characterized in that: Reading the template document information and writing the template document information into a preconfigured monitoring component template file to generate a monitoring component specifically includes: Using a preset script to read the template document information, extracting the interface information and configuration information in the template document; The interface information and the configuration information are written into the pre-configured monitoring component template file to perform information replacement, so as to generate the monitoring component.

3. The chip module level simulation test method according to claim 1 or 2, characterized in that: The input port is connected to an input end monitor, the output port is connected to an output end monitor, and the method further comprises: The input end monitor is used to capture a first transaction from the input port and transmit the first transaction to the monitoring component; The output end monitor is used to capture a second transaction from the output port and transmit the second transaction to the monitoring component; Parsing the first transaction and the second transaction by the monitoring component to obtain a transaction address; storing the first transaction and the second transaction in corresponding storage queues respectively according to the transaction addresses; Obtaining a queue state in the storage queue within a first preset time, and if the queue state does not change and is not 0, obtaining the last group of data transactions in the storage queue, and setting the type of the last group of data transactions to data exception; Alternatively, counting starts when all standby flags are pulled high, and in response to the count value being equal to a preset simulation timeout in the template document, the last group of data transactions in the storage queue is obtained, and the type of the last group of data transactions is set to time anomaly.

4. The chip module level simulation test method according to claim 3, characterized in that: After parsing the first transaction and the second transaction by the monitoring component to obtain a transaction address, the method further includes: If the transaction address is an address for controlling the start or reset of the module to be tested, clearing the storage queue; Alternatively, if the transaction address is a function address of controlling the module to be tested, storing the function address of controlling the module to be tested in a command queue of the storage queue; Alternatively, if the transaction address is a control data volume address, the control data volume address is parsed to obtain the total data transmission amount, and the total data transmission amount is stored in the data queue of the storage queue.

5. The chip module level simulation test method according to claim 3, characterized in that: The method further comprises: In response to the port signal of the input port or the output port not changing within the second preset time, a standby flag is pulled high; Alternatively, in response to a jump in a port signal of the input port or the output port, the standby flag is pulled low.

6. The chip module level simulation test method according to claim 1 or 2, characterized in that: The method further comprises: Obtaining the total amount of data transmission of the module to be tested within a preset simulation time, and calculating the average transmission performance parameter within the preset simulation time; The average transmission performance parameter is set as the transmission performance parameter of the associated output port.

7. The chip module level simulation test method according to claim 3, characterized in that: After the setting of replacing the abnormal transaction into the monitoring log of the monitoring component, the method further includes: Acquire all the abnormal transactions in the simulation process, and classify the abnormal transactions into the associated monitoring logs according to the transaction types of the abnormal transactions; In response to receiving that the abnormal transaction is a time abnormal transaction, the monitoring log is updated and the simulation ends.

8. A chip module level simulation test system, used to implement the chip module level simulation test method according to any one of claims 1 to 7, characterized in that: Applied to a chip to be tested, the chip to be tested includes a module to be tested, the module to be tested is provided with an input port and an output port, each of the input port and the output port is connected to a monitoring component, and the system further includes: A template configuration unit, configured to configure a template document in combination with the input port and the output port information of the module to be tested; A design unit, used for reading the template document information and writing the template document information into a pre-configured monitoring component template file to generate a monitoring component; The dynamic monitoring unit is used to use the monitoring component to monitor the input port transaction and / or the output port transaction to capture abnormal transactions, set the abnormal transactions to be replaced in the monitoring log of the monitoring component, and output the monitoring log.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images