Radio frequency identification tag, baseband communication receiving link circuit thereof and baseband communication method thereof

Abstract

The invention relates to a radio frequency identification tag, a baseband communication receiving link circuit of the radio frequency identification tag and a baseband communication method of the radio frequency identification tag. The baseband communication receiving link circuit comprises a clock frequency division module, a gating clock module, a PIE decoding module, a command analysis module and a CRC verification module. The PIE decoding module is used for receiving to-be-decoded data, decoding the to-be-decoded data to obtain decoded data, and simultaneously providing the decoded data to the command analysis module and the CRC verification module; the command analysis module is used for receiving the decoded data and carrying out command judgment and parameter analysis on the decoded data so as to output command parameters and analysis commands; and the CRC module is used for receiving the decoded data and executing cyclic redundancy check to output a check result. In the design, when the PIE decoding module begins to decode the received to-be-decoded data, the command analysis module and the CRC verification module also immediately start to process the decoded data, and the sub-modules adopt a parallel working mode, so that the processing time can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency identification technology, and in particular to a radio frequency identification tag, a baseband communication receiving link circuit thereof, and a baseband communication method thereof. Background Art

[0002] Radio Frequency Identification (RFID) technology, as a means of long-distance communication, is widely used in scenarios such as object identification, tracking, positioning and management. In particular, it has broad application prospects in the fields of industrial automation, commercial automation, transportation control and management, anti-counterfeiting, and military use, and has attracted widespread attention.

[0003] In the related art, due to the limitation of its own structure, the efficiency of the tag in processing data is limited to a certain extent (ie, low efficiency). Therefore, how to effectively improve the efficiency of the tag in processing data has become an urgent problem to be solved. Summary of the invention

[0004] The purpose of the present invention is to provide a radio frequency identification tag, a baseband communication receiving link circuit thereof, and a baseband communication method thereof, which can solve the problem of low efficiency of tag processing data due to the limitation of its own structure in the related art.

[0005] In a first aspect, the present invention provides a baseband communication receiving link circuit of a radio frequency identification tag; the baseband communication receiving link circuit includes a clock division module, a gated clock module, a PIE decoding module, a command parsing module and a CRC check module; the clock division module is electrically connected to the gated clock module, and is used to receive a system clock signal and output a plurality of divided clock signals to the gated clock module; the gated clock module is electrically connected to the PIE decoding module, the command parsing module and the CRC check module, and is used to receive a plurality of divided clock signals, and provide the required clock signals to the PIE decoding module, the command parsing module and the CRC check module; the PIE decoding module is electrically connected to the command parsing module and the CRC check module, and is used to receive data to be decoded, and decode the data to be decoded to obtain decoded data, so as to provide the decoded data to the command parsing module and the CRC check module at the same time; the command parsing module is used to receive the decoded data and perform instruction judgment and parameter parsing on the decoded data to output command parameters and parsing commands; the CRC check module is electrically connected to the command parsing module, and is used to receive the decoded data and perform a cyclic redundancy check to output a check result.

[0006] Based on the baseband communication receiving link circuit of the radio frequency identification tag in the present invention, when processing data, the traditional RFID tag usually completes decoding first, then performs CRC check, and finally executes command parsing; however, in the present invention, through the parallel working mode of each submodule, when the PIE decoding module starts to decode the received data to be decoded, the command parsing module and the CRC check module also immediately start to process the decoded data after decoding, without waiting for the end of the entire decoding process of the PIE decoding module, which greatly reduces the processing time. By processing data immediately instead of storing it first and then operating it, there is no need to use a large number of registers to store intermediate results, which can reduce the use of registers, not only reducing the label area, but also reducing the running time and power consumption.

[0007] In a second aspect, the present invention provides a radio frequency identification tag; the radio frequency identification tag includes a carrier, a baseband communication receiving link circuit arranged on the carrier, a radio frequency analog front end, and a memory, the radio frequency analog front end includes a radio frequency antenna and is electrically connected to the baseband communication receiving link circuit, the memory is electrically connected to the baseband communication receiving link circuit, and is characterized in that the baseband communication receiving link circuit adopts the baseband communication receiving link circuit of any one of the radio frequency identification tags mentioned above.

[0008] Based on the radio frequency identification tag in the present invention, with the above-mentioned baseband communication receiving link circuit, through the parallel working mode of each submodule, when the PIE decoding module starts to decode the received data to be decoded, the command parsing module and the CRC check module also immediately start to process the decoded data after decoding, without waiting for the end of the entire decoding process of the PIE decoding module, which greatly reduces the processing time. By processing data immediately instead of storing it first and then operating it, there is no need to use a large number of registers to store intermediate results, which can reduce the use of registers, not only reducing the label area, but also reducing the running time and power consumption.

[0009] In a third aspect, the present invention provides a baseband communication method for a radio frequency identification tag; the baseband communication method for a radio frequency identification tag comprises the following steps:

[0010] Used to receive data to be decoded, and decode the data to be decoded to obtain decoded data, so as to provide the decoded data to the command parsing module and the CRC check module at the same time;

[0011] The command parsing module receives the decoded data and performs instruction judgment and parameter parsing on the decoded data to output command parameters and parsed commands; and

[0012] The CRC check module receives the decoded data and performs a cyclic redundancy check to output a check result.

[0013] Based on the baseband communication method of the radio frequency identification tag in the present invention, when the baseband communication method of the traditional RFID tag is used to process data, decoding is usually completed first, then CRC check is performed, and finally command parsing is performed; however, the baseband communication method of the radio frequency identification tag in the present invention decodes the received data to be decoded, and the command parsing module and the CRC check module also immediately start processing the decoded data after decoding. This parallel working mode does not need to wait for the end of the entire decoding process, which can greatly reduce the processing time. By processing data immediately instead of storing it first and then operating it, there is no need to use a large number of registers to store intermediate results, which can reduce the use of registers, not only reducing the tag area, but also reducing the running time and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a radio frequency identification tag provided by one embodiment of the present invention;

[0015] Figure 2 A schematic diagram of a module framework structure of a baseband communication receiving link circuit of a radio frequency identification tag provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of PIE encoding of a preamble, data "0" and data "1" provided in one embodiment of the present invention;

[0017] Figure 4 A schematic diagram of a state transition process of a PIE decoding state machine provided by an embodiment of the present invention;

[0018] Figure 5 A schematic diagram of a flow chart of parallel processing of modules in a baseband communication receiving link circuit provided by one embodiment of the present invention;

[0019] Figure 6 for Figure 5 The command header parsing flow chart of the parsing command in;

[0020] Figure 7 A schematic diagram of a CRC check module provided by one embodiment of the present invention;

[0021] Figure 8 A schematic flow chart of a baseband communication method for a radio frequency identification tag provided by an embodiment of the present invention.

[0022] Figure numerals: 1. Radio frequency identification tag; 10. Carrier; 20. Baseband communication receiving link circuit; 21. Clock division module; 22. Gate control clock module; 23. PIE decoding module; 231. PIE pre-synchronization code counting detection circuit; 232. PIE data judgment circuit; 24. Command parsing module; 241. Instruction parsing circuit; 242. Parameter extraction circuit; 25. CRC check module; 251. CRC mode control circuit; 252. CRC-5 mode check circuit; 253. CRC-16 mode check circuit; 26. General control module; 30. RF analog front end; 40. Memory. DETAILED DESCRIPTION

[0023] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0024] Radio Frequency Identification (RFID) technology, as a means of long-distance communication, is widely used in scenarios such as object identification, tracking, positioning and management. In particular, it has broad application prospects in the fields of industrial automation, commercial automation, transportation control and management, anti-counterfeiting, and military use, and has attracted widespread attention.

[0025] In related technologies, due to the limitation of its own structure, after receiving data, the tag usually completes decoding first, then performs CRC check, and finally executes command parsing. This sequential processing method limits the overall performance and efficiency of the system to a certain extent (especially in application scenarios that require fast response). Therefore, how to effectively improve the efficiency of tag processing data has become an urgent problem to be solved.

[0026] In order to solve the above problems, the embodiment of the present invention provides a baseband communication receiving link circuit 20 of a radio frequency identification tag 1 with high efficiency, a radio frequency identification tag 1 and a baseband communication method thereof. Among them, the baseband communication receiving link circuit 20 of the radio frequency identification tag 1, the radio frequency identification tag 1 and the baseband communication method thereof can be used in, but not limited to, scenes such as object identification, tracking, positioning and management; in particular, they have broad application prospects in industrial automation, commercial automation, transportation control management, anti-counterfeiting, and military use, and have attracted widespread attention.

[0027] Reference Figure 1 As shown, Figure 1 The figure is a schematic diagram of the structure of a radio frequency identification tag in one embodiment of the present invention. Figure 1 The illustrated radio frequency identification tag 1 includes a carrier 10 , a baseband communication receiving link circuit 20 disposed on the carrier 10 , a radio frequency analog front end 30 (which may be composed of a transmitting circuit and a receiving circuit), and a memory 40 .

[0028] The carrier 10 is a physical medium used for storing and transmitting data in the RFID tag 1 , and can be made of, but is not limited to, paper, plastic (such as PET), polyester, and other materials.

[0029] The baseband communication receiving link circuit 20 is used to execute the operation corresponding to the command, and the baseband communication receiving link circuit 20 will be specifically introduced below. It should be noted that the RFID tag 1 having the baseband communication receiving link circuit 20 is an ultra-high RFID tag 1, and the frequency band of the RFID tag 1 is 0.3-3GHZ.

[0030] The RF analog front end 30 includes an RF antenna and is electrically connected to the baseband communication receiving link circuit 20. The RF analog front end 30 is used to receive external commands and forward them to the baseband communication receiving link circuit 20. It is also used to receive data that the baseband communication receiving link circuit 20 needs to send out and send the data out.

[0031] The memory 40 is used to store data and is electrically connected to the baseband communication receiving link circuit 20. The memory 40 can be, but is not limited to, ROM / RAM, a magnetic disk, an optical disk, etc.

[0032] Understandably, Figure 1 The structure of the RFID tag 1 shown in the figure does not constitute a limitation on the RFID tag 1. In actual implementation, the RFID tag 1 may also include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0033] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a module framework structure of a baseband communication receiving link circuit of an RFID tag shown in an embodiment of the present invention. Figure 2 As shown, the baseband communication receiving link circuit 20 includes a clock division module 21, a gated clock module 22, a PIE (Pulse Interval Encoding) decoding module 23, a command parsing module 24 and a CRC (Cyclic Redundancy Check) checking module 25.

[0034] The clock frequency division module 21 is electrically connected to the gated clock module 22 . The clock frequency division module 21 is used to receive a system clock signal and output a plurality of frequency-divided clock signals to the gated clock module 22 .

[0035] Among them, the clock frequency division module 21 can perform clock frequency division control according to the requirements of different submodules. It can be understood that the selection of system clock frequency is the key to reducing power consumption, and the lower the operating clock frequency, the lower the chip power consumption. According to the minimum clock frequency required by the protocol, the clock must meet a certain frequency to accurately decode the incoming data and backscatter the response at each specified data rate. Therefore, the system clock frequency used in the present invention is 1.92MHz, and the clock frequency of each submodule is provided by the clock frequency division module 21 by dividing the system clock frequency 1.92MHz. In order to optimize the balance between power consumption and performance; for example, the clock frequency division module 21 can provide a 1.92MHz system clock for the PIE decoding module 23; the clock frequency division module 21 can provide a 480KHz clock for the command parsing module 24 and the CRC check module 25; the clock frequency division module 21 can provide a 240KHz clock for the general control module 26 (described below). Since different submodules have different requirements for clock frequency, this multi-clock design can significantly reduce the overall power consumption while meeting the functional requirements of each submodule. It is worth mentioning that a high-speed clock is used for sub-modules with processing speed requirements (such as the PIE decoding module 23), and a low-speed clock is used for sub-modules with more registers or more operations (such as the command parsing module 24, the CRC check module 25 and the main control module 26). This design can significantly reduce power consumption.

[0036] The gated clock module 22 is electrically connected to the PIE decoding module 23 , the command parsing module 24 and the CRC checking module 25 . The gated clock module 22 is used to receive multiple divided clock signals and provide the required divided clock signals to the PIE decoding module 23 , the command parsing module 24 and the CRC checking module 25 .

[0037] The gated clock module 22 generates a stable and glitch-free clock signal by calling the gated clock unit in the standard design unit, and controls the normal operation of each submodule by generating a clock gating enable signal. The gated clock module 22 enables each submodule according to different working stages, and reduces unnecessary dynamic power consumption by controlling the clock signal of each submodule, so as to ensure that the corresponding submodule is activated only when needed, thereby saving power.

[0038] The gated clock module 22 has three different working phases: power-on phase, idle phase and receiving phase, which are specifically:

[0039] Power-on stage: the tag reads the CRC-16 data in the EPC address area in its internal EEPROM memory 40, and uses the read CRC-16 data as the initial value of the CRC check.

[0040] Idle phase: the tag waits for the frequency division clock command to arrive, the PIE decoding module 23 and the MCM (Multi-Chip Module) module are running, and jumps to the receiving phase when the frequency division clock command arrives.

[0041] Receiving stage: The PIE decoding module 23, the command parsing module 24 and the CRC checking module 25 are activated, and the decoded data are parsed and CRC checked while decoding the data to be decoded.

[0042] The PIE decoding module 23 is electrically connected to the command parsing module 24 and the CRC checking module 25 . The PIE decoding module 23 is used to receive data to be decoded, and decode the data to be decoded to obtain decoded data, so as to provide the decoded data to the command parsing module 24 and the CRC checking module 25 at the same time.

[0043] The PIE decoding module 23 receives the data to be decoded returned by the RF analog front end 30. The PIE decoding module 23 determines the delimiter, R=>T check mark (RTcal), T=>R check mark (TRcal), data "0" and data "1" by judging the time length between two rising edges of the data to be decoded. Figure 2 As shown, the input signal is the data to be decoded of the analog part, and the rising edge is obtained for counting, and then the count value N is obtained by the counter, and compared with the pivot, so as to obtain the decoded data after the PIE decoding module 23 decodes. For the PIE decoding module 23, the present invention extracts the following by designing the PIE decoding module 23 as a PIE decoding state machine: Figure 3 The relevant parameters in the preamble or frame sync code shown in FIG. 1 and the state transition flow diagram of the PIE decoding state machine are shown in FIG. Figure 4 As shown, Figure 4 As shown, the PIE decoding state machine has the following 6 decision states:

[0044] IDLE determination state: In this state, the data is initialized to determine whether the delimiter has arrived. If so, it jumps to the delimiter determination state, otherwise, it continues to maintain this state.

[0045] Delimiter determination state: The time length of the Delimiter in the frame structure is about 12.5us. This state determines whether the delimiter is valid at this time. If so, it waits for the next clock rising edge and then jumps to the Tari determination state. If not, it jumps to the IDLE state.

[0046] Tari determination state: In this state, the counter counts Tari and determines the time length of a Tari together with the clock cycle, and then waits for the next clock rising edge to jump to the RTcal determination state.

[0047] RTcal determination state: In this state, the counter counts RTcal to determine the RTcal frame field, and then determines whether the count value exceeds the specified range of the protocol (2.5Tari~3.0Tari). If so, it enters the ERROR state, outputs the decoding error flag and jumps to the IDLE state. If not, the count value is recorded as RTcal_CNT, and jumps to the TRcal determination state at the next clock rising edge.

[0048] TRcal determination state: In this state, the counter counts TRcal, data "0" or data "1". If the count length of CNT is less than RTcal_CNT, it means that CNT counts data "0" and data "1". Then, it is compared with RTcal_CNT / 2 (called pivot) to determine whether it is data "0" or data "1", and the state jumps to the subsequent data determination state. If the count length of CNT is greater than or equal to RTcal_CNT, it means that CNT counts TRcal, so CNT is assigned to the count value of TRcal, and then jumps to the subsequent data determination state when the rising edge of the clock arrives. It should be noted that since the frame structure includes the preamble and the frame synchronization code, and the frame synchronization code does not have TRcal, it is not possible to immediately determine whether CNT counts TRcal or counts data "0" or data "1". Since the length range of TRcal is larger than the length range of data "0" and data "1" (the length range of TRcal is 1.1RTcal≤TRcal≤3RTcal, and the length range of RTcal is 2.5Tari≤RTcal≤3Tari), it is most appropriate to use RTcal_CNT as the judgment standard of CNT. The length of data "0" is 1Tari, and the length range of data "1" is 2.5Tari≤Data-1≤3Tari. Half of the length of RTcal_CNT (called piovt) is used as the judgment standard of data "0" and data "1". If CNT exceeds the range of the protocol (i.e. CNT>3RTcal_CNT), the data to be decoded is determined to be illegal data, enters the ERROR state, outputs the decoding error flag and jumps to the IDLE state.

[0049] Data determination state: In this state, data "0" and data "1" are counted, and then it is determined whether CNT at this time exceeds the specified range of the protocol. If RTcal_CNT<CNT<2RTcal_CNT, the data to be decoded is determined to be illegal data, and the ERROR state is entered. The decoding error flag is output and the state is jumped to the IDLE state. If CNT≤RTcal_CNT or CNT≥2RTcal_CNT, it remains in this state and compares CNT with RTcal_CNT / 2 (i.e. pivot) to determine whether it is data "0" or data "1". If CNT exceeds 2 times RTcal_CNT and is still counting, the decoding is completed and the decoding completion flag is output.

[0050] like Figure 2 As shown, the command parsing module 24 is used to receive decoded data and perform instruction judgment and parameter parsing on the decoded data so as to output command parameters and parsed commands.

[0051] The command parsing module 24 can determine the command header, data bits and possible check bits (such as CRC-5, CRC-16 and no CRC) of the decoded data. The command parsing module 24 first parses the command header of the decoded data, determines the command type of the decoded data through the command header, and then parses the data bits of the decoded data and the data length of the decoded data according to the command header, and feeds back the data length of the decoded data to the CRC check module 25 (so that the CRC check module 25 can know how much data needs to be processed to complete the check process, and thus determine when to stop the check), thereby completing the entire parsing process.

[0052] It should be noted that the command header is usually located at the beginning of each decoded data, including the operation code and other control information, which identifies the specific command type of the decoded data (such as Query command, Read command, Write command, etc.). The command header is used to help the tag determine the next operation to be performed. For example, the Query command is used to start the inventory cycle, and the Read command requests the tag to return to a specific storage area.

[0053] The data bits follow the command header and are used to provide specific information needed to complete the parsing command; for example, in a Query command, the data bits may include information such as the Q value (slot counter parameter) and target selection. In a Read command, the data bits may specify the memory address and length to be read.

[0054] It is understandable that in the command system of the ISO / IEC18000-6C protocol, parsing commands use non-equal length codes of 2, 4 and 8 bits, so the parsing of parsing commands needs to consider the judgment of the command header length. In the command system of the ISO / IEC18000-6C protocol, parsing commands with variable length codes meet the characteristics of Huffman coding, and Huffman coding stipulates that events with larger weights and higher occurrence frequencies have shorter codes. In the ISO / IEC18000-6C protocol, the common operation of tags is identification, and the command sequence under the normal process is Select command-Query command-ACK command. Since it is necessary to send ACK commands multiple times in practice to obtain and confirm the tag identity, the probability of the ACK command appearing is relatively high. At the same time, in actual applications, considering the anti-collision mechanism of multiple tags based on time slots, the probability of the QueryRep command appearing is relatively large; secondly, the QueryAdjust command is used to adjust the key parameter Q in the anti-collision algorithm (the parameter in the Query command, used to set the number of time slots in the inventory cycle), and its probability of appearance is equivalent to that of the Query command; and the remaining Read commands, Write commands, etc. belong to the access operations to the tag after tag identification, and their weights are relatively lower than those of the Query command; it can be seen that the command system of the ISO / IEC18000-6C protocol fully complies with the characteristics of Huffman coding. The present invention takes into account the principle of Huffman coding and proposes a command header parsing method based on the Huffman tree. According to the characteristics of the decoded data, it is parsed by using a multi-step hierarchical approach. The parsing idea flow is as follows: Figure 5 and Figure 6 As shown, from Figure 5 and Figure 6 It can be seen that the highest bit of pie_data is first determined. If the highest bit pie_data is 0, it jumps to the Command_2 (command header of length 2) state, and parses the QueryRep command and ACK command in this state; if the highest bit pie_data is 1, it jumps to the Command_4 (command header of length 4) state, and continues to determine the second highest bit of pie_data in this state. If pie_data is 0 at this time, the Select command, Query command, and QueryAdjust command are parsed in this state. If pie_data is 1 at this time, it jumps to the Command_8 (command header of length 8) state, and parses the NAK command, Req_RN command, Read command, Write command, Lock command, Kill command, and Access command in this state. It should be noted that during the parsing process, if the command parsing module 24 encounters decoded data that exceeds the provisions of the current command system, the corresponding error flag bit should be given and the parsing should be stopped.

[0055] like Figure 2As shown, the CRC check module 25 is electrically connected to the command parsing module 24, and the CRC check module 25 is used to receive the decoded data and perform a cyclic redundancy check to output a check result.

[0056] Among them, the CRC check module 25 is designed according to the protocol standard, and uses a cyclic redundancy check code (CRC) during the communication between the reader and the tag to ensure the correctness of data transmission. The CRC check module 25 mainly works in the following three stages:

[0057] Power-on phase: read the data from 10h to the end of the EPC area and calculate the CRC-16 value, and save the calculated result StoreCRC to the address 00h-0Fh of the EPC area.

[0058] Receiving stage: For parsing commands that require CRC verification, the decoded data is verified.

[0059] Sending stage: CRC is calculated for the data sequence to be sent by the tag, and then combined with the data to be sent and sent to the sending module for encoding.

[0060] The baseband communication receiving link circuit 20 of the present invention can achieve the following beneficial effects, but is not limited to, by designing a clock frequency division module 21, a gated clock module 22, a PIE decoding module 23, a command parsing module 24 and a CRC check module 25, and the clock frequency division module 21, the gated clock module 22, the PIE decoding module 23, the command parsing module 24 and the CRC check module 25 cooperate with each other:

[0061] When processing data, traditional RFID tags usually complete decoding first, then perform CRC verification, and finally execute command parsing; however, in the present invention, through the parallel working mode of each sub-module, when the PIE decoding module 23 starts to decode the received data to be decoded, the command parsing module 24 and the CRC verification module 25 also immediately start processing the decoded data after decoding, without waiting for the completion of the entire decoding process of the PIE decoding module 23, which greatly reduces the processing time (especially for those application scenarios with high requirements for response speed, this design greatly improves efficiency).

[0062] By processing data immediately instead of storing it first and then operating it, there is no need to use a large number of registers to store intermediate results, which can reduce the use of registers, not only reducing the label area, but also reducing the running time and power consumption.

[0063] like Figure 2 As shown, the specific designs of the PIE decoding module 23, the command parsing module 24 and the CRC checking module 25 will be introduced in detail below.

[0064] Specifically, the PIE decoding module 23 includes a PIE preamble count detection circuit 231 and a PIE data determination circuit 232 .

[0065] The PIE preamble count detection circuit 231 is used to determine the values ​​of Tari, TRcal, and RTcal according to the above data to be decoded, and can set a dynamic sampling decision threshold for subsequent data decoding. The dynamic sampling decision threshold is not a pre-set fixed value, but is dynamically adjusted according to the characteristics of the actual received data to be decoded.

[0066] Specifically, the PIE preamble count detection circuit 231 can ensure that the tag correctly identifies which type of data to be decoded is sent by the reader. Because different data to be decoded require the tag to perform different operations; for example, the Query command requires the tag to start the inventory cycle, and the ACK command is used to confirm the tag, etc. The PIE preamble count detection circuit 231 determines the actual values ​​of Tari, TRcal and RTcal based on the total number of sample counts of the data to be decoded "0", TRcal (tag to reader calibration), and RTcal (reader to tag calibration) according to the symbol sampling count. At the same time, the PIE preamble count detection circuit 231 will determine whether the leading head of the current data to be decoded is the leading head of the Query command based on the data obtained from the above sampling counts. The leading head of the data to be decoded is divided into a preamble and a frame synchronization code. The preamble corresponds to receiving the Query command, and the frame synchronization code corresponds to receiving other commands; when the PIE preamble count detection circuit 231 receives the preamble, it proves that the data to be decoded is a Query command.

[0067] The PIE preamble count detection circuit 231 can also ensure synchronous communication between the tag and the reader. By identifying the leading header of the data to be decoded, the tag can know when to start processing the next data frame, which is crucial for accurate transmission of information. If the PIE preamble count detection circuit 231 determines that it is yes (that is, the leading header of the current data to be decoded is the leading header of the Query command), the tag will continue to receive and parse subsequent command parameters (taking Query as an example, parameters such as DR, M, TRext, Sel, call, target, Q, CRC-5, etc. are parsed in the subsequent command parsing module 24, and the PIE decoding module 23 only decodes these data to be decoded). If the PIE pre-synchronization code count detection circuit 231 judges as yes or no (that is, the leading header of the current data to be decoded is not a pre-synchronization code and does not belong to a Query command), it will determine whether the leading header with the decoded data belongs to a frame synchronization code. If it is determined to be a frame synchronization code, it may be other specific commands such as an ACK command, a QueryAdjust command, a QueryRep command, and these commands meet the response conditions under the current state of the tag; if it is neither a pre-synchronization code nor a frame synchronization code, the tag will ignore the data to be decoded and wait for the next valid leading header of the data to be decoded.

[0068] The PIE data judgment circuit 232 is responsible for completing the state jump of each stage of decoding, distinguishing data "0" and data "1", and obtaining the above-mentioned decoded data.

[0069] Specifically, the PIE decoding module 23 is also used to send a data pointer to the command parsing module 24 and the CRC checking module 25, and the data pointer and the decoded data are serial data respectively.

[0070] By sending data pointers and decoded data in a serial manner, efficient data transmission and processing can be achieved, hardware cost and power consumption can be reduced to save bandwidth and resources, interference and errors can be reduced to improve communication reliability, complexity can be reduced to simplify hardware design, and dynamic data structures can be supported to improve system flexibility and efficiency.

[0071] Specifically, the command parsing module 24 is used to parse the decoded data to obtain the parsing command and command parameters, and provide the parsing command to the CRC check module 25 and output the command parameters. The CRC check module 25 is used to receive the parsing command and select the corresponding check circuit according to the parsing command to check the decoded data to output the check result.

[0072] like Figure 2 As shown, more specifically, the command parsing module 24 includes an instruction parsing circuit 241 and a parameter extraction circuit 242 .

[0073] The instruction parsing circuit 241 is used to obtain the command header according to the above decoded data, and obtain the parsed command according to the command header. The instruction parsing circuit 241 receives the data pointer and decoded data sent by the PIE decoding module 23 in serial, and the instruction parsing circuit 241 obtains the command header, data bits and possible check bits (CRC-5, CRC-16 and no CRC) of the decoded data according to the above decoded data.

[0074] The parameter extraction circuit 242 is used to output command parameters according to the parsed command.

[0075] The CRC check module 25 includes a CRC mode control circuit 251 , a CRC-5 mode check circuit 252 and a CRC-16 mode check circuit 253 .

[0076] The CRC mode control circuit 251 is used to select the CRC-5 mode check circuit 252 and the CRC-16 mode check circuit 253 for data check according to the parsed command. When the parsed command is a Query command, the CRC mode control circuit 251 selects the CRC-5 mode check circuit 252 for data check and enables the input and output signals of the CRC-5 mode check circuit 252; when the parsed command is a non-Query command, the CRC mode control circuit 251 selects the CRC-16 mode check circuit 253 for data check and enables the input and output signals of the CRC-16 mode check circuit 253. Among them, the non-Query command includes one of Select, Req_RN, Read, Write, Kill, Lock, Access, BlockWrite and BlockErase.

[0077] It should be noted that one function of the CRC mode control circuit 251 is to select the CRC mode. There are two CRC modes, CRC-16 and CRC-5. Different modes are adopted according to the type of parsing command received. The second function of the CRC mode control circuit 251 is to enable the input and output signals of the CRC-5 mode check circuit 252 and the CRC-16 mode check circuit 253, and the enable control signal is output and controlled by the main control module 26.

[0078] The CRC-5 mode check circuit 252 is used to complete the CRC check when receiving the decoded data, wherein the decoded data is obtained after the to-be-decoded data is decoded by the PIE decoding module 23 .

[0079] The verification process of the CRC-5 mode verification circuit 252 is as follows: first, the initial value of Q[4:0] is given as 5'b01001, and then the data to be verified (including data information and verification code) is sequentially transmitted from high to low according to the data output of the PIE decoding module 23, and the cyclic redundancy code check is sequentially performed through the change of the data pointer. When the pointer length is equal to the command data length, it means that the data transmission is completed, and after the data transmission is completed, if Q[4:0] is 5'b00000, it means that the data verification is successful.

[0080] The CRC-16 mode check circuit 253 is used to generate a CRC check code when sending a return command. It is worth mentioning that the purpose of generating a CRC check code is to ensure the integrity and accuracy of the data. Specifically: when sending a command (such as a tag sending data to a reader), generating a CRC check code can ensure that the sent data has not been tampered with or damaged, and the receiver can verify the correctness of the data by recalculating the CRC and comparing it with the received CRC. The reader sends data to the tag, that is, the process of the tag receiving data is the same. For the tag, adding a CRC check code when sending a return command helps the reader verify the validity of the tag response, thereby improving the reliability of the entire system.

[0081] The verification process of the CRC16 mode verification circuit is as follows: first, the initial value of Q[15:0] is given as 16'hFFFF, and then similarly, the data to be verified (including data information and verification code) is sequentially transmitted from high to low according to the data output of the PIE decoding module 23, and the cyclic redundancy code is sequentially checked through the change of the data pointer. When the pointer length is equal to the command data length, it means that the data transmission is completed, and after the data transmission is completed, if Q[15:0] is 16'h1D0F, it means that the data verification is successful.

[0082] It should be noted that "data verification is successful" can be used to indicate that the command (such as the data to be decoded) transmitted from the reader to the tag does not generate any erroneous data during the transmission process, and can also be used to indicate that a one-way communication process between the reader and the tag is completed and the communication with the tag is successful. It can be known from the ISO / IEC18000-6C protocol that the Query command needs to be verified using the CRC-5 mode verification circuit 252, and the Select command, Req_RN command, Read command, Write command, Kill command, Lock command, Access command, BlockWrite command and BlockErase command all use the CRC-16 mode verification circuit 253 for verification. The CRC mode can be determined based on the current command header parsed by the command parsing module 24.

[0083] See also Figure 7 , Figure 7FIG. 1 is a schematic diagram of a CRC check module in an embodiment of the present invention. Figure 7 As shown, after the CRC-5 mode check circuit 252 completes the check, it outputs a 5-bit check result, which is XORed with the preset value 0000h. If the XOR result is 0, it means that the CRC-5 mode check circuit 252 has successfully checked. After the CRC-16 mode check circuit 253 completes the check, it outputs a 16-bit check result, which is XORed with the preset value 1D0Fh. If the XOR result is 0, it means that the CRC-16 mode check circuit 253 has successfully checked. Figure 7 It can be seen that the outputs of the two XOR gates are logically ORed to obtain the final verification success / error flag. If the output of any XOR gate is 0, the final flag is the verification success flag. If the outputs of the two XOR gates are both non-zero values, the final flag is the verification error flag.

[0084] like Figure 2 As shown, specifically, the baseband communication receiving link circuit 20 also includes a general control module 26 , which is responsible for outputting an enable signal of each submodule and controlling the opening and closing of each submodule through the gated clock module 22 .

[0085] The general control module 26 is electrically connected to the PIE decoding module 23 , and is used to control the PIE decoding module 23 to enter an enabled working state and receive a synchronization code receiving flag output by the PIE decoding module 23 .

[0086] The general control module 26 is electrically connected to the CRC check module 25 . The general control module 26 is also used to control the CRC check module 25 to enter an enabled working state and receive a check success / error flag output by the CRC check module 25 .

[0087] The overall control module 26 is electrically connected to the command parsing module 24 .

[0088] The CRC check module 25 is also used to output a check success / error flag to the command parsing module 24 .

[0089] The general control module 26 is also used to turn off the enable signal of activating the PIE decoding module 23 and the CRC check module 25 after the PIE decoding module 23 receives complete data, and stop the operation of each submodule in the receiving stage, thereby completing a complete data receiving process.

[0090] like Figure 2As shown, when the PIE decoding module 23 is about to complete the detection of the front synchronization code, the general control module 26 turns on the enable signal of the activation command parsing module 24 and the CRC check module 25, and the enable signal turns on the command parsing module 24, the CRC mode control circuit 251, the CRC-5 mode check circuit 252 and the CRC-16 mode check circuit 253 through the gated clock module 22. The command parsing module 24 determines the specific command type according to the non-equal length coding of the command header (i.e., 2-bit, 4-bit and 8-bit command codes), and sends the obtained parsed command to the CRC mode control circuit 251, at which time the CRC-5 mode check circuit 252 and the CRC-16 mode check circuit 253 are in operation at the same time; if the parsed command is a Query command, the CRC mode control circuit 251 turns off the CRC-16 mode check circuit 253, so that the CRC-5 mode check circuit 252 keeps running until the verification is completed; if the parsed command is a non-Query command, the CRC mode control circuit 251 turns off the CRC-5 mode check circuit 252, so that the CRC-16 mode check circuit 253 keeps running until the verification is completed.

[0091] When the CNT of the PIE decoding module 23 exceeds 2 times RTcal_CNT and is still counting, the PIE decoding module 23 enters the decoding completion state and outputs a decoding completion flag. The command parsing module 24 ends the command parsing process after receiving the decoding completion flag output by the PIE decoding module 23. The CRC check module 25 determines the end of the check based on the command length obtained in advance in the command parsing module 24.

[0092] See also Figure 8 , Figure 8 The present invention proposes a baseband communication method for a radio frequency identification tag. Figure 8 As shown, the method includes steps S202 to S206:

[0093] Step S202 : receiving the data to be decoded, and decoding the data to be decoded to obtain decoded data, so as to provide the decoded data to the command parsing module 24 and the CRC checking module 25 at the same time.

[0094] In step S202, the PIE decoding module 23 is used to receive the data to be decoded, and the PIE decoding module 23 receives the data to be decoded returned by the RF analog front end 30; the specific introduction of the PIE decoding module 23 can be found above and will not be repeated here.

[0095] Step S204: the command parsing module 24 receives the decoded data and performs instruction judgment and parameter parsing on the decoded data to output command parameters and parsed commands.

[0096] In step S204, the command parsing module 24 can determine the command header, data bits and possible check bits (such as CRC-5, CRC-16 and no CRC) of the decoded data; the specific introduction of the command parsing module 24 can be found above and will not be repeated here.

[0097] Step S206: The CRC check module 25 receives the decoded data and performs a cyclic redundancy check to output a check result.

[0098] In step S206, the CRC check module 25 is designed according to the protocol standard, and a cyclic redundancy check (CRC) check code is used during the communication between the reader and the tag to ensure the correctness of data transmission; the specific introduction of the CRC check module 25 can be found above and will not be repeated here.

[0099] The baseband communication method of the radio frequency identification tag 1 in the present invention can have, but is not limited to, the following beneficial effects:

[0100] When the baseband communication method of the traditional RFID tag is used to process data, decoding is usually completed first, then CRC check is performed, and finally command parsing is executed; however, the baseband communication method of the radio frequency identification tag 1 in the present invention decodes the received data to be decoded, and the command parsing module 24 and the CRC check module 25 also immediately start processing the decoded data after decoding. This parallel working mode does not need to wait for the end of the entire decoding process, which can greatly reduce the processing time (especially for those application scenarios with high requirements for response speed, this design greatly improves efficiency).

[0101] By processing data immediately instead of storing it first and then operating it, there is no need to use a large number of registers to store intermediate results, which can reduce the use of registers, not only reducing the label area, but also reducing the running time and power consumption.

[0102] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A baseband communication receiving link circuit for a radio frequency identification tag, characterized in that: Including clock frequency division module, gated clock module, PIE decoding module, command parsing module and CRC check module; The clock frequency division module is electrically connected to the gated clock module and is used to receive a system clock signal and output a plurality of frequency-divided clock signals to the gated clock module; The gated clock module is electrically connected to the PIE decoding module, the command parsing module and the CRC checking module, and is used to receive the multiple frequency-divided clock signals and provide the required clock signals to the PIE decoding module, the command parsing module and the CRC checking module; The PIE decoding module is electrically connected to the command parsing module and the CRC checking module, and is used to receive data to be decoded, and decode the data to be decoded to obtain decoded data, so as to provide the decoded data to the command parsing module and the CRC checking module at the same time; The command parsing module is used to receive the decoded data and perform instruction judgment and parameter parsing on the decoded data to output command parameters and parsed commands; The CRC check module is electrically connected to the command parsing module and is used to receive the decoded data and perform a cyclic redundancy check to output a check result.

2. The baseband communication receiving link circuit according to claim 1, characterized in that: The PIE decoding module includes a PIE pre-synchronization code counting detection circuit and a PIE data judgment circuit. The PIE pre-synchronization code counting detection circuit is used to determine the values ​​of Tari, TRcal, and RTcal based on the data to be decoded, and set a dynamic sampling decision threshold for subsequent data decoding; the PIE data judgment circuit is responsible for completing the state jump of each stage of decoding, distinguishing between data "0" and data "1", and obtaining the decoded data.

3. The baseband communication receiving link circuit according to claim 1, characterized in that: The PIE decoding module is also used to send a data pointer to the command parsing module and the CRC checking module, and the data pointer and the decoded data are serial data respectively.

4. The baseband communication receiving link circuit according to claim 1, characterized in that: The command parsing module is used to parse the decoded data to obtain the parsing command and the command parameters, and to provide the parsing command to the CRC verification module and output the command parameters. The CRC verification module is used to receive the parsing command and select a corresponding verification circuit according to the parsing command to verify the decoded data to output a verification result.

5. The baseband communication receiving link circuit according to claim 4, characterized in that: The command parsing module includes an instruction parsing circuit and a parameter extraction circuit. The instruction parsing circuit is used to obtain a command header based on parsing the decoded data and obtain the parsed command based on the command header. The parameter extraction module is used to output command parameters based on the parsed command.

6. The baseband communication receiving link circuit according to claim 4, characterized in that: The CRC check module includes a CRC mode control circuit, a CRC-5 mode check circuit and a CRC-16 mode check circuit. The CRC mode control circuit is used to select the CRC-5 mode check circuit and the CRC-16 mode check circuit for data check according to the parsing command. When the parsing command is a Query command, the CRC mode control circuit selects the CRC-5 mode check circuit for data check and enables the input and output signals of the CRC-5 mode check circuit. When the parsing command is a non-Query command, the CRC mode control circuit selects the CRC-16 mode check circuit for data check and enables the input and output signals of the CRC-16 mode check circuit. The non-Query command includes one of Select, Req_RN, Read, Write, Kill, Lock, Access, BlockWrite and BlockErase.

7. The baseband communication receiving link circuit according to claim 1, characterized in that: The baseband communication receiving link circuit also includes a general control module, which is electrically connected to the PIE decoding module, the command parsing module and the CRC check module. The general control module is used to control the PIE decoding module to enter an enabled working state and receive a synchronization code reception flag output by the PIE decoding module; the general control module is also used to control the CRC check module to enter an enabled working state and receive a check success / error flag output by the CRC check module; the CRC check module is also used to output the check success / error flag to the command parsing module; the general control module is also used to turn off the enable signal that activates the PIE decoding module and the CRC check module after the PIE decoding module receives complete data, and stop the operation of each sub-module in the receiving stage, thereby completing a complete data receiving process.

8. The baseband communication receiving link circuit according to claim 7, characterized in that: The RFID tag of the baseband communication receiving link circuit of the RFID tag is an ultra-high frequency RFID tag, and the frequency band of the RFID tag is 0.3-3 GHZ; The clock frequency division module provides a clock signal with a frequency of 1.92 MHz for the PIE decoding module, a clock signal with a frequency of 480 KHz for the command parsing module and the CRC check module, and a clock signal with a frequency of 240 KHz for the general control module.

9. A radio frequency identification tag, characterized in that: The radio frequency identification tag includes a carrier, a baseband communication receiving link circuit arranged on the carrier, a radio frequency analog front end, and a memory, the radio frequency analog front end includes a radio frequency antenna and is electrically connected to the baseband communication receiving link circuit, the memory is electrically connected to the baseband communication receiving link circuit, and is characterized in that the baseband communication receiving link circuit adopts the baseband communication receiving link circuit of the radio frequency identification tag as described in any one of claims 1 to 8.

10. A baseband communication method for a radio frequency identification tag, characterized in that: The method comprises: Used to receive data to be decoded, and decode the data to be decoded to obtain decoded data, so as to provide the decoded data to the command parsing module and the CRC check module at the same time; The command parsing module receives the decoded data and performs instruction judgment and parameter parsing on the decoded data to output command parameters and parsed commands; and The CRC check module receives the decoded data and performs a cyclic redundancy check to output a check result.

Images