Pixel circuits, their driving methods, and display panels

Abstract

This invention discloses a pixel circuit, its driving method, and a display panel. The pixel circuit includes a time control module, a current control module, a first potential control module, a second potential control module, a reset module, and a light-emitting module. The reset module is connected to the output terminal of the time control module and is used to reset the output terminal of the time control module during the reset phase. Both the first and second potential control modules are connected between the output terminal of the time control module and the control terminal of the current control module. The second potential control module is used to maintain the voltage at the control terminal of the current control module at the on-state voltage during the reset phase, and the first potential control module is used to maintain the voltage at the control terminal of the current control module at the off-state voltage during the light-emitting phase. This solution can improve the flickering or uneven display phenomenon caused by the unstable output signal of the time control module when the pixel circuit is turned off, thus improving the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit, its driving method, and a display panel. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the display effect of display devices.

[0003] Display driving methods include PWM (Pulse Width Modulation), PAM (Pulse Amplitude Modulation), and combinations of both. Currently, existing mixed-signal driving methods suffer from poor display quality. Summary of the Invention

[0004] This invention provides a pixel circuit, its driving method, and a display panel to improve display performance.

[0005] According to one aspect of the present invention, a pixel circuit is provided, the pixel circuit comprising: a time control module, a current control module, a first potential control module, a second potential control module, a reset module, and a light-emitting module;

[0006] The current control module and the light-emitting module are connected between the first power line and the second power line. The current control module is used to drive the light-emitting module to emit light according to the data signal during the light-emitting stage.

[0007] The time control module is used to control the potential of its output terminal according to the time signal and the frequency sweep signal during the light emission stage, so as to control the light emission time of the light emission module;

[0008] The reset module is connected to the output of the time control module, and the reset module is used to reset the output of the time control module during the reset phase.

[0009] The first potential control module is connected between the output terminal of the time control module and the control terminal of the current control module. The second potential control module is connected between the output terminal of the time control module and the control terminal of the current control module. The second potential control module is used to maintain the voltage of the control terminal of the current control module at the on-state voltage according to the voltage of the output terminal of the time control module during the reset phase. The first potential control module is used to maintain the voltage of the control terminal of the current control module at the off-state voltage according to the voltage of the output terminal of the time control module during the light-emitting phase.

[0010] Optionally, the first potential control module includes a first logic unit and a first switching unit. The first input terminal of the first logic unit is connected to a first reference signal, the second input terminal of the first logic unit is connected to the output terminal of the time control module, the output terminal of the first logic unit is connected to the control terminal of the first switching unit, the first terminal of the first switching unit is connected to a third power supply line, and the second terminal of the first switching unit is connected to the control terminal of the current control module.

[0011] The second potential control module includes a second logic unit and a second switch unit. The first input terminal of the second logic unit is connected to a second reference signal. The second input terminal of the second logic unit is connected to the output terminal of the time control module. The output terminal of the second logic unit is connected to the control terminal of the second switch unit. The first terminal of the second switch unit is connected to a first initialization signal line. The second terminal of the second switch unit is connected to the control terminal of the current control module.

[0012] Optionally, the first logic unit includes a NAND gate, the first switching unit includes a first transistor, the first input terminal of the NAND gate is connected to a first reference signal, the second input terminal of the NAND gate is connected to the output terminal of the time control module, the output terminal of the NAND gate is connected to the gate of the first transistor, the first electrode of the first transistor is connected to a third power supply line, and the second electrode of the first transistor is connected to the control terminal of the current control module.

[0013] The second logic unit includes a NOR gate, the second switching unit includes a second transistor, the first input terminal of the NOR gate is connected to a second reference signal, the second input terminal of the NOR gate is connected to the output terminal of the time control module, the output terminal of the NOR gate is connected to the gate of the second transistor, the first terminal of the second transistor is connected to the first initialization signal line, and the second terminal of the second transistor is connected to the control terminal of the current control module.

[0014] Optionally, the first reference signal and the second reference signal are inverse signals of each other;

[0015] Optionally, the channel type of the first transistor and the channel type of the second transistor are different;

[0016] Optionally, the reset module is connected between the first initialization signal line and the output of the time control module.

[0017] Optionally, the pixel circuit also includes a third potential control module, which is connected to the control terminal of the current control module. The third potential control module is used to continuously conduct in response to the first reference signal in the high brightness display mode so as to continuously maintain the control terminal voltage of the current control module at the conduction voltage.

[0018] Optionally, the third potential control module includes a third transistor, the gate of the third transistor is connected to a first reference signal, the first terminal of the third transistor is connected to a first initialization signal line, and the second terminal of the third transistor is connected to the control terminal of the current control module.

[0019] Optionally, the pixel circuit further includes a first storage unit, a first end of which is connected to a second power supply line, and a second end of which is connected to the control terminal of the current control module.

[0020] Optionally, the current control module includes a first drive unit, a first data writing unit, and a current control unit;

[0021] The current control unit and the first driving unit are connected between the first power line and the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power line. The first data writing unit is connected to the first driving unit. The first data writing unit is used to write data signals to the control end of the first driving unit.

[0022] Optionally, the current control module further includes a first compensation unit, which is connected between the second end of the first driving unit and the control end. The first data writing unit is connected to the first end of the first driving unit, and the control end of the first data writing unit and the control end of the first compensation unit are both connected to the first scan line.

[0023] Optionally, the current control module further includes a first light-emitting control unit and a second light-emitting control unit. A first terminal of the first light-emitting control unit is connected to a first power supply line, a second terminal of the first light-emitting control unit is connected to a first terminal of a first driving unit, a second terminal of the first driving unit is connected to a first terminal of the current control unit, a second terminal of the current control unit is connected to the first terminal of the second light-emitting control unit, and a second terminal of the second light-emitting control unit is connected to a first terminal of the light-emitting module. The control terminal of the second light-emitting control unit is connected to a first light-emitting control signal line, and the control terminal of the first light-emitting control unit is connected to a second light-emitting control signal line.

[0024] Optionally, the current control module further includes a second storage unit, which is connected between the control terminal of the first drive unit and the first power line;

[0025] Optionally, the current control module further includes a first initialization unit, a first terminal of which is connected to a first initialization signal line, a second terminal of which is connected to a control terminal of the first drive unit, and a control terminal of which is connected to a second scan line.

[0026] Optionally, the current control module further includes a second initialization unit, the first end of which is connected to a second power supply line or a second initialization signal line, the second end of which is connected to a first end of the light-emitting module, and the control end of which is connected to a second scan line.

[0027] Optionally, the time control module includes a second drive unit, a second data writing unit, a third initialization unit, and a coupling unit;

[0028] The second drive unit is connected between the third power line and the output of the time control module. The second data writing unit is used to write the time signal to the control terminal of the second drive unit. The third initialization unit is connected between the third initialization signal line and the control terminal of the second drive unit. The control terminal of the third initialization unit is connected to the first scan line.

[0029] The coupling unit is connected to the control terminal of the second drive unit, and the coupling unit is used to control the potential of the control terminal of the second drive unit according to the frequency sweep signal;

[0030] Optionally, the time control module further includes a second compensation unit, which is connected between the control terminal and the second terminal of the second drive unit. The control terminal of the second compensation unit and the control terminal of the second data writing unit are both connected to the third scan line, and the second data writing unit is connected to the first terminal of the second drive unit.

[0031] Optionally, the time control module further includes a third light-emitting control unit and a fourth light-emitting control unit. The control terminals of the third light-emitting control unit and the fourth light-emitting control unit are both connected to the second light-emitting control signal line. The first terminal of the third light-emitting control unit is connected to the third power supply line. The second terminal of the third light-emitting control unit is connected to the first terminal of the second drive unit. The first terminal of the fourth light-emitting control unit is connected to the second terminal of the second drive unit. The second terminal of the fourth light-emitting control unit is connected to the output terminal of the time control module.

[0032] Optionally, the time control module further includes a third storage unit, which is connected between the third power line and the control terminal of the second drive unit.

[0033] According to another aspect of the present invention, a method for driving a pixel circuit is provided, the method comprising:

[0034] During the reset phase, the control reset module resets the output of the time control module and controls the second potential control module to maintain the control terminal voltage of the current control module at the on-state voltage according to the voltage of the output of the time control module.

[0035] During the light-emitting phase, the current control module drives the light-emitting module to emit light according to the data signal, and the time control module controls the potential of its output terminal according to the time signal and the frequency sweep signal. At the end of the light-emitting phase, the first potential control module controls the voltage of the control terminal of the current control module to maintain the voltage of the control terminal of the current control module at the off voltage according to the voltage of the output terminal of the time control module, so as to control the light-emitting time of the light-emitting module.

[0036] Optionally, the pixel circuit further includes a third potential control module; the driving method of the pixel circuit further includes:

[0037] In high-brightness display mode, the control third potential control module responds to the first reference signal of its own control terminal to keep the control terminal voltage of the current control module continuously at the on-state voltage.

[0038] According to another aspect of the present invention, a display panel is provided, the display panel including the pixel circuit provided in any embodiment of the present invention.

[0039] The technical solution provided by this invention provides a second potential control module between the output terminal of the time control module and the control terminal of the current control module to maintain the control terminal of the current control module at the on-state voltage during the reset phase. A first potential control module is also provided between the output terminal of the time control module and the control terminal of the current control module to quickly and stably maintain the potential of the control terminal of the current control module at the off-state voltage when the light-emitting module stops emitting light. This maintains the stability of the potential at the control terminal of the current control module, allowing for rapid shutdown of the current control module and effectively avoiding unstable light emission from the light-emitting module. This, in turn, helps to improve the flickering or uneven display caused by the unstable output signal of the time control module when the pixel circuit is turned off, thus enhancing the display effect.

[0040] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0043] Figure 2This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of the structure of a current control module provided in an embodiment of the present invention;

[0047] Figure 6 This is a schematic diagram of the structure of a time control module provided in an embodiment of the present invention;

[0048] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0050] Figure 9 A flowchart illustrating a pixel circuit driving method provided in an embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0052] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0053] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0054] As described in the background section, existing mixed-signal driving methods suffer from poor display quality. Through careful research, the inventors discovered that this problem arises because existing pixel circuits using mixed analog-digital driving typically include a PWM drive module and a PAM drive module. The PWM drive module converts the analog grayscale voltage into a switching time that controls the PAM drive module to generate the driving current, thereby controlling the emission time of the light-emitting element. However, the timing control signal output by the PWM drive module is susceptible to leakage current or threshold voltage drift within the PWM drive module itself, resulting in signal attenuation and unstable node potentials. This affects the node voltage of the PAM drive module, leading to poor uniformity of brightness and reduced display quality.

[0055] To address the above problems, embodiments of the present invention provide a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1 The pixel circuit provided in this embodiment includes a time control module 10, a current control module 20, a first potential control module 30, a second potential control module 40, a reset module 50, and a light-emitting module 60.

[0056] The current control module 20 and the light-emitting module 60 are connected between the first power line L1 and the second power line L2. The current control module 20 is used to drive the light-emitting module 60 to emit light according to the data signal Vdata_I during the light-emitting stage. The time control module 10 is used to control the potential of its own output terminal according to the time signal Vdata_t and the sweep frequency signal SWEEP during the light-emitting stage, so as to control the light-emitting time of the light-emitting module 30.

[0057] The reset module 50 is connected to the output terminal of the time control module 10, and the reset module 50 is used to reset the output terminal of the time control module 10 during the reset phase;

[0058] The first potential control module 30 is connected between the output terminal of the time control module 10 and the control terminal of the current control module 20, and the second potential control module 40 is connected between the output terminal of the time control module 10 and the control terminal of the current control module 20. The second potential control module 40 is used to maintain the voltage of the control terminal of the current control module 20 at the on-state voltage according to the voltage of the output terminal of the time control module 10 during the reset phase. The first potential control module 30 is used to maintain the voltage of the control terminal of the current control module 20 at the off-state voltage according to the voltage of the output terminal of the time control module 10 during the light-emitting phase.

[0059] The first power line L1 provides a first power supply voltage VDDA, and the second power line L2 provides a second power supply voltage VSS. When the connection path between the first power line L1 and the second power line L2 is open, the current control module 20 generates a driving current based on the data signal Vdata_I to drive the light-emitting module 60 to emit light. The magnitude of this driving current is related to the magnitude of the data signal Vdata_I.

[0060] Specifically, the output terminal of the time control module 10 is connected to the input terminals of the first potential control module 30 and the second potential control module 40 at the first node PW1, and the control terminal of the current control module 20 is connected to the output terminals of the first potential control module 30 and the second potential control module 40 at the second node PW2. The first potential control module 30 and the second potential control module 40 are respectively connected between the first node PW1 and the second node PW2. The operation of this pixel circuit includes at least a reset stage and a light emission stage. In the reset stage, the reset module 50 is turned on to reset the potential of the first node PW1, and at the same time, it controls the second potential control module 40 to be turned on. The second potential control module 40 maintains the voltage of the second node PW2 at the on-state voltage according to the voltage of the first node PW1. In the light emission stage, the current control module 20 generates a driving current according to the data signal Vdata_I to drive the light emission module 60 to emit light. When the light emission ends, the time control module 10 outputs a time control signal based on the time signal Vdata_t and the sweep frequency signal SWEEP. The first potential control module 30 maintains the voltage of the second node PW2 at the off voltage based on the time control signal to control the current control module 20 to turn off, thereby controlling the light emission module 60 to turn off.

[0061] In this embodiment, the potential of the control terminal (i.e., the second node PW2) of the current control module 20 is controlled by the first potential control module 30 and the second potential control module 40. Even if the voltage of the first node PW1 is unstable due to factors such as leakage or threshold voltage drift of the time control module 10, the first potential control module 30 can stabilize the potential of the control terminal of the current control module 20 at the turn-off voltage (for example, the turn-off voltage can be the third power supply voltage VDDW; in other embodiments, the turn-off voltage can be any voltage that can turn off the current control module 20). This prevents the potential of the control terminal of the current control module 20 from becoming unstable, thus ensuring that the current control module 20 can be quickly turned off when the light emission ends. This reduces the phenomenon of drive current attenuation caused by the unstable potential of the control terminal of the current control module 20, improves the difference in drive current between different pixels, enhances the uniformity of drive current, effectively avoids the difference in light emission time between different pixels, and is beneficial to improving the display effect.

[0062] The pixel circuit provided in this embodiment of the invention sets a second potential control module between the output terminal of the time control module and the control terminal of the current control module to maintain the control terminal of the current control module at the on-state voltage during the reset phase. A first potential control module is also set between the output terminal of the time control module and the control terminal of the current control module to quickly and stably maintain the potential of the control terminal of the current control module at the off-state voltage when the light-emitting module stops emitting light. This maintains the stability of the potential of the control terminal of the current control module, allowing for rapid shutdown of the current control module and effectively avoiding unstable light emission from the light-emitting module. This, in turn, helps to improve the flickering or uneven display caused by the unstable output signal of the time control module when the pixel circuit is turned off, thus improving the display effect.

[0063] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 2 Based on the above technical solution, optionally, the first potential control module 30 includes a first logic unit 301 and a first switch unit 302. The first input terminal of the first logic unit 301 is connected to the first reference signal EN1. The second input terminal of the first logic unit 301 is connected to the output terminal of the time control module 10. The output terminal of the first logic unit 301 is connected to the control terminal of the first switch unit 302. The first terminal of the first switch unit 302 is connected to the third power line. The second terminal of the first switch unit 302 is connected to the control terminal of the current control module 20.

[0064] The third power line can transmit the third power supply voltage VDDW, which is the shutdown voltage and can turn off the current control module 20.

[0065] The second potential control module 40 includes a second logic unit 401 and a second switch unit 402. The first input terminal of the second logic unit 401 is connected to the second reference signal EN2. The second input terminal of the second logic unit 401 is connected to the output terminal of the time control module 10. The output terminal of the second logic unit 401 is connected to the control terminal of the second switch unit 402. The first terminal of the second switch unit 402 is connected to the first initialization signal line. The second terminal of the second switch unit 402 is connected to the control terminal of the current control module 20.

[0066] The first initialization signal line is used to transmit the first initialization voltage Vinit1. The first initialization voltage Vinit is a turn-on voltage that enables the current control module 20 to be turned on.

[0067] Specifically, during the reset phase, the reset module 50 resets the first node PW1, and the second logic unit 401 controls the second switching unit 402 to turn on according to the second reference signal EN2 and the voltage of the first node PE1. The second switching unit 402 transmits the first initialization voltage Vinit1 to the second node PW2, so that the current control module 20 turns on.

[0068] During the light-emitting phase, the current control module 20 drives the light-emitting module 60 to emit light. When the light-emitting phase ends, the time control module 10 generates a time control signal based on the time signal Vdata_t and the sweep frequency signal SWEEP. The first logic unit 301 controls the first switching unit 302 to turn on based on the voltage of the first node PW1 and the first reference signal EN1 (at this time, the second logic unit 401 is turned off). The first switching unit 302 transmits the third power supply voltage VDDW to the second node PW2, causing the current control module 20 to turn off, thereby controlling the light-emitting module 60 to turn off.

[0069] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, specifically... Figure 2 The pixel circuit shown is illustrated with a detailed structural diagram of the first potential control module 30 and the second potential control module 40, as shown in the reference diagram. Figure 3 The first logic unit 301 includes a NAND gate U1, the first switching unit 302 includes a first transistor M1, the first input terminal of the NAND gate U1 is connected to the first reference signal EN1, the second input terminal of the NAND gate U1 is connected to the output terminal of the time control module 10, the output terminal of the NAND gate U1 is connected to the gate of the first transistor M1, the first electrode of the first transistor M1 is connected to the third power supply line, and the second electrode of the first transistor M1 is connected to the control terminal of the current control module 20.

[0070] The second logic unit 401 includes a NOR gate U2, the second switching unit 402 includes a second transistor M2, the first input terminal of the NOR gate U2 is connected to the second reference signal EN2, the second input terminal of the NOR gate U2 is connected to the output terminal of the time control module 10, the output terminal of the NOR gate U2 is connected to the gate of the second transistor M2, the first terminal of the second transistor M2 is connected to the first initialization signal line, and the second terminal of the second transistor M2 is connected to the control terminal of the current control module 20.

[0071] The first transistor M1 and the second transistor M2 have different channel types.

[0072] Specifically, the reset module 50 can be connected between the first initialization signal line and the first node PW1. During the reset phase, the reset module 50 transmits the first initialization voltage Vinit1 to the first node PW1. The potential of the first node PW1 is low. The NOR gate U2 outputs a high level according to the first initialization voltage Vinit1 and the second reference signal EN2. The NAND gate U1 outputs a high level according to the first initialization voltage Vinit1 and the first reference signal EN2. The first transistor M1 is turned off, the second transistor M2 is turned on, the first initialization voltage Vinit1 is transmitted to the second node PW2, and the current control module 20 is turned on.

[0073] During the light-emitting phase, the current control module 20 generates a driving current based on the data signal Vdata_I, driving the light-emitting module 60 to emit light. Under the influence of the sweep frequency signal SWEEP, the time control module 10 gradually outputs a time control signal to the first node PW1. When the voltage of the first node PW1 causes the NAND gate U1 to output a low level, the first transistor M1 turns on. At this time, the NOR gate U2 outputs a low level, and the second transistor M2 turns off. The first transistor M1 transmits the third power supply voltage VDDW to the second node PW2, quickly raising the potential of the control terminal of the current control module 20, controlling the current control module 20 to turn off, and ending the light-emitting phase. This effectively avoids the potential of the control terminal of the current control module 20 gradually changing with the time control signal of the first node PW1, ensuring the stability of the potential of the control terminal of the current control module 20, and thus ensuring the stability of the light-emitting phase.

[0074] Optionally, the first reference signal EN1 and the second reference signal EN2 are inverse signals to ensure that the output levels of NAND gate U1 and NOR gate U2 change simultaneously, ensuring the synchronization of the timing actions of NAND gate U1 and NOR gate U2, and further improving the control accuracy of the potential of the control terminal of the current control module 20.

[0075] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 4Based on the above technical solutions, the pixel circuit may optionally include a third potential control module 70, which is connected to the control terminal of the current control module 10. The third potential control module 70 is used to continuously conduct in response to the first reference signal EN1 in the high brightness display mode, so as to continuously maintain the control terminal voltage of the current control module 20 at the conduction voltage.

[0076] Specifically, in some special scenarios, continuous high brightness display is required. In this case, the third potential control module 70 can be controlled to respond to the first reference signal EN1 and transmit the first initialization voltage Vinit1 to the control terminal of the current control module 20, so that the current control module 20 is continuously turned on and the light-emitting module 60 continuously emits light.

[0077] Optionally, the third potential control module 70 includes a third transistor M3, the gate of the third transistor M3 is connected to the first reference signal EN1, the first terminal of the third transistor M3 is connected to the first initialization signal line, and the second terminal of the third transistor M3 is connected to the control terminal of the current control module 20.

[0078] Continue to refer to Figure 4 The pixel circuit also includes a first storage unit 80, which is connected between the second power line L2 and the control terminal of the current control module 20. The first storage unit 80 may include a first capacitor C1, used to store the potential of the control terminal of the current control module 20, and to maintain the stability of the potential of the control terminal of the current control module 20 when it is turned off, thereby enabling the current control module 20 to be turned off more reliably.

[0079] Optionally, in this embodiment, the reset module 50, the second switch unit 402, and the third potential control module 70 are all connected to the first initialization signal line, which helps to reduce the number of signal lines and thus improves PPI.

[0080] The technical solution provided in this embodiment controls the potential of the control terminal of the current control module 20 through the first potential control module 30 and the second potential control module 40. When the time control module 10 gradually outputs a time control signal according to the sweep frequency signal SWEEP and the time signal Vdata_t, when the potential of the first node PW1 causes the first switching unit 302 in the first potential control module 30 to be turned on, the positioning of the control terminal of the current control module 20 is quickly maintained at the off voltage, avoiding the gradual change of the potential of the control terminal of the current control module 20 with the change of the time control signal of the first node PW1, thus ensuring the stability of the potential of the control terminal of the current control module 20, and thus ensuring the stability of light emission. In addition, by setting the third potential control module 70, the light emission module 60 can be made to continuously emit light to meet the requirements of high brightness display, enriching the function of the pixel circuit driven by the digital-analog hybrid drive.

[0081] Figure 5 This is a schematic diagram of a current control module provided in an embodiment of the present invention, with reference to... Figure 5 Based on the above technical solutions, optionally, the current control module 20 includes a first driving unit 201, a first data writing unit 202, and a current control unit 203. The current control unit 203 and the first driving unit 201 are connected between the first power line L1 and the first end of the light-emitting module 60. The second end of the light-emitting module 60 is connected to the second power line L2. The first data writing unit 202 is connected to the first driving unit 201 and is used to write the data signal Vdata_I to the control terminal of the first driving unit 201. The control terminal of the current control unit 203 serves as the control terminal of the current control module 20 and is connected to the second node PW2. During the light-emitting phase, the light-emitting time of the light-emitting module 60 is controlled by controlling the on / off state of the current control unit 203.

[0082] The current control module 20 also includes a first compensation unit 204, which is connected between the second terminal and the control terminal of the first drive unit 204. A first data writing unit 202 is connected to the first terminal of the first drive unit 201. Both the control terminal of the first data writing unit 202 and the control terminal of the first compensation unit 204 are connected to the first scan line. The first scan line is used to transmit the first scan signal S1, and the first compensation unit 204 is used to compensate for the threshold voltage of the first drive unit 201 to improve the problem of poor uniformity of the drive current caused by changes in the threshold voltage characteristics of the first drive unit 201.

[0083] The current control module 20 also includes a first light-emitting control unit 205 and a second light-emitting control unit 206. The first terminal of the first light-emitting control unit 205 is connected to the first power line L1, and the second terminal of the first light-emitting control unit 205 is connected to the first terminal of the first driving unit 201. The second terminal of the first driving unit 201 is connected to the first terminal of the current control unit 203, and the second terminal of the current control unit 203 is connected to the first terminal of the second light-emitting control unit 206. The second terminal of the second light-emitting control unit 206 is connected to the first terminal of the light-emitting module 60. The control terminal of the second light-emitting control unit 206 is connected to the first light-emitting control signal line, and the control terminal of the first light-emitting control unit 205 is connected to the second light-emitting control signal line. Specifically, the first light-emitting control unit 205 is used to disconnect the connection between the first driving unit 201 and the first power line L1 during the non-light-emitting phase to prevent the first power supply voltage VDDA from interfering with the data signal Vdata_I when the data signal Vdata_I is transmitted to the first terminal of the first driving unit 201, thus affecting the light-emitting quality. At the start of the light-emitting stage, by controlling the first light-emitting control unit 205 and the second light-emitting control unit 206 to be turned on, the connection path between the first power line L1 and the second power line L2 is turned on, and the light-emitting stage begins.

[0084] Optionally, continue to refer to Figure 5 The current control module 20 also includes a second storage unit 208, which is connected between the control terminal of the first drive unit 201 and the first power line L1, and is used to store the voltage of the control terminal of the first drive unit 201.

[0085] Optionally, the current control module 20 further includes a first initialization unit 207. The first terminal of the first initialization unit 207 is connected to the first initialization signal line, the second terminal of the first initialization unit 207 is connected to the control terminal of the first drive unit 201, and the control terminal of the first initialization unit 207 is connected to the second scan line. The first initialization unit 207 is used to initialize the potential of the control terminal of the first drive unit 201 in response to the second scan signal S2 on the second scan line being turned on, so as to prevent residual charge from having an adverse effect on the drive current.

[0086] Optionally, the current control module 20 further includes a second initialization unit 209. The first terminal of the second initialization unit 209 is connected to the second power supply line L2 or the second initialization signal line, the second terminal of the second initialization unit 209 is connected to the first terminal of the light-emitting module 60, and the control terminal of the second initialization unit 209 is connected to the second scan line. The second initialization unit 209 is used to transmit the second power supply voltage VSS or the second initialization voltage Vinit2 on the second initialization signal line to the first terminal of the light-emitting module 60 in response to the conduction of the second scan signal S2 on the second scan line, thereby initializing the potential of the first terminal of the light-emitting module 60. Specifically, both the second initialization voltage Vinit2 and the second power supply voltage VSS are negative, and the second initialization voltage Vinit2 is lower than the second power supply voltage VSS.

[0087] Figure 6 This is a schematic diagram of the structure of a time control module provided in an embodiment of the present invention, with reference to... Figure 6 Based on the above technical solutions, optionally, the time control module 10 includes a second driving unit 101, a second data writing unit 102, a third initialization unit 103, and a coupling unit 104. The second driving unit 101 is connected between the third power line L3 and the output terminal of the time control module 10. The second data writing unit 102 is used to write the time signal Vdata_t to the control terminal of the second driving unit 101. The third initialization unit 103 is connected between the third initialization signal line and the control terminal of the second driving unit 101. The control terminal of the third initialization unit 103 is connected to the first scan line.

[0088] The coupling unit 104 is connected to the control terminal of the second drive unit 101. The coupling unit 104 is used to control the potential of the control terminal of the second drive unit 101 according to the sweep frequency signal SWEEP.

[0089] Optionally, the time control module 10 further includes a second compensation unit 105. The second compensation unit 105 is connected between the control terminal and the second terminal of the second drive unit 101. The control terminal of the second compensation unit 105 and the control terminal of the second data writing unit 102 are both connected to the third scan line. The second data writing unit 102 is connected to the first terminal of the second drive unit 101. The second compensation unit 105 is used to compensate the threshold voltage of the second drive unit 101 to ensure the accuracy of the time control signal output by the time control module 10.

[0090] Optionally, the time control module 10 further includes a third light-emitting control unit 106 and a fourth light-emitting control unit 107. The control terminals of the third light-emitting control unit 106 and the fourth light-emitting control unit 107 are both connected to the second light-emitting control signal line. The first terminal of the third light-emitting control unit 106 is connected to the third power line L3, the second terminal of the third light-emitting control unit 106 is connected to the first terminal of the second drive unit 101, the first terminal of the fourth light-emitting control unit 107 is connected to the second terminal of the second drive unit 101, and the second terminal of the fourth light-emitting control unit 107 is connected to the output terminal of the time control module 10.

[0091] Optionally, the time control module 10 further includes a third storage unit 108, which is connected between the third power line L3 and the control terminal of the second drive unit 101, and is used to store the voltage of the control terminal of the second drive unit 101.

[0092] Specifically, before the light-emitting stage, the third initialization unit 103 is turned on in response to the first scan signal S1 on the first scan line, transmitting the third initialization voltage Vinit3 on the third initialization signal line to the control terminal of the second driving unit 101, initializing the potential of the control terminal of the second driving unit 101, and turning on the second driving unit 101. Afterwards, the second data writing unit 102 and the second compensation unit 105 are turned on in response to the third scan signal S3 on the third scan line, transmitting the time signal Vdata_t to the control terminal of the second driving unit 101, and maintaining a constant voltage difference across the coupling unit 104. During the light-emitting stage, the current control module 20 can generate a driving current according to the voltage state of its control terminal, driving the light-emitting module 60 to emit light. The frequency sweep signal SWEEP is used to scan the signal from high level to low level or from low level to high level during the light emission stage, so as to control the voltage of the output terminal (first node PW1) of the time control module 10, thereby controlling the voltage of the control terminal of the current control module 20, and then controlling the working state (on or off) of the current control module 20, so as to control the light emission time of the light emission module 60.

[0093] As a preferred embodiment provided in this example, Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, specifically a schematic diagram of the pixel circuit detailed as a device structure. (See reference) Figure 7The first driving unit 201 includes a fourth transistor M4, the first data writing unit 202 includes a fifth transistor M5, the current control unit 203 includes a sixth transistor M6, the first compensation unit 204 includes a seventh transistor M7, the first light-emitting control unit 205 includes an eighth transistor M8, the second light-emitting control unit 206 includes a ninth transistor M9, the first initialization unit 207 includes a tenth transistor M10, the second initialization unit 209 includes an eleventh transistor M11, and the second storage unit 208 includes a second capacitor C2. The light-emitting module 60 includes a light-emitting diode D1, which can be an LED, OLED, Micro LED, or Mini LED.

[0094] The second driving unit 101 includes a twelfth transistor M12, the second data writing unit 102 includes a thirteenth transistor M13, the second compensation unit 105 includes a fourteenth transistor M14, the third initialization unit 103 includes a fifteenth transistor M15, the third light-emitting control unit 106 includes a sixteenth transistor M16, the fourth light-emitting control unit 107 includes a seventeenth transistor M17, the coupling unit 104 includes a third capacitor C3, and the third storage unit 108 includes a fourth capacitor C4.

[0095] The reset module 50 includes the eighteenth transistor M18.

[0096] Figure 8 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention, which can be applied to... Figure 7 The pixel circuit shown, combined with Figure 7 and Figure 8 Taking the example that all transistors except the second transistor M2 are P-type transistors, the pixel circuit provided in this embodiment includes a voltage writing stage T1, a reset stage T2, and a light emission stage T3. The voltage writing stage T1 includes an initialization stage t1, a first data writing stage t2, and a second data writing stage t3.

[0097] During initialization phase t1, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a low-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the reset signal line is configured to transmit a high-level reset signal Set, the first light-emitting control signal line is configured to transmit a high-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a high-level second light-emitting control signal EM2. Therefore, the tenth transistor M10 and the eleventh transistor M11 are turned on. The first initialization voltage Vinit1 transmitted on the first initialization signal line is written to the gate of the fourth transistor M4, initializing the gate potential of the fourth transistor M4 and turning it on. Simultaneously, the second initialization voltage Vinit2 on the second initialization signal line or the second power supply voltage VSS on the second power supply line L2 is transmitted to the first terminal of the light-emitting diode D1 via the eleventh transistor M11, initializing the potential of the first terminal of the light-emitting diode D1.

[0098] During the first data writing phase t2, the first scan signal line is configured to transmit a low-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the reset signal line is configured to transmit a high-level reset signal Set, the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1, and the second light emission control signal line is configured to transmit a high-level second light emission control signal EM2. Therefore, the fifth transistor M5, the seventh transistor M7, and the fifteenth transistor M15 are turned on. The data signal Vdata_I is transmitted to the gate of the fourth transistor M4 via the fifth transistor M5, the fourth transistor M4, and the seventh transistor M7. The gate potential of the fourth transistor M4 is Vdata_I + Vth4, and it is stored in the second capacitor C2, where Vth4 is the threshold voltage of the fourth transistor M4, achieving threshold compensation for the fourth transistor M4.

[0099] The third initialization voltage Vinit3 transmitted on the third initialization signal line is transmitted to the gate of the twelfth transistor M12 via the fifteenth transistor M15, thereby initializing the gate potential of the twelfth transistor M12 and turning on the twelfth transistor M12.

[0100] During the second data writing phase t3, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a low-level third scan signal S3, the reset signal line is configured to transmit a high-level reset signal Set, the first light-emitting control signal line is configured to transmit a high-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a high-level second light-emitting control signal EM2. Therefore, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on. The time signal Vdata_t is transmitted through the thirteenth transistor M13, the twelfth transistor M12, and the fourteenth transistor M14 to the gate of the twelfth transistor M12 until the gate potential of the twelfth transistor M12 reaches Vdata_t + Vth12, at which point the twelfth transistor M12 is turned off. A constant voltage difference is maintained across the third capacitor C3.

[0101] The t4 stage is the time period of the voltage writing stage T1 for each of the remaining sub-pixels to complete the data writing for all pixel rows.

[0102] During the reset phase T2, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the reset signal line is configured to transmit a low-level reset signal Set, the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1, and the second light emission control signal line is configured to transmit a high-level second light emission control signal EM2. Therefore, the eighteenth transistor M18 is turned on, and the first initialization voltage Vinit1 on the first initialization signal line is transmitted to the first node PW1 via the eighteenth transistor M18, initializing the first node PW1.

[0103] The NOR gate U2 outputs a high level based on the low-level first initialization voltage Vinit1 and the low-level second reference voltage EN2, controlling the second transistor M2 to turn on. The first initialization voltage Vinit1 is transmitted to the second node PW2 through the second transistor M2, and the sixth transistor M6 turns on.

[0104] During the light-emitting stage T3, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the reset signal line is configured to transmit a high-level reset signal Set, the first light-emitting control signal line is configured to transmit a low-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a low-level second light-emitting control signal EM2. Therefore, the eighth transistor M8, the ninth transistor M9, the sixteenth transistor M16, and the seventeenth transistor M17 are turned on. The first power supply voltage VDDA on the first power supply line L1 is transmitted to the first terminal of the fourth transistor M4. The fourth transistor M4 generates a driving current under the control of its gate voltage, driving the light-emitting diode D1 to emit light.

[0105] Simultaneously, the sweep signal SWEEP gradually changes from high level SWEEP-H to low level SWEEP-L. Due to the coupling effect of the third capacitor C3, the potential of the gate of the twelfth transistor M12 changes synchronously. When the potential of the gate of the twelfth transistor M12 causes it to conduct, the third power supply voltage VDDW is transmitted to the first node PW1 through the sixteenth transistor M16, the twelfth transistor M12, and the seventeenth transistor M17, making the first node PW1 high. The NOR gate U2 outputs a low level under the high level of the first node PW1, controlling the second transistor M2 to turn off. The NAND gate U1 outputs a low level under the high level of the first node PW1 and the high-level first reference signal EN1, controlling the first transistor M1 to conduct. The first transistor M1 transmits the third power supply voltage VDDW to the second node PW2, thereby rapidly pulling the potential of the second node PW2 up to the turn-off voltage of the current control module 20, controlling the sixth transistor M6 to turn off, and the light-emitting diode D1 stops emitting light.

[0106] In addition, when continuous high brightness is required, the first reference signal EN1 is switched to a low level, the third transistor M3 is kept on, and the gate voltage of the sixth transistor M6 is kept at the on-state voltage, so that the light-emitting diode D1 continues to emit light.

[0107] Optionally, embodiments of the present invention also provide a driving method for a pixel circuit, which can be applied to the pixel circuit provided by any of the above-described technical solutions. Figure 9 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention, combined with... Figure 1 and Figure 9 Specifically, the driving method for this pixel circuit includes:

[0108] S110. During the reset phase, the control reset module resets the output terminal of the time control module, and controls the second potential control module to maintain the control terminal voltage of the current control module at the on-state voltage according to the voltage of the output terminal of the time control module.

[0109] S120. During the light-emitting stage, the control current control module drives the light-emitting module to emit light according to the data signal, and the control time control module controls the potential of its own output terminal according to the time signal and the frequency sweep signal. When the light-emitting stage ends, the control first potential control module keeps the control terminal voltage of the current control module at the off voltage according to the voltage of the output terminal of the time control module, so as to control the light-emitting time of the light-emitting module.

[0110] The pixel circuit driving method provided in this invention provides a second potential control module between the output terminal of the time control module and the control terminal of the current control module to maintain the control terminal of the current control module at the on-state voltage during the reset phase. A first potential control module is also provided between the output terminal of the time control module and the control terminal of the current control module to quickly and stably maintain the potential of the control terminal of the current control module at the off-state voltage when the light-emitting module stops emitting light. This maintains the stability of the potential at the control terminal of the current control module, allowing for rapid shutdown of the current control module and effectively avoiding unstable light emission from the light-emitting module. This, in turn, helps improve the flickering or uneven display caused by the unstable output signal of the time control module when the pixel circuit is turned off, thus enhancing the display effect.

[0111] Optionally, the driving method for the pixel circuit further includes:

[0112] In high-brightness display mode, the control third potential control module responds to the first reference signal of its own control terminal to keep the control terminal voltage of the current control module at the on-state voltage to meet the high-brightness display requirements.

[0113] This invention also provides a display panel, which includes the pixel circuit provided in any embodiment of this invention. Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. The display panel 200 can not only serve as... Figure 10 The mobile phone panel shown can also be a display panel in tablets, mobile phones, watches, wearable devices, as well as in-vehicle displays, camera displays, televisions, and computer screens. Since this display panel includes the pixel circuits provided in any embodiment of the present invention, the display panel provided in the embodiments of the present invention also possesses the beneficial effects described in any embodiment of the present invention.

[0114] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0115] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, include: The module includes a time control module, a current control module, a first potential control module, a second potential control module, a reset module, and a light-emitting module. The current control module and the light-emitting module are connected between the first power line and the second power line. The current control module is used to drive the light-emitting module to emit light according to the data signal during the light-emitting stage. The time control module is used to control the potential of its output terminal according to the time signal and the frequency sweep signal during the light emission stage, so as to control the light emission time of the light emission module. The reset module is connected to the output terminal of the time control module, and the reset module is used to reset the output terminal of the time control module during the reset phase; The first potential control module is connected between the output terminal of the time control module and the control terminal of the current control module, and the second potential control module is connected between the output terminal of the time control module and the control terminal of the current control module. The second potential control module is used to maintain the voltage of the control terminal of the current control module at the on-state voltage according to the voltage of the output terminal of the time control module during the reset phase. The first potential control module is used to maintain the voltage of the control terminal of the current control module at the off-state voltage according to the voltage of the output terminal of the time control module during the light-emitting phase.

2. The pixel circuit according to claim 1, characterized in that, The first potential control module includes a first logic unit and a first switch unit. The first input terminal of the first logic unit is connected to a first reference signal. The second input terminal of the first logic unit is connected to the output terminal of the time control module. The output terminal of the first logic unit is connected to the control terminal of the first switch unit. The first terminal of the first switch unit is connected to a third power line. The second terminal of the first switch unit is connected to the control terminal of the current control module. The second potential control module includes a second logic unit and a second switch unit. The first input terminal of the second logic unit is connected to a second reference signal. The second input terminal of the second logic unit is connected to the output terminal of the time control module. The output terminal of the second logic unit is connected to the control terminal of the second switch unit. The first terminal of the second switch unit is connected to a first initialization signal line. The second terminal of the second switch unit is connected to the control terminal of the current control module.

3. The pixel circuit according to claim 2, characterized in that, The first logic unit includes a NAND gate, the first switching unit includes a first transistor, the first input terminal of the NAND gate is connected to the first reference signal, the second input terminal of the NAND gate is connected to the output terminal of the time control module, the output terminal of the NAND gate is connected to the gate of the first transistor, the first terminal of the first transistor is connected to the third power supply line, and the second terminal of the first transistor is connected to the control terminal of the current control module. The second logic unit includes a NOR gate, the second switching unit includes a second transistor, the first input terminal of the NOR gate is connected to the second reference signal, the second input terminal of the NOR gate is connected to the output terminal of the time control module, the output terminal of the NOR gate is connected to the gate of the second transistor, the first terminal of the second transistor is connected to the first initialization signal line, and the second terminal of the second transistor is connected to the control terminal of the current control module. The first reference signal and the second reference signal are inverse signals of each other.

4. The pixel circuit according to claim 3, characterized in that, The channel type of the first transistor is different from that of the second transistor.

5. The pixel circuit according to claim 3, characterized in that, The reset module is connected between the first initialization signal line and the output of the time control module.

6. The pixel circuit according to claim 1, characterized in that, It also includes a third potential control module, which is connected to the control terminal of the current control module. The third potential control module is used to continuously conduct in response to the first reference signal in the high brightness display mode, so as to continuously maintain the control terminal voltage of the current control module at the conduction voltage.

7. The pixel circuit according to claim 6, characterized in that, The third potential control module includes a third transistor, the gate of which is connected to the first reference signal, the first terminal of which is connected to the first initialization signal line, and the second terminal of which is connected to the control terminal of the current control module.

8. The pixel circuit according to claim 6, characterized in that, It also includes a first storage unit, a first end of which is connected to the second power line, and a second end of which is connected to the control terminal of the current control module.

9. The pixel circuit according to claim 1, characterized in that, The current control module includes a first driving unit, a first data writing unit, and a current control unit; The current control unit and the first driving unit are connected between the first power line and the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power line. The first data writing unit is connected to the first driving unit and is used to write the data signal to the control terminal of the first driving unit.

10. The pixel circuit according to claim 9, characterized in that, The current control module further includes a first compensation unit, which is connected between the second end and the control end of the first driving unit. The first data writing unit is connected to the first end of the first driving unit. The control end of the first data writing unit and the control end of the first compensation unit are both connected to the first scan line.

11. The pixel circuit according to claim 10, characterized in that, The current control module further includes a first light-emitting control unit and a second light-emitting control unit. A first end of the first light-emitting control unit is connected to the first power line, a second end of the first light-emitting control unit is connected to the first end of the first driving unit, a second end of the first driving unit is connected to the first end of the current control unit, a second end of the current control unit is connected to the first end of the first end of the second light-emitting control unit, and a second end of the second light-emitting control unit is connected to the first end of the light-emitting module. The control end of the second light-emitting control unit is connected to a first light-emitting control signal line, and the control end of the first light-emitting control unit is connected to a second light-emitting control signal line.

12. The pixel circuit according to claim 11, characterized in that, The current control module further includes a second storage unit, which is connected between the control terminal of the first drive unit and the first power line.

13. The pixel circuit according to claim 11, characterized in that, The current control module further includes a first initialization unit, a first end of which is connected to a first initialization signal line, a second end of which is connected to the control end of the first drive unit, and the control end of the first initialization unit is connected to a second scan line.

14. The pixel circuit according to claim 13, characterized in that, The current control module further includes a second initialization unit. The first end of the second initialization unit is connected to the second power line or the second initialization signal line, the second end of the second initialization unit is connected to the first end of the light-emitting module, and the control end of the second initialization unit is connected to the second scan line.

15. The pixel circuit according to claim 1, characterized in that, The time control module includes a second driving unit, a second data writing unit, a third initialization unit, and a coupling unit; The second driving unit is connected between the third power line and the output terminal of the time control module; the second data writing unit is used to write the time signal to the control terminal of the second driving unit; the third initialization unit is connected between the third initialization signal line and the control terminal of the second driving unit; the control terminal of the third initialization unit is connected to the first scan line. The coupling unit is connected to the control terminal of the second driving unit, and the coupling unit is used to control the potential of the control terminal of the second driving unit according to the frequency sweep signal.

16. The pixel circuit according to claim 15, characterized in that, The time control module further includes a second compensation unit, which is connected between the control terminal and the second terminal of the second drive unit. The control terminal of the second compensation unit and the control terminal of the second data writing unit are both connected to the third scan line. The second data writing unit is connected to the first terminal of the second drive unit.

17. The pixel circuit according to claim 16, characterized in that, The time control module further includes a third light-emitting control unit and a fourth light-emitting control unit. The control terminals of the third and fourth light-emitting control units are both connected to the second light-emitting control signal line. The first terminal of the third light-emitting control unit is connected to the third power supply line. The second terminal of the third light-emitting control unit is connected to the first terminal of the second driving unit. The first terminal of the fourth light-emitting control unit is connected to the second terminal of the second driving unit. The second terminal of the fourth light-emitting control unit is connected to the output terminal of the time control module.

18. The pixel circuit according to claim 17, characterized in that, The time control module further includes a third storage unit, which is connected between the third power line and the control terminal of the second drive unit.

19. A driving method for a pixel circuit, characterized in that, During the reset phase, the control reset module resets the output of the time control module, and controls the second potential control module to maintain the control terminal voltage of the current control module at the on-state voltage according to the voltage of the output of the time control module. During the light-emitting phase, the current control module drives the light-emitting module to emit light according to the data signal, and controls the time control module to control the potential of its output terminal according to the time signal and the frequency sweep signal. When the light-emitting phase ends, the first potential control module controls the voltage of the control terminal of the current control module to maintain the voltage of the control terminal of the time control module at the off voltage according to the voltage of the output terminal of the time control module, so as to control the light-emitting time of the light-emitting module.

20. The driving method for a pixel circuit according to claim 19, characterized in that, The pixel circuit also includes a third potential control module; The driving method for the pixel circuit further includes: In high-brightness display mode, the third potential control module is controlled to continuously conduct in response to the first reference signal of its own control terminal, so as to continuously maintain the control terminal voltage of the current control module at the conduction voltage.

21. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1-18.

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