Pixel driving circuit, control method of pixel driving circuit, and display device

Abstract

The application discloses a pixel driving circuit, a control method of the pixel driving circuit and a display device. The circuit is responsive to a first control signal, a first voltage writing unit writes a first voltage to a control end of a driving transistor, and a first compensation unit stores a second voltage; responsive to a second control signal, a data signal writing unit writes a third voltage to the control end of the driving transistor through the first compensation unit; responsive to a third control signal, a second compensation unit stores a fourth voltage and writes the fourth voltage to the control end of the driving transistor; and the driving transistor is further used for writing a working voltage to a light-emitting control unit corresponding to the driving transistor after the fourth voltage is written to the control end of the driving transistor. Through the response to different control signals, the separation processing of the data writing stage and the compensation stage in the pixel driving circuit is realized, thereby avoiding the problem that the display effect of a display module is poor due to the short data writing time and compensation time.

Description

Technical Field

[0001] The present disclosure generally relates to the field of circuit design technology, and more particularly to a pixel driving circuit, a control method for a pixel driving circuit, and a display device. Background Art

[0002] With the rapid development of display technology, active-matrix organic light-emitting diodes (AMOLED) have been widely used in screen displays.

[0003] However, in order to meet the requirements of high pixel resolution, high refresh rate, high peak brightness, and display uniformity under low brightness conditions for displayed images, existing AMOLED display modules shorten the compensation time and data writing time for each frame when displaying images. This results in the display effect of the AMOLED display module being unable to be guaranteed. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a pixel driving circuit, a control method for a pixel driving circuit, and a display device. The pixel driving circuit can realize separate processing of the data writing phase and the compensation phase in the pixel driving circuit by responding to different control signals, thereby avoiding the problem of poor display effect of the display module due to short data writing time and compensation time.

[0005] The circuit is as follows:

[0006] According to a first aspect of the present application, a pixel driving circuit is provided, comprising: a driving transistor, a first voltage writing unit, a data signal writing unit, a first compensation unit, a second compensation unit, and a light emitting control unit.

[0007] In response to the first control signal, the first voltage writing unit writes a first voltage to the control terminal of the driving transistor, the first voltage including the threshold voltage of the driving transistor, and, in response to the first control signal, the first compensation unit stores a second voltage, the second voltage being the compensation voltage of the data signal writing unit;

[0008] In response to the second control signal, the data signal writing unit writes a third voltage to the control terminal of the driving transistor through the first compensation unit; the third voltage includes the first voltage, the second voltage and the data voltage;

[0009] In response to the third control signal, the second compensation unit stores a fourth voltage and writes the fourth voltage into the control terminal of the driving transistor;

[0010] The driving transistor is further configured to write an operating voltage into a light emitting control unit corresponding to the driving transistor after the fourth voltage is written into the control terminal of the driving transistor.

[0011] In addition, the pixel driving circuit of the present application may also have the following additional technical features:

[0012] Preferably, the first voltage writing unit is connected to the first input end of the driving transistor, the data signal writing unit is connected to the first compensation unit, the first compensation unit is connected to the control end of the driving transistor, the second compensation unit is connected to the control end of the driving transistor, and the first input end of the driving transistor is connected to the light-emitting control unit.

[0013] Preferably, the first voltage writing unit includes a first transistor, a control terminal of the first transistor is used to receive a first control signal, a first input terminal of the first transistor is connected to a first input terminal of the driving transistor, and a voltage of a second input terminal of the first transistor is a source reference voltage.

[0014] The first transistor is used to write a source reference voltage to the first input terminal of the driving transistor in response to a first control signal, so that the driving transistor is turned on when the source reference voltage is less than the initial voltage of the control terminal of the driving transistor and the control terminal voltage of the driving transistor includes the threshold voltage and the source reference voltage.

[0015] Preferably, the first compensation unit includes a second transistor and a first capacitor, the first input terminal of the second transistor is connected to the first capacitor, the first capacitor is connected to the control terminal of the driving transistor, and the voltage of the second input terminal of the second transistor is a negative voltage of the second voltage.

[0016] The control terminal of the second transistor is used to receive a first control signal, and write a second voltage into the first capacitor in response to the first control signal.

[0017] Preferably, the data signal writing unit includes a third transistor, a first input terminal of the third transistor is connected to the control terminal of the driving transistor through the first compensation unit, and a voltage at a second input terminal of the third transistor is the data voltage.

[0018] The control terminal of the third transistor is used to receive the second control signal, and write a third voltage into the control terminal of the driving transistor through the first compensation unit in response to the first control signal.

[0019] Preferably, the second compensation unit includes a fourth transistor and a second capacitor, the first input terminal of the fourth transistor is respectively connected to the first input terminal of the driving transistor and one end of the second capacitor, the second capacitor is connected to the control terminal of the driving transistor, the control terminal of the fourth transistor is used to receive a third control signal and write a fourth voltage to the second capacitor in response to the third control signal; the fourth voltage is a negative voltage of the threshold voltage.

[0020] Preferably, the pixel driving circuit further includes a reset unit connected to the control terminal of the driving transistor.

[0021] The reset unit is configured to write an initial voltage into the control terminal of the driving transistor in response to a fourth control signal.

[0022] Preferably, the reset unit includes a fifth transistor, the first input terminal of the fifth transistor is connected to the control terminal of the driving transistor, the voltage of the second input terminal of the fifth transistor is the initial voltage, the control terminal of the fifth transistor is used to receive a fourth control signal, and write the initial voltage to the control terminal of the driving transistor in response to the fourth control signal.

[0023] Preferably, the pixel driving circuit further includes a signal generating unit, and an output terminal of the signal generating unit is connected to the control terminal of the driving transistor.

[0024] Preferably, the signal generating unit includes a first clock signal, a second clock signal, a first off-voltage and a second off-voltage, wherein the driving capability of the first clock signal is higher than the driving capability of the second clock signal, and the first off-voltage is lower than the second off-voltage;

[0025] The signal generating unit is configured to turn on the first clock signal and the second off voltage when the time for the driving transistor to write the operating voltage to the corresponding light emitting control unit is less than a preset threshold;

[0026] The signal generating unit is further configured to turn on the second clock signal and the first off-voltage when the time for the driving transistor to write the operating voltage to the corresponding light emitting control unit is greater than a preset threshold.

[0027] Preferably, the transistors in the pixel driving circuit are N-type thin film transistors.

[0028] According to a second aspect of the present application, a method for controlling a pixel driving circuit is provided. The method is applied to the pixel driving circuit according to the first aspect, and the method includes:

[0029] Obtaining a preset duration for a driving transistor in a pixel driving circuit to write an operating voltage to a light emitting control unit corresponding to the driving transistor;

[0030] Determining the number of compensation times of the pixel driving circuit based on a preset time length;

[0031] Based on the number of compensation times, the pixel driving circuit writes an operating voltage to the light emitting control unit corresponding to the driving transistor.

[0032] Preferably, determining the number of compensation times of the pixel driving circuit based on a preset time length includes:

[0033] When the preset time length is less than the preset threshold, the pixel driving circuit performs compensation at most once;

[0034] When the preset time length is greater than the preset threshold, the pixel driving circuit performs compensation at least twice.

[0035] According to a third aspect of the present application, a display device is provided, which includes the pixel driving circuit described in the first aspect.

[0036] The pixel driving circuit, the control method of the pixel driving circuit, and the display device provided in the embodiments of the present application realize separate processing of the data writing stage and the compensation stage in the pixel driving circuit by responding to different control signals; specifically, on the one hand, the pixel driving circuit determines and compensates the threshold voltage of the driving transistor control terminal by responding to different control signals in each stage, so as to avoid the influence of the negative bias generated by the driving transistor control terminal on the working voltage when the driving transistor writes the working voltage to the corresponding light-emitting control unit, thereby ensuring the display effect of the display module corresponding to the pixel driving circuit; on the other hand, by responding to the first control signal, the first compensation unit can store the second voltage, so as to compensate the voltage of the data signal writing unit when the pixel driving circuit responds to the second control signal, thereby further ensuring the accuracy of the data voltage written by the data signal writing unit to the driving transistor control terminal.

[0037] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0039] Figure 1 A schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0040] Figure 2 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0041] Figure 3 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0042] Figure 4 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0043] Figure 5 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0044] Figure 6A schematic diagram of a driving signal corresponding to each transistor in the pixel driving circuit provided in an embodiment of the present application;

[0045] Figure 7 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0046] Figure 8 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0047] Figure 9 A schematic diagram of another driving signal corresponding to each transistor in the pixel driving circuit provided in an embodiment of the present application;

[0048] Figure 10 A schematic diagram of another driving signal corresponding to each transistor in the pixel driving circuit provided in an embodiment of the present application;

[0049] Figure 11 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0050] Figure 12 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application

[0051] Figure 13 A flowchart of a method for controlling a pixel driving circuit according to an embodiment of the present application;

[0052] Figure 14 A corresponding schematic diagram of the driving phase of the pixel driving circuit provided in an embodiment of the present application;

[0053] Figure 15 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0055] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. In addition, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The terms "first" and "second" in the description and claims of the embodiments of this application are used to distinguish different objects, rather than to describe a specific order of objects.

[0056] The existing AMOLED display module still has the problem of poor display effect when displaying images.

[0057] Therefore, the pixel driving circuit provided in the present application can separate the data writing stage and the compensation stage in the pixel driving circuit by responding to different control signals, thereby avoiding the problem of poor display effect of the display module due to short data writing time and compensation time.

[0058] Figure 1 is a schematic diagram of the pixel driving circuit provided in the present application, as shown in Figure 1 The circuit includes a driving transistor 10, a first voltage writing unit 20, a data signal writing unit 30, a first compensation unit 40, a second compensation unit 50, and a light-emitting control unit 60.

[0059] Specifically, the first voltage writing unit 20 is connected with the first input end of the driving transistor 10, the data signal writing unit 30 is connected with the first compensation unit 40, the first compensation unit 40 is connected with the control end of the driving transistor 10, the second compensation unit 50 is connected with the control end of the driving transistor 10, and the first input end of the driving transistor 10 is connected with the light-emitting control unit 60.

[0060] For example, the driving transistor 10 is a thin film transistor (TFT) used for controlling each pixel in a liquid crystal display screen, wherein the input end of the driving transistor 10 can be a source or a drain, and the control end can be a gate.

[0061] Specifically, the driving transistor 10 is an N-type metal-oxide-semiconductor (NMOS), and based on this, the control end of the driving transistor 10 is in a high-level conduction state.

[0062] In the present application, each unit in the pixel driving circuit can respond to different control signals to compensate for the negative bias voltage of the gate of the driving transistor 10 based on Figure 1 the conduction state between different units.

[0063] For example, the pixel driving circuit responds to a first control signal S1, the first voltage writing unit 20 writes a first voltage to the control end of the driving transistor 10, and the first compensation unit 40 stores a second voltage; wherein the second voltage is the compensation voltage of the data signal writing unit 30.

[0064] Specifically, the first voltage includes the threshold voltage Vth of the driving transistor 10, that is, the first stage responded by the pixel driving circuit is used to determine the threshold voltage Vth of the driving transistor 10. Based on this, the first control signal S1 can be a compensation scanning signal corresponding to the compensation stage, and the driving transistor 10 is turned on in this compensation stage.

[0065] For example, when the driving transistor 10 is an N-type transistor, the driving transistor 10 is turned on at a high level.

[0066] Exemplarily, in response to the second control signal S2 , the pixel driving circuit writes the third voltage to the control terminal of the driving transistor 10 through the first compensation unit 40 in the data signal writing unit 30 .

[0067] Specifically, the third voltage includes the first voltage, the second voltage and the data voltage Vdata, that is, the second stage responded by the pixel driving circuit is used to write the data voltage Vdata to the driving transistor 10. Based on this, the second control signal S2 can be a data writing scan signal corresponding to the data writing stage, and the driving transistor 10 is turned on in this data writing stage.

[0068] Exemplarily, in response to the third control signal S3 , the second compensation unit 50 of the pixel driving circuit stores the fourth voltage and writes the fourth voltage into the control terminal of the driving transistor 10 .

[0069] Specifically, the fourth voltage is a negative voltage -Vth of the threshold voltage Vth, that is, the third stage responded by the pixel driving circuit is used to write a negative voltage -Vth of the threshold voltage Vth to the driving transistor 10 to eliminate the threshold voltage Vth of the control end of the driving transistor 10. Based on this, the third control signal S3 can be a light-emitting control scanning signal EM signal corresponding to the light-emitting control stage, and the driving transistor 10 is turned on in this light-emitting control stage.

[0070] Exemplarily, the driving transistor 10 is further configured to write an operating voltage to the light emitting control unit 60 corresponding to the driving transistor 10 after writing the fourth voltage -Vth to the control terminal of the driving transistor 10 (ie, eliminating the threshold voltage Vth of the control terminal of the driving transistor 10 ).

[0071] In some embodiments of the present application, a specific device distribution of the first voltage writing unit 20 in the pixel driving circuit is also provided.

[0072] For example, Figure 2 is another schematic diagram of the pixel driving circuit provided in an embodiment of the present application. Figure 2As shown, the first voltage writing unit 20 includes a first transistor 21, the first input terminal of the first transistor 21 is connected to the first input terminal of the driving transistor 10, the voltage of the second input terminal of the first transistor 21 is the source reference voltage Vs, and the control terminal of the first transistor 21 is used to receive the first control signal S1.

[0073] Exemplarily, the first transistor 21 may be an NMOS transistor or a P-type metal-oxide-semiconductor (Positive channel Metal Oxide Semiconductor, referred to as PMOS), which is not specifically limited here.

[0074] In the following, the first transistor 21 is taken as an NMOS transistor as an example. The first input terminal of the first transistor 21 is the source, and the second input terminal is the drain. The voltage of the drain is the source reference voltage Vs.

[0075] Specifically, the first transistor 21 writes the source reference voltage Vs to the first input terminal of the driving transistor 10 in response to the first control signal S1, so that the driving transistor 10 is turned on when the source reference voltage Vs is less than the initial voltage Vinit1 of the control terminal of the driving transistor 10, and the control terminal voltage of the driving transistor 10 includes the threshold voltage Vth and the source reference voltage Vs.

[0076] Based on this, during the compensation phase responded by the pixel driving circuit, the voltage at the control terminal of the driving transistor 10 is Vth+Vs.

[0077] In some embodiments of the present application, a specific device distribution of the first compensation unit 40 in the pixel driving circuit is also provided.

[0078] For example, Figure 3 is another schematic diagram of the pixel driving circuit provided in an embodiment of the present application. Figure 3 As shown, the first compensation unit 40 includes a second transistor 41 and a first capacitor 42, the first input terminal of the second transistor 41 is connected to the first capacitor 42, the first capacitor 42 is connected to the control terminal of the driving transistor 10, the voltage of the second input terminal of the second transistor 41 is the negative voltage of the second voltage, and the control terminal of the second transistor 41 is used to receive the first control signal S1.

[0079] Exemplarily, the second transistor 41 may be an NMOS transistor or a PMOS transistor, which is not specifically limited here.

[0080] In the following, the second transistor 41 is taken as an NMOS transistor as an example. The first input terminal of the second transistor 41 is the drain, and the second input terminal is the source. The voltage of the source is a negative voltage of the second voltage.

[0081] Specifically, in response to the first control signal S1, the second transistor 41 writes the second voltage into the first capacitor 42. For example, when the voltage at the source of the second transistor 41 is the initialization voltage Vinit2, the second voltage is -Vinit2.

[0082] In some embodiments of the present application, a specific device distribution of the data signal writing unit 30 in the pixel driving circuit is also provided.

[0083] For example, Figure 4 is another schematic diagram of the pixel driving circuit provided in an embodiment of the present application. Figure 4 As shown, the data signal writing unit 30 includes a third transistor 31, the first input terminal of the third transistor 31 is connected to the control terminal of the driving transistor 10 through the first compensation unit 40, the voltage of the second input terminal of the third transistor 31 is the data voltage Vdata, and the control terminal of the third transistor 31 is used to receive the second control signal.

[0084] Specifically, combined Figure 3 In the specific layout of the first compensation unit 40 shown, the first input terminal of the third transistor 31 is connected to the control terminal of the driving transistor 10 through the first capacitor 42 in the first compensation unit 40 .

[0085] Exemplarily, the third transistor 31 may be an NMOS transistor or a PMOS transistor, which is not specifically limited here.

[0086] In the following, the third transistor 31 is taken as an NMOS transistor as an example. The first input terminal of the third transistor 31 is the drain, and the second input terminal is the source. The voltage of the source is the data voltage Vdata.

[0087] Based on this, in the data writing phase responded by the pixel driving circuit, the third transistor 31 writes the data voltage Vdata into the control terminal of the driving transistor 10 through the first capacitor 42, that is, the control terminal voltage of the driving transistor 10 is Vth+Vs+Vdata-Vinit2.

[0088] In some embodiments of the present application, a specific device distribution of the second compensation unit 50 in the pixel driving circuit is also provided.

[0089] For example, Figure 5 is another schematic diagram of the pixel driving circuit provided in an embodiment of the present application. Figure 5 As shown, the second compensation unit 50 includes a fourth transistor 51 and a second capacitor 52, the first input end of the fourth transistor 51 is respectively connected to the first input end of the driving transistor 10 and one end of the second capacitor 52, the second capacitor 52 is connected to the control end of the driving transistor 10, and the control end of the fourth transistor 51 is used to receive a third control signal.

[0090] Exemplarily, the fourth transistor 51 may be an NMOS transistor or a PMOS transistor, which is not specifically limited here.

[0091] In the following, the fourth transistor 51 is taken as an NMOS transistor as an example, the first input terminal of the fourth transistor 51 is the source, and the second input terminal is the drain.

[0092] Specifically, the fourth transistor 51 writes the fourth voltage −Vth into the second capacitor 52 in response to the third control signal.

[0093] Based on this, in the light emitting control stage responded by the pixel driving circuit, the fourth transistor 51 writes the fourth voltage -Vth to the second capacitor 52, and uses the second capacitor 52 to write the fourth voltage -Vth into the control end of the driving transistor 10, that is, the voltage of the control end of the driving transistor 10 in this stage is Vs+Vdata-Vinit2 (the on-state voltage of the driving transistor 10 is Vdata-Vinit2).

[0094] In some embodiments of the present application, the driving timing of each control signal described in the above embodiments is also provided.

[0095] For example, when the above transistors are all NMOS transistors, the timing of each control signal is as follows: Figure 6 As shown:

[0096] In the first stage, the first control signal S1 is at a high level, the second control signal S2 and the third control signal S3 are at a low level, and the reference signal Figure 5 , the driving transistor 10, the first transistor 21 and the second transistor 41 are in the on state, and the other transistors are in the off state;

[0097] In the second stage, the second control signal S2 is at a high level, the first control signal S1 and the third control signal S3 are at a low level, and the reference signal Figure 5 , the driving transistor 10 and the third transistor 31 are in the on state, and the other transistors are in the off state;

[0098] In the third stage, the third control signal S3 is at a high level, the first control signal S1 and the second control signal S2 are at a low level, and the reference signal Figure 5 , the driving transistor 10 and the fourth transistor 51 are in the on state, and the other transistors are in the off state.

[0099] In some embodiments of the present application, other module distributions of the pixel driving circuit are also provided. Exemplarily, the pixel driving circuit further includes a reset unit 70 , which is connected to the control terminal of the driving transistor 10 .

[0100] Specifically,Figure 7 is another schematic diagram of the pixel driving circuit provided by the embodiments of the present application, as shown in Figure 7 The reset unit 70 includes a fifth transistor 71, the first input end of the fifth transistor 71 is connected with the control end of the driving transistor 10, the voltage of the second input end of the fifth transistor 71 is the initial voltage Vinit1, and the control end of the fifth transistor 71 is used for receiving the fourth control signal S4.

[0101] For example, the fifth transistor 71 can be an NMOS transistor or a PMOS transistor, which is not specifically limited here.

[0102] For example, the first input end of the fifth transistor 71 is the source and the second input end is the drain, wherein the voltage of the drain is the initial voltage Vinit1.

[0103] Specifically, the fifth transistor 71 writes the initial voltage Vinit1 to the control end of the driving transistor 10 in response to the fourth control signal S4 (i.e., the initial voltage of the control end of the driving transistor 10 is Vinit1).

[0104] Therefore, the fourth control signal S4 can be an initialization signal to which the pixel driving circuit responds, and the stage of responding to the initialization signal can be referred to as an initialization stage.

[0105] Correspondingly, referring to Figure 7 The second transistor 41 can also receive the fourth control signal S4 to initialize the voltage in response to the fourth control signal S4, so as to eliminate the interference of the historical state.

[0106] It should be noted that when the control signal to which the pixel driving circuit responds includes the first to fourth control signals (i.e., S1-S4), the pixel driving circuit first responds to the fourth control signal S4 (i.e., first enters the initialization stage), and then responds to the first to third control signals in sequence (i.e., then enters the compensation-data writing-emitting control stage in sequence).

[0107] In some embodiments of the present application, other device distributions of the pixel driving circuit are also provided. For example, the pixel driving circuit further includes a sixth transistor 81, a seventh transistor 82, an eighth transistor 83, and a ninth transistor 84.

[0108] For example, the sixth transistor 81, the seventh transistor 82, the eighth transistor 83, and the ninth transistor 84 can be an NMOS transistor or a PMOS transistor, which is not specifically limited here.

[0109] In the following, it is taken as an example that the sixth transistor 81 , the seventh transistor 82 , the eighth transistor 83 and the ninth transistor 84 are all NMOS transistors, and the first input terminal of each transistor is a source, and the second input terminal is a drain.

[0110] For example, Figure 8 is another schematic diagram of the pixel driving circuit provided in an embodiment of the present application. Figure 8 As shown, the first input terminal of the sixth transistor 81 is the first power supply voltage VDD, the second input terminal of the sixth transistor 81 is connected to the second input terminal of the driving transistor 10, and the control terminal of the sixth transistor 81 is used to receive the third control signal S3; the input terminal of the seventh transistor 82 is respectively connected to the control terminal and the second input terminal of the driving transistor 10, and the control terminal of the seventh transistor 82 is used to receive the first control signal S1; the first input terminal of the eighth transistor 83 is connected to the second input terminal of the fourth transistor 51, the second input terminal of the eighth transistor 83 is the initial voltage Vinit3, and the control terminal of the eighth transistor 83 is used to receive the first control signal S1, the second control signal S2 or the fourth control signal S4; the first input terminal of the ninth transistor 84 is connected to the second input terminal of the driving transistor 10, the second input terminal of the ninth transistor 84 is the initial voltage Vinit4, and the control terminal of the ninth transistor 84 is used to receive the fourth control signal S4.

[0111] Specifically, the sixth transistor 81 is used to turn on the sixth transistor 81 in response to the third control signal S3; the seventh transistor 82 is used to turn on the seventh transistor 82 in response to the first control signal S1; the eighth transistor 83 is used to turn on the eighth transistor 83 in response to the first control signal S1, the second control signal S2 or the fourth control signal S4; the ninth transistor 84 is used to turn on the ninth transistor 84 in response to the fourth control signal S4.

[0112] In some embodiments of the present application, the driving timing of each control signal described in the above embodiments is also provided.

[0113] For example, Figure 8 When the transistors in the pixel driving circuit shown are all NMOS transistors, the timing of each control signal is as follows: Figure 9 As shown:

[0114] In the first stage, the fourth control signal S4 is at a high level, the first control signal S1, the second control signal S2 and the third control signal S3 are at a low level, Figure 8 , the ninth transistor 84, the fifth transistor 71, the eighth transistor 83 and the second transistor 41 are in the on state, and the other transistors are in the off state; at this time, the pixel driving circuit is in the initialization stage;

[0115] In the second stage, the first control signal S1 is at a high level, the second control signal S2, the third control signal S3 and the fourth control signal S4 are at a low level, Figure 8 , the seventh transistor 82, the eighth transistor 83, the driving transistor 10, the first transistor 21 and the second transistor 41 are in the on state, and the other transistors are in the off state; at this time, the pixel driving circuit is in the compensation stage;

[0116] In the third stage, the second control signal S2 is at a high level, the first control signal S1, the third control signal S3 and the fourth control signal S4 are at a low level, Figure 8 , the eighth transistor 83, the driving transistor 10, and the third transistor 31 are in the on state, and the other transistors are in the off state; at this time, the pixel driving circuit is in the data writing stage;

[0117] In the fourth stage, the third control signal S3 is at a high level, the first control signal S1, the second control signal S2 and the fourth control signal S4 are at a low level, Figure 8 , the sixth transistor 81, the driving transistor 10, and the fourth transistor 51 are in the on state, and the other transistors are in the off state; at this time, the pixel driving circuit is in the light emitting control stage.

[0118] For example, the duration of the light emitting control phase may be set to be longer than the durations of the initialization phase, the compensation phase, and the data writing phase.

[0119] In an embodiment of the present application, by initializing the voltages of each node in the pixel driving circuit in the above-mentioned initialization stage, the hysteresis effect caused by the grayscale difference between adjacent pixels under low brightness conditions can be effectively improved, thereby effectively avoiding the ghosting phenomenon caused by the hysteresis effect; secondly, by separating the above-mentioned initialization stage, compensation stage and data writing stage, the crosstalk problem caused by the coupling of the data writing voltage Vdata and the power supply voltage Vdd can be effectively avoided.

[0120] It should be noted that when the stability of the pixel driving circuit is high (for example, when the display module is in a high refresh state), the above-mentioned initialization stage and compensation stage can be skipped to improve the writing quality of the Data in the pixel driving circuit, thereby improving the picture display quality of the display module.

[0121] Specifically, Figure 10 This is another schematic diagram of driving signals corresponding to each transistor in the pixel driving circuit provided in an embodiment of the present application, such as Figure 10 As shown:

[0122] In the first stage, the second control signal S2 is at a high level, the first control signal S1, the third control signal S3 and the fourth control signal S4 are at a low level, Figure 8, the eighth transistor 83, the driving transistor 10, and the third transistor 31 are in the on state, and the other transistors are in the off state; at this time, the pixel driving circuit is in the data writing stage;

[0123] In the second stage, the third control signal S3 is at a high level, the first control signal S1, the second control signal S2 and the fourth control signal S4 are at a low level, Figure 8 , the sixth transistor 81, the driving transistor 10, and the fourth transistor 51 are in the on state, and the other transistors are in the off state; at this time, the pixel driving circuit is in the light emitting control stage.

[0124] In some embodiments of the present application, other module distributions of the pixel driving circuit are also provided. Exemplarily, the pixel driving circuit further includes a signal generating unit 90 , the output terminal of the signal generating unit 90 is connected to the control terminal of the driving transistor 10 .

[0125] Exemplarily, the signal generating unit 90 includes a first clock signal CLK1 , a second clock signal CLK2 , a first off-state voltage VGL1 , and a second off-state voltage VGL2 .

[0126] Exemplarily, the signal generating unit 90 further includes a transistor 91 , a transistor 92 , a transistor 93 , a transistor 94 , a transistor 95 and a signal generating module 96 .

[0127] Exemplarily, the signal generating module 93 may be a single GOA generating unit.

[0128] Specifically, Figure 11 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application, such as Figure 11 As shown, the output end of the signal generating module 96 is connected to the control end of the transistor 93 , the control end of the transistor 94 , and the control end of the transistor 95 , respectively.

[0129] Specifically, the first input terminals of transistor 93 and transistor 94 are the first clock signal CLK1 and the second clock signal CLK2 respectively; the second input terminals of transistor 91 and transistor 92 are the first turn-off voltage VGL1 and the second turn-off voltage VGL2 respectively; the first input terminal of transistor 95 is connected to the control terminal of the driving transistor 10.

[0130] Exemplarily, the driving capability of the first clock signal CLK1 is higher than that of the second clock signal CLK2 , and the first off-state voltage VGL1 is lower than the second off-state voltage VGL2 .

[0131] Specifically, the signal generating unit 90 is used to turn on the first clock signal CLK1 and the second shutdown voltage VGL2 when the time for the driving transistor 10 to write the operating voltage to the corresponding light-emitting control unit 60 is less than a preset threshold; and is also used to turn on the second clock signal CLK2 and the first shutdown voltage VGL1 when the time for the driving transistor 10 to write the operating voltage to the corresponding light-emitting control unit 60 is greater than a preset threshold.

[0132] It should be noted that in the case of high brightness and high refresh, existing display modules usually need to increase the climbing speed of the GOA level in the pixel driving circuit, while in the case of low brightness, it is usually necessary to prevent leakage current to improve low grayscale uniformity.

[0133] In this regard, the embodiment of the present application can generate driving signals respectively through the two clock signals CLK1 and CLK2 in the signal generating unit 90, so that when the display module is in high brightness and high refresh, the CLK1 with higher driving capability can be used to effectively improve the ability of the Gate signal to turn on the above-mentioned transistors, thereby improving the driving capability of the pixel driving circuit under high brightness; and when the display module is in low brightness and low refresh, the use of CLK2 can reduce power consumption and improve the display uniformity of the pixel unit of the pixel driving circuit under low brightness; at the same time, the above-mentioned transistors 93 and 94 are used as the output units of CLK1 and CLK2, which can effectively improve the tolerance of the output unit.

[0134] Secondly, when the display module is in low brightness and low refresh mode and the leakage current accounts for a large proportion, VGL1 can be used to enhance the off state of each transistor in the pixel driving circuit. When the display module is in normal brightness, using VGL2 can save circuit power consumption. In addition, using transistors 91 and 92 as output units of VGL1 and VGL2 can also effectively improve the tolerance of the output unit.

[0135] In some embodiments of the present application, a pixel driving circuit arrangement is also provided. For example, Figure 12 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application, such as Figure 12 As shown, one end of the second capacitor 52 is connected to one end of the first capacitor 42 and the first input end of the third transistor 31 respectively.

[0136] In some embodiments of the present application, a specific structural distribution of transistors is also provided. Exemplarily, the transistors in the above pixel driving circuit are all top-gate structures.

[0137] In the embodiment of the present application, by setting the transistor 10 as a top gate structure, the overlapping portion between the gate, source and drain in each transistor can be made smaller, thereby reducing the capacitance parasitics; it also effectively avoids the direct impact of environmental factors such as humidity and oxygen on the channel, reduces the drift of the threshold voltage; and at the same time improves the carrier mobility.

[0138] In some embodiments of the present application, a method for controlling a pixel driving circuit is further provided. Figure 13 A flowchart of a method for controlling a pixel driving circuit according to an embodiment of the present invention is shown in FIG. Figure 13 As shown, the method includes the following steps:

[0139] S1301 , obtaining a preset duration for the driving transistor 10 in the pixel driving circuit to write an operating voltage to the light emitting control unit 60 corresponding to the driving transistor 10 .

[0140] Exemplarily, the preset duration for the driving transistor 10 to write the operating voltage to the light emitting control unit 60 can be used to determine the driving capability of the pixel driving circuit, and the driving capability of the pixel driving circuit corresponds to the refresh rate of the display module.

[0141] For example, when the refresh rate of the display module is high (i.e., high refresh), the driving capability of the pixel driving circuit is required to be high, and at this time, the preset time for the driving transistor 10 to write the working voltage to the light-emitting control unit 60 is required to be shorter; when the refresh rate of the display module is low (i.e., low refresh), the driving capability requirement of the pixel driving circuit is not high, and at this time, the preset time for the driving transistor 10 to write the working voltage to the light-emitting control unit 60 is required to be longer.

[0142] S1302: Determine the number of compensation times of the pixel driving circuit based on a preset time length.

[0143] In the embodiment of the present application, different preset time lengths when the pixel driving circuit writes the operating voltage correspond to different refresh conditions of the display module, and the stability corresponding to different refresh conditions and the charging requirement rate of the Data voltage are different. Therefore, in order to adapt to different refresh conditions, the pixel driving circuit needs to implement different compensation times to ensure the display effect.

[0144] Correspondingly, when the above refresh rate is low, the display is unstable. At this time, it is necessary to increase the compensation time of the pixel driving circuit. Since the charging requirement rate of the Data voltage is low, the number of compensations needs to be appropriately increased. When the above refresh rate is high, the display is stable. At this time, it is necessary to reduce the compensation time of the pixel driving circuit. Since the charging requirement rate of the Data voltage is high, the number of compensations needs to be appropriately reduced.

[0145] Exemplarily, when the preset duration is less than a preset threshold, the pixel driving circuit compensates at most once; wherein the preset threshold can be the critical value of the pixel driving circuit changing from the writing duration required to cope with the low refresh condition of the display module to the writing duration required to cope with the high refresh condition of the display module.

[0146] For example, the pixel driving circuit may be compensated once. Figure 14 A corresponding schematic diagram of the driving phase of the pixel driving circuit provided in the embodiment of the present application is shown in FIG. Figure 14 As shown in (a), when the preset time length is less than the preset threshold, the number of compensation times decreases. Therefore, during the display of one frame of image, the driving phase of the pixel driving circuit may include two light emitting control phases and one compensation phase.

[0147] Optionally, when the preset time length is greater than a preset threshold, the pixel driving circuit performs compensation at least twice.

[0148] For example, the pixel driving circuit may be compensated three times. Figure 14 As shown in (b), when the preset time length is greater than the preset threshold, the number of compensation times increases. Therefore, during the display process of one frame of image, the driving stage of the pixel driving circuit may include one light emitting control stage and three compensation stages.

[0149] S1303 , based on the number of compensation times, the pixel driving circuit writes the operating voltage to the light emitting control unit 60 corresponding to the driving transistor 10 .

[0150] In another embodiment of the present application, a computer device 1500 is provided. The computer device 1500 includes a central processing unit (CPU) 1501, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 1502 or programs loaded from a storage unit 1508 into a random access memory (RAM) 1503. The random access memory (RAM) 1503 also stores various programs and data required for the system's operating instructions. The central processing unit (CPU) 1501, the read-only memory (ROM) 1502, and the random access memory (RAM) 1503 are connected to each other via a bus 1504. An input / output (I / O) interface 1505 is also connected to the bus 1504.

[0151] The following components are connected to the input / output (I / O) interface 1505: an input section 1506 including a keyboard, mouse, and the like; an output section 1507 including components such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 1508 including components such as a hard disk; and a communication section 1509 including a network interface card such as a LAN card or a modem. The communication section 1509 performs communication processing via a network such as the Internet. A drive 1510 is also connected to the input / output (I / O) interface 1505 as needed. Removable media 1511, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 1510 as needed, so that computer programs read from the removable media can be installed in the storage section 1508 as needed.

[0152] In particular, according to the embodiment of the present application, the above reference flow chart Figure 13 The described processes can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for executing the method illustrated in the flowchart. In such an embodiment, the computer program contains program code for executing the method illustrated in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1509 and / or installed from removable media 1511. When the computer program is executed by the central processing unit (CPU) 1501, the aforementioned functions defined in the system of the present application are performed.

[0153] It should be noted that the computer-readable medium described herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium compatible with a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical cable, RF, or any suitable combination thereof.

[0154] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operating instructions of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the aforementioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than the order marked in the accompanying drawings. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operating instruction, or can be implemented using a combination of dedicated hardware and computer instructions.

[0155] The units or modules involved in the embodiments described in this application can be implemented by software or by hardware. The described units or modules can also be set in a processor. For example, it can be described as: a processor includes a semantic extraction unit, a weight allocation unit, and a determination unit. Among them, the names of these units or modules do not constitute a limitation on the units or modules themselves under certain circumstances.

[0156] As another aspect, the present application further provides a computer-readable storage medium, which may be included in the computer device described in the above embodiment, or may exist independently without being assembled into the computer device. The above computer-readable storage medium stores one or more programs, and when the above programs are used by one or more processors to execute the method described in the present application. For example, it can be executed Figure 13 The individual steps of the method are shown.

[0157] The present application embodiment provides a computer program product, which includes instructions. When the instructions are executed, the method described in the embodiment of the present application is executed. For example, you can execute Figure 13 The individual steps of the method are shown.

[0158] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features having similar functions disclosed in this application.

Claims

1. A pixel driving circuit, characterized in that: The device comprises a driving transistor, a first voltage writing unit, a data signal writing unit, a first compensation unit, a second compensation unit and a light emitting control unit. In response to a first control signal, the first voltage writing unit writes a first voltage into the control terminal of the driving transistor, the first voltage including the threshold voltage of the driving transistor; and in response to the first control signal, the first compensation unit stores a second voltage, the second voltage being the compensation voltage of the data signal writing unit; In response to a second control signal, the data signal writing unit writes a third voltage to the control terminal of the driving transistor through the first compensation unit; the third voltage includes the first voltage, the second voltage and the data voltage; In response to a third control signal, the second compensation unit stores a fourth voltage and writes the fourth voltage into the control terminal of the driving transistor; The driving transistor is further configured to write an operating voltage into a light emitting control unit corresponding to the driving transistor after the fourth voltage is written into the control terminal of the driving transistor.

2. The pixel driving circuit according to claim 1, wherein: The first voltage writing unit is connected to the first input end of the driving transistor, the data signal writing unit is connected to the first compensation unit, the first compensation unit is connected to the control end of the driving transistor, the second compensation unit is connected to the control end of the driving transistor, and the first input end of the driving transistor is connected to the light emitting control unit.

3. The pixel driving circuit according to claim 1 or 2, wherein: The first voltage writing unit includes a first transistor, a control terminal of the first transistor is used to receive the first control signal, a first input terminal of the first transistor is connected to the first input terminal of the driving transistor, and a voltage of a second input terminal of the first transistor is a source reference voltage. The first transistor is used to write the source reference voltage to the first input terminal of the driving transistor in response to the first control signal, so that the driving transistor is turned on when the source reference voltage is less than the initial voltage of the control terminal of the driving transistor and the control terminal voltage of the driving transistor includes the threshold voltage and the source reference voltage.

4. The pixel driving circuit according to claim 1 or 2, wherein: The first compensation unit includes a second transistor and a first capacitor, wherein a first input terminal of the second transistor is connected to the first capacitor, the first capacitor is connected to the control terminal of the driving transistor, and a voltage at a second input terminal of the second transistor is a negative voltage of the second voltage. The control terminal of the second transistor is configured to receive the first control signal and write the second voltage into the first capacitor in response to the first control signal.

5. The pixel driving circuit according to claim 1 or 2, wherein: The data signal writing unit includes a third transistor, a first input terminal of the third transistor is connected to the control terminal of the driving transistor through the first compensation unit, and a voltage at a second input terminal of the third transistor is the data voltage. The control terminal of the third transistor is used to receive the second control signal, and write a third voltage into the control terminal of the driving transistor through the first compensation unit in response to the first control signal.

6. The pixel driving circuit according to claim 1 or 2, characterized in that: The second compensation unit includes a fourth transistor and a second capacitor, the first input terminal of the fourth transistor is respectively connected to the first input terminal of the driving transistor and one end of the second capacitor, the second capacitor is connected to the control terminal of the driving transistor, the control terminal of the fourth transistor is used to receive the third control signal and write the fourth voltage to the second capacitor in response to the third control signal, wherein the fourth voltage is a negative voltage of the threshold voltage.

7. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a reset unit connected to the control terminal of the driving transistor. The reset unit is configured to write an initial voltage into the control terminal of the driving transistor in response to a fourth control signal.

8. The pixel driving circuit according to claim 7, wherein: The reset unit includes a fifth transistor, a first input terminal of the fifth transistor is connected to the control terminal of the driving transistor, a voltage at the second input terminal of the fifth transistor is the initial voltage, and the control terminal of the fifth transistor is used to receive the fourth control signal and write the initial voltage to the control terminal of the driving transistor in response to the fourth control signal.

9. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a signal generating unit, wherein an output terminal of the signal generating unit is connected to the control terminal of the driving transistor.

10. The pixel driving circuit according to claim 9, wherein: The signal generating unit includes a first clock signal, a second clock signal, a first off-voltage, and a second off-voltage, wherein the driving capability of the first clock signal is higher than the driving capability of the second clock signal, and the first off-voltage is lower than the second off-voltage; The signal generating unit is configured to turn on the first clock signal and the second off-voltage when the time for the driving transistor to write the operating voltage to the corresponding light emitting control unit is less than a preset threshold; The signal generating unit is further configured to turn on the second clock signal and the first off voltage when the time during which the driving transistor writes the operating voltage to the corresponding light emitting control unit is greater than a preset threshold.

11. The pixel driving circuit according to any one of claims 1 to 10, characterized in that: The transistors in the pixel driving circuit are N-type thin film transistors.

12. A method for controlling a pixel driving circuit, characterized in that: Applied to the pixel driving circuit according to any one of claims 1 to 11, the method comprising: Obtaining a preset duration for a driving transistor in the pixel driving circuit to write an operating voltage to a light emitting control unit corresponding to the driving transistor; Determining a compensation number of the pixel driving circuit based on the preset time length; Based on the compensation times, the pixel driving circuit writes the operating voltage into the light emitting control unit corresponding to the driving transistor.

13. The method for controlling a pixel driving circuit according to claim 12, wherein: The determining the number of compensation times of the pixel driving circuit based on the preset time length includes: When the preset time length is less than a preset threshold, the pixel driving circuit performs compensation at most once; When the preset time length is greater than a preset threshold, the pixel driving circuit performs compensation at least twice.

14. A display device, characterized in that: The display device comprises the pixel driving circuit according to any one of claims 1 to 11.

Images