Display substrate, manufacturing method and display device

Abstract

The invention provides a display substrate, a manufacturing method and a display device. The display substrate comprises a scanning driving circuit and a display area. The scanning driving circuit comprises a plurality of shifting register units, a first voltage signal line, a second voltage signal line, a first clock signal line and a second clock signal line. The first voltage signal line, the second voltage signal line, the first clock signal line and the second clock signal line extend along a first direction; the display area comprises at least one driving transistor, and the driving transistor is configured to drive a light-emitting element to display; at least one shift register unit in the plurality of shift register units comprises an output circuit and a signal output line; the output circuit is respectively coupled with the first voltage signal line, the second voltage signal line and the signal output line; the signal output line extends along a second direction, and the first direction intersects with the second direction; a transistor included in the output circuit is arranged between the first voltage signal line and the second voltage signal line.

Description

[0001] This application is a divisional application of the Chinese invention application with application date of March 16, 2020 and application number 202080000254.7. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display substrate, a manufacturing method and a display device. Background Art

[0003] Active-Matrix Organic Light-Emitting Diode (AMOLED) display panels are widely used in various fields due to their advantages such as low power consumption, low production cost, and wide color gamut.

[0004] The AMOLED display panel includes a pixel circuit located in the display area and a scan drive circuit located in the edge area. The pixel circuit includes a plurality of sub-pixel circuits distributed in an array. The scan drive circuit includes a plurality of shift register units, each of which is used to provide a light-emitting control signal for a corresponding sub-pixel circuit. Since the scan drive circuit is arranged in the edge area of ​​the AMOLED display panel, the arrangement of the scan drive circuit determines the border width of the AMOLED display panel. Summary of the invention

[0005] The main purpose of the present invention is to provide a display substrate, a manufacturing method and a display device.

[0006] In one aspect, an embodiment of the present invention provides a display substrate, comprising a scan drive circuit and a display area disposed on a substrate, wherein the scan drive circuit comprises a plurality of shift register units, and the scan drive circuit further comprises a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line; the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line extend along a first direction; the display area comprises at least one driving transistor, and the driving transistor is configured to drive a light-emitting element to display;

[0007] At least one shift register unit among the plurality of shift register units comprises an output circuit and a signal output line; the output circuit is coupled to the first voltage signal line, the second voltage signal line and the signal output line respectively; the signal output line extends along a second direction, and the first direction intersects with the second direction;

[0008] The output circuit includes a transistor disposed between the first voltage signal line and the second voltage signal line.

[0009] Optionally, the first voltage signal line provides a first voltage to the output circuit, and the second voltage signal line provides a second voltage to the output circuit, and the first voltage is higher than the second voltage.

[0010] Optionally, the signal output line is located between output circuits in adjacent shift register units.

[0011] Optionally, the first voltage signal line is located on a side of the second voltage signal line away from the display area.

[0012] Optionally, the output circuit includes an output transistor and an output reset transistor;

[0013] The output reset transistor and the output transistor are arranged along a first direction;

[0014] The first electrode of the output reset transistor is coupled to the first voltage signal line, and the first electrode of the output transistor is coupled to the second voltage signal line;

[0015] A second electrode of the output transistor and a second electrode of the output reset transistor are both coupled to the signal output line.

[0016] Optionally, the active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer;

[0017] The first semiconductor layer and the signal output line are arranged along a first direction.

[0018] Optionally, the gate of the output reset transistor includes at least one output reset gate pattern, the first electrode of the output reset transistor includes at least one first electrode pattern, and the second electrode of the output reset transistor includes at least one second electrode pattern;

[0019] The output reset gate pattern is located between the adjacent first electrode pattern and the second electrode pattern;

[0020] The second electrode pattern, the output reset gate pattern and the first electrode pattern all extend along a second direction;

[0021] The first direction intersects the second direction.

[0022] Optionally, the gate of the output transistor includes at least one output gate pattern, the first electrode of the output transistor includes at least one third electrode pattern, and the second electrode of the output transistor includes at least one fourth electrode pattern;

[0023] The output gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern;

[0024] The fourth electrode pattern, the output gate pattern and the third electrode pattern all extend along the second direction;

[0025] The first direction intersects the second direction;

[0026] The second electrode pattern in the output reset transistor that is closest to the gate of the output transistor is multiplexed as a fourth electrode pattern of the output transistor.

[0027] Optionally, the active layer of the output reset transistor includes at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each first channel portion is arranged between two adjacent first conductive portions;

[0028] The first channel portions correspond to the output reset gate patterns one by one, and the orthographic projection of each of the first channel portions on the substrate is located inside the orthographic projection of the corresponding output reset gate pattern on the substrate;

[0029] A portion of the first conductive portions in the output reset transistor corresponds to the first electrode pattern one by one, an orthographic projection of the first electrode pattern on the substrate and an orthographic projection of the corresponding first conductive portion on the substrate have a first overlapping area, and the first electrode pattern is coupled to the corresponding first conductive portion through at least one first via hole provided in the first overlapping area;

[0030] Another part of the first conductive portion in the output reset transistor corresponds one-to-one to the second electrode pattern, and an orthographic projection of the second electrode pattern on the substrate has a second overlapping area with an orthographic projection of the corresponding first conductive portion on the substrate, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via hole arranged in the second overlapping area.

[0031] Optionally, the active layer of the output transistor includes at least two second conductive portions arranged opposite to each other along the first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions;

[0032] The second channel portions correspond to the output gate patterns one by one, and the orthographic projection of each of the second channel portions on the substrate is located inside the orthographic projection of the corresponding output gate pattern on the substrate;

[0033] A part of the second conductive parts in the output transistor corresponds to the third electrode pattern one by one, an orthographic projection of the third electrode pattern on the substrate and an orthographic projection of the corresponding second conductive part on the substrate have a third overlapping area, and the third electrode pattern is coupled to the corresponding second conductive part through at least one third via hole arranged in the third overlapping area;

[0034] Another part of the second conductive part in the output transistor corresponds one-to-one to the fourth electrode pattern, and the orthographic projection of the fourth electrode pattern on the substrate has a fourth overlapping area with the orthographic projection of the corresponding second conductive part on the substrate, and the fourth electrode pattern is coupled to the corresponding second conductive part through at least one fourth via hole arranged in the fourth overlapping area.

[0035] Optionally, the number of the first voltage signal line is one;

[0036] The output circuit includes an output reset transistor; the at least one shift register unit also includes an output capacitor, a first transistor and a second capacitor connection transistor;

[0037] The first electrode of the output reset transistor, the first plate of the output capacitor, the first electrode of the first transistor and the first electrode of the second capacitor connection transistor are all coupled to the first voltage signal line.

[0038] Optionally, the display substrate further includes a third voltage signal line, and the first voltage signal line is located between the second voltage signal line and the third voltage signal line.

[0039] Optionally, the first electrode of the second capacitor-connected transistor is coupled to the signal line conductive connection portion through a fifth connection via, and the signal line conductive connection portion is coupled to the first voltage signal line, so that the first electrode of the second capacitor-connected transistor is coupled to the first voltage signal line;

[0040] The signal line conductive connection portion and the first voltage signal line are included in a source-drain metal layer, and the second capacitor is connected to a first electrode of a transistor included in an active layer.

[0041] Optionally, the at least one shift register unit further includes a first capacitor;

[0042] The orthographic projection of the signal line conductive connection portion on the substrate partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate.

[0043] Optionally, the orthographic projection of the first plate of the output capacitor on the substrate has a signal line overlapping area with the orthographic projection of the first voltage signal line on the substrate, and the first plate of the output capacitor is coupled to the first voltage signal line through at least one signal line via arranged in the signal line overlapping area.

[0044] Optionally, the at least one shift register unit further includes a first node control transistor and a second capacitor;

[0045] The gate of the first node control transistor is coupled to the second plate of the second capacitor;

[0046] The orthographic projection of the first electrode plate of the second capacitor on the substrate is within the orthographic projection of the second electrode plate of the second capacitor on the substrate;

[0047] The first electrode plate of the second capacitor is L-shaped;

[0048] The first plate of the second capacitor includes a second horizontal plate portion;

[0049] An orthographic projection of the gate of the first node control transistor on the substrate and an orthographic projection of the second horizontal plate portion on the substrate are arranged along a first direction.

[0050] Optionally, the scan drive circuit further includes a third voltage signal line; the third voltage signal line extends along the first direction; the third voltage signal line is located on a side of the first voltage signal line away from the second voltage signal line; the first node control transistor is located between the third voltage signal line and the first voltage signal line;

[0051] The first electrode plate of the second capacitor further includes a second vertical electrode plate portion coupled to the second horizontal electrode plate portion; an orthographic projection of the second vertical electrode plate portion on the substrate partially overlaps with an orthographic projection of the third voltage signal line on the substrate.

[0052] Optionally, the first clock signal line is located at a side of the third voltage signal line away from the first voltage signal line;

[0053] The output circuit includes an output transistor; the at least one shift register unit also includes a second conductive connection portion disposed between a gate of the output transistor and a second plate of the second capacitor; the second conductive connection portion is coupled to the gate of the output transistor and the second plate of the second capacitor, respectively;

[0054] The at least one shift register unit further includes a third conductive connection portion coupled to the second plate of the second capacitor;

[0055] The orthographic projection of the third conductive connection portion on the substrate and the orthographic projection of the first clock signal line on the substrate have a sixth overlapping area, and the first clock signal line is coupled to the first plate of the second capacitor through at least one sixth via hole arranged in the sixth overlapping area.

[0056] Optionally, the first node control transistor includes a second active pattern; the second active pattern is U-shaped;

[0057] The second active pattern includes a first first node control channel portion, a second first node control channel portion, a first first node control conductive portion coupled to the first first node control channel portion, and a second first node control conductive portion coupled to the second first node control channel portion;

[0058] The gate of the first node control transistor includes a first gate pattern and a second gate pattern coupled to each other;

[0059] The first gate pattern corresponds to the first first node control channel portion, and the second gate pattern corresponds to the second first node control channel portion;

[0060] The first first-node control conductive portion corresponds to the second electrode of the first-node control transistor, and the second first-node control conductive portion corresponds to the first electrode of the first-node control transistor.

[0061] Optionally, the at least one shift register unit further comprises a second node control transistor; the at least one shift register unit comprises a second capacitor connection transistor;

[0062] The second electrode of the second node control transistor is coupled to the second electrode of the first node control transistor via a fourth conductive connection portion;

[0063] The at least one shift register unit further comprises a fifth conductive connection portion coupled to the gate of the second capacitor-connected transistor; a seventh overlapping region exists between an orthographic projection of the fifth conductive connection portion on the substrate and an orthographic projection of the fourth conductive connection portion on the substrate;

[0064] The fifth conductive connection portion is coupled to the fourth conductive connection portion through a seventh via hole disposed in the seventh overlapping region.

[0065] Optionally, the scan driving circuit further includes a third voltage signal line; the third voltage signal line is located on a side of the first voltage signal line away from the second voltage signal line;

[0066] The first electrode of the first node control transistor is coupled to the sixth conductive connection portion; the gate of the second node control transistor is coupled to the seventh conductive connection portion;

[0067] There is an eighth overlapping region between the orthographic projection of the sixth conductive connection portion on the substrate and the orthographic projection of the seventh conductive connection portion on the substrate, and the sixth conductive connection portion is coupled to the seventh conductive connection portion through an eighth via hole disposed within the eighth overlapping region;

[0068] A first electrode of the second node control transistor is coupled to the third voltage signal line.

[0069] Optionally, the gate of the second node control transistor is also coupled to an eighth conductive connection portion; there is a ninth overlapping area between the orthographic projection of the eighth conductive connection portion on the substrate and the orthographic projection of the second clock signal line on the substrate, and the eighth conductive connection portion is coupled to the second clock signal line through a ninth via hole arranged in the ninth overlapping area.

[0070] Optionally, the scan driving circuit further includes a third voltage signal line; the third voltage signal line extends along the first direction;

[0071] The second clock signal line is arranged between the first clock signal line and the third voltage signal line; or the first clock signal line is arranged between the second clock signal line and the third voltage signal line.

[0072] Optionally, the at least one shift register unit further comprises an input transistor;

[0073] The first electrode of the input transistor is coupled to the input signal terminal;

[0074] The second electrode of the input transistor is coupled to the ninth conductive connection portion, and there is a tenth overlapping area between the orthographic projection of the ninth conductive connection portion on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate, and the ninth conductive connection portion is coupled to the second plate of the second capacitor through a tenth via hole arranged in the tenth overlapping area.

[0075] Optionally, the at least one shift register unit further includes a third node control transistor, a second capacitor connection transistor and an input transistor;

[0076] The gate of the third node control transistor is coupled to the first clock signal line;

[0077] The active layer of the input transistor, the active layer of the third node control transistor and the active layer of the second capacitor connection transistor are formed by a continuous third semiconductor layer;

[0078] The active layer of the input transistor comprises a first fifth conductive portion, a fifth channel portion and a second fifth conductive portion sequentially arranged along a first direction;

[0079] The second fifth conductive portion is multiplexed as the first sixth conductive portion;

[0080] The active layer of the third node control transistor includes a first sixth conductive portion, a sixth channel portion and a second sixth conductive portion sequentially arranged along the first direction;

[0081] The second sixth conductive portion is multiplexed as the first seventh conductive portion;

[0082] The active layer of the second capacitor connection transistor includes a first seventh conductive portion, a seventh channel portion and a second seventh conductive portion which are sequentially arranged along the first direction.

[0083] Optionally, the scan drive circuit further includes a third voltage signal line;

[0084] The third voltage signal line extends along the first direction;

[0085] The orthographic projection of the third voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate and the orthographic projection of the second clock signal line on the substrate are all located on a side of the orthographic projection of the shift register unit on the substrate away from the display area of ​​the display substrate.

[0086] Optionally, the scan drive circuit further includes a third voltage signal line; the at least one shift register unit further includes an output capacitor, a first capacitor, a second capacitor, a first transistor, a second transistor, a first capacitor connection transistor, a second capacitor connection transistor, a first node control transistor, a second node control transistor, an input transistor, and a third node control transistor;

[0087] The second electrode of the first transistor is coupled to the second plate of the output capacitor, the first electrode of the first transistor is coupled to the first voltage signal line, and the gate of the first transistor is coupled to the second electrode of the third node control transistor;

[0088] A first electrode of the second transistor is coupled to a first plate of the first capacitor, a second electrode of the second transistor is coupled to a second electrode of the first capacitor connection transistor, and a gate of the second transistor is coupled to a gate of the third node control transistor;

[0089] The gate of the first capacitor-connected transistor and the gate of the second capacitor-connected transistor are respectively coupled to the second plate of the first capacitor; the second electrode of the first capacitor-connected transistor is coupled to the first plate of the first capacitor; the first electrode of the first capacitor-connected transistor is coupled to the gate of the second transistor;

[0090] The first electrode of the second capacitor-connected transistor is coupled to the first voltage signal line; the gate of the second capacitor-connected transistor is coupled to the second electrode of the second node-controlled transistor; the second electrode of the second capacitor-connected transistor is coupled to the first electrode of the third node-controlled transistor;

[0091] The first electrode of the first node control transistor is coupled to the gate of the second node control transistor; the gate of the first node control transistor is coupled to the second plate of the second capacitor;

[0092] The second electrode of the second node control transistor is coupled to the second electrode of the first node control transistor; the gate of the second node control transistor is coupled to the second clock signal line; the first electrode of the second node control transistor is coupled to the third voltage signal line;

[0093] The gate of the input transistor is coupled to the gate of the second node control transistor; the first electrode of the input transistor is coupled to the input signal terminal; the second electrode of the input transistor is coupled to the second plate of the second capacitor;

[0094] The gate of the third node control transistor is coupled to the first clock signal line;

[0095] The first plate of the output capacitor is coupled to the first voltage signal line, and the second plate of the output capacitor is coupled to the gate of the output reset transistor;

[0096] The second plate of the second capacitor is coupled to the gate of the output transistor, and the first plate of the second capacitor is coupled to the first clock signal line;

[0097] A second electrode of the output transistor and a second electrode of the output reset transistor are both coupled to the signal output line.

[0098] Optionally, along the direction close to the display area, the first clock signal line, the second clock signal line and the third voltage signal line are arranged in sequence; or, along the direction close to the display area, the second clock signal line, the first clock signal line and the third voltage signal line are arranged in sequence.

[0099] Optionally, the first electrode plate of the first capacitor includes a first horizontal electrode plate portion and a first vertical electrode plate portion;

[0100] The output transistor and the output reset transistor are arranged between the first voltage signal line and the second voltage signal line; along the first direction, the output reset transistor, the output transistor and the signal output line are arranged in sequence;

[0101] The third voltage signal line is arranged on a side of the first voltage signal line away from the second voltage signal line; the first capacitor, the first transistor, the second transistor, the first capacitor connection transistor, the second capacitor connection transistor, the first node control transistor, the second node control transistor, the input transistor and the third node control transistor are all arranged between the first voltage signal line and the third voltage signal line;

[0102] The first transistor, the second transistor and the first vertical plate portion are arranged in sequence along a first direction, the input transistor, the third node control transistor, the second capacitor connection transistor and the first horizontal plate portion are arranged in sequence along the first direction, and the second node control transistor and the first node control transistor are arranged in sequence along the first direction;

[0103] The orthographic projection of the gate of the first capacitor connection transistor on the substrate is arranged between the orthographic projection of the second electrode plate of the first capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate;

[0104] The orthographic projection of the gate of the second transistor on the substrate is arranged between the orthographic projection of the gate of the third node control transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate;

[0105] The orthographic projection of the gate of the first node control transistor on the substrate is arranged between the orthographic projection of the third voltage signal line on the substrate and the orthographic projection of the first plate of the first capacitor on the substrate;

[0106] The minimum distance in the second direction between the orthographic projection of the gate of the first node control transistor on the substrate and the orthographic projection of the third voltage signal line on the substrate is greater than the minimum distance in the second direction between the orthographic projection of the gate of the second capacitor connection transistor on the substrate and the orthographic projection of the third voltage signal line on the substrate.

[0107] Optionally, the orthographic projection of the first electrode plate of the output capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate have a signal line overlapping area; the orthographic projection of the second electrode plate of the output capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate partially overlap;

[0108] The orthographic projection of the first electrode plate of the second capacitor on the substrate is within the orthographic projection of the second electrode plate of the second capacitor on the substrate; the first electrode plate of the second capacitor is L-shaped;

[0109] The first electrode plate of the second capacitor includes a second horizontal electrode plate portion and a second vertical electrode plate portion;

[0110] The gate of the first node control transistor and the second horizontal plate portion are arranged along a first direction;

[0111] An orthographic projection of the second vertical plate portion on the substrate partially overlaps with an orthographic projection of the third voltage signal line on the substrate.

[0112] Optionally, the display substrate further comprises a plurality of rows of pixel circuits disposed on the base; the pixel circuits comprise a light emitting control terminal;

[0113] The shift register unit included in the scanning driving circuit corresponds to the row pixel circuit one by one

[0114] The signal output line of the shift register unit is coupled to the light emitting control terminal of the corresponding row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control terminal of the corresponding row of pixel circuits.

[0115] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a display substrate, the method comprising manufacturing a scan drive circuit on a substrate, and manufacturing at least one drive transistor in a display area included in the display substrate; the drive transistor is configured to drive a light-emitting element for display;

[0116] The scan driving circuit comprises a plurality of shift register units, a first voltage signal line, a second voltage signal line, a first clock signal line and a second clock signal line, at least one shift register unit of the plurality of shift register units comprises an output circuit and a signal output line;

[0117] The method for manufacturing the display substrate further includes:

[0118] The transistor included in the output circuit is fabricated between the first voltage signal line and the second voltage signal line;

[0119] The first voltage signal line, the second voltage signal line, the first clock signal line and the second clock signal line are arranged to extend along a first direction, and the signal output line is arranged to extend along a second direction;

[0120] The first direction and the second direction intersect.

[0121] Optionally, the method for manufacturing a display substrate according to at least one embodiment of the present invention further includes:

[0122] The signal output line is arranged between output circuits in adjacent shift register units.

[0123] Optionally, the first voltage signal line is located on a side of the second voltage signal line away from the display area.

[0124] Optionally, the output circuit includes an output transistor and an output reset transistor, and the steps of manufacturing the transistor included in the output circuit specifically include:

[0125] forming a first semiconductor layer between the first voltage signal line and the second voltage signal line;

[0126] Manufacturing a first gate metal layer on a side of the first semiconductor layer facing away from the substrate, and performing a patterning process on the first gate metal layer to form a gate of the output transistor and a gate of the output reset transistor;

[0127] Using the gate of the output transistor and the gate of the output reset transistor as masks, the portion of the first semiconductor layer not covered by the gate is doped, so that the portion of the first semiconductor layer not covered by the gate is formed into a conductive portion, and the portion of the first semiconductor layer covered by the gate is formed into a channel portion.

[0128] Optionally, the manufacturing method of the display substrate further includes: providing a second gate metal layer on a side of the first gate metal layer facing away from the first semiconductor layer, and performing a patterning process on the second gate metal layer to form a signal output line extending along a second direction;

[0129] An orthographic projection of the first semiconductor layer on the substrate and an orthographic projection of the signal output line on the substrate are arranged along a first direction, and the first direction intersects with the second direction.

[0130] Optionally, the steps of manufacturing the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line specifically include:

[0131] A source-drain metal layer is formed on a side of the second gate metal layer facing away from the first gate metal layer, and the source-drain metal layer is patterned to form the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line.

[0132] Optionally, the number of the first voltage signal line is one; the output circuit includes an output reset transistor; the at least one shift register unit also includes an output capacitor, a first plate and a second capacitor connection transistor; the manufacturing method of the display substrate also includes:

[0133] The first electrode of the output reset transistor, the first plate of the output capacitor, the first electrode of the first transistor and the first electrode of the second capacitor connection transistor are arranged to be coupled to the first voltage signal line.

[0134] In a third aspect, an embodiment of the present invention further provides a display device, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0135] Figure 1 is a circuit diagram of at least one embodiment of at least one shift register unit included in the display substrate according to an embodiment of the present invention;

[0136] Figure 2A yes Figure 1 The working timing diagram of at least one embodiment of the shift register unit shown in FIG.

[0137] Figure 2B is a schematic diagram of area division of a display substrate according to at least one embodiment of the present invention;

[0138] Figure 2C is a schematic diagram of the connection relationship between the scan drive circuit and the pixel circuit included in the display substrate according to at least one embodiment of the present invention;

[0139] Figure 2D is a schematic diagram of a layout of a shift register unit provided by at least one embodiment of the present invention;

[0140] Figure 3 Another schematic diagram of the layout of a shift register unit provided by at least one embodiment of the present invention;

[0141] Figure 4 is a schematic diagram of an active layer in a shift register unit provided in at least one embodiment of the present invention;

[0142] Figure 5 is a schematic diagram of a first gate metal layer in a shift register unit provided by at least one embodiment of the present invention;

[0143] Figure 6 is a schematic diagram of a second gate metal layer in a shift register unit provided by at least one embodiment of the present invention;

[0144] Figure 7 is a schematic diagram of a via hole used in a shift register unit provided in at least one embodiment of the present invention;

[0145] Figure 8 A schematic diagram of a source-drain metal layer in a shift register unit provided by at least one embodiment of the present invention;

[0146] Fig. 9 is Figure 6Schematic diagram of the division of the plates of the capacitor based on the invention;

[0147] Fig. 10A is a schematic diagram of the distance between the orthographic projection of the first voltage signal line VGH on the substrate and the orthographic projection of the first third conductive portion 211 of the second semiconductor layer and serving as the first electrode S8 of the first transistor T8 on the substrate;

[0148] Fig. 10B is a schematic diagram of the distance between the orthographic projection of the first voltage signal line VGH on the substrate and the orthographic projection of the second third conductive portion 212 included in the second semiconductor layer and serving as the second electrode D8 of the first transistor T8 on the substrate;

[0149] Fig. 10C Schematic diagram of the distances between the orthographic projection of the gate G5 of T5 on the substrate, the orthographic projection of the gate G6 of T6 on the substrate, and the orthographic projection of the first voltage signal line VGH on the substrate. DETAILED DESCRIPTION

[0150] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0151] like Figure 1 As shown, the present invention provides a display substrate, the display substrate includes a scan drive circuit located in the edge area of ​​the display substrate, the scan drive circuit includes a first voltage signal line VGH, a second voltage signal line VGL1, a third voltage signal line VGL2, a first clock signal line CB, a second clock signal line CK and a signal output line EOUT; the scan drive circuit also includes a plurality of shift register units;

[0152] like Figure 1 As shown, at least one embodiment of at least one shift register unit among the plurality of shift register units includes an output reset transistor T9, an output transistor T10, an output capacitor C3, a first capacitor C1, a second capacitor C2, a first transistor T8, a second transistor T7, a first capacitor connection transistor T6, a second capacitor connection transistor T5, a first node control transistor T2, a second node control transistor T3, an input transistor T1, and a third node control transistor T4;

[0153] The gate G9 of the output reset transistor T9 is coupled to the second plate C3b of the output capacitor C3, and the first electrode S9 of the output reset transistor T9 is connected to the high voltage signal Vgh;

[0154] The gate G10 of the output transistor T10 is coupled to the second plate C2b of the second capacitor C2, and the first electrode S10 of the output transistor T10 is connected to the low voltage signal Vgl;

[0155] The second electrode D9 of the output reset transistor T9 and the second electrode D10 of the output transistor T10 are both coupled to the signal output line EOUT;

[0156] The second electrode D8 of the first transistor T8 is coupled to the second plate C3b of the output capacitor C3, the first electrode S8 of the first transistor T8 is connected to the high voltage signal Vgh, and the gate G8 of the first transistor T8 is coupled to the second electrode D4 of the third node control transistor T4;

[0157] The second electrode D7 of the second transistor T7 is coupled to the first plate C1a of the first capacitor C1, the first electrode S7 of the second transistor T7 is coupled to the second plate C3b of the output capacitor C3, and the gate G7 of the second transistor T7 is coupled to the gate G4 of the third node control transistor T4;

[0158] The gate G6 of the first capacitor-connected transistor T6 and the gate G5 of the second capacitor-connected transistor T5 are respectively coupled to the second plate C1b of the first capacitor C1; the second electrode D6 of the first capacitor-connected transistor T6 is coupled to the first plate C1a of the first capacitor C1; the first electrode S6 of the first capacitor-connected transistor T6 is coupled to the gate G7 of the second transistor T7;

[0159] The first electrode S5 of the second capacitor connection transistor T5 is coupled to the first voltage signal line VGH; the gate G5 of the second capacitor connection transistor T5 is coupled to the second electrode D3 of the second node control transistor T3; the second electrode D5 of the second capacitor connection transistor T5 is coupled to the first electrode S4 of the third node control transistor T4;

[0160] The first electrode S2 of the first node control transistor T2 is coupled to the gate G3 of the second node control transistor T3; the gate G2 of the first node control transistor T2 is coupled to the second plate C2b of the second capacitor C2;

[0161] The second electrode D3 of the second node control transistor T3 is coupled to the second electrode D2 of the first node control transistor T2; the gate G3 of the second node control transistor T3 is coupled to the second clock signal line CK; the first electrode S3 of the second node control transistor T3 is connected to the low voltage signal Vgl;

[0162] The gate G1 of the input transistor T1 is coupled to the gate G3 of the second node control transistor T3; the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1; the second electrode D1 of the input transistor T1 is coupled to the second plate C2b of the second capacitor C2;

[0163] The gate G4 of the third node control transistor T4 is coupled to the first clock signal line CB;

[0164] The first plate C3a of the output capacitor C3 is connected to the high voltage signal Vgh, and the second plate C3b of the output capacitor C3 is coupled to the gate G9 of the output reset transistor T9;

[0165] The second plate C2b of the second capacitor C2 is coupled to the gate G10 of the output transistor T10, and the first plate C2a of the second capacitor C2 is coupled to the first clock signal line CB.

[0166] exist Figure 1 In at least one embodiment of the shift register unit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0167] In an embodiment of the present invention, Figure 1 At least one embodiment of the shift register unit shown may be a light emitting control scan driving circuit, but is not limited thereto.

[0168] In at least one embodiment of the present invention, the first electrode of the transistor may be a source, and the second electrode of the transistor may be a drain; or the first electrode of the transistor may be a drain, and the second electrode of the transistor may be a source.

[0169] exist Figure 1 Among them, the node labeled N1 is the first node, the node labeled N2 is the second node, the node labeled N3 is the third node, and the node labeled N4 is the fourth node.

[0170] like Figure 2A As shown, the present invention is Figure 1 At least one embodiment of the shift register unit shown in FIG. 1 is in operation.

[0171] In the first stage P1, CK inputs a low level, T1 and T3 are turned on, and the turned-on T1 transmits the high level input signal provided by E1 to the first node N1, so that the potential of the first node N1 becomes a high level, so that T2, T8 and T10 are turned off; in addition, the turned-on T3 transmits Vgl to the second node N2, so that the level of the second node N2 becomes a low level, so T5 and T6 are turned on. Since CB inputs a high level, T7 is turned off; in addition, due to the energy storage effect of C3, the potential of the fourth node N4 can be kept at a high level, so that T9 is turned off; in the first stage P1, since T9 and T10 are both turned off, EOUT keeps outputting a low level;

[0172] In the second stage P2, CB inputs a low level, T4 and T7 are turned on; since CK inputs a high level, T1 and T3 are turned off; due to the energy storage effect of the first capacitor C1, the potential of the second node N2 can continue to maintain the low level of the previous stage, T5 and T6 are turned on, Vgh is transmitted to the first node N1 through the turned-on T5 and T4, so that the potential of the first node N1 continues to maintain the high level of the previous stage, so T2, T8 and T10 are turned off; in addition, the low level provided by CB is transmitted to the fourth node N4 through the turned-on T6 and T7, so that the potential of the fourth node N4 becomes a low level, so T9 is turned on, and EOUT outputs a high voltage signal Vgh;

[0173] In the third stage P3, CK inputs a low level, T1 and T3 are turned on; CB provides a high level, so T4 and T7 are turned off; due to the energy storage function of C3, the potential of the fourth node N4 can maintain the low level of the previous stage, so that T9 remains in the on state, and EOUT outputs a high voltage signal Vgh;

[0174] In the fourth stage P4, CK inputs a high level, T1 and T3 are turned off; CB inputs a low level, T4 and T7 are turned on; due to the energy storage effect of the second capacitor C2, the potential of the first node N1 remains at the high level of the previous stage, so that T2, T8 and T10 are turned off. Due to the energy storage effect of the first capacitor C1, the potential of the second node N2 continues to maintain the low level of the previous stage, so that T5 and T6 are turned on. In addition, the low voltage signal input by CB is transmitted to the fourth node N4 through the turned-on T6 and T7, so that the level of the fourth node N4 becomes a low level, T9 is turned on, and the turned-on T9 outputs a high voltage Vgh, and EOUT outputs a high voltage signal Vgh;

[0175] In the fifth stage P5, CK inputs a low voltage signal, T1 and T3 are turned on; CB inputs a high voltage signal, T4 and T7 are turned off. The turned-on T1 transmits the low-level input signal provided by E1 to the first node N1, so that the potential of the first node N1 becomes a low level, so T2, T8 and T10 are turned on; the turned-on T2 transmits the low-level second clock signal to the second node N2, so that the potential of the second node N2 can be further lowered, so the potential of the second node N2 continues to maintain the low level of the previous stage, so that T5 and T6 are turned on; in addition, the turned-on T8 transmits Vgh to the fourth node N4, so that the potential of the fourth node N4 becomes a high voltage, so T9 is turned off; the turned-on T10 outputs Vgl, and EOUT outputs a low voltage signal Vgl.

[0176] like Figure 2B As shown, the one labeled J1 is the display substrate, the one labeled A0 is the display area, the one labeled B1 is the first edge area, and the one labeled B2 is the second edge area.

[0177] A plurality of light emitting control lines, a plurality of gate lines and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the plurality of gate lines and the plurality of data lines may be arranged in the display area A0 of the display substrate J1;

[0178] A scan driving circuit may be provided in the first edge region B1 and / or the second edge region B2, wherein the scan driving circuit includes a plurality of shift register units;

[0179] The scan drive circuit includes a plurality of shift register units corresponding to the plurality of light-emitting control lines one by one, and a signal output line of each shift register unit is coupled to a corresponding light-emitting control line for providing a light-emitting control signal to the corresponding light-emitting control line.

[0180] In a specific implementation, one of the light emitting control lines is coupled to a light emitting control terminal of a corresponding row of pixel circuits.

[0181] Optionally, the display substrate further comprises a plurality of rows of pixel circuits disposed on the base; the pixel circuits comprise a light emitting control terminal;

[0182] The shift register unit included in the scanning driving circuit corresponds to the row pixel circuit one by one

[0183] The signal output line of the shift register unit is coupled to the light emitting control terminal of the corresponding row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control terminal of the corresponding row of pixel circuits.

[0184] In at least one embodiment of the present invention, the pixel circuit may be disposed in an effective display area of ​​the display substrate, and the scan driving circuit may be disposed in an edge area of ​​the display substrate.

[0185] like Figure 2C As shown, the unit labeled Y1 is a scan driving circuit, the unit labeled S11 is a first-stage shift register unit included in the scan driving circuit S1, the unit labeled S12 is a second-stage shift register unit included in the scan driving circuit S1, the unit labeled S1N-1 is an N-1th-stage shift register unit included in the scan driving circuit S1, and the unit labeled S1N is an Nth-stage shift register unit included in the scan driving circuit S1, where N is an integer greater than 3;

[0186] exist Figure 2C , the pixel circuit labeled R1 is the first row, the pixel circuit labeled R2 is the second row, the pixel circuit labeled RN-1 is the N-1th row, and the pixel circuit labeled RN is the Nth row;

[0187] S11 corresponds to R1, S12 corresponds to R2, S1N-1 corresponds to RN-1, and S1N corresponds to RN;

[0188] S11 provides a first row light control signal for R1, S12 provides a second row light control signal for R2, S1N-1 provides an N-1th row light control signal for R1N-1, and S1N provides an Nth row light control signal for R1N.

[0189] like Figure 2C As shown, in the edge area, the display substrate may further include a gate driving circuit, the gate driving circuit includes a multi-stage gate driving unit, the gate driving unit also corresponds to the pixel row one by one, and is used to provide a corresponding gate driving signal for the corresponding row of pixels;

[0190] exist Figure 2C In the figure, the gate driving circuit is labeled Y2, the gate driving circuit is labeled S21, the gate driving circuit includes a first row of gate driving units, the gate driving circuit is labeled S22, the gate driving circuit includes a second row of gate driving units, the gate driving circuit is labeled S2N-1, the gate driving circuit includes an N-1th row of gate driving units, and the gate driving circuit is labeled S2N, the gate driving circuit includes an Nth row of gate driving units.

[0191] like Figure 2D As shown, the first voltage signal line VGH provides a high voltage signal Vgh, the second voltage signal line VGL1 and the third voltage signal line VGL2 provide a low voltage signal Vgl, and the fourth voltage signal line VGH0 provides a high voltage signal Vgh;

[0192] like Figure 2DAs shown, ESTV, VGH0, VGL2, VGH, VGL1, CK and CB are arranged in a direction away from the display area; ESTV, VGH0, VGL2, VGH, VGL1, CK and CB extend in the first direction;

[0193] T8, T9 and T10 are arranged between VGL2 and VGH0, T9 and T10 are arranged along the first direction; T8 is arranged between T9 and VGL2;

[0194] T6, T7, C1, T1, T4 and T5 are set between VGH and VGL2;

[0195] C1 is set between VGL2 and T6; T4 is set between VGL2 and T6;

[0196] T7 and T6 are arranged in sequence along the first direction, and T1, T4 and T5 are arranged in sequence along the first direction;

[0197] T2 and T3 are arranged between VGL1 and VGH, and T3 and T2 are arranged in sequence along the first direction;

[0198] The orthographic projection of C3 on the substrate partially overlaps with the orthographic projection of VGH0 on the substrate, and the orthographic projection of C2 on the substrate partially overlaps with the orthographic projection of VGL1 on the substrate.

[0199] exist Figure 2D Among them, the line labeled ESTV is the starting signal line.

[0200] like Figure 2D As shown, D1 is multiplexed into D4, S4 is multiplexed into D5, and D6 is multiplexed into D7.

[0201] exist Figure 2D and Figure 3, the gate of T1 is marked with G1, the first electrode of T1 is marked with S1, and the second electrode of T1 is marked with D1; the gate of T2 is marked with G2, the first electrode of T2 is marked with S2, and the second electrode of T2 is marked with D2; the gate of T3 is marked with G3, the first electrode of T3 is marked with S3, and the second electrode of T3 is marked with D3; the gate of T4 is marked with G4, the first electrode of T4 is marked with S4, and the second electrode of T4 is marked with D4; the gate of T5 is marked with G5, the first electrode of T5 is marked with S5, and the second electrode of T5 is marked with D5; G6 is the gate of T6, S6 is the first electrode of T6, and D6 is the second electrode of T6; G7 is the gate of T7, S7 is the first electrode of T7, and D7 is the second electrode of T7; G8 is the gate of T8, S8 is the first electrode of T8, and D8 is the second electrode of T8; G9 is the gate of T9, S9 is the first electrode of T9, and D9 is the second electrode of T9; G10 is the gate of T10, S10 is the first electrode of T10, and D10 is the second electrode of T10.

[0202] exist Figure 2D Among them, the line labeled ESTV is the starting signal line.

[0203] Above Figure 2D In the layout of the gate drive circuit shown, due to the use of two signal lines providing high voltage signals, the signal line connection method is messy, the space between T10 in the n-th shift register unit and the output reset transistor in the n+1-th shift register unit is not fully utilized to set EOUT, and C1 does not fully utilize the space between the gate of T5 and the second conductive connection part, and C2 does not fully utilize the space between T2 and the adjacent next-stage shift register unit, resulting in a large lateral width of the shift register unit, which is not conducive to the development of a narrow frame of the display substrate.

[0204] Figure 2D The shift register unit shown may be an n-th stage shift register unit included in the scan driving circuit, where n is a positive integer.

[0205] Based on the above problems, the inventors of the present invention have found through research that the occupied area of ​​the shift register unit can be reduced by adjusting the layout of each transistor in the shift register unit, thereby reducing the border width of the display substrate.

[0206] exist Figure 3In the layout shown, the first voltage signal line VGH provides a high voltage signal Vgh, and the second voltage signal line VGL1 and the third voltage signal line VGL2 provide a low voltage signal Vgl; at least one embodiment of the present invention reduces one signal line providing a high voltage signal Vgh, and sets VGH between VGL1 and VGL2 to facilitate layout.

[0207] and Figure 2D compared to, Figure 3 At least one embodiment shown removes the fourth voltage signal line VGH0 , uses only the first voltage signal line VGH, the second voltage signal line VGL1 , and the third voltage signal line VGL2 , and places VGH between VGL1 and VGL2 .

[0208] like Figure 3 As shown, the first electrode S9 of the output reset transistor T9 is coupled to the first voltage signal line VGH, the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL1, the first electrode S8 of the first transistor T8 is coupled to the first voltage signal line VGH, the first electrode S5 of the second capacitor connection transistor T5 is coupled to the first voltage signal line VGH, the first electrode S3 of the second node control transistor T3 is coupled to the third voltage signal line VGL2, and the first plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH.

[0209] like Figure 3 As shown, when the shift register unit of the above structure is arranged in the edge area of ​​the display substrate, the second voltage signal line VGL1, the first voltage signal line VGH and the third voltage signal line VGL2 are arranged in sequence along the direction away from the display area of ​​the display substrate; the second voltage signal line VGL1, the first voltage signal line VGH and the third voltage signal line VGL2 all extend along the first direction;

[0210] Furthermore, a first clock signal line CB, a second clock signal line CK and a start signal line ESTV are provided on a side of the third voltage signal line VGL2 away from the first voltage signal line VGH; the first clock signal line CB, the second clock signal line CK and the start signal line ESTV are arranged in sequence along a second direction away from the display area; the first clock signal line CB, the second clock signal line CK and the start signal line ESTV all extend along the first direction;

[0211] The output reset transistor T9 and the output transistor T10 are arranged between the first voltage signal line VGH and the second voltage signal line VGL1; along the first direction, the output reset transistor T9, the output transistor T10 and the signal output line EOUT are arranged in sequence;

[0212] The first capacitor C1, the first transistor T8, the second transistor T7, the first capacitor connection transistor T6, the second capacitor connection transistor T5, the first node control transistor T2, the second node control transistor T3, the input transistor T1 and the third node control transistor T4 are all arranged between the first voltage signal line VGH and the third voltage signal line VGL2;

[0213] The first transistor T8, the second transistor T7 and the first capacitor C1 are arranged in sequence along the first direction, the input transistor T1, the third node control transistor T4, the second capacitor connection transistor T5 and the first capacitor C1 are arranged in sequence along the first direction, and the second node control transistor T3 and the first node control transistor T2 are arranged in sequence along the first direction;

[0214] The second transistor T7 and the third node control transistor T4 are arranged in sequence along the second direction;

[0215] The first capacitor-connected transistor T6 and the second capacitor-connected transistor T5 are arranged in sequence along the second direction;

[0216] The first transistor T8, the input transistor T1 and the second node control transistor T3 are arranged along a second direction;

[0217] Furthermore, the active pattern of the first node control transistor T2 is arranged in a U-shaped structure so that T2 forms a double-gate structure.

[0218] In at least one embodiment of the present invention, the input signal terminal of the first-stage shift register unit included in the scan driving circuit is coupled to the start signal line ESTV, and the input signal terminal is a terminal coupled to the first electrode S1 of the input transistor T1.

[0219] In at least one embodiment of the present invention, the first direction intersects with the second direction. For example, the first direction may be perpendicular to the second direction, but the present invention is not limited thereto.

[0220] Specifically, the angle at which the second direction intersects the first direction can be set according to actual needs. For example, the second direction is perpendicular to the first direction.

[0221] In at least one embodiment of the present invention, the position of the first clock signal line CB and the position of the second clock signal line CK can be swapped, but this is not limited to it.

[0222] For example, in Figure 3 In the layout shown, the first direction may be a vertical direction from top to bottom, and the second direction may be a horizontal direction from right to left, but the present invention is not limited thereto.

[0223] In actual operation, the signal line width will mainly affect the resistance. A wider signal line has a smaller resistance, which is conducive to signal stability. Among them, the first voltage signal line VGH, the second voltage signal line VGL1 and the third voltage signal line VGL2 provide a DC voltage, which is less affected by the line width. The first clock signal line CB and the second clock signal line CK provide a clock signal. When the potential of the clock signal is converted from a high voltage to a low voltage, the clock signal line with a small resistance is more likely to make the potential of the clock signal quickly reach a low voltage. Therefore, in at least one embodiment of the present invention, the line width of the first clock signal line CB and the line width of the second clock signal line are set to be wider.

[0224] like Figure 3 As shown, the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate have a signal line overlapping area; the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate partially overlap;

[0225] The orthographic projection of the first electrode plate C2a of the second capacitor C2 on the substrate is within the orthographic projection of the second electrode plate C2b of the second capacitor C2 on the substrate; the first electrode plate C2a of the second capacitor C2 is L-shaped;

[0226] Depend on Figure 3 It can be seen that the lateral portion of the first electrode plate of C2 is arranged between T2 in the n-th shift register unit and the second node control transistor in the n+1-th shift register unit, making full use of the space between T2 in the n-th shift register unit and the second node control transistor in the n+1-th shift register unit, and the lateral portion of the first electrode plate of C1 is located between the gate of T5 and the second conductive connection part L2, making full use of the space between the gate of T5 and the second conductive connection part L2.

[0227] In the present invention Figure 3In the layout shown, since the output reset transistor T9 is coupled to the first voltage signal line VGH and the output transistor T10 is coupled to the second voltage signal line VGL1, the output reset transistor T9 and the output transistor T10 are arranged between the first voltage signal line VGH and the second voltage signal line VGL1, and the space between T10 included in the n-th stage shift register unit and the output reset transistor included in the n+1-th stage shift register unit is fully utilized to set the signal output line EOUT, so that T9 and T10 are arranged between VGH and VGL1, and no other signal lines and components included in other transistors are arranged between the first voltage signal line VGH and the output circuit (the output circuit includes T9 and T10), and no other signal lines and components included in other transistors are arranged between the second voltage signal line VGL1 and the output circuit (the output circuit includes T9 and T10), the distance from VGH to T9 and T10 is narrowed, and the distance from VGL1 to T9 and T10 is narrowed, so that the lateral width of the shift register unit is reduced.

[0228] In at least one embodiment of the present invention, Figure 3 The shift register unit shown may be an n-th stage shift register unit included in the scan driving circuit, where n is a positive integer.

[0229] Furthermore, in the present invention Figure 3 In the layout shown, since the first electrode S8 of T8 is coupled to the first voltage signal line VGH, and the second electrode D8 of T8 is coupled to the second electrode plate C3b of the output capacitor C3, the closer T8 is to VGH and C3, the more reasonable the corresponding layout will be. At least one embodiment of the present invention sets T8 on the side of the first voltage signal line VGH away from the second voltage signal line VGL1, and sets T8 close to the adjacent previous shift register unit, so as to utilize the space between T8 in the nth shift register unit and the first transistor included in the n+1th shift register unit, and reduce the length of the signal line between the source of T8 and VGH, and reduce the length of the signal line between the drain of T8 and C3, so as to reduce the lateral width of the shift register unit. Figure 3 As shown, T7, T6 and C1 are all arranged in the space between T8 in the nth shift register unit and the first transistor included in the n+1th shift register unit, making full use of the space between T8 in the nth shift register unit and the first transistor included in the n+1th shift register unit.

[0230] Furthermore, the gate G5 of T5 is coupled to the second plate C1b of C1, and the second electrode D6 of T6 is coupled to the first plate C1a of the first capacitor C1. Then, the positions of T5 and T6 should be close to VGH, and the distance between T5 and T6 can be shortened to adjust the shape of C1. Figure 3As shown, at least one embodiment of the present invention sets the plate of the first capacitor C1 to be L-shaped. Figure 3 As shown, C2 makes full use of the extra space between T2 in the nth stage shift register unit and the second node control transistor in the n+1th stage shift register unit, and sets the plate of the second capacitor C2 to be L-shaped. By setting as above, the horizontal width of the shift register unit can be shortened to a certain extent, and the vertical height can be optimized.

[0231] like Figure 3 As shown, the display substrate according to at least one embodiment of the present invention comprises a scan drive circuit and a display area arranged on the substrate, the scan drive circuit comprises a plurality of shift register units; the scan drive circuit further comprises a first voltage signal line VGH, a second voltage signal line VGL1, a first clock signal line CB and a second clock signal line CK; the first voltage signal line VGH, the second voltage signal line VGL1, the first clock signal line CB and the second clock signal line CK extend along a first direction; the display area comprises at least one driving transistor, and the driving transistor is configured to drive a light emitting element for display;

[0232] At least one shift register unit among the plurality of shift register units comprises an output circuit O1 and a signal output line EOUT; the output circuit O1 is coupled to the first voltage signal line VGH, the second voltage signal line VGL1 and the signal output line EOUT respectively; the signal output line EOUT extends along a second direction, and the first direction intersects the second direction;

[0233] The output circuit O1 includes a transistor disposed between the first voltage signal line VGH and the second voltage signal line VGL1 .

[0234] The display substrate described in at least one embodiment of the present invention arranges the output circuit O1 between the first voltage signal line VGH and the second voltage signal line VGL1, so that in terms of spatial structure, the first voltage signal line VGH is arranged on the side of the output circuit O1 away from the display area, and no other signal lines and components included in other transistors are arranged between the first voltage signal line VGH and the output circuit O1, and the second voltage signal line VGL1 is arranged on the side of the output circuit O1 close to the display area, and no other signal lines and components included in other transistors are arranged between the second voltage signal line VGL1 and the output circuit O1. The distance from the first voltage signal line VGH to the output circuit O1 can be narrowed, and the distance from the second voltage signal line VGL1 to the output circuit O1 can be narrowed, so that the lateral width of the shift register unit is reduced.

[0235] In a specific implementation, the first voltage signal line VGH is located at a side of the second voltage signal line VGL1 away from the display area.

[0236] In at least one embodiment of the present invention, the first voltage signal line VGH provides a first voltage to the output circuit O1 , and the second voltage signal line VGL1 provides a second voltage to the output circuit O1 , and the first voltage is higher than the second voltage.

[0237] In a specific implementation, the first voltage may be a high voltage Vgh, and the second voltage may be a low voltage Vgl, but is not limited thereto.

[0238] Optionally, the output circuit may include an output transistor and an output reset transistor;

[0239] The output reset transistor and the output transistor are arranged along a first direction;

[0240] A first electrode of the output reset transistor is coupled to the first voltage signal line, and a first electrode of the output transistor is coupled to the second voltage signal line.

[0241] like Figure 3 As shown, the output circuit O1 includes an output reset transistor T9 and an output transistor T10;

[0242] The output reset transistor T9 and the output transistor T10 are arranged in sequence from top to bottom, the first electrode S9 of the output reset transistor T9 is coupled to the first voltage signal line VGH, and the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL1.

[0243] In at least one embodiment of the present invention, the second electrode of the output transistor and the second electrode of the output reset transistor are both coupled to the signal output line;

[0244] The signal output line is located between output circuits in adjacent shift register units.

[0245] In a specific implementation, the output transistor and the output reset transistor are both coupled to the signal output line, so the output transistor and the output reset transistor should be close to the signal output line. At least one embodiment of the present invention moves the signal output line down to between the output circuits in adjacent shift register units, thereby narrowing the lateral width of the shift register unit.

[0246] In at least one embodiment of the present invention, the output reset transistor T9 is used to provide an invalid light emitting control signal, and the output transistor T10 is used to provide a valid light emitting control signal.

[0247] In at least one embodiment of the present invention, the valid light-emitting control signal may be a voltage signal capable of turning on a light-emitting control transistor in a pixel circuit (the gate of the light-emitting control transistor is coupled to the light-emitting control line), and the invalid light-emitting control signal may be a voltage signal capable of turning off the light-emitting control transistor.

[0248] Specifically, the display area of ​​the display substrate includes multiple sub-pixels; at least one of the multiple sub-pixels includes a pixel driving circuit; the pixel driving circuit includes a driving transistor, a gate line, a light-emitting control line and a data line, and the driving transistor is configured to drive the light-emitting element for display; the scanning driving circuit includes multiple shift register units corresponding to multiple light-emitting control lines one by one, and the signal output line of each shift register unit is coupled to the corresponding light-emitting control line for providing a light-emitting control signal to the corresponding light-emitting control line.

[0249] In at least one embodiment of the present invention, the active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer;

[0250] The first semiconductor layer and the signal output line are arranged along a first direction.

[0251] In a specific implementation, the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer, but the present invention is not limited thereto.

[0252] In at least one embodiment of the present invention, the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer;

[0253] The active layer of the output reset transistor includes at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each of the first channel portions is arranged between two adjacent first conductive portions;

[0254] The active layer of the output transistor may include at least two second conductive portions arranged opposite to each other along the first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions;

[0255] The first conductive portion of the active layer of the output reset transistor that is closest to the active layer of the output transistor can be reused as the second conductive portion of the output transistor, which can further reduce the layout space of the output transistor and the output reset transistor, and is conducive to achieving a narrow frame of the display substrate.

[0256] like Figure 4As shown, the active layer of the output reset transistor T9 and the active layer of the output transistor T10 may be formed by a continuous first semiconductor layer 10;

[0257] The active layer of the output reset transistor T9 includes a first first conductive portion 111, a second first conductive portion 112 and a third first conductive portion 113 which are arranged opposite to each other along a first direction, and the active layer of the output reset transistor T9 also includes a first first channel portion 121 and a second first channel portion 122;

[0258] The first first channel portion 121 is disposed between the first first conductive portion 111 and the second first conductive portion 112 , and the second first channel portion 122 is disposed between the second first conductive portion 112 and the third first conductive portion 113 ;

[0259] The first conductive portion 113 is multiplexed as the first second conductive portion included in the active layer of the output transistor T10;

[0260] The active layer of the output transistor T10 further includes a second second conductive portion 132 and a third second conductive portion 133 which are arranged opposite to each other along the first direction, and the active layer of the output transistor T10 further includes a first second channel portion 141 and a second second channel portion 142;

[0261] The first second channel portion 141 is disposed between the first second conductive portion and the second second conductive portion 132 , and the second second channel portion 142 is disposed between the second second conductive portion 132 and the third second conductive portion 133 .

[0262] In the output reset transistor T9 and the output transistor T10, the conductive parts on both sides of the channel part of each transistor can correspond to the first electrode and the second electrode of the transistor respectively, or can be coupled to the first electrode of the transistor and the second electrode of the transistor respectively, so that T9 and T10 can be electrically connected through the third first conductive part 113.

[0263] When manufacturing the first semiconductor layer 11, illustratively, a first semiconductor material layer can be formed first, and then after forming the gate G9 of the output reset transistor T9 and the gate G10 of the output transistor T10, the gate G9 of the output reset transistor T9 and the gate G10 of the output transistor T10 are used as masks to dope the portion of the first semiconductor material layer not covered by the gates of each transistor, so that the portion of the first semiconductor material layer not covered by the gates of each transistor is formed as the conductive portion, and the portion of the first semiconductor material layer covered by each transistor is formed as the channel portion.

[0264] According to the specific structure of the above-mentioned display substrate, it can be known that in the display substrate described in at least one embodiment of the present invention, the output reset transistor T9 and the output transistor T10 in the shift register unit can be arranged along the first direction, thereby reducing the area occupied by the shift register unit in the second direction, thereby making the display substrate more in line with the development needs of narrow borders.

[0265] Specifically, the gate of the output reset transistor may include at least one output reset gate pattern, the first electrode of the output reset transistor includes at least one first electrode pattern, and the second electrode of the output reset transistor includes at least one second electrode pattern;

[0266] The output reset gate pattern is located between the adjacent first electrode pattern and the second electrode pattern;

[0267] The second electrode pattern, the output reset gate pattern and the first electrode pattern all extend along a second direction;

[0268] The first direction intersects the second direction.

[0269] Specifically, the gate of the output transistor may include at least two output gate patterns arranged along the first direction, the first electrode of the output transistor includes at least one third electrode pattern, and the second electrode of the output transistor includes at least one fourth electrode pattern;

[0270] The output gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern;

[0271] The fourth electrode pattern, the output gate pattern and the third electrode pattern all extend along the second direction;

[0272] The first direction intersects the second direction;

[0273] The second electrode pattern in the output reset transistor that is closest to the gate of the output transistor is multiplexed as a fourth electrode pattern of the output transistor.

[0274] In a specific implementation, the number of the output reset gate patterns, the number of the first electrode patterns, the number of the second electrode patterns, the number of the output gate patterns, the number of the third electrode patterns and the number of the fourth electrode patterns can be set according to actual needs. For example, Figure 5 and Figure 8As shown, the number of the output gate patterns and the number of the output reset gate patterns can be two, the number of the first electrode patterns and the number of the third electrode patterns can be one, and the number of the second electrode patterns and the number of the fourth electrode patterns can be two.

[0275] Furthermore, since the second electrode of the output transistor and the second electrode of the output reset transistor are both coupled to the signal output line, when laying out the output transistor and the output reset transistor, the second electrode pattern of the output reset transistor that is closest to the gate of the output transistor can be reused as the fourth electrode pattern of the output transistor. This can further reduce the layout space of the output transistor and the output reset transistor, which is conducive to achieving a narrow frame of the display substrate.

[0276] like Figure 3 and Figure 5 As shown, in some embodiments, the gate G9 of the output reset transistor T9 may include: a first output reset gate pattern G91 and a second output reset gate pattern G92;

[0277] The gate G10 of the output transistor T10 may include: a first output gate pattern G101 and a second output gate pattern G102;

[0278] The first output reset gate pattern G91, the second output reset gate pattern G92, the first output gate pattern G101 and the second output gate pattern G102 are arranged in sequence along a first direction;

[0279] The first output reset gate pattern G91, the second output reset gate pattern G92, the first output gate pattern G101 and the second output gate pattern G102 all extend along a second direction, and the second direction intersects the first direction;

[0280] The first output reset gate pattern G91 and the second output reset gate pattern G92 are coupled to each other, and the first output gate pattern G101 and the second output gate pattern G102 are coupled to each other;

[0281] like Figure 8 As shown, the second electrode D9 of the output reset transistor T9 includes a first second electrode pattern D91 and a second second electrode pattern D92;

[0282] D91, S9 and D92 are arranged in sequence along the first direction, and D91, S9 and D92 are all extended along the second direction, and S9 is coupled to the first voltage signal line VGH;

[0283] D92 is multiplexed as the first fourth electrode pattern in the second electrode D10 of the output transistor T10;

[0284] The second electrode D10 of the output transistor T10 further includes a second fourth electrode pattern D102;

[0285] D92, S10 and D102 are arranged in sequence along the first direction; S10 is coupled to the second voltage signal line VGL1;

[0286] like Figure 3 , Figure 5 , Figure 8 As shown, the orthographic projection of G91 on the substrate is set between the orthographic projection of D91 on the substrate and the orthographic projection of S9 on the substrate, the orthographic projection of G92 on the substrate is set between the orthographic projection of S9 on the substrate and the orthographic projection of D92 on the substrate, the orthographic projection of G101 on the substrate is between the orthographic projection of D92 on the substrate and the orthographic projection of S10 on the substrate, and the orthographic projection of G102 on the substrate is between the orthographic projection of S10 on the substrate and the orthographic projection of D102 on the substrate.

[0287] In at least one embodiment of the present invention, when at least one shift register unit included in the scan drive circuit is in operation, when T10 is turned on, the shift register unit continuously outputs a low voltage signal. In order to keep the voltage signal connected to the gate of T10 stable, the gate G10 of T10 should be prevented from overlapping with the clock signal line. Here, G10 is set to overlap with the second voltage signal line VGL1 (VGL1 is a DC voltage signal line), which minimizes the impact on the voltage signal connected to the gate G10 of T10.

[0288] In a specific implementation, the active layer of the output reset transistor may include at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each first channel portion is arranged between two adjacent first conductive portions;

[0289] The first channel portions correspond to the output reset gate patterns one by one, and the orthographic projection of each of the first channel portions on the substrate is located inside the orthographic projection of the corresponding output reset gate pattern on the substrate;

[0290] A portion of the first conductive portions in the output reset transistor corresponds to the first electrode pattern one by one, an orthographic projection of the first electrode pattern on the substrate and an orthographic projection of the corresponding first conductive portion on the substrate have a first overlapping area, and the first electrode pattern is coupled to the corresponding first conductive portion through at least one first via hole provided in the first overlapping area;

[0291] Another part of the first conductive portion in the output reset transistor corresponds one-to-one to the second electrode pattern, and an orthographic projection of the second electrode pattern on the substrate has a second overlapping area with an orthographic projection of the corresponding first conductive portion on the substrate, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via hole arranged in the second overlapping area.

[0292] In a specific implementation, the active layer of the output transistor may include at least two second conductive portions arranged opposite to each other along the first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions;

[0293] The second channel portions correspond to the output gate patterns one by one, and the orthographic projection of each of the second channel portions on the substrate is located inside the orthographic projection of the corresponding output gate pattern on the substrate;

[0294] A part of the second conductive parts in the output transistor corresponds to the third electrode pattern one by one, an orthographic projection of the third electrode pattern on the substrate and an orthographic projection of the corresponding second conductive part on the substrate have a third overlapping area, and the third electrode pattern is coupled to the corresponding second conductive part through at least one third via hole arranged in the third overlapping area;

[0295] Another part of the second conductive part in the output transistor corresponds one-to-one to the fourth electrode pattern, and the orthographic projection of the fourth electrode pattern on the substrate has a fourth overlapping area with the orthographic projection of the corresponding second conductive part on the substrate, and the fourth electrode pattern is coupled to the corresponding second conductive part through at least one fourth via hole arranged in the fourth overlapping area.

[0296] like Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, the first first channel portion 121 corresponds to the first output reset gate pattern G91, and the second first channel portion 122 corresponds to the second output reset gate pattern G92;

[0297] The orthographic projection of the first first channel portion 121 on the substrate is located inside the orthographic projection of G91 on the substrate;

[0298] The orthographic projection of the second first channel portion 122 on the substrate is located inside the orthographic projection of G92 on the substrate;

[0299] The first first conductive portion 111 corresponds to the first second electrode pattern D91, the second first conductive portion 112 corresponds to the first electrode S9 of the output reset transistor, and the third first conductive portion 113 corresponds to the second second electrode pattern D92;

[0300] The orthographic projection of S9 on the substrate has a first overlapping region with the orthographic projection of the second first conductive portion 112 on the substrate, and S9 is coupled to the second first conductive portion 112 via at least one first via H1 disposed in the first overlapping region;

[0301] The orthographic projection of D91 on the substrate has a first second overlapping region with the orthographic projection of the first first conductive portion 111 on the substrate, and D91 is coupled to the first first conductive portion 111 through at least one second via H2 disposed in the first second overlapping region;

[0302] The orthographic projection of D92 on the substrate has a second second overlapping region with the orthographic projection of the third first conductive portion 113 on the substrate, and D92 is coupled to the third first conductive portion 113 through at least one second via H2 disposed in the second second overlapping region;

[0303] The first second channel portion 141 corresponds to the first output gate pattern G101, and the second second channel portion 142 corresponds to the second output gate pattern G102;

[0304] The orthographic projection of the first second channel portion 141 on the substrate is located inside the orthographic projection of G101 on the substrate;

[0305] The orthographic projection of the second second channel portion 142 on the substrate is located inside the orthographic projection of G102 on the substrate;

[0306] D92 is multiplexed into the first fourth electrode pattern; the third first conductive portion 113 is multiplexed into the first second conductive portion;

[0307] The first second conductive portion corresponds to the first fourth electrode pattern;

[0308] The second second conductive portion 132 corresponds to the first electrode S10 of the output transistor, and the third second conductive portion 133 corresponds to the second fourth electrode pattern D102;

[0309] The orthographic projection of S10 on the substrate has a third overlapping region with the orthographic projection of the second second conductive portion 132 on the substrate, and S10 is coupled to the second second conductive portion 132 via at least one third via H3 disposed in the third overlapping region;

[0310] The orthographic projection of D102 on the substrate has a fourth overlapping region with the orthographic projection of the third second conductive portion 133 on the substrate, and D102 is coupled to the third second conductive portion 133 via at least one fourth via H4 disposed in the fourth overlapping region.

[0311] In at least one embodiment of the present invention, the number of the first via holes, the number of the second via holes, the number of the third via holes, and the number of the fourth via holes can be set according to actual needs.

[0312] In the display substrate provided by the above embodiment, the first semiconductor layer 10 is used to form the active layer of the output reset transistor T9 and the active layer of the output transistor T10, which not only makes the space occupied by T9 and T10 smaller in the second direction, but also can ensure the channel width of T9 and the channel width of T10 by increasing the size of the active layer of the output reset transistor T9 and the active layer of the output transistor T10 in the first direction, thereby achieving the reduction of the border width of the display substrate while ensuring the working performance of T9 and the working performance of T10.

[0313] like Figure 3 , Figure 4 and Figure 6 As shown, the orthographic projection of the signal output line EOUT on the substrate is between the orthographic projection of the first semiconductor layer 10 in the n-th shift register unit on the substrate and the orthographic projection of the first semiconductor layer in the n+1-th shift register unit on the substrate, and the first semiconductor layer 10 and the signal output line EOUT are arranged along the first direction, which can narrow the lateral width of the shift register unit.

[0314] In at least one embodiment of the present invention, Figure 4 yes Figure 3 Schematic diagram of the active layer in Figure 5 yes Figure 3 Schematic diagram of the first gate metal layer in FIG. Figure 6 yes Figure 3 Schematic diagram of the second gate metal layer in FIG. Figure 7 is a schematic diagram of a via hole made after the active layer, the first gate metal layer and the second gate metal layer are sequentially arranged. Figure 8 yes Figure 3 Schematic diagram of the source and drain metal layers in .

[0315] In a specific implementation, an active layer, a first gate metal layer, a second gate metal layer, a via hole and a source-drain metal layer are sequentially arranged on a substrate to form a display substrate.

[0316] In at least one embodiment of the present invention, the at least one shift register unit may include a plurality of transistors in addition to an output transistor and an output reset transistor; the conductive portions on both sides of the channel portion of each transistor may correspond to the first electrode and the second electrode of the transistor, respectively, or may be coupled to the first electrode of the transistor and the second electrode of the transistor, respectively.

[0317] In at least one embodiment of the present invention, Figure 3 As shown, the number of the first voltage signal line VGH may be one;

[0318] like Figure 1 and Figure 3 As shown, the output circuit includes an output reset transistor T9; the at least one shift register unit also includes an output capacitor C3, a first transistor T8 and a second capacitor connection transistor T5;

[0319] The first electrode of the output reset transistor T9, the first plate of the output capacitor C3, the first electrode of the first transistor T8 and the first electrode of the second capacitor connection transistor T5 are all coupled to the first voltage signal line VGH, so that each transistor included in the shift register unit is coupled to the same first voltage signal line VGH, reducing the number of signal lines used.

[0320] In at least one embodiment of the present invention, VGH is set between VGL1 and VGL2 so that the first voltage signal line VGH can simultaneously provide a first voltage signal to the first electrode of the second capacitor connection transistor T5 and the first electrode of the first transistor T8, and the first voltage signal line VGH can charge the first plate of the output capacitor C3.

[0321] like Figure 3 As shown, the display substrate further includes a third voltage signal line VGL2, and the first voltage signal line VGH is located between the second voltage signal line VGL1 and the third voltage signal line VGL3.

[0322] like Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the first electrode S5 of the second capacitor-connected transistor T5 is coupled to the signal line conductive connection portion L40 through the fifth connection via H85, and the signal line conductive connection portion L40 is coupled to the first voltage signal line VGH, so that the first electrode S5 of the second capacitor-connected transistor T5 is coupled to the first voltage signal line VGH;

[0323] The signal line conductive connection portion L40 and the first voltage signal line VGH are included in a source-drain metal layer, and the second capacitor is connected to the first electrode S5 of the transistor T5 and is included in an active layer.

[0324] like Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the at least one shift register unit further includes a first capacitor C1;

[0325] The orthographic projection of the signal line conductive connection portion L40 on the substrate partially overlaps with the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate.

[0326] like Figure 3 , Figure 6 and Figure 7 As shown, the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate has a signal line overlap region with the orthographic projection of the first voltage signal line VGH on the substrate, and the first plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH through at least one signal line via H01 provided in the signal line overlap region. In at least one embodiment of the present invention, as shown in FIG2 , the at least one shift register unit may further include an output capacitor C3 and a first transistor T8;

[0327] like Figure 3 , Figure 6 and Figure 7 As shown, the orthographic projection of the first electrode plate C3a of the output capacitor C3 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate have a signal line overlapping area, and the first electrode plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH through at least one signal line via H01 arranged in the signal line overlapping area;

[0328] The first transistor T8 is located on a side of the first voltage signal line VGH away from the output reset transistor T9;

[0329] like Figure 8 As shown, the at least one shift register unit further includes a plate conductive connection portion 71 coupled to the second electrode D8 of the first transistor T8;

[0330] like Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the second electrode D8 of the first transistor T8 is coupled to the plate conductive connection portion 71 through the first connection via H81;

[0331] like Figure 3 , Figure 5 , Figure 7 and Figure 8 As shown, the orthographic projection of the plate conductive connection portion 71 on the substrate and the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate have a plate overlapping region, and the plate conductive connection portion 71 is coupled to the second plate C3b of the output capacitor C3 through at least one plate via H02 provided in the plate overlapping region;

[0332] A first electrode S8 of the first transistor T8 is coupled to the first voltage signal line VGH.

[0333] In specific implementation, Figure 7 As shown, the first electrode S8 of the first transistor T8 is coupled to the first voltage signal line VGH through the second connecting via H82.

[0334] In at least one embodiment of the present invention, T8 is moved to a side of the first voltage signal line VGH away from the second voltage signal line VGL1, and the orthographic projection of the plate of the output capacitor C3 on the substrate is set to partially overlap with the orthographic projection of the first voltage signal line VGH on the substrate, so as to reduce the distance between the first electrode S8 of the first transistor T8 and the first voltage signal line VGH, and reduce the distance between the second electrode D8 of the first transistor T8 and the second plate C3b of the output capacitor C3, so that T8 can be conveniently coupled to the first voltage signal line VGH and the second plate C3b of the output capacitor C3, respectively, so that the space is compact and the layout is more reasonable.

[0335] In a preferred case, a maximum distance in the second direction between an orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and an orthographic projection of the first voltage signal line VGH on the substrate is less than a first predetermined distance, and a maximum distance in the second direction between an orthographic projection of the second electrode D8 of the first transistor T8 on the substrate and an orthographic projection of the second electrode plate C3b of the output capacitor C3 on the substrate is less than a second predetermined distance, so that the first transistor T8 is close to the first voltage signal line VGH and the output capacitor C3, shortening the lateral width of the shift register unit, and facilitating the realization of a narrow frame.

[0336] In at least one embodiment of the present invention, the first predetermined distance and the second predetermined distance can be selected according to actual conditions. For example, the first predetermined distance can be greater than or equal to 20um (micrometers) and less than or equal to 30um, and the second predetermined distance can be greater than or equal to 25um (micrometers) and less than or equal to 35um.

[0337] In at least one embodiment of the present invention, S8 and D8 are arranged in the active layer, such as Figure 4As shown, the first third conductive portion 211 is used as the first electrode S8 of the first transistor T8, and the second third conductive portion 212 is used as the second electrode D8 of the first transistor T8.

[0338] In at least one embodiment of the present invention, the maximum distance in the second direction between the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate refers to: the maximum distance along the second direction between any point on the edge line of the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and the edge line of the orthographic projection of the first voltage signal line VGH on the substrate;

[0339] The maximum distance in the second direction between the orthographic projection of the second electrode D8 of the first transistor T8 on the substrate and the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate refers to: the maximum distance along the second direction between any point on the edge line of the orthographic projection of the second electrode D8 of the first transistor T8 on the substrate and the edge line of the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate.

[0340] exist Fig. 10A In the Figure 4 The orthographic projection of the second semiconductor layer (the second semiconductor layer includes the first third conductive portion 211 and the second third conductive portion 212) on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate;

[0341] exist Fig. 10B In the Figure 4 The orthographic projection of the second semiconductor layer (the second semiconductor layer includes the first third conductive portion 211 and the second third conductive portion 212) on the substrate and the orthographic projection of the second electrode plate of the output capacitor C3 on the substrate;

[0342] exist Fig. 10A and Fig. 10B In the figure, X1 is the edge line of the positive projection of the first electrode S8 of the first transistor T8 on the substrate, X2 is the edge line of the positive projection of the first voltage signal line VGH on the substrate, X3 is the edge line of the positive projection of the second electrode D8 of the first transistor T8 on the substrate, and X4 is the edge line of the positive projection of the second plate C3b of the output capacitor C3 on the substrate.

[0343] exist Fig. 10A In the figure, the distance d1 is the maximum distance in the second direction between the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate.

[0344] exist Fig. 10B In the figure, the distance labeled d2 is the maximum distance in the second direction between the orthographic projection of the second electrode D8 of the first transistor T8 on the substrate and the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate.

[0345] Specifically, Figure 5 As shown, the gate G9 of the output reset transistor T9 includes a first output reset gate pattern G91 and a second output reset gate pattern G92 coupled to the second plate C3b of the output capacitor C3;

[0346] like Figure 3 and Figure 6 As shown, the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate.

[0347] In a specific implementation, the display substrate may further include a third voltage signal line; the third voltage signal line is located at a side of the first transistor away from the first voltage signal line;

[0348] The third voltage signal line extends along a first direction.

[0349] In at least one embodiment of the present invention, the third voltage signal line may be a low voltage signal line, and the low voltage provided by the third voltage signal line may be the same as the low voltage provided by the first voltage signal line, but is not limited thereto.

[0350] Specifically, the first transistor may be disposed between the first voltage signal line and the third voltage signal line.

[0351] In at least one embodiment of the present invention, Figure 3 As shown, the at least one shift register unit may further include a second transistor T7;

[0352] like Figure 4 As shown, the active layer of the first transistor T8 and the active layer of the second transistor T7 are formed by a continuous second semiconductor layer 20; the second semiconductor layer 20 extends along the first direction;

[0353] The active layer of the first transistor T8 includes a first third conductive portion 211, a third channel portion 221 and a second third conductive portion 212 sequentially arranged along the first direction;

[0354] The second third conductive portion 212 is multiplexed as the first fourth conductive portion;

[0355] The active layer of the second transistor T7 includes the first fourth conductive portion, the fourth channel portion 241 and the second fourth conductive portion 232 sequentially arranged along the first direction;

[0356] like Figure 3 and Figure 8 As shown, the second electrode D8 of the first transistor T8 is multiplexed as the first electrode S7 of the second transistor T7.

[0357] In at least one embodiment of the present invention, the first third conductive portion 211 is used as the first electrode S8 of the first transistor T8, the second third conductive portion 212 is used as the second electrode D8 of the first transistor T8; the second fourth conductive portion 232 is used as the second electrode D7 of the second transistor T7.

[0358] In at least one embodiment of the present invention, T7 is disposed between T8 and C1, and the second electrode S8 of T8 is reused as the second electrode of T7, so as to reduce the vertical height of the shift register unit while narrowing the horizontal width of the shift register unit.

[0359] Optionally, the at least one shift register unit may further include a first capacitor, and a transistor coupled to a second plate of the first capacitor;

[0360] The first capacitor and the transistor coupled to the second plate of the first capacitor are both arranged on a side of the first voltage signal line away from the second voltage signal line;

[0361] A maximum distance in the second direction between an orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor and an orthographic projection of the first voltage signal line on the substrate is smaller than a third predetermined distance.

[0362] In a specific implementation, since the transistor coupled to the second plate of the first capacitor is also coupled to the first voltage signal line, the position of the transistor coupled to the second plate of the first capacitor is preferably close to the first voltage signal line. At least one embodiment of the present invention sets the maximum distance in the second direction between the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate to be less than the third predetermined distance, so as to narrow the lateral width of the shift register unit.

[0363] In at least one embodiment of the present invention, the third predetermined distance may be selected according to actual conditions. For example, the third predetermined distance is greater than or equal to 30 um (micrometers) and less than or equal to 40 um.

[0364] In at least one embodiment of the present invention, the maximum distance in the second direction between the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor and the orthographic projection of the first voltage signal line on the substrate refers to: the maximum distance along the second direction between any point on the edge line of the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate and the edge line of the orthographic projection of the first voltage signal line on the substrate.

[0365] Specifically, Figure 1 and Figure 3 As shown, the transistor coupled to the second plate C1b of the first capacitor C1 may include a first capacitor connection transistor T6 and a second capacitor connection transistor T5;

[0366] like Figure 3 and Figure 5 As shown, the gate G6 of the first capacitor-connected transistor T6 and the gate G5 of the second capacitor-connected transistor T5 are respectively coupled to the second plate C1b of the first capacitor C1;

[0367] like Figure 3 , Figure 7 and Figure 8 As shown, the at least one shift register unit also includes a first conductive connection portion L1 coupled to the second electrode D6 of the first capacitor-connected transistor T6, and there is a fifth overlapping area between the orthographic projection of the first conductive connection portion L1 on the substrate and the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate, and the first conductive connection portion L1 is coupled to the first electrode plate C1a of the first capacitor C1 through at least one fifth via H5 arranged in the fifth overlapping area.

[0368] In at least one embodiment of the present invention, the second electrode D6 of the first capacitor connection transistor T6 is coupled to the first conductive connection portion L1 through a third connection via H83 .

[0369] Optionally, the first conductive connection portion L1 may be L-shaped, but is not limited thereto.

[0370] exist Fig. 10C In the figure, only the orthographic projections of the gate G5 of T5, the gate G6 of T6, the second electrode plate C1b of C1 and the fifth conductive connection portion L5 on the substrate, and the orthographic projection of the first voltage signal line VGH on the substrate are shown;

[0371] exist Fig. 10C In the figure, X2 is the edge line of the positive projection of the first voltage signal line VGH on the substrate, X5 is the edge line of the positive projection of G5 on the substrate, and X6 is the edge line of the positive projection of G5 on the substrate;

[0372] like Fig. 10C As shown, d3 is the maximum distance between the orthographic projection of the gate G5 of T5 on the substrate and the orthographic projection of VGH on the substrate in the second direction;

[0373] The reference d4 is the maximum distance in the second direction between the orthographic projection of the gate G6 of T6 on the substrate and the orthographic projection of VGH on the substrate.

[0374] In at least one embodiment of the present invention, Figure 1 and Figure 3 As shown, the at least one shift register unit may further include a second transistor T7;

[0375] like Figure 3 , Figure 5 , Figure 7 and Figure 8 As shown, the at least one shift register unit further includes a gate connection conductive portion 51 coupled to the gate G7 of the second transistor T7, and a first electrode connection conductive portion 52 coupled to the first electrode S6 of the first capacitor connection transistor T6;

[0376] There is a connection overlap region between the gate connection conductive portion 51 and the first electrode connection conductive portion 52;

[0377] The gate connection conductive portion 51 is coupled to the first electrode connection conductive portion 52 through the electrode connection via H05 provided in the connection overlap region, so that the gate G7 of the second transistor T7 is coupled to the first electrode S6 of the first capacitor connection transistor T6.

[0378] In at least one embodiment of the present invention, the first electrode S6 of the first capacitor connection transistor T6 is coupled to the first electrode connection conductive portion 52 through a fourth connection via H84;

[0379] The second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1 .

[0380] Specifically, Figure 3 As shown, the first electrode S5 of the second capacitor connection transistor T5 can be coupled to the first voltage signal line VGH;

[0381] like Figure 3 and Fig. 10CAs shown, a maximum distance d32 in the second direction between an orthographic projection of the gate G6 of the first capacitor-connected transistor T6 on the substrate and an orthographic projection of the first voltage signal line VGH on the substrate is smaller than a maximum distance d31 in the second direction between an orthographic projection of the gate of the second capacitor-connected transistor T5 on the substrate and an orthographic projection of the first voltage signal line VGH on the substrate, that is, T5 is arranged on the side of T6 away from the first voltage signal line VGH.

[0382] In at least one embodiment of the present invention, Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the first electrode S5 of the second capacitor connection transistor T5 is coupled to the signal line conductive connection part L40 through the fifth connection via H85, and the signal line conductive connection part L40 is coupled to the first voltage signal line VGH, so that the first electrode S5 of the second capacitor connection transistor T5 is coupled to the first voltage signal line VGH.

[0383] Optionally, the signal line conductive connecting portion L40 may be L-shaped.

[0384] In at least one embodiment of the present invention, an orthographic projection of the signal line conductive connection portion L40 on the substrate partially overlaps with an orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate.

[0385] In the preferred case, Figure 5 As shown, the longest distance between the gate G6 of the first capacitor-connected transistor T6 and the gate G5 of the second capacitor-connected transistor T5 in the second direction is less than a fourth predetermined distance;

[0386] like Figure 3 As shown, the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate is within the orthographic projection of the second electrode plate C1b of the first capacitor C1 on the substrate;

[0387] like Figure 6 As shown, the first electrode plate C1a of the first capacitor C1 is L-shaped.

[0388] In at least one embodiment of the present invention, T5 and T6 are arranged at a close distance so as to be able to adjust the shape of the electrode plate of C1, and the first electrode plate C1a of C1 is arranged to be L-shaped, thereby making full use of the routing space between the gate of T5 and the second conductive connection portion, so as to make the layout more reasonable, effectively narrow the lateral width of the shift register unit, and reduce the longitudinal height of the shift register unit.

[0389] In at least one embodiment of the present invention, the fourth predetermined distance may be selected according to actual conditions. For example, the fourth predetermined distance is greater than or equal to 20 um (micrometers) and less than or equal to 30 um.

[0390] In at least one embodiment of the present invention, the longest distance between the gate G6 of the first capacitor-connected transistor T6 and the gate G5 of the second capacitor-connected transistor T5 in the second direction refers to: the maximum distance between any point on the edge line of G5 and the edge line of G6 in the second direction, such as Fig. 10C As shown, d4 is the maximum distance between any point on the edge line of G5 and the edge line of G6 in the second direction.

[0391] In specific implementation, Figure 1 As shown, the shift register unit may include a first transistor T8 and a second transistor T7;

[0392] like Fig. 9 As shown, in Figure 6 On the basis of, the first electrode plate C1a of the first capacitor C1 includes a first horizontal electrode plate portion C1a1 and a first vertical electrode plate portion C1a2;

[0393] like Figure 3 and Fig. 9 As shown, the orthographic projection of the gate G5 of the second capacitor connection transistor T5 on the substrate and the orthographic projection of the first horizontal electrode portion C1a1 on the substrate are arranged along a first direction;

[0394] The orthographic projection of the gate G8 of the first transistor T8 on the substrate, the orthographic projection of the gate G7 of the second transistor T7 on the substrate, and the orthographic projection of the first vertical electrode portion C1a2 on the substrate are arranged along a first direction;

[0395] The orthographic projection of the first vertical plate portion C1a2 on the substrate is located between the orthographic projection of the second electrode D6 of the first capacitor-connected transistor T6 on the substrate and the orthographic projection of the first electrode S5 of the second capacitor-connected transistor T5 on the substrate;

[0396] The first electrode S7 of the second transistor T7 is coupled to the second plate C3b of the output capacitor C3.

[0397] In at least one embodiment of the present invention, C1 is arranged using the space between T5 and T6 and the space between the gate of T5 and the second conductive connection portion, and the electrode plate of C1 is arranged in an L shape for a reasonable layout.

[0398] In at least one embodiment of the present invention, the second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1 through the sixth connection via H86, so that the second electrode D7 of the second transistor T7 is coupled to the second electrode D6 of the first capacitor connection transistor T6.

[0399] Optional, such as Figure 1 As shown, the at least one shift register unit may further include a first node control transistor T2 and a second capacitor C2;

[0400] like Figure 5 As shown, the gate of the first node control transistor T2 includes a first gate pattern G21 and a second gate pattern G22 which are respectively coupled to the second plate C2b of the second capacitor C2;

[0401] like Figure 3 , Figure 5 and Figure 6 As shown, the orthographic projection of the first electrode plate C2a of the second capacitor C2 on the substrate is within the orthographic projection of the second electrode plate C2b of the second capacitor C2 on the substrate;

[0402] The first electrode plate C2a of the second capacitor C2 is L-shaped;

[0403] like Fig. 9 As shown, in Figure 6 On the basis of, the first electrode plate C2a of the second capacitor C2 includes a second horizontal electrode plate portion C2a1;

[0404] The orthographic projection of the gate G2 of the first node control transistor T2 on the substrate and the orthographic projection of the second horizontal electrode portion C2a1 on the substrate are arranged along a first direction.

[0405] In at least one embodiment of the present invention, the plate of C2 is set to be L-shaped, and the horizontal plate portion included in the plate of C2 is placed in the space between T2 in the n-th stage shift register unit and the second node control transistor in the n+1-th stage shift register unit to narrow the lateral width of the shift register unit.

[0406] In at least one embodiment of the present invention, Figure 3 and Figure 8 As shown, the scan driving circuit further includes a third voltage signal line VGL2; the third voltage signal line VGL2 extends along the first direction;

[0407] The first node control transistor T2 is located at a side of the second capacitor connection transistor T5 away from the first voltage signal line VGH; the first node control transistor T2 is located between the third voltage signal line VGL2 and the first voltage signal line VGH;

[0408] like Fig. 9 As shown, the first electrode plate C2a of the second capacitor C2 also includes a second vertical electrode plate portion C2a2 coupled to the second horizontal electrode plate portion C2a1; the orthographic projection of the second vertical electrode plate portion C2a2 on the substrate partially overlaps with the orthographic projection of the third voltage signal line VGL2 on the substrate.

[0409] Specifically, the electrode plate of C2 is set to be L-shaped, and the orthographic projection of the second vertical electrode plate portion C2a2 of C2 on the substrate partially overlaps with the orthographic projection of the third voltage signal line VGL2 on the substrate to reduce the vertical height of the shift register unit.

[0410] like Figure 3 , Figure 4 and Fig. 9 As shown, the orthographic projection of the second active pattern A2 of T2 on the substrate and the orthographic projection of the second horizontal electrode portion C2a1 on the substrate are arranged in sequence along the first direction, and the horizontal electrode portion of C2 is set by utilizing the space between A2 in the nth shift register unit and the n+1th shift register unit.

[0411] like Figure 1 and Figure 3 As shown, the first clock signal line CB is located at a side of the third voltage signal line VGL2 away from the first voltage signal line VGH;

[0412] The output circuit includes an output transistor T10; Figure 5 As shown, the at least one shift register unit further includes a second conductive connection portion L2 disposed between the gate G10 of the output transistor T10 and the second plate C2b of the second capacitor C2; the second conductive connection portion L2 is coupled to the gate G10 of the output transistor T10 and the second plate C2b of the second capacitor C2, respectively;

[0413] The at least one shift register unit further includes a third conductive connection portion L3 coupled to the first electrode plate C2a of the second capacitor C2;

[0414] like Figure 3 and Figure 7 As shown, there is a sixth overlapping area between the orthographic projection of the third conductive connection portion L3 on the substrate and the orthographic projection of the first clock signal line CB on the substrate, and the first clock signal line CB is coupled to the first plate C2a of the second capacitor C2 through at least one sixth via H6 arranged in the sixth overlapping area.

[0415] Optionally, the second conductive connection portion L2 may extend along the second direction, and is used to couple the gate G10 of the output transistor T10 and the second electrode plate C2b of the second capacitor C2;

[0416] The third conductive connection portion L3 may extend along the second direction, and the third conductive connection portion L3 is coupled to the first electrode plate C2a of the second capacitor C2 through a sixth via hole H6.

[0417] Specifically, Figure 3 and Figure 4 As shown, the first capacitor connection transistor T6 includes a first active pattern A1; the first active pattern A1 extends along a first direction;

[0418] The first active pattern A1 includes a first first capacitor connecting conductive portion L111 and a second first capacitor connecting conductive portion L112 which are arranged opposite to each other along a first direction, and a first capacitor connecting channel portion L12 located between the first first capacitor connecting conductive portion L111 and the second first capacitor connecting conductive portion L112.

[0419] In at least one embodiment of the present invention, the first first capacitor connection conductive portion L111 is used as the first capacitor connection transistor T6 first electrode S6, and the second first capacitor connection conductive portion L112 is used as the first capacitor connection transistor T6 second electrode D6.

[0420] Optionally, the first active pattern A1 of T6 extends along the first direction, and T6 is disposed between T5 and VGH, so as to narrow the lateral width of the shift register unit.

[0421] In specific implementation, Figure 1 and Figure 3 As shown, the at least one shift register unit may include a second transistor T7;

[0422] The second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1 .

[0423] like Figure 3 , Figure 7 and Figure 8 As shown, the second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1 through the sixth connection via H86.

[0424] Specifically, Figure 4 As shown, the first node control transistor T2 may include a second active pattern A2; the second active pattern A2 may be U-shaped;

[0425] The second active pattern A2 includes a first first node control channel portion A211, a second first node control channel portion A212, a first first node control conductive portion A221, and a second first node control conductive portion A222;

[0426] like Figure 5 As shown, the gate of the first node control transistor T2 includes a first gate pattern G21 and a second gate pattern G22 coupled to each other;

[0427] The first gate pattern G21 corresponds to the first first node control channel portion A211, and the second gate pattern G22 corresponds to the second first node control channel portion A212;

[0428] like Figure 3 and Figure 4 As shown, the first first-node control conductive portion A221 is used as the second electrode D2 of the first-node control transistor T2, and the second first-node control conductive portion A222 is used as the first electrode S2 of the first-node control transistor T2.

[0429] like Figure 3 and Figure 4 As shown, the active pattern of the first node control transistor T2 is set to a U-shaped structure so that T2 forms a double-gate structure. The purpose of the double-gate structure design is that: in the second stage P2, when the shift register unit included in the scan drive circuit outputs a high voltage signal Vgh, T10 should be completely closed, and the high level connected to the gate of T10 is input by the source of T5. Therefore, in the second stage P2, it is necessary to ensure that T5 is turned on, that is, the potential of the second node N2 needs to be low voltage; and in the second stage P2, the potential of the gate of T2 is high voltage. In order to ensure that T2 does not leak electricity and cause the potential of the second node N2 to rise, T2 is set to adopt a double-gate design, so that T2 is easier to turn off.

[0430] In actual production exposure, if the active pattern of T2 is set to a U-shape without missing corners, metal will be deposited after exposure, which will make the U-shaped active pattern V-shaped. Therefore, in actual products, considering the actual production exposure process, a small part of the inner side of the U-shaped active pattern is dug out at two right angles for compensation, so as to make the actual pattern as U-shaped as possible and not affect the width-to-length ratio of T2.

[0431] In at least one embodiment of the present invention, Figure 1 and Figure 3 As shown, the at least one shift register unit may further include a second node control transistor T3; the at least one shift register unit includes a second capacitor connection transistor T5;

[0432] like Figure 4 and Figure 8 As shown, the second electrode D3 of the second node control transistor T3 is coupled to the second electrode D2 of the first node control transistor T2 via a fourth conductive connection portion L4;

[0433] like Figure 3 , Figure 4 , Figure 5 and Figure 8 As shown, the at least one shift register unit further includes a fifth conductive connection portion L5 coupled to the gate G5 of the second capacitor-connected transistor T5; there is a seventh overlapping region between the orthographic projection of the fifth conductive connection portion L5 on the substrate and the orthographic projection of the fourth conductive connection portion L4 on the substrate;

[0434] The fifth conductive connection portion L5 is coupled to the fourth conductive connection portion L4 through a seventh via hole H7 disposed in the seventh overlapping region.

[0435] In specific implementation, Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the second electrode D3 of the second node control transistor T3 is coupled to the fourth conductive connection part L4 through the seventh connection via H87, and the second electrode D2 of the first node control transistor T2 is coupled to the fourth conductive connection part L4 through the eighth connection via H88, so that the second electrode D3 of the second node control transistor T3 is coupled to the second electrode D2 of the first node control transistor T2.

[0436] In at least one embodiment of the present invention, the fourth conductive connection portion L4 may extend along the first direction to reduce the lateral width of the shift register unit.

[0437] In specific implementation, Figure 1 and Figure 3 As shown, the display substrate may further include a third voltage signal line VGL2; the third voltage signal line VGL2 is arranged on a side of the second node control transistor T3 away from the first voltage signal line VGH;

[0438] like Figure 3 , Figure 4 and Figure 5 As shown, the first electrode S2 of the first node control transistor T2 is coupled to the sixth conductive connection portion L6; the gate G3 of the second node control transistor T3 is coupled to the seventh conductive connection portion L7;

[0439] There is an eighth overlapping region between the orthographic projection of the sixth conductive connection portion L6 on the substrate and the orthographic projection of the seventh conductive connection portion L7 on the substrate, and the sixth conductive connection portion L6 is coupled to the seventh conductive connection portion L7 through an eighth via H8 disposed within the eighth overlapping region;

[0440] A first electrode S3 of the second node control transistor T3 is coupled to the third voltage signal line VGL2 .

[0441] like Figure 3 and Figure 7 As shown, the first electrode S2 of the first node control transistor T2 is coupled to the sixth conductive connection portion L6 through a ninth connection via H89, and the sixth conductive connection portion L6 may extend along the first direction to narrow the lateral width of the shift register unit.

[0442] like Figure 5 As shown, the gate G3 of the second node control transistor T3 is coupled to the seventh conductive connection part L7, and the sixth conductive connection part L6 is coupled to the seventh conductive connection part L7 through the eighth via H8 arranged in the eighth overlapping area, so that the first electrode S2 of the first node control transistor T2 is coupled to the gate G3 of the second node control transistor T3.

[0443] like Figure 4 As shown, the second node control transistor T3 includes a third active pattern A3, and the third active pattern includes a first control conductive portion A311, a control channel portion A32, and a second control conductive portion A312 sequentially arranged along a first direction;

[0444] The first control conductive portion A311 is used as the first electrode S3 of T3, and the second control conductive portion A312 is used as the second electrode D3 of T3.

[0445] like Figure 5 As shown, the gate G3 of the second node control transistor T3 is also coupled to the eighth conductive connection portion L8; Figure 3 As shown, there is a ninth overlapping area between the orthographic projection of the eighth conductive connection portion L8 on the substrate and the orthographic projection of the second clock signal line CK on the substrate, as shown in FIG. Figure 7 As shown, the eighth conductive connection portion L8 is coupled to the second clock signal line CK through a ninth via hole H9 disposed in the ninth overlapping region.

[0446] Since the gate of T3 is coupled to the second clock signal line CK, the gate of T3 may be arranged to be close to the second clock signal line CK for reasonable layout.

[0447] Specifically, Figure 1 and Figure 3 As shown, the scan driving circuit may include a first clock signal line CB and a third voltage signal line VGL2; the first clock signal line CB and the third voltage signal line VGL2 extend along a first direction;

[0448] The second clock signal line CK is disposed between the first clock signal line CB and the third voltage signal line VGL2 .

[0449] Optionally, the first clock signal line may also be arranged between the second clock signal line and the third voltage signal line.

[0450] In specific implementation, Figure 1 and Figure 3 As shown, the at least one shift register unit may further include an input transistor T1;

[0451] like Figure 5 As shown, the gate G1 of the input transistor T1 is coupled to the seventh conductive connection portion L7; Figure 3 As shown, the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1;

[0452] The second electrode D1 of the input transistor T1 is coupled to the ninth conductive connection part L9, and there is a tenth overlapping area between the orthographic projection of the ninth conductive connection part L9 on the substrate and the orthographic projection of the second electrode plate C2b of the second capacitor C2 on the substrate, and the ninth conductive connection part L9 is coupled to the second electrode plate C2b of the second capacitor C2 through a tenth via H10 arranged in the tenth overlapping area.

[0453] like Figure 3 , Figure 4 , Figure 6 , Figure 7 and Figure 8 As shown, the first electrode S1 of the input transistor T1 is coupled to the input conductive connection portion L70 through the ninth connection via H89, and the input conductive connection portion L70 is coupled to the input signal terminal E1 through the tenth connection via H810, so that the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1;

[0454] like Figure 3 , Figure 4 , Figure 6 , Figure 7 and Figure 8As shown, the second electrode D1 of the input transistor T1 is coupled to the ninth conductive connection portion L9, and the ninth conductive connection portion L9 is coupled to the second plate C2b of the second capacitor C2 through the tenth via H10 provided in the tenth overlapping region, so that the second electrode D1 of the input transistor T1 is coupled to the second plate C2b of the second capacitor C2;

[0455] In at least one embodiment of the present invention, the ninth conductive connection portion L9 may extend along the first direction to narrow the lateral width of the shift register unit.

[0456] In at least one embodiment of the present invention, Figure 1 and Figure 3 As shown, the at least one shift register unit may further include a third node control transistor T4;

[0457] like Figure 5 As shown, the gate G4 of the third node control transistor T4 is coupled to the tenth conductive connection portion L10;

[0458] like Figure 3 and Figure 7 As shown, there is an eleventh overlapping area between the orthographic projection of the tenth conductive connection portion L10 on the substrate and the orthographic projection of the first clock signal line CB on the substrate, and the tenth conductive connection portion L10 is coupled to the first clock signal line CB through an eleventh via H11 arranged in the eleventh overlapping area.

[0459] Optionally, the tenth conductive connection portion L10 may be arranged along the second direction, but is not limited thereto.

[0460] Specifically, Figure 1 and Figure 3 As shown, the at least one shift register includes a second transistor T7;

[0461] like Figure 5 As shown, the gate G4 of the third node control transistor T4 is coupled to the gate G7 of the second transistor T7.

[0462] Since the gate G4 of T4 and the gate G7 of T7 need to be coupled, T4 and T7 may be arranged to be close to each other during layout.

[0463] In at least one embodiment of the present invention, Figure 1 and Figure 3 As shown, the at least one shift register unit may include a second capacitor connection transistor T5;

[0464] like Figure 4As shown, the active layer of the input transistor T1, the active layer of the third node control transistor T4 and the active layer of the second capacitor connection transistor T5 can be formed by a continuous third semiconductor layer 30;

[0465] The active layer of the input transistor T1 includes a first fifth conductive portion 311, a fifth channel portion 32 and a second fifth conductive portion 312 sequentially arranged along the first direction;

[0466] The second fifth conductive portion 312 is multiplexed as the first sixth conductive portion;

[0467] The active layer of the third node control transistor T4 includes a first sixth conductive portion, a sixth channel portion 34 and a second sixth conductive portion 332 sequentially arranged along the first direction;

[0468] The second sixth conductive portion 332 is multiplexed as the first seventh conductive portion;

[0469] The active layer of the second capacitor-connecting transistor T5 includes a first seventh conductive portion, a seventh channel portion 36 and a second seventh conductive portion 352 sequentially arranged along the first direction.

[0470] In at least one embodiment of the present invention, Figure 3 and Figure 4 As shown, the first fifth conductive portion 311 is used as the first electrode S1 of the input transistor T1, the second fifth conductive portion 312 is used as the second electrode D1 of the input transistor T1, the second sixth conductive portion 332 is used as the first electrode S4 of the third node control transistor T4, and the second seventh conductive portion 352 is used as the first electrode S5 of the second capacitor connection transistor T5;

[0471] And, if Figure 3 As shown, the second electrode D1 of the input transistor T1 is multiplexed as the second electrode D4 of the third node control transistor T4, and the first electrode S4 of the third node control transistor T4 is multiplexed as the second electrode D5 of the second capacitor connection transistor T5. That is, in the display substrate described in at least one embodiment of the present invention, in the input transistor T1, the third node control transistor T4 and the second capacitor connection transistor T5, adjacent transistors can be directly coupled through the conductive portion included in the third semiconductor layer 30, thereby reducing the area occupied by T1, T4 and T5 in the first direction.

[0472] Specifically, the scan driving circuit may further include a third voltage signal line;

[0473] The third voltage signal line, the first clock signal line and the second clock signal line all extend along a first direction;

[0474] The orthographic projection of the third voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate and the orthographic projection of the second clock signal line on the substrate are all located on a side of the orthographic projection of the shift register unit on the substrate away from the display area of ​​the display substrate;

[0475] The signal output line extends along a second direction, and the first direction intersects the second direction.

[0476] Specifically, the specific positions of the first clock signal line, the second clock signal line and the third voltage signal line can be set according to actual needs. For example, the first clock signal line, the second clock signal line and the third voltage signal line can be set at the edge of the display substrate, so that the orthographic projection of the third voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate and the orthographic projection of the second clock signal line on the substrate are all located on the side of the orthographic projection of the shift register unit on the substrate away from the display area of ​​the display substrate. In this way, when laying out the shift register unit, it is possible to avoid excessive overlap between the transistors in the shift register unit and the first clock signal line, the second clock signal line and the third voltage signal line, which is more conducive to improving the working performance of the shift register unit.

[0477] In addition, by arranging the first clock signal line, the second clock signal line and the third voltage signal line to extend along the first direction, it is more conducive to achieving a narrow frame of the display substrate.

[0478] In a specific implementation, the phases of the first clock signal output by the first clock signal line and the second clock signal output by the second clock signal line may be opposite, but the present invention is not limited thereto.

[0479] In specific implementation, Figure 1 and Figure 3 As shown, the scan drive circuit may include a first voltage signal line VGH, a second voltage signal line VGL1, a third voltage signal line VGL2, a first clock signal line CB, and a second clock signal line CK; the at least one shift register unit may also include a signal output line EOUT, an output capacitor C3, a first capacitor C1, a second capacitor C2, an output reset transistor T9, an output transistor T10, a first transistor T8, a second transistor T7, a first capacitor connection transistor T6, a second capacitor connection transistor T5, a first node control transistor T2, a second node control transistor T3, an input transistor T1, and a third node control transistor T4;

[0480] The output reset transistor T9 and the output transistor T10 are arranged along a first direction;

[0481] The first electrode S9 of the output reset transistor T9 is coupled to the first voltage signal line VGH, and the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL1;

[0482] The output transistor T10 and the signal output line EOUT are arranged along a first direction, and the second electrode D9 of the output reset transistor T9 and the second electrode D10 of the output transistor T10 are both coupled to the signal output line EOUT;

[0483] The signal output line EOUT extends along a second direction, and the first direction intersects with the second direction;

[0484] The second electrode D8 of the first transistor T8 is coupled to the second plate C3b of the output capacitor C3, the first electrode S8 of the first transistor T8 is coupled to the first voltage signal line VGH, and the gate G8 of the first transistor T8 is coupled to the second electrode D4 of the third node control transistor T4;

[0485] The second electrode D7 of the second transistor T7 is coupled to the first plate C1a of the first capacitor C1, the first electrode S7 of the second transistor T7 is coupled to the second plate C3b of the output capacitor C3, and the gate G7 of the second transistor T7 is coupled to the gate G4 of the third node control transistor T4;

[0486] The gate G6 of the first capacitor-connected transistor T6 and the gate G5 of the second capacitor-connected transistor T5 are respectively coupled to the second plate C1b of the first capacitor C1; the second electrode D6 of the first capacitor-connected transistor T6 is coupled to the first plate C1a of the first capacitor C1; the first electrode S6 of the first capacitor-connected transistor T6 is coupled to the gate G7 of the second transistor T7;

[0487] The first electrode S5 of the second capacitor connection transistor T5 is coupled to the first voltage signal line VGH; the gate G5 of the second capacitor connection transistor T5 is coupled to the second electrode D3 of the second node control transistor T3; the second electrode D5 of the second capacitor connection transistor T5 is coupled to the first electrode S4 of the third node control transistor T4;

[0488] The first electrode S2 of the first node control transistor T2 is coupled to the gate G3 of the second node control transistor T3; the gate G2 of the first node control transistor T2 is coupled to the second plate C2b of the second capacitor C2;

[0489] The second electrode D3 of the second node control transistor T3 is coupled to the second electrode D2 of the first node control transistor T2; the gate G3 of the second node control transistor T3 is coupled to the second clock signal line CK; the first electrode S3 of the second node control transistor T3 is coupled to the third voltage signal line VGL2;

[0490] The gate G1 of the input transistor T1 is coupled to the gate G3 of the second node control transistor T3; the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1; the second electrode D1 of the input transistor T1 is coupled to the second plate C2b of the second capacitor C2;

[0491] The gate G4 of the third node control transistor T4 is coupled to the first clock signal line CB;

[0492] The first plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH, and the second plate C3b of the output capacitor C3 is coupled to the gate G9 of the output reset transistor T9;

[0493] The second plate C2b of the second capacitor C2 is coupled to the gate G10 of the output transistor T10, and the first plate C2a of the second capacitor C2 is coupled to the first clock signal line CB;

[0494] The second electrode D9 of the output reset transistor T9 and the second electrode D10 of the output transistor T10 are both coupled to the signal output line EOUT.

[0495] In at least one embodiment of the present invention, the first clock signal line, the second clock signal line and the third voltage signal line are arranged in sequence along a direction close to the display area; or, the second clock signal line, the first clock signal line and the third voltage signal line are arranged in sequence along a direction close to the display area.

[0496] like Fig. 9 As shown, in Figure 6 On the basis of, the first electrode plate C1a of the first capacitor C1 may include a first horizontal electrode plate portion C1a1 and a first vertical electrode plate portion C1a2;

[0497] like Figure 3 As shown, the output reset transistor T9 and the output transistor T10 are arranged between the first voltage signal line VGH and the second voltage signal line VGL1; along the first direction, the output reset transistor T9, the output transistor T10 and the signal output line EOUT are arranged in sequence;

[0498] The third voltage signal line VGL2 is arranged on a side of the first voltage signal line VGH away from the second voltage signal line VGL1; the first capacitor C1, the first transistor T8, the second transistor T7, the first capacitor connection transistor T6, the second capacitor connection transistor T5, the first node control transistor T2, the second node control transistor T3, the input transistor T1 and the third node control transistor T4 are all arranged between the first voltage signal line VGH and the third voltage signal line VGL2;

[0499] The first transistor T8, the second transistor T7 and the first vertical plate portion C1a2 are arranged in sequence along the first direction, the input transistor T1, the third node control transistor T4, the second capacitor connection transistor T5 and the first horizontal plate portion C1a1 are arranged in sequence along the first direction, and the second node control transistor T3 and the first node control transistor T2 are arranged in sequence along the first direction;

[0500] The orthographic projection of the gate G6 of the first capacitor connection transistor T6 on the substrate is arranged between the orthographic projection of the second electrode plate C1b of the first capacitor C1 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate;

[0501] The orthographic projection of the gate G7 of the second transistor T7 on the substrate is arranged between the orthographic projection of the gate G4 of the third node control transistor T4 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate;

[0502] The orthographic projection of the gate G2 of the first node control transistor T2 on the substrate is arranged between the orthographic projection of the third voltage signal line VGL2 on the substrate and the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate;

[0503] The minimum distance in the second direction between the orthographic projection of the gate G2 of the first node control transistor T2 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate is greater than the minimum distance in the second direction between the orthographic projection of the gate G5 of the second capacitor connection transistor T5 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate.

[0504] In the present invention Figure 3In the layout shown, since the output reset transistor T9 is coupled to the first voltage signal line VGH and the output transistor T10 is coupled to the second voltage signal line VGL1, the output reset transistor T9 and the output transistor T10 are arranged between the first voltage signal line VGH and the second voltage signal line VGL1, and the space between T10 in the n-th stage shift register unit and the output reset transistor in the n+1-th stage shift register unit is fully utilized to set the signal output line EOUT, so that the first voltage signal line VGH is arranged on the side of the output circuit O1 away from the display area, and no other signal lines and components included in other transistors are arranged between the first voltage signal line VGH and the output circuit O1, and the second voltage signal line VGL1 is arranged on the side of the output circuit O1 close to the display area, and no other signal lines and components included in other transistors are arranged between the second voltage signal line VGL1 and the output circuit O1, narrowing the distance from VGH to T9 and T10, and narrowing the distance from VGL1 to T9 and T10, so that the lateral width of the shift register unit is reduced.

[0505] In the present invention Figure 3 In the layout shown, T8 is moved to the side of the first voltage signal line VGH away from the second voltage signal line VGL1, and the orthographic projection of the plate of the output capacitor C3 on the substrate is set to partially overlap with the orthographic projection of the first voltage signal line VGH on the substrate, so as to reduce the distance between the first electrode S8 of the first transistor T8 and the first voltage signal line VGH, and reduce the distance between the second electrode D8 of the first transistor T8 and the second plate C3b of the output capacitor C3, so that T8 can be conveniently coupled to the first voltage signal line VGH and the second plate C3b of the output capacitor C3, respectively, so that the space is compact and the layout is more reasonable.

[0506] In the present invention Figure 3 In the layout shown, T5 and T6 are arranged at a close distance so as to be able to adjust the shape of the electrode plate of C1, and the first electrode plate C1a of C1 is arranged in an L shape, so as to make full use of the routing space between the gate of T5 and the second conductive connection portion, so as to make the layout more reasonable, effectively narrow the lateral width of the shift register unit, and reduce the longitudinal height of the shift register unit.

[0507] In at least one embodiment of the present invention, the minimum distance between the orthographic projection of the gate G2 of the first node control transistor T2 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate in the second direction refers to: the minimum distance between any point on the edge line of the orthographic projection of G2 on the substrate and the edge line of the orthographic projection of VGL2 on the substrate in the second direction;

[0508] The minimum distance between the orthographic projection of the gate G5 of the second capacitor connection transistor T5 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate in the second direction refers to: the minimum distance between any point on the edge line of the orthographic projection of G5 on the substrate and the edge line of the orthographic projection of VGL2 on the substrate in the second direction. In a specific implementation, the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate have a signal line overlapping area; the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate partially overlap;

[0509] The orthographic projection of the first electrode plate C2a of the second capacitor C2 on the substrate is within the orthographic projection of the second electrode plate C2b of the second capacitor C2 on the substrate; the first electrode plate C2a of the second capacitor C2 is L-shaped;

[0510] like Fig. 9 As shown, the first electrode plate C2a of the second capacitor C2 includes a second horizontal electrode plate portion C2a1 and a second vertical electrode plate portion C2a2;

[0511] The gate G2 of the first node control transistor T2 and the second horizontal plate portion C2a1 are arranged along a first direction;

[0512] The orthographic projection of the second vertical plate portion C2a2 on the substrate partially overlaps with the orthographic projection of the third voltage signal line VGL2 on the substrate.

[0513] In the present invention Figure 3 In the layout shown, the plate of C2 is set to be L-shaped, and the horizontal plate portion included in the plate of C2 is placed in the space between T2 in the nth shift register unit and the n+1th shift register unit to narrow the lateral width of the shift register unit.

[0514] In at least one embodiment of the present invention, Figure 4 The semiconductor layer shown and Figure 5 A first gate insulating layer may also be provided between the first gate metal layers shown in FIG. Figure 5 The first gate metal layer shown and Figure 6 A second gate insulating layer may also be provided between the second gate metal layers shown in FIG. Figure 6 The second gate metal layer shown and Figure 8 An insulating layer may also be included between the source and drain metal layers shown.

[0515] When manufacturing the display substrate according to at least one embodiment of the present invention, a semiconductor material layer is firstly provided on a substrate, and a patterning process is performed on the semiconductor material layer to form an active layer of each transistor; Figure 4 As shown, a first semiconductor layer 10, a second semiconductor layer 20, a third semiconductor layer 30, the first capacitor connection transistor T6 including a first active pattern A1, a second active pattern A2 of the first node control transistor T2 and the second node control transistor T3 including a third active pattern A3 are formed;

[0516] Forming a first gate insulating layer on a side of the active layer facing away from the substrate;

[0517] A first gate metal layer is formed on a side of the first gate insulating layer facing away from the active layer, and a patterning process is performed on the first gate metal layer, such as Figure 5 As shown, the gates of each transistor included in the shift register unit, the second plate of the output capacitor C3, the second plate of the first capacitor C1 and the second plate of the second capacitor C2 are formed;

[0518] Using the gates of the transistors as masks, doping the portion of the active layer not covered by the gates, so that the portion of the active layer not covered by the gates forms a conductive portion, and the portion of the active layer covered by the gates forms a channel portion; the conductive portion is used as a first electrode or a second electrode; or the conductive portion is coupled to the first electrode or the second electrode;

[0519] Disposing a second gate insulating layer on a side of the first gate metal layer facing away from the first gate metal layer;

[0520] A second gate metal layer is disposed on a side of the second gate insulating layer facing away from the first gate metal layer, and a patterning process is performed on the second gate metal layer, such as Figure 6 As shown, a signal output line EOUT, an input signal terminal R1, a first plate of an output capacitor C3, a first plate of a first capacitor C1 and a first plate of a second capacitor C2 are formed;

[0521] Disposing an insulating layer on a side of the second gate metal layer facing away from the second gate insulating layer;

[0522] like Figure 7 As shown, a plurality of via holes are provided on a substrate provided with an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer and an insulating layer;

[0523] A source-drain metal layer is disposed on a side of the insulating layer facing away from the second gate metal layer, and a patterning process is performed on the source-drain metal layer, such as Figure 8As shown, a first voltage signal line VGH, a second voltage signal line VGL1, a third voltage signal line VGL2, a first clock signal line CB, a second clock signal line CK, a start signal line ESTV, a second electrode of the output reset transistor T9, a first electrode S9 of the output reset transistor T9, a second electrode D10 of the output transistor T10, and a first electrode S10 of the output transistor T10 are formed.

[0524] The method for manufacturing a display substrate according to at least one embodiment of the present invention comprises manufacturing a scan drive circuit on a substrate, and manufacturing at least one drive transistor in a display area included in the display substrate; the drive transistor is configured to drive a light-emitting element to display;

[0525] The scan driving circuit comprises a plurality of shift register units, a first voltage signal line, a second voltage signal line, a first clock signal line and a second clock signal line, at least one shift register unit of the plurality of shift register units comprises an output circuit and a signal output line;

[0526] The method for manufacturing the display substrate further includes:

[0527] The transistor included in the output circuit is fabricated between the first voltage signal line and the second voltage signal line;

[0528] The first voltage signal line, the second voltage signal line, the first clock signal line and the second clock signal line are arranged to extend along a first direction, and the signal output line is arranged to extend along a second direction;

[0529] The first direction and the second direction intersect.

[0530] In the manufacturing method of the display substrate described in at least one embodiment of the present invention, the output circuit is arranged between the first voltage signal line and the second voltage signal line, so that in terms of spatial structure, the first voltage signal line is arranged on the side of the output circuit away from the display area, and no other signal lines and components included in other transistors are arranged between the first voltage signal line and the output circuit, and the second voltage signal line is arranged on the side of the output circuit close to the display area, and no other signal lines and components included in other transistors are arranged between the second voltage signal line and the output circuit. The distance from the first voltage signal line to the output circuit can be narrowed, and the distance from the second voltage signal line to the output circuit can be narrowed, so that the lateral width of the shift register unit is reduced.

[0531] In at least one embodiment of the present invention, the first voltage signal line may be located on a side of the second voltage signal line away from the display area.

[0532] Optionally, the method for manufacturing a display substrate according to at least one embodiment of the present invention may further include: arranging the signal output line between output circuits in adjacent shift register units.

[0533] In a specific implementation, the output circuit is coupled to the signal output line, and the output circuit should be close to the signal output line. At least one embodiment of the present invention moves the signal output line down to between the output circuits in adjacent shift register units to narrow the lateral width of the shift register unit.

[0534] Optionally, the output circuit may include an output transistor and an output reset transistor, and the steps of manufacturing the transistor included in the output circuit specifically include:

[0535] forming a first semiconductor layer extending along a first direction between the first voltage signal line and the second voltage signal line;

[0536] Manufacturing a first gate metal layer on a side of the first semiconductor layer facing away from the substrate, and performing a patterning process on the first gate metal layer to form a gate of the output transistor and a gate of the output reset transistor;

[0537] Using the gate of the output transistor and the gate of the output reset transistor as masks, the portion of the first semiconductor layer not covered by the gate is doped, so that the portion of the first semiconductor layer not covered by the gate is formed into a conductive portion, and the portion of the first semiconductor layer covered by the gate is formed into a channel portion.

[0538] In a specific implementation, the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer, but the present invention is not limited thereto.

[0539] In at least one embodiment of the present invention, the active layer of the output transistor and the active layer of the output reset transistor can be formed by a continuous first semiconductor layer, which extends along a first direction; the active layer of the output reset transistor includes at least one first conductive portion arranged opposite to each other along the first direction, and at least one first channel portion; each of the first channel portions is arranged between two adjacent first conductive portions; the active layer of the output transistor can include at least two second conductive portions arranged opposite to each other along the first direction, and at least one second channel portion; each of the second channel portions is arranged between two adjacent second conductive portions; the first conductive portion in the active layer of the output reset transistor that is closest to the active layer of the output transistor can be reused as the second conductive portion in the output transistor, which can further reduce the layout space of the output transistor and the output reset transistor, and is conducive to achieving a narrow frame of the display substrate.

[0540] In a specific implementation, the manufacturing method of the display substrate may further include: providing a second gate metal layer on a side of the first gate metal layer facing away from the first semiconductor layer, and performing a patterning process on the second gate metal layer to form a signal output line extending along a second direction;

[0541] An orthographic projection of the first semiconductor layer on the substrate and an orthographic projection of the signal output line on the substrate are arranged along a first direction, and the first direction intersects with the second direction.

[0542] In at least one embodiment of the present invention, the orthographic projection of the first semiconductor layer on the substrate and the orthographic projection of the signal output line on the substrate are arranged along a first direction, which can narrow the lateral width of the shift register unit.

[0543] In at least one embodiment of the present invention, the steps of manufacturing the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line may specifically include:

[0544] A source-drain metal layer is formed on a side of the second gate metal layer facing away from the first gate metal layer, and the source-drain metal layer is patterned to form the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line.

[0545] Optionally, the at least one shift register unit may further include an output capacitor and a first transistor; and the method for manufacturing the display substrate may further include:

[0546] The output capacitor is manufactured, and a first transistor is formed on a side of the first voltage signal line away from the second voltage signal line, so that a first electrode of the first transistor is coupled to the first voltage signal line, and a second electrode of the first transistor is coupled to a plate of the output capacitor.

[0547] In a preferred case, the maximum distance in the second direction between the orthographic projection of the first electrode of the first transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate is less than a first predetermined distance, and the maximum distance in the second direction between the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the plate of the output capacitor on the substrate is less than a second predetermined distance.

[0548] In at least one embodiment of the present invention, since the first electrode of the first transistor is coupled to the first voltage signal line, and the second electrode of the first transistor is coupled to the second plate of the output capacitor, when manufacturing the display substrate, the closer the first transistor is to the first voltage signal line and the output capacitor, the more reasonable the corresponding layout will be. In at least one embodiment of the present invention, the first transistor is arranged on the side of the first voltage signal line away from the second voltage signal line to form a side of the first transistor, and the maximum distance between the orthographic projection of the first electrode of the first transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate in the second direction is less than a first predetermined distance, and the maximum distance between the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the plate of the output capacitor on the substrate in the second direction is less than a second predetermined distance, so as to arrange the layout reasonably.

[0549] Optionally, the at least one shift register unit may further include a second transistor, and the steps of manufacturing the first transistor and the second transistor specifically include:

[0550] forming a second semiconductor layer extending along a first direction on a side of the first voltage signal line away from the second voltage signal line;

[0551] Manufacturing a first gate metal layer on a side of the second semiconductor layer facing away from the substrate, and performing a patterning process on the first gate metal layer to form a gate of the first transistor and a gate of the second transistor;

[0552] Using the gate of the first transistor and the gate of the second transistor as masks, doping a portion of the second semiconductor layer not covered by the gate, so that the portion of the second semiconductor layer not covered by the gate forms a conductive portion, and the portion of the second semiconductor layer covered by the gate forms a channel portion;

[0553] The second semiconductor layer includes a third conductive portion, a third channel portion, a second third conductive portion, a fourth channel portion and a second fourth conductive portion which are sequentially arranged along the first direction;

[0554] The second third conductive portion is multiplexed as the first fourth conductive portion;

[0555] The first third conductive portion is used as a first electrode of the first transistor, the second third conductive portion is used as a second electrode of the first transistor; and the second fourth conductive portion is used as a second electrode of the second transistor.

[0556] In a specific implementation, the plate of the output capacitor coupled to the second electrode of the first transistor may be the second plate of the output capacitor; the specific steps of manufacturing the output capacitor include:

[0557] Performing a patterning process on the first gate metal layer to form a second electrode plate of the output capacitor;

[0558] Manufacturing a second gate metal layer on a side of the first gate metal layer facing away from the second semiconductor layer, and performing a patterning process on the second gate metal layer to form a first electrode plate of the output capacitor;

[0559] Manufacturing a source-drain metal layer on a side of the second gate metal layer facing away from the first gate metal layer, and patterning the source-drain metal layer to form a plate conductive connection portion, the first voltage signal line, and the second voltage signal line;

[0560] The orthographic projection of the first electrode plate of the output capacitor on the substrate has a signal line overlapping area with the orthographic projection of the first voltage signal line on the substrate, and the first electrode plate of the output capacitor is coupled to the first voltage signal line through at least one signal line via hole arranged in the signal line overlapping area;

[0561] The orthographic projection of the plate conductive connection portion on the substrate has a plate overlapping area with the orthographic projection of the second plate of the output capacitor on the substrate, and the plate conductive connection portion is coupled to the second plate of the output capacitor through at least one plate via arranged in the plate overlapping area.

[0562] In at least one embodiment of the present invention, the active layer of the first transistor and the active layer of the second transistor can be formed by a continuous second semiconductor layer; the second semiconductor layer extends along the first direction; the active layer of the first transistor includes a first third conductive part, a third channel part and a second third conductive part arranged in sequence along the first direction; the second third conductive part is reused as a first fourth conductive part; the active layer of the second transistor includes the first fourth conductive part, a fourth channel part and a second fourth conductive part arranged in sequence along the first direction; the first third conductive part is used as a first electrode of the first transistor, the second third conductive part is used as a second electrode of the first transistor; the second fourth conductive part is used as a second electrode of the second transistor. In at least one embodiment of the present invention, the second transistor is arranged between the first transistor and the first capacitor, and the second electrode of the first transistor is reused as the second electrode of the second transistor, so as to reduce the vertical height of the shift register unit while narrowing the lateral width of the shift register unit.

[0563] Optionally, the at least one shift register unit may further include a first capacitor, and at least two transistors coupled to a second plate of the first capacitor; the method for manufacturing the display substrate may further include:

[0564] On a side of the first voltage signal line away from the second voltage signal line, the first capacitor and the at least two transistors are manufactured;

[0565] A maximum distance in the second direction between an orthographic projection of the gates of the at least two transistors on the substrate and an orthographic projection of the first voltage signal line on the substrate is smaller than a third predetermined distance.

[0566] In a specific implementation, since the transistor coupled to the second plate of the first capacitor is also coupled to the first voltage signal line, the position of the transistor coupled to the second plate of the first capacitor is preferably close to the first voltage signal line. At least one embodiment of the present invention sets the maximum distance in the second direction between the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate to be less than the third predetermined distance, so as to narrow the lateral width of the shift register unit.

[0567] In a specific implementation, the at least two transistors include a first capacitor-connected transistor and a second capacitor-connected transistor;

[0568] The specific steps of manufacturing the first capacitor-connected transistor and the second capacitor-connected transistor include:

[0569] forming an active layer of the first capacitor-connected transistor and an active layer of the second capacitor-connected transistor on the substrate;

[0570] A first gate metal layer is formed on a side of the active layer facing away from the substrate, and the first gate metal layer is patterned to form a gate of the first capacitor connected to the transistor, a gate of the second capacitor connected to the transistor, and a second electrode plate of the first capacitor, and the gate of the first capacitor connected to the transistor and the gate of the second capacitor connected to the transistor are respectively coupled to the second electrode plate of the first capacitor;

[0571] Using the gate of the first capacitor-connected transistor and the gate of the second capacitor-connected transistor as masks, doping the portion of the active layer not covered by the gate, so that the portion of the active layer not covered by the gate forms a conductive portion, and the portion of the active layer covered by the gate forms a channel portion; the active layer of the first capacitor-connected transistor includes a first first capacitor-connected conductive portion, a first capacitor-connected channel portion, and a second first capacitor-connected conductive portion sequentially arranged along a first direction; the active layer of the second capacitor-connected transistor includes a first seventh conductive portion, a seventh channel portion, and a second seventh conductive portion sequentially arranged along the first direction; the first first capacitor-connected conductive portion is used as a first electrode of the first capacitor-connected transistor, and the second first capacitor-connected conductive portion is used as a second electrode of the first capacitor-connected transistor;

[0572] Forming a second gate metal layer on a side of the first gate metal layer facing away from the active layer, and performing a patterning process on the second gate metal layer to form a first electrode plate of the first capacitor;

[0573] Manufacturing a source-drain metal layer on a side of the second gate metal layer facing away from the first gate metal layer, and patterning the source-drain metal layer to form the first voltage signal line, the second voltage signal line and a first conductive connection portion;

[0574] There is a fifth overlapping area between the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the first electrode plate of the first capacitor on the substrate, and the first conductive connection portion is coupled to the first electrode plate of the first capacitor through at least one fifth via hole arranged in the fifth overlapping area.

[0575] In at least one embodiment of the present invention, the first seventh conductive portion may be used as the second capacitor connected to the second electrode of the transistor, the second seventh conductive portion may be used as the second capacitor connected to the first electrode of the transistor, and the first electrode of the second capacitor connected to the transistor is coupled to the first voltage signal line;

[0576] The distance in the second direction between the orthographic projection of the gate of the first capacitor-connected transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate is smaller than the distance in the second direction between the orthographic projection of the gate of the second capacitor-connected transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate.

[0577] In a specific implementation, the distance in the second direction between the orthographic projection of the gate of the first capacitor-connected transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate is smaller than the distance in the second direction between the orthographic projection of the gate of the second capacitor-connected transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate, that is, the second capacitor-connected transistor is arranged on a side of the first capacitor-connected transistor away from the first voltage signal line.

[0578] In a preferred case, the longest distance between the gate of the first capacitor-connected transistor and the gate of the second capacitor-connected transistor in the second direction is less than a fourth predetermined distance;

[0579] The orthographic projection of the first electrode plate of the first capacitor on the substrate is within the orthographic projection of the second electrode plate of the first capacitor on the substrate;

[0580] The first electrode plate of the first capacitor is L-shaped.

[0581] In at least one embodiment of the present invention, the first capacitor connection transistor and the second capacitor connection transistor are arranged to be close to each other so that the shape of the electrode plate of the first capacitor can be adjusted, and the first electrode plate of the first capacitor is arranged to be L-shaped, so that the routing space between the gate of the second capacitor connection transistor and the second conductive connection part is fully utilized, so that the layout is more reasonable, the lateral width of the shift register unit is effectively narrowed, and the longitudinal height of the shift register unit is reduced.

[0582] Optionally, the at least one shift register unit may further include a first node control transistor and a second capacitor;

[0583] The steps of manufacturing the first node control transistor and the second capacitor may include:

[0584] forming an active layer of the first node control transistor on the substrate while forming an active layer of the first capacitor connection transistor and an active layer of the second capacitor connection transistor on the substrate;

[0585] Performing a patterning process on the first gate metal layer to form a gate of the first node control transistor and a second plate of the second capacitor, and coupling the gate of the first node control transistor to the second plate of the second capacitor;

[0586] Using the gate of the first node control transistor as a mask, doping a portion of the active layer of the first node control transistor that is not covered by the gate of the first node control transistor;

[0587] Performing a patterning process on the second gate metal layer to form a first electrode plate of the second capacitor, and making an orthographic projection of the first electrode plate of the second capacitor on the substrate within an orthographic projection of the second electrode plate of the second capacitor on the substrate; the first electrode plate of the second capacitor is L-shaped;

[0588] The first electrode plate of the second capacitor includes a second horizontal electrode plate portion; the orthographic projection of the gate of the first node control transistor on the substrate and the orthographic projection of the second horizontal electrode plate portion on the substrate are arranged along a first direction.

[0589] In at least one embodiment of the present invention, the first plate of the second capacitor is set to be L-shaped, and the horizontal plate portion included in the first plate of the second capacitor is placed in the space between the first node control transistor and the adjacent next-stage shift register unit to narrow the lateral width of the shift register unit.

[0590] Optionally, the method for manufacturing a display substrate according to at least one embodiment of the present invention may further include:

[0591] Performing a patterning process on the source-drain metal layer to form a third voltage signal line extending along the first direction;

[0592] The first node control transistor is located at a side of the second capacitor connection transistor away from the first voltage signal line; the first node control transistor is located between the third voltage signal line and the first voltage signal line;

[0593] The first electrode plate of the second capacitor further includes a second vertical electrode plate portion coupled to the second horizontal electrode plate portion; an orthographic projection of the second vertical electrode plate portion on the substrate partially overlaps with an orthographic projection of the third voltage signal line on the substrate.

[0594] Specifically, the first plate of the second capacitor is set to be L-shaped, and the orthographic projection of the second vertical plate portion of the second capacitor on the substrate partially overlaps with the orthographic projection of the third voltage signal line on the substrate to reduce the vertical height of the shift register unit.

[0595] Optionally, the number of the first voltage signal line is one; the output circuit includes an output reset transistor; the at least one shift register unit also includes an output capacitor, a first plate and a second capacitor connection transistor; the manufacturing method of the display substrate also includes:

[0596] The first electrode of the output reset transistor, the first plate of the output capacitor, the first electrode of the first transistor and the first electrode of the second capacitor connection transistor are arranged to be coupled to the first voltage signal line to reduce the number of voltage signal lines used and facilitate layout.

[0597] A display device according to at least one embodiment of the present invention includes the above-mentioned display substrate.

[0598] Since the display substrate provided in the above embodiment can achieve a narrow frame, the display device provided in at least one embodiment of the present invention can also achieve the beneficial effect of having a narrow frame when including the above display substrate, which will not be described in detail here.

[0599] The display device provided in at least one embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0600] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0601] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0602] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0603] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: The present invention comprises a scanning driving circuit and a display area disposed on a substrate, wherein the scanning driving circuit comprises a plurality of shift register units, and the scanning driving circuit further comprises a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line; the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line extend along a first direction; the display area comprises at least one driving transistor, and the driving transistor is configured to drive a light emitting element to display; At least one shift register unit among the plurality of shift register units comprises an output circuit and a signal output line; the output circuit is coupled to the first voltage signal line, the second voltage signal line and the signal output line respectively; the signal output line extends along a second direction, and the first direction intersects with the second direction; The output circuit includes a transistor disposed between the first voltage signal line and the second voltage signal line; The at least one shift register unit further comprises a first transistor; The first transistor is disposed on a side of the first voltage signal line away from the second voltage signal line.

2. The display substrate according to claim 1, wherein: The output circuit includes an output transistor and an output reset transistor; the display substrate also includes a third voltage signal line; The output reset transistor and the output transistor are arranged along a first direction; The first transistor is disposed between the output reset transistor and the third voltage signal line.

3. The display substrate according to claim 1, wherein: The at least one shift register unit further comprises a second transistor; The active layer of the first transistor and the active layer of the second transistor are formed by a continuous second semiconductor layer; the second semiconductor layer extends along a first direction.

4. The display substrate according to claim 1, wherein: The at least one shift register unit further comprises a first capacitor and a first capacitor connecting transistor; The orthographic projection of the gate of the first capacitor connection transistor on the substrate is arranged between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate.

5. The display substrate according to claim 1, wherein: The at least one shift register unit further includes a first capacitor and a first capacitor connecting transistor; the display substrate further includes a third voltage signal line; At least a portion of the first capacitor is disposed between the third voltage signal line and the first capacitor connection transistor.

6. The display substrate according to claim 1, wherein: The at least one shift register unit further comprises a first capacitance-connected transistor and a second capacitance-connected transistor; The first capacitor-connected transistor and the second capacitor-connected transistor are arranged in sequence along a second direction.

7. The display substrate according to claim 1, wherein: The at least one shift register cell further comprises an input transistor and a second node control transistor; The first transistor, the input transistor and the second node control transistor are arranged in sequence along a second direction.

8. The display substrate according to claim 1, wherein: The at least one shift register unit further comprises a first node control transistor and a second capacitor; The orthographic projection of the first electrode plate of the second capacitor on the substrate is within the orthographic projection of the second electrode plate of the second capacitor on the substrate; The first plate of the second capacitor includes a second horizontal plate portion; An orthographic projection of the gate of the first node control transistor on the substrate and an orthographic projection of the second horizontal plate portion on the substrate are arranged along a first direction.

9. The display substrate according to claim 1, wherein: The first voltage signal line provides a first voltage to the output circuit, and the second voltage signal line provides a second voltage to the output circuit, wherein the first voltage is higher than the second voltage.

10. The display substrate according to claim 1, wherein: The signal output line is located between output circuits in adjacent shift register units.

11. The display substrate according to claim 1, wherein: The first voltage signal line is located at a side of the second voltage signal line away from the display area.

12. The display substrate according to claim 2, wherein: The first electrode of the output reset transistor is coupled to the first voltage signal line, and the first electrode of the output transistor is coupled to the second voltage signal line; A second electrode of the output transistor and a second electrode of the output reset transistor are both coupled to the signal output line.

13. The display substrate according to claim 12, wherein: The active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer; The first semiconductor layer and the signal output line are arranged along a first direction.

14. The display substrate according to claim 12, wherein: The gate of the output reset transistor includes at least one output reset gate pattern, the first electrode of the output reset transistor includes at least one first electrode pattern, and the second electrode of the output reset transistor includes at least one second electrode pattern; The output reset gate pattern is located between the adjacent first electrode pattern and the second electrode pattern; The second electrode pattern, the output reset gate pattern and the first electrode pattern all extend along a second direction; The first direction intersects the second direction.

15. The display substrate according to claim 12, wherein: The gate of the output transistor includes at least one output gate pattern, the first electrode of the output transistor includes at least one third electrode pattern, and the second electrode of the output transistor includes at least one fourth electrode pattern; The output gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern; The fourth electrode pattern, the output gate pattern and the third electrode pattern all extend along the second direction; The first direction intersects the second direction; The second electrode pattern in the output reset transistor that is closest to the gate of the output transistor is multiplexed as a fourth electrode pattern of the output transistor.

16. The display substrate according to claim 14, wherein: The active layer of the output reset transistor includes at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each first channel portion is arranged between two adjacent first conductive portions; The first channel portions correspond to the output reset gate patterns one by one, and the orthographic projection of each of the first channel portions on the substrate is located inside the orthographic projection of the corresponding output reset gate pattern on the substrate; A portion of the first conductive portions in the output reset transistor corresponds to the first electrode pattern one by one, an orthographic projection of the first electrode pattern on the substrate and an orthographic projection of the corresponding first conductive portion on the substrate have a first overlapping area, and the first electrode pattern is coupled to the corresponding first conductive portion through at least one first via hole provided in the first overlapping area; Another part of the first conductive portion in the output reset transistor corresponds one-to-one to the second electrode pattern, and an orthographic projection of the second electrode pattern on the substrate has a second overlapping area with an orthographic projection of the corresponding first conductive portion on the substrate, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via hole arranged in the second overlapping area.

17. The display substrate according to claim 15, wherein: The active layer of the output transistor comprises at least two second conductive portions arranged opposite to each other along a first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions; The second channel portions correspond to the output gate patterns one by one, and the orthographic projection of each of the second channel portions on the substrate is located inside the orthographic projection of the corresponding output gate pattern on the substrate; A part of the second conductive parts in the output transistor corresponds to the third electrode pattern one by one, an orthographic projection of the third electrode pattern on the substrate and an orthographic projection of the corresponding second conductive part on the substrate have a third overlapping area, and the third electrode pattern is coupled to the corresponding second conductive part through at least one third via hole arranged in the third overlapping area; Another part of the second conductive part in the output transistor corresponds one-to-one to the fourth electrode pattern, and the orthographic projection of the fourth electrode pattern on the substrate has a fourth overlapping area with the orthographic projection of the corresponding second conductive part on the substrate, and the fourth electrode pattern is coupled to the corresponding second conductive part through at least one fourth via hole arranged in the fourth overlapping area.

18. The display substrate according to claim 1, wherein: The number of the first voltage signal line is one; The output circuit includes an output reset transistor; the at least one shift register unit also includes an output capacitor and a second capacitor connection transistor; The first electrode of the output reset transistor, the first plate of the output capacitor, the first electrode of the first transistor and the first electrode of the second capacitor connection transistor are all coupled to the first voltage signal line.

19. The display substrate according to claim 18, wherein: The display substrate further includes a third voltage signal line, and the first voltage signal line is located between the second voltage signal line and the third voltage signal line.

20. The display substrate according to claim 18, wherein: The first electrode of the second capacitor-connected transistor is coupled to the signal line conductive connection portion through a fifth connection via, and the signal line conductive connection portion is coupled to the first voltage signal line, so that the first electrode of the second capacitor-connected transistor is coupled to the first voltage signal line; The signal line conductive connection portion and the first voltage signal line are included in a source-drain metal layer, and the second capacitor is connected to a first electrode of a transistor included in an active layer.

21. The display substrate according to claim 20, wherein: The at least one shift register unit further comprises a first capacitor; The orthographic projection of the signal line conductive connection portion on the substrate partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate.

22. The display substrate according to claim 18, wherein: The orthographic projection of the first plate of the output capacitor on the substrate has a signal line overlapping area with the orthographic projection of the first voltage signal line on the substrate, and the first plate of the output capacitor is coupled to the first voltage signal line through at least one signal line via arranged in the signal line overlapping area.

23. The display substrate according to claim 8, wherein: The scan driving circuit further comprises a third voltage signal line; the third voltage signal line extends along a first direction; the third voltage signal line is located on a side of the first voltage signal line away from the second voltage signal line; the first node control transistor is located between the third voltage signal line and the first voltage signal line; The first plate of the second capacitor further includes a second vertical plate portion coupled to the second horizontal plate portion; An orthographic projection of the second vertical plate portion on the substrate partially overlaps with an orthographic projection of the third voltage signal line on the substrate.

24. The display substrate according to claim 23, wherein: The first clock signal line is located at a side of the third voltage signal line away from the first voltage signal line; The output circuit includes an output transistor; the at least one shift register unit also includes a second conductive connection portion disposed between a gate of the output transistor and a second plate of the second capacitor; the second conductive connection portion is coupled to the gate of the output transistor and the second plate of the second capacitor, respectively; The at least one shift register unit further includes a third conductive connection portion coupled to the second plate of the second capacitor; The orthographic projection of the third conductive connection portion on the substrate and the orthographic projection of the first clock signal line on the substrate have a sixth overlapping area, and the first clock signal line is coupled to the first plate of the second capacitor through at least one sixth via hole arranged in the sixth overlapping area.

25. The display substrate according to claim 8, wherein: The at least one shift register unit further comprises a second node control transistor; the at least one shift register unit comprises a second capacitor connection transistor; the at least one shift register unit further comprises an input transistor; The first electrode of the input transistor is coupled to the input signal terminal The second electrode of the second node control transistor is coupled to the second electrode of the first node control transistor via a fourth conductive connection portion; The at least one shift register unit further comprises a fifth conductive connection portion coupled to the gate of the second capacitance connection transistor; There is a seventh overlapping area between the orthographic projection of the fifth conductive connection portion on the substrate and the orthographic projection of the fourth conductive connection portion on the substrate; The fifth conductive connection portion is coupled to the fourth conductive connection portion through a seventh via hole disposed in the seventh overlapping region.

26. The display substrate according to claim 25, characterized in that: The scan driving circuit further comprises a third voltage signal line; the third voltage signal line is located at a side of the first voltage signal line away from the second voltage signal line; The first electrode of the first node control transistor is coupled to the sixth conductive connection portion; the gate of the second node control transistor is coupled to the seventh conductive connection portion; There is an eighth overlapping region between the orthographic projection of the sixth conductive connection portion on the substrate and the orthographic projection of the seventh conductive connection portion on the substrate, and the sixth conductive connection portion is coupled to the seventh conductive connection portion through an eighth via hole disposed within the eighth overlapping region; A first electrode of the second node control transistor is coupled to the third voltage signal line.

27. The display substrate according to claim 25, wherein: The gate of the second node control transistor is also coupled to the eighth conductive connection portion; there is a ninth overlapping area between the orthographic projection of the eighth conductive connection portion on the substrate and the orthographic projection of the second clock signal line on the substrate, and the eighth conductive connection portion is coupled to the second clock signal line through a ninth via hole arranged in the ninth overlapping area.

28. The display substrate according to claim 1, wherein: The scan driving circuit further includes a third voltage signal line; the third voltage signal line extends along the first direction; The second clock signal line is arranged between the first clock signal line and the third voltage signal line; or the first clock signal line is arranged between the second clock signal line and the third voltage signal line.

29. The display substrate according to claim 8, wherein: The at least one shift register unit further comprises a third node control transistor, a second capacitance connection transistor and an input transistor; The active layer of the third node control transistor includes a first sixth conductive portion, a sixth channel portion and a second sixth conductive portion sequentially arranged along the first direction; The second sixth conductive portion is multiplexed as the first seventh conductive portion; The active layer of the second capacitor connection transistor includes a first seventh conductive portion, a seventh channel portion and a second seventh conductive portion which are sequentially arranged along the first direction.

30. The display substrate according to claim 1, wherein: The scan driving circuit further includes a third voltage signal line; The third voltage signal line extends along the first direction; The orthographic projection of the third voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate and the orthographic projection of the second clock signal line on the substrate are all located on a side of the orthographic projection of the shift register unit on the substrate away from the display area of ​​the display substrate.

31. The display substrate according to claim 12, wherein: The scan drive circuit further includes a third voltage signal line; the at least one shift register unit further includes an output capacitor, a first capacitor, a second capacitor, a first transistor, a second transistor, a first capacitor connection transistor, a second capacitor connection transistor, a first node control transistor, a second node control transistor, an input transistor, and a third node control transistor; The second electrode of the first transistor is coupled to the second plate of the output capacitor, and the first electrode of the first transistor is coupled to the first voltage signal line; A first electrode of the second transistor is coupled to a first plate of the first capacitor, a second electrode of the second transistor is coupled to a second electrode of the first capacitor connection transistor, and a gate of the second transistor is coupled to a gate of the third node control transistor; The gate of the first capacitor-connected transistor and the gate of the second capacitor-connected transistor are respectively coupled to the second plate of the first capacitor; the second electrode of the first capacitor-connected transistor is coupled to the first plate of the first capacitor; the first electrode of the first capacitor-connected transistor is coupled to the gate of the second transistor; The first electrode of the second capacitor-connected transistor is coupled to the first voltage signal line; the gate of the second capacitor-connected transistor is coupled to the second electrode of the second node-controlled transistor; the second electrode of the second capacitor-connected transistor is coupled to the first electrode of the third node-controlled transistor; A second electrode of the second node control transistor is coupled to a second electrode of the first node control transistor; The gate of the second node control transistor is coupled to the second clock signal line; The first electrode of the second node control transistor is coupled to the third voltage signal line; The first electrode of the input transistor is coupled to the input signal terminal; the second electrode of the input transistor is coupled to the second plate of the second capacitor; The first plate of the output capacitor is coupled to the first voltage signal line, and the second plate of the output capacitor is coupled to the gate of the output reset transistor; The second plate of the second capacitor is coupled to the gate of the output transistor; A second electrode of the output transistor and a second electrode of the output reset transistor are both coupled to the signal output line.

32. The display substrate according to claim 31, wherein: Along the direction close to the display area, the first clock signal line, the second clock signal line and the third voltage signal line are arranged in sequence; or, along the direction close to the display area, the second clock signal line, the first clock signal line and the third voltage signal line are arranged in sequence.

33. The display substrate according to claim 31, wherein: The output transistor and the output reset transistor are arranged between the first voltage signal line and the second voltage signal line; along the first direction, the output reset transistor, the output transistor and the signal output line are arranged in sequence; The third voltage signal line is arranged on a side of the first voltage signal line away from the second voltage signal line; the first capacitor, the first transistor, the second transistor, the first capacitor connection transistor, the second capacitor connection transistor, the first node control transistor, the second node control transistor, the input transistor and the third node control transistor are all arranged between the first voltage signal line and the third voltage signal line; The second node control transistor and the first node control transistor are arranged in sequence along a first direction; The orthographic projection of the gate of the first capacitor connection transistor on the substrate is arranged between the orthographic projection of the second electrode plate of the first capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate; The orthographic projection of the gate of the second transistor on the substrate is arranged between the orthographic projection of the gate of the third node control transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate; The orthographic projection of the gate of the first node control transistor on the substrate is arranged between the orthographic projection of the third voltage signal line on the substrate and the orthographic projection of the first plate of the first capacitor on the substrate.

34. The display substrate according to claim 33, wherein: The orthographic projection of the first electrode plate of the output capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate have a signal line overlapping area; the orthographic projection of the second electrode plate of the output capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate partially overlap; The orthographic projection of the first electrode plate of the second capacitor on the substrate is within the orthographic projection of the second electrode plate of the second capacitor on the substrate; The gate of the first node control transistor and the second horizontal plate portion included in the first plate of the second capacitor are arranged along a first direction; The orthographic projection of the second vertical plate portion included in the first electrode plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the third voltage signal line on the substrate.

35. The display substrate according to claim 1, wherein: The display substrate further comprises a plurality of rows of pixel circuits arranged on the base; the pixel circuits comprise a light emitting control terminal; The shift register unit included in the scanning driving circuit corresponds to the row pixel circuit one by one The signal output line of the shift register unit is coupled to the light emitting control terminal of the corresponding row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control terminal of the corresponding row of pixel circuits.

36. A display substrate, characterized in that: The present invention comprises a scanning driving circuit and a display area disposed on a substrate, wherein the scanning driving circuit comprises a plurality of shift register units, and the scanning driving circuit further comprises a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line; the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line extend along a first direction; the display area comprises at least one driving transistor, and the driving transistor is configured to drive a light emitting element to display; At least one shift register unit among the plurality of shift register units comprises an output circuit and a signal output line; the output circuit is coupled to the first voltage signal line, the second voltage signal line and the signal output line respectively; the signal output line extends along a second direction, and the first direction intersects with the second direction; The output circuit includes a transistor disposed between the first voltage signal line and the second voltage signal line; The at least one shift register unit further comprises a first transistor; The first transistor is arranged on a side of the first voltage signal line away from the second voltage signal line; The at least one shift register unit further includes an output capacitor; an orthographic projection of a first electrode plate of the output capacitor on the substrate and an orthographic projection of the first voltage signal line on the substrate have a signal line overlapping region.

37. The display substrate according to claim 36, wherein: The at least one shift register unit further comprises a second transistor; The first electrode of the second transistor is coupled to the second plate of the output capacitor.

38. The display substrate according to claim 36, wherein: The output circuit includes an output reset transistor; The orthographic projection of the second electrode plate of the output capacitor on the substrate partially overlaps with the orthographic projection of the first voltage signal line on the substrate; The first plate of the output capacitor is coupled to the first voltage signal line, and the second plate of the output capacitor is coupled to the gate of the output reset transistor; The first plate of the output capacitor is coupled to the first voltage signal line through at least one signal line via disposed in the signal line overlapping area.

39. The display substrate according to claim 38, wherein: The at least one shift register unit further comprises a third node control transistor; The second electrode of the first transistor is coupled to the second plate of the output capacitor, the first electrode of the first transistor is coupled to the first voltage signal line, and the gate of the first transistor is coupled to the second electrode of the third node control transistor; The first plate of the output capacitor is coupled to the first voltage signal line, and the second plate of the output capacitor is coupled to the gate of the output reset transistor.

40. A method for manufacturing a display substrate, characterized in that: The method comprises manufacturing a scan driving circuit on a substrate and manufacturing at least one driving transistor in a display area included in a display substrate; the driving transistor is configured to drive a light emitting element to display; The scan driving circuit comprises a plurality of shift register units, a first voltage signal line, a second voltage signal line, a first clock signal line and a second clock signal line, at least one shift register unit among the plurality of shift register units comprises an output circuit and a signal output line; the at least one shift register unit further comprises a first transistor; The method for manufacturing the display substrate further includes: The transistor included in the output circuit is fabricated between the first voltage signal line and the second voltage signal line; The first voltage signal line, the second voltage signal line, the first clock signal line and the second clock signal line are arranged to extend along a first direction, and the signal output line is arranged to extend along a second direction; The first direction and the second direction intersect; The first transistor is disposed on a side of the first voltage signal line away from the second voltage signal line.

41. The method for manufacturing a display substrate according to claim 40, wherein: The output circuit includes an output transistor and an output reset transistor; the display substrate also includes a third voltage signal line; the manufacturing method of the display substrate also includes: Arrange the output reset transistor and the output transistor along a first direction; The first transistor is disposed between the output reset transistor and the third voltage signal line.

42. A display device, characterized in that: The display substrate comprises a display substrate as claimed in any one of claims 1 to 39.

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