Display panel, display module and electronic equipment

Abstract

The embodiment of the invention discloses a display panel, a display module and electronic equipment, relates to the technical field of display, and is used for reducing the size of a frame and reducing power consumption. The display panel comprises a pixel circuit located in a display area, and a first shift register and a second shift register which are located in a frame area. The pixel circuit comprises a data write-in circuit, a driving circuit and a compensating circuit, and transistors included in the data write-in circuit and the compensating circuit are metal oxide thin film transistors. The first shift register is electrically connected with the data write-in circuit of the row of pixel circuits. The first shift register is configured to provide a first scan signal to the connected data write circuit. The data write circuit is configured to be turned on in response to a first scan signal. The second shift register is electrically connected with the compensation circuit of at least one row of pixel circuits. The second shift register is configured to provide a second scanning signal to the connected compensation circuit. The compensation circuit is configured to be turned on in response to a second scan signal.

Description

[0001] This application claims the priority of Chinese patent application filed on January 22, 2025, with application number 202510106193.7 and application name “Display panel, display module and electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel, a display module and an electronic device. Background Art

[0003] The scan drive circuit is an important component of the display panel. The scan drive circuit may include a cascaded multi-stage shift register, which may be electrically connected to multiple lines in the display panel, such as gate lines, enable signal lines or reset signal lines, to input scan signals to the multiple lines in the display panel, so that the pixel circuit in the display panel can drive the light-emitting device electrically connected thereto to emit light, thereby enabling the display panel to display images.

[0004] However, the same pixel circuit usually needs to be connected to multiple shift registers, which not only easily increases the frame size of the display panel, but also easily increases the power consumption of the display panel. Summary of the invention

[0005] Embodiments of the present application provide a display panel, a display module, and an electronic device, which are used to reduce the frame size of the display panel and reduce the power consumption of the display panel.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a display panel is provided, which has a display area and a frame area, wherein the frame area is located at least on two sides outside the display area, and the display panel includes: a plurality of rows of pixel circuits located in the display area, and a first shift register and a second shift register located in the frame area. Each row of pixel circuits includes a data writing circuit, a driving circuit and a compensation circuit, wherein the data writing circuit is electrically connected to the driving circuit and the data signal terminal, and the driving circuit is electrically connected to the compensation circuit. The transistors included in the data writing circuit and the compensation circuit are all metal oxide thin film transistors. The first shift register is electrically connected to the data writing circuit of a row of pixel circuits. The first shift register is configured to provide a first scanning signal to the data writing circuit of the pixel circuit connected to the first shift register. The data writing circuit is configured to be turned on in response to the first scanning signal, and transmit the data signal from the data signal terminal to the compensation circuit. The second shift register is electrically connected to the compensation circuit of at least one row of pixel circuits. The second shift register is configured to provide a second scanning signal to the compensation circuit of the pixel circuit connected to the second shift register. The compensation circuit is configured to be turned on in response to the second scanning signal, and transmit the data signal to the driving circuit.

[0008] In the display panel provided by some embodiments of the present application, a first shift register and a second shift register are provided so that the first shift register is electrically connected to a data writing circuit located in the same row of pixel circuits, and the second shift register is electrically connected to a compensation circuit located in at least one row of pixel circuits, and the transistors included in the data writing circuit and the compensation circuit are provided as metal oxide transistors. Thus, on the one hand, leakage can be reduced by the data writing circuit and the compensation circuit, the potential of the relevant nodes inside the pixel circuit can be maintained, and the power consumption caused by leakage can be reduced; on the other hand, it is beneficial to reduce the load of the first shift register and the second shift register, and the first shift register and the second shift register can cooperate with each other to more flexibly control the display panel to display the picture; on the other hand, in the case that the display panel is a small or medium-sized display panel, the first shift register can be provided in a unilateral driving manner, thereby reducing the number of shift registers used to drive the pixel circuit, for example, reducing the number of first shift registers used to drive the data writing circuit, and correspondingly reducing the number of gate driving circuits, so that on the basis of reducing the power consumption caused by more gate driving circuits, the space occupied by the gate driving circuit can be reduced, the frame size of the display panel can be reduced, and the narrow frame design of the display panel can be realized.

[0009] In a possible design of the first aspect, the first shift register is located on a side outside the display area, and / or the second shift register is located on a side outside the display area. This can improve the flexibility of the arrangement of the first shift register and the second shift register, and is applicable to more types of display panels.

[0010] In a possible design of the first aspect, the above-mentioned row of pixel circuits is electrically connected to a first shift register, and the above-mentioned at least one row of pixel circuits is electrically connected to a second shift register. Along the row direction of the multiple rows of pixel circuits, the first shift register and the second shift register are respectively located on both sides outside the display area. In this case, the display panel is, for example, a small or medium-sized display panel. In this way, along the row direction of the multiple rows of pixel circuits, the number of gate drive circuits belonging to the shift registers on both sides outside the display area can be balanced, so that the widths of the border areas on both sides outside the display area are the same or approximately the same, and it is beneficial to the wiring arrangement of the border area.

[0011] In a possible design of the first aspect, the above-mentioned row of pixel circuits is electrically connected to two first shift registers, and the above-mentioned at least one row of pixel circuits is electrically connected to two second shift registers. Along the row direction of the multiple rows of pixel circuits, the two first shift registers are respectively located on both sides outside the display area, and the two second shift registers are respectively located on both sides outside the display area. In this case, the display panel is, for example, a large-size display panel. The use of a bilateral drive method is not only conducive to reducing the load of the first shift register and the second shift register, but also conducive to improving the display uniformity of the display panel.

[0012] In a possible design method of the first aspect, the data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor, and the first transistor and the third transistor are both metal oxide thin film transistors. Among them, the control electrode of the first transistor is electrically connected to the first shift register, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor. The control electrode of the third transistor is electrically connected to the second shift register. In this way, it is conducive to simplifying the structure of the data writing circuit, the driving circuit and the compensation circuit, and reducing the structural complexity and preparation difficulty of the display panel.

[0013] In a possible design mode of the first aspect, the pixel circuit further includes a first reset circuit, which is electrically connected to the drive circuit, the compensation circuit and the first initial signal terminal, and the transistor included in the first reset circuit is a metal oxide thin film transistor. The first shift register is also electrically connected to the first reset circuit of a row of pixel circuits. The first shift register is also configured to provide a first scan signal to the first reset circuit of each pixel circuit connected to the first shift register. The first reset circuit is configured to be turned on in response to the first scan signal, and transmit the first initial signal from the first initial signal terminal to the drive circuit and the compensation circuit. Among them, the pixel circuits to which the first reset circuit and the data writing circuit connected to the same first shift register belong are located in different rows. In this way, on the one hand, it is conducive to reducing the leakage of the first reset circuit and maintaining the potential of the corresponding node in the pixel circuit; on the other hand, the number of shift registers electrically connected to the pixel circuit can be further reduced, and accordingly, the number of gate drive circuits electrically connected to the pixel circuit can be further reduced, and then on the basis of further reducing the power consumption caused by more gate drive circuits, the space occupied by the gate drive circuit can be further reduced, and the frame size of the display panel can be reduced, so as to facilitate the narrow frame design of the display panel.

[0014] In a possible design of the first aspect, the pixel circuit to which the first reset circuit connected to the same first shift register belongs is located in the previous row of the pixel circuit to which the data writing circuit connected to the same first shift register belongs. That is, the same first shift register can provide the first scanning signal for two adjacent rows of pixel circuits. This facilitates the coordination with other shift registers to realize the driving of the pixel circuit, and is also conducive to simplifying the design of the driving timing of the pixel circuit.

[0015] In a possible design of the first aspect, the first reset circuit includes a fourth transistor, which is a metal oxide thin film transistor. The control electrode of the fourth transistor is electrically connected to the first shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the drive circuit and the compensation circuit. This is conducive to simplifying the structure of the first reset circuit and reducing the structural complexity and manufacturing difficulty of the display panel.

[0016] In a second aspect, a display panel is provided, which includes a display area and a frame area, and the frame area is located on at least two sides outside the display area. In addition, the display panel includes: a plurality of rows of pixel circuits located in the display area and a first shift register located in the frame area. Each row of pixel circuits includes a data write circuit, a drive circuit and a compensation circuit, and the data write circuit is electrically connected to the drive circuit and the data signal end, and the drive circuit is electrically connected to the compensation circuit. The data write circuit and the compensation circuit both include metal oxide thin film transistors. The first shift register is electrically connected to the data write circuit and the compensation circuit of a row of pixel circuits. The first shift register is configured to provide a first scan signal to the data write circuit and the compensation circuit of the pixel circuit connected to the first shift register. The data write circuit and the compensation circuit are configured to be turned on in response to the first scan signal, and transmit the data signal from the data signal end to the drive circuit.

[0017] The display panel provided in some embodiments of the present application is configured such that the transistors included in the data writing circuit and the compensation circuit are configured as metal oxide transistors, and a first shift register is configured such that the first shift register is electrically connected to the data writing circuit and the compensation circuit located in the same row of pixel circuits. This can not only reduce leakage through the data writing circuit and the compensation circuit, maintain the potential of related nodes inside the pixel circuit, and reduce power consumption caused by leakage; it can also reduce the number of shift registers electrically connected to the pixel circuit through sharing the first shift register, and correspondingly reduce the number of gate driving circuits. This can reduce the space occupied by the gate driving circuit and reduce the border size of the display panel on the basis of reducing power consumption caused by more gate driving circuits, thereby facilitating the realization of a narrow border design for the display panel.

[0018] In a possible design mode of the second aspect, the data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor, and the first transistor and the third transistor are both metal oxide thin film transistors. The control electrode of the first transistor is electrically connected to the first shift register, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor. The control electrode of the third transistor is electrically connected to the first shift register.

[0019] In a possible design mode of the second aspect, the pixel circuit further includes a first reset circuit, which is electrically connected to the drive circuit, the compensation circuit and the first initial signal terminal; the first reset circuit includes a metal oxide thin film transistor. The display panel further includes a second shift register located in the frame area, which is electrically connected to the first reset circuit of at least one row of pixel circuits; the second shift register is configured to provide a second scanning signal to the first reset circuit of the pixel circuit connected to the second shift register; the first reset circuit is configured to be turned on in response to the second scanning signal, and transmit the first initial signal from the first initial signal terminal to the drive circuit and the compensation circuit. By setting the second shift register to be electrically connected to the first reset circuit, it is beneficial to reduce the load of the second shift register, and more flexibly control the display panel to display the picture.

[0020] In a possible design of the second aspect, the first shift register is located on a side outside the display area, and / or the second shift register is located on a side outside the display area. This can improve the flexibility of the arrangement of the first shift register and the second shift register, and is applicable to more types of display panels.

[0021] In a possible design of the second aspect, the above-mentioned row of pixel circuits is electrically connected to a first shift register, and the above-mentioned at least one row of pixel circuits is electrically connected to a second shift register. Along the row direction of the multiple rows of pixel circuits, the first shift register and the second shift register are respectively located on both sides outside the display area. In this case, the display panel is, for example, a small or medium-sized display panel. In this way, along the row direction of the multiple rows of pixel circuits, the number of gate drive circuits belonging to the shift registers on both sides outside the display area can be balanced, so that the widths of the border areas on both sides of the display area are the same or approximately the same, and it is beneficial to the wiring arrangement of the border area.

[0022] In a possible design of the second aspect, the above-mentioned row of pixel circuits is electrically connected to two first shift registers, and the above-mentioned at least one row of pixel circuits is electrically connected to two second shift registers. Along the row direction of the multiple rows of pixel circuits, the two first shift registers are respectively located on both sides outside the display area, and the two second shift registers are respectively located on both sides outside the display area. In this case, the display panel is, for example, a large-size display panel. The use of a bilateral drive method is not only conducive to reducing the load of the first shift register and the second shift register, but also conducive to improving the display uniformity of the display panel.

[0023] In a possible design mode of the second aspect, the first reset circuit includes a fourth transistor, which is a metal oxide thin film transistor. The control electrode of the fourth transistor is electrically connected to the second shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the drive circuit and the compensation circuit. This is conducive to simplifying the structure of the first reset circuit and reducing the structural complexity and manufacturing difficulty of the display panel.

[0024] In a possible design of the first aspect or the second aspect, the second transistor is a metal oxide thin film transistor. This can improve the crystallization uniformity of the active layer of the second transistor and improve the uniformity of the characteristics of the second transistor. Alternatively, the second transistor is a low temperature polycrystalline silicon thin film transistor. This can make the second transistor have a higher electron mobility.

[0025] In a possible design mode of the first aspect or the second aspect, the display panel further includes a light emitting device, a third shift register and a fourth shift register, the light emitting device is located in the display area, and the third shift register and the fourth shift register are located outside the display area. The pixel circuit further includes a light emitting control circuit, a second reset circuit and a third reset circuit. The light emitting control circuit is electrically connected to the first voltage signal terminal, the driving circuit, and the light emitting device, the second reset circuit is electrically connected to the second initial signal terminal and the light emitting device, and the third reset circuit is electrically connected to the third initial signal terminal and the driving circuit. Among them, the third shift register is electrically connected to the second reset circuit and the third reset circuit of at least one row of pixel circuits. The third shift register is configured to provide a third scan signal to the second reset circuit and the third reset circuit of the pixel circuit connected to the third shift register. The second reset circuit is configured to be turned on in response to the third scan signal, and the second initial signal from the second initial signal terminal is transmitted to the light emitting device. The third reset circuit is configured to be turned on in response to the third scan signal, and the third initial signal from the third initial signal terminal is transmitted to the driving circuit. The fourth shift register is electrically connected to the light emitting control circuit of at least one row of pixel circuits. The fourth shift register is configured to provide a fourth scan signal to the light emitting control circuit of the pixel circuit connected to the fourth shift register. The light emitting control circuit is configured to be turned on in response to the fourth scan signal to connect the path between the first voltage signal terminal and the light emitting device.

[0026] By setting a third reset circuit, the third initial signal can be used to adjust the output end of the third reset circuit, such as the second node or the first node, and the voltage difference between the third node, so that the driving circuit is in a biased state, and the problem of low frame rate flickering is improved when the display panel displays a low-brightness picture. By using the same third shift register to synchronously drive the second reset circuit and the second reset circuit of each pixel circuit in at least one row of pixel circuits, it is possible to avoid increasing the number of shift registers and avoid increasing power consumption and border size. In addition, by connecting the data write circuit and the second reset circuit to different shift registers, respectively, the conduction conditions of the data write circuit and the second reset circuit can be controlled respectively. In this way, the conduction frequency of the second reset circuit can be increased on the basis of meeting the control requirements of the data write circuit, which is conducive to achieving flicker-free frame rate switching within a higher frame rate range, such as 90Hz-120Hz.

[0027] In a possible design of the first aspect or the second aspect, the third shift register is located on a side outside the display area, and / or the fourth shift register is located on a side outside the display area. This can improve the flexibility of setting the third shift register and the fourth shift register, and is applicable to more types of display panels.

[0028] In a possible design of the first aspect or the second aspect, the at least one row of pixel circuits is electrically connected to a third shift register and a fourth shift register. Along the row direction of the multiple rows of pixel circuits, the third shift register and the fourth shift register are respectively located on both sides outside the display area. In this way, along the row direction of the multiple rows of pixel circuits, the number of shift registers on both sides of the display area and the gate drive circuits to which they belong can be balanced, so that the widths of the border areas on both sides outside the display area are the same or approximately the same, and are conducive to the wiring arrangement of the non-display area.

[0029] In a possible design of the first aspect or the second aspect, the at least one row of pixel circuits is electrically connected to two third shift registers and two fourth shift registers. Along the row direction of the multiple rows of pixel circuits, the two third shift registers are respectively located on two sides outside the display area, and the two fourth shift registers are respectively located on two sides outside the display area. The use of a bilateral drive method is conducive to improving the display uniformity of the display panel.

[0030] In a possible design mode of the first aspect or the second aspect, the light emitting control circuit includes a fifth transistor and a sixth transistor, the second reset circuit includes a seventh transistor, and the third reset circuit includes an eighth transistor. The control electrode of the fifth transistor is electrically connected to the fourth shift register, the first electrode of the fifth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the driving circuit. The control electrode of the sixth transistor is electrically connected to the fourth shift register, the first electrode of the sixth transistor is electrically connected to the driving circuit, and the second electrode of the sixth transistor is electrically connected to the light emitting device. The control electrode of the seventh transistor is electrically connected to the third shift register, the first electrode of the seventh transistor is electrically connected to the second initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the light emitting device. The control electrode of the eighth transistor is electrically connected to the third shift register, the first electrode of the eighth transistor is electrically connected to the third initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the driving circuit. In this way, it is conducive to simplifying the structure of the light emitting control circuit, the second reset circuit and the third reset circuit, and reducing the structural complexity and manufacturing difficulty of the display panel.

[0031] In a possible design of the first aspect or the second aspect, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all low-temperature polysilicon thin film transistors, which is beneficial to improving the electrical performance of the pixel circuit.

[0032] In a third aspect, a display module is provided, the display module comprising: a display panel as described in any one of the embodiments in the first aspect, and a display driver. The display driver is electrically connected to the display panel.

[0033] In a fourth aspect, an electronic device is provided, the electronic device comprising: a display module as described in any one of the embodiments in the third aspect, and a drive controller. The drive controller is coupled to the display module.

[0034] The technical effects brought about by any design method in the third aspect and the fourth aspect can refer to the technical effects brought about by different design methods in the first aspect or the second aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application;

[0036] Figure 2 A partial structural diagram of an electronic device provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of a gate drive circuit according to an embodiment of the present application;

[0038] Figure 4 An equivalent circuit diagram of a sub-pixel provided in an embodiment of the present application;

[0039] Figure 5 A timing diagram provided for an embodiment of the present application;

[0040] Figure 6 A partial structural diagram of a display panel provided in an embodiment of the present application;

[0041] Figure 7 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0042] Figure 8 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0043] Fig. 9 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0044] Fig.10 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0045] Fig.11 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0046] Fig.12 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0047] Fig.13 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0048] Fig.14 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0049] Fig.15 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0050] Fig.16 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0051] Fig.17 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0052] Fig.18 Another timing diagram provided for an embodiment of the present application;

[0053] Fig.19 Another timing diagram provided for an embodiment of the present application;

[0054] Fig. 20 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0055] Fig.21 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0056] Fig. 22 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0057] Fig.23 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0058] Fig.24 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0059] Fig.25 An equivalent circuit diagram of another sub-pixel provided in an embodiment of the present application;

[0060] Fig.26 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0061] Fig. 27 A partial structural diagram of another display panel provided in an embodiment of the present application;

[0062] Fig.28 Another timing diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0063] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0064] In the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one item" or similar expressions refers to any combination of these items, including any combination of a single item or plural items.

[0065] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0066] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "coupled" may, for example, indicate that two or more components are in direct physical or electrical contact, or it may mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The term "connected" should be understood in a broad sense, for example, "connected" can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other action "based on" one or more of the conditions or values ​​described may be based on additional conditions or values ​​beyond the described values ​​in practice.

[0067] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to being defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to the change in the orientation of the components in the drawings. In the drawings, for the sake of clarity, the thickness of the layers and regions is exaggerated, and the dimensional ratio relationship between the parts in the drawings does not reflect the actual dimensional ratio relationship. Therefore, changes in the shape relative to the drawings due to, for example, manufacturing technology and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the areas shown in the present application, but include shape deviations caused by, for example, manufacturing. For example, an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the areas of the device, and are not intended to limit the scope of the exemplary embodiments.

[0068] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0069] In the circuit structures provided in some embodiments of the present application, such as pixel circuits, the transistors used may be thin film transistors (TFT), field effect transistors (MOS) or other switching devices with the same characteristics. Further, the first electrode of each transistor used is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor may be symmetrical in structure, the source and drain thereof may be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in some embodiments of the present application may be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; or, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source. In addition, the control electrode of the transistor refers to, for example, the gate of the transistor.

[0070] In the circuit structures provided in some embodiments of the present application, such as pixel circuits, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0071] Some embodiments of the present application provide an electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. Among them, the consumer electronic product may be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, a personal computer (PC), a netbook, and a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device, etc., and the smart wearable device is, for example, a smart watch, a smart bracelet, and the embodiments of the present application do not impose any special restrictions on the specific type of the electronic device. Home electronic products may be smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances, etc., and rechargeable small household appliances may be, for example, soymilk machines and sweeping robots. Vehicle-mounted electronic products may be vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products may be ATM machines, self-service terminals, etc. The embodiments of the present application do not impose any special restrictions on the specific forms of the above-mentioned electronic devices.

[0072] For the sake of convenience, the following description is made using a straight-screen mobile phone as an example of an electronic device. This cannot be regarded as a specific limitation on the structural form of the electronic device. Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application, Figure 2 This is a partial structural diagram of an electronic device provided in an embodiment of the present application. Those skilled in the art can understand that: Figure 1 and Figure 2 The architecture of the electronic device shown in the figure does not constitute a limitation on the electronic device, and the electronic device may include, for example Figure 1 and Figure 2 More or fewer components may be shown, or they may be combined as shown. Figure 1 and Figure 2 Some of the components shown may be combined with Figure 1 and Figure 2 The components shown are arranged differently.

[0073] In some embodiments, Figure 1 As shown, the electronic device 1000 mainly includes: a display module 100 , a middle frame 200 , a housing 300 and a cover plate 400 .

[0074] Among them, the shell 300 is located on the backlight side of the display module 100. The middle frame 200 is located between the display module 100 and the shell 300. The side surface of the middle frame 200 away from the display module 100 is used to install internal components such as batteries, circuit boards, cameras, antennas, etc. The side surface of the middle frame 200 away from the display module 100 refers to the side surface of the middle frame 200 facing the shell 300. The cover plate 400 is located on the side of the display module 100 away from the middle frame 200. The cover plate 400 can be, for example, a cover glass, and the cover glass can have a certain toughness. The display module 100 has a light-emitting side capable of displaying an image and a backlight side arranged opposite to the light-emitting side. The middle frame 200 is arranged on the backlight side of the display module 100, and the cover plate 400 is arranged on the light-emitting side of the display module 100.

[0075] In some examples, such as Figure 2 As shown, the electronic device 1000 further includes a driving controller 500, which is coupled to the display module 100, for example. The driving controller 500 can receive the image signal RGB and the control signal CTRL, and output the image data signal DATA matching the interface specification of the display module 100 according to the image signal RGB. The driving controller 500 can also output the data control signal DCS. The driving controller 500, for example, includes a system on chips (SOC).

[0076] The display module 100 includes, for example, a display panel 10 and a display driver 20. The display driver 20 can be coupled to the drive controller 500, receive signals output by the drive controller 500, and provide display signals for the display panel 10. Of course, the display module 100 also includes, for example, a flexible circuit board and other structures.

[0077] Exemplarily, the display driver 20 receives a data control signal DCS and an image data signal DATA from the drive controller 500. The display driver 20 converts the image data signal DATA into a data signal, and outputs the data signal to a plurality of data signal lines DL in the display panel 10. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA. The display driver 20 may also output a scan control signal SCS required for display, such as a clock signal CLK, an initial input signal STV, a reset signal RST, etc., to the display panel 10. The display driver 20 includes, for example, a display driver integrated circuit (DDIC).

[0078] In some examples, the display panel 10 may be a self-luminous display panel, which has the advantages of light weight, thin thickness, high contrast, etc. Optionally, the display panel 10 may be a self-luminous display panel such as an organic light emitting diode (OLED) display panel, an active-matrix organic light-emitting diode (AMOLED) display panel, a mini organic light-emitting diode (Mini-OLED) display panel, a micro light-emitting diode (Micro-LED) display panel, a micro organic light-emitting diode (Micro-OLED) display panel, a quantum dot light emitting diode (QLED) display panel, etc. At this time, the display panel 10 may be a rigid display panel or a flexible display panel.

[0079] For any of the above display panels 10, the display panel 10 has an active area (AA) and a frame area BB located around the active area AA, and the active area AA is used to display images. Figure 2 As shown, the display panel 10 includes a plurality of sub-pixels P disposed in the display area AA, and a scan driving circuit 1 disposed in the frame area BB. Accordingly, the scan driving circuit 1 is disposed outside the display area AA.

[0080] The above-mentioned multiple sub-pixels P can receive data signals provided by the display driver 20. In some embodiments of the present application, multiple sub-pixels P are arranged in a matrix form as an example for explanation, and sub-pixels P arranged in a row along the row direction X are called sub-pixels P in the same row, and sub-pixels P arranged in a row along the column direction Y are called sub-pixels P in the same column.

[0081] The scan drive circuit 1 can receive a scan control signal SCS provided by the display driver 20. The scan drive circuit 1 includes, for example, a plurality of array substrate gate drive circuits (gate driver on array, GOA) 11. The array substrate gate drive circuit 11 is referred to as the gate drive circuit 11 hereinafter. Each gate drive circuit 11 in the scan drive circuit 1 adopts a technology that integrates a row scan circuit of a flat panel display (FPD) into a panel design, realizes a narrow frame, reduces the cost of the display panel 10, and eliminates a gate drive chip.

[0082] Figure 3 An architectural diagram of a gate drive circuit provided in an embodiment of the present application.

[0083] In some embodiments, Figure 3 As shown, the gate driving circuit 11 includes a plurality of cascaded shift registers (SR), namely shift registers SR(1), SR(2), SR(3), SR(4) ... SR(n), wherein n is a positive integer.

[0084] Exemplarily, the signal input terminal InP of the first-stage shift register SR(1) is electrically connected to the start signal terminal STV for receiving a scan start signal or a scan end start signal. Except for the first-stage shift register SR(1), the signal input terminal InP of each stage shift register is electrically connected to the signal output terminal OutP of the previous stage shift register, for example, the signal input terminal InP of the shift register SR(3) is electrically connected to the signal output terminal OutP of the shift register SR(2). Except for the last stage shift register SR(n), the reset signal terminal of each stage shift register is electrically connected to the signal output terminal OutP of the next stage shift register, for example, the reset signal terminal of the shift register SR(3) is electrically connected to the signal output terminal OutP of the shift register SR(4). The reset signal terminal of the last stage shift register SR(n) is electrically connected to the start signal terminal STV.

[0085] When the start signal terminal STV inputs the scan start signal, the first-stage shift register SR(1) of the gate drive circuit 11 starts to work, and then the multi-stage shift registers start to work step by step. The electrical signal received by the signal input terminal InP of a certain stage of the shift register is the electrical signal output by the signal output terminal OutP of the previous stage of the shift register. When the signal input terminal InP is not triggered, the internal reset function of the circuit will reset the circuit output to a certain default state, so as to transmit the on / off signal to the sub-pixel P row by row, and turn on / off certain transistors in the sub-pixel P in turn.

[0086] The signal output terminal OutP of each stage of the shift register may be electrically connected to one, two, four or more rows of sub-pixels P, which is not limited in the embodiment of the present application.

[0087] For example, Figure 3 As shown, the gate drive circuit 11 also includes a plurality of clock signal lines and power supply voltage signal lines, etc. Each level of shift register is electrically connected to the plurality of clock signal lines and power supply voltage signal lines, etc., to receive corresponding clock signals and power supply voltage signals.

[0088] It is understandable that the signal output terminals OutP of the shift registers of different types of gate driving circuits 11 can output different types of scan signals to the corresponding sub-pixels P. For the various types of scan signals, please refer to the relevant description below, which will not be repeated here.

[0089] In some embodiments, the sub-pixel P includes a pixel circuit and a light-emitting device electrically connected to the pixel circuit. The light-emitting device is, for example, an OLED. The pixel circuit can generate a drive signal and transmit the drive signal to the light-emitting device electrically connected thereto to drive the light-emitting device to emit light. The light emitted by the light-emitting devices of the multiple sub-pixels P cooperates to enable the electronic device 1000 to display an image.

[0090] The above-mentioned pixel circuit usually includes a plurality of transistors, such as a driving transistor, and the plurality of transistors are, for example, low temperature polysilicon (LTPS) thin film transistors, and accordingly, the pixel circuit is an LTPS pixel circuit. However, due to the leakage problem of the LTPS pixel circuit, the voltage of the control electrode of the driving transistor is difficult to maintain for a long time, which leads to a more serious screen flickering problem when the display panel is performing low-frequency display, and it is difficult to realize low frame rate applications, such as 1Hz or 10Hz.

[0091] To improve this problem, the industry has developed low temperature polycrystalline oxide (LTPO) technology. LTPO technology combines the high mobility of LTPS thin-film transistors and the low leakage characteristics of indium gallium zinc oxide (IGZO) thin-film transistors, which can not only maintain the high brightness and high frame rate of the screen, but also display at a low frame rate when the SOC does not send a picture or sends a low frame rate picture. This can achieve a smoother display at a high frame rate, and can reduce power consumption when a high frame rate is not required, that is, a low frame rate display.

[0092] Figure 4 shows an equivalent circuit diagram of a sub-pixel, Figure 5 is a timing diagram, which can be applied to sub-pixels of various structures. In the embodiment of the present application, the timing diagram is applied to Figure 4 The sub-pixel shown in FIG. 1 is used as an example to illustrate. Figure 4 In the sub-pixel shown, the pixel circuit is an LTPO pixel circuit.

[0093] In some embodiments, Figure 4As shown, the pixel circuit 21 in the sub-pixel P is electrically connected to the light-emitting device 22. The pixel circuit 21 may include a data writing circuit 211, a driving circuit 212, a compensation circuit 213, a first reset circuit 214, a light-emitting control circuit 215, an energy storage sub-circuit 216 and a second reset circuit 217.

[0094] Exemplarily, the data writing circuit 211 includes a first transistor T1, the driving circuit 212 includes a second transistor T2, the compensation circuit 213 includes a third transistor T3, the first reset circuit 214 includes a fourth transistor T4, the light emitting control circuit 215 includes a fifth transistor T5 and a sixth transistor T6, the energy storage sub-circuit 216 includes a storage capacitor Cst, and the second reset circuit 217 includes a seventh transistor T7.

[0095] Continue reading Figure 4 , the first transistor T1 and the second transistor T2 are electrically connected, and the junction point of the two is, for example, the first node N1. The second transistor T2 and the third transistor T3 are electrically connected, and the junction point of the two is, for example, the second node N2 and the third node N3. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal SC1, the first electrode of the first transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the second scan signal terminal SC2, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The first electrode of the storage capacitor Cst is electrically connected to the third node N3, and the second electrode of the storage capacitor Cst is electrically connected to the first voltage signal terminal ELVDD.

[0096] The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal SC3, the first electrode of the fourth transistor T4 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the fourth scan signal terminal SC4, the first electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1. The control electrode of the sixth transistor T6 is electrically connected to the fourth scan signal terminal SC4, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting device 22, and the cathode of the light emitting device 22 is electrically connected to the second voltage signal terminal ELVSS. The electrical connection junction point of the sixth transistor T6 and the light emitting device 22 is, for example, the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the fifth scan signal terminal SC5, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0097] Optionally, the third transistor T3 and the fourth transistor T4 are both metal oxide thin film transistors, such as IGZO thin film transistors, and further, both are N-type transistors, and can be turned on in response to a high-level electrical signal. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all LTPS thin film transistors, and further, all five are P-type transistors, and can be turned on in response to a low-level electrical signal.

[0098] Below, the pixel circuit 21 in the nth row of sub-pixels P is taken as an example, where n is a positive integer. Figure 4 and Figure 5 , the working process of the pixel circuit 21 is schematically described. Figure 5 , SC1(n) represents the first scanning signal received by each pixel circuit 21 in the sub-pixel P in the n-th row, SC1(n+1) represents the first scanning signal received by each pixel circuit 21 in the sub-pixel P in the n+1-th row, SC2(n) represents the second scanning signal received by each pixel circuit 21 in the sub-pixel P in the n-th row, SC3(n) represents the third scanning signal received by each pixel circuit 21 in the sub-pixel P in the n-th row, SC4(n) represents the fourth scanning signal received by each pixel circuit 21 in the sub-pixel P in the n-th row, and SC5(n) represents the fifth scanning signal received by each pixel circuit 21 in the sub-pixel P in the n-th row.

[0099] like Figure 5 As shown, the working process of the pixel circuit 21 includes: a non-luminous stage S1 and a luminous stage S2. The non-luminous stage S1 includes a first reset stage t1, a data writing and compensation stage t2, and a second reset stage t3.

[0100] In the non-light-emitting stage S1, the level of the fourth scanning signal is high, the fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0101] In the first reset stage t1 of the non-luminous stage S1, the levels of the second scanning signal and the third scanning signal are both high. The third transistor T3 and the fourth transistor T4 are both turned on, and the first initial signal from the first initial signal terminal Vinit1 is transmitted to the third node N3 via the fourth transistor T4, the second node N2, and the third transistor T3 in sequence, and the third node N3 is reset.

[0102] In the data writing and compensation stage t2 of the non-luminous stage S1, the level of the second scanning signal is high, and the level of the first scanning signal is low. The third transistor T3 and the first transistor T1 are both turned on, and the data signal from the data signal terminal Data is transmitted to the third node N3 through the first transistor T1, the first node N1, the second transistor T2, the second node N2, and the third transistor T3 in sequence, so as to realize the writing of the data signal and the compensation of the threshold voltage of the second transistor T2. During this period, the storage capacitor Cst is also charged to maintain the potential of the third node N3.

[0103] In the second reset stage t3 of the non-luminous stage S1, the level of the fifth scanning signal is low. The seventh transistor T7 is turned on, and the second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 through the seventh transistor T7, and the fourth node N4 is reset, that is, the anode of the light emitting device 22 is reset.

[0104] In the above-mentioned light-emitting stage S2, the level of the fourth scanning signal is a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, connecting the path between the first voltage signal terminal ELVDD and the light-emitting device 22, and the driving signal generated based on the data signal and the first voltage signal from the first voltage signal terminal ELVDD is transmitted to the light-emitting device 22 to drive the light-emitting device 22 to emit light.

[0105] In some embodiments, in order to optimize power consumption and achieve a set of frame rates compatible with 1 Hz, 10 Hz, 30 Hz, 60 Hz and 120 Hz, the driving circuit 1 includes, for example, five types of gate driving circuits 11. The five types of gate driving circuits 11 are, for example, a first gate driving circuit 11a, a second gate driving circuit 11b, a third gate driving circuit 11c, a fourth gate driving circuit 11d and a fifth gate driving circuit 11e.

[0106] In some examples, such as Figure 6As shown, for a display panel of small or medium size, the number of the first gate driving circuit 11a is, for example, two, and the number of the second gate driving circuit 11b, the third gate driving circuit 11c, the fourth gate driving circuit 11d, and the fifth gate driving circuit 11e are, for example, one. For example, along the row direction X of multiple rows of sub-pixels P, three gate driving circuits 11 are provided on each side outside the display area AA.

[0107] In the embodiment of the present application, two adjacent sub-pixels P are used as an example to represent two adjacent rows of sub-pixels P.

[0108] Combination Figure 4 and Figure 6 , along the row direction X of the multiple rows of sub-pixels P, the two first gate driving circuits 11a are, for example, located on both sides outside the display area AA, i.e., on the left and right sides, and adopt a bilateral driving mode, which can also be called a bilateral driving. Among them, a first shift register GP-GOA in each first gate driving circuit 11a is, for example, electrically connected to each pixel circuit 21 in a row of sub-pixels P through a first scanning signal terminal SC1, so as to provide a first scanning signal to the corresponding pixel circuit 21.

[0109] Along the row direction X of the multiple rows of sub-pixels P, the second gate driving circuit 11b is, for example, located on one side outside the display area AA, for example, on the right side, and adopts a unilateral driving mode, which can also be called a unilateral driving. Among them, a second shift register GN-GOA in each second gate driving circuit 11b is, for example, electrically connected to each pixel circuit 21 in the two rows of sub-pixels P through the second scanning signal terminal SC2, so as to provide the second scanning signal to the corresponding pixel circuit 21.

[0110] Along the row direction X of the multiple rows of sub-pixels P, the third gate driving circuit 11c is, for example, located on one side outside the display area AA, for example, on the left side, and adopts a unilateral driving mode. Among them, a third shift register Rst-NGOA in each third gate driving circuit 11c is, for example, electrically connected to each pixel circuit 21 in the two rows of sub-pixels P through the third scanning signal terminal SC3, so as to provide the third scanning signal to the corresponding pixel circuit 21.

[0111] Along the row direction X of the multiple rows of sub-pixels P, the fourth gate driving circuit 11d is, for example, located on one side outside the display area AA, for example, on the left side, and adopts a unilateral driving mode. Among them, a fourth shift register EM-GOA in each fourth gate driving circuit 11d is, for example, electrically connected to each pixel circuit 21 in the two rows of sub-pixels P through the fourth scanning signal terminal SC4, so as to provide the fourth scanning signal to the corresponding pixel circuit 21.

[0112] Along the row direction X of the multiple rows of sub-pixels P, the fifth gate driving circuit 11e is, for example, located on one side outside the display area AA, for example, on the right side, and adopts a unilateral driving mode. Among them, a fifth shift register Rst-PGOA in each fifth gate driving circuit 11e is, for example, electrically connected to each pixel circuit 21 in the two rows of sub-pixels P through the fifth scanning signal terminal SC5, so as to provide the fifth scanning signal to the corresponding pixel circuit 21.

[0113] That is to say, every two rows of sub-pixels P need to be driven by eight shift registers.

[0114] Combination Figure 5 and Figure 6 In the process of image display, the nth row sub-pixel P and the n+1th row sub-pixel P synchronously execute the first reset stage t1; then the data writing and compensation stage t2 is executed in a time-sharing manner, and the writing of the data signal and the compensation of the threshold voltage are scanned line by line; then the second reset stage t3 and the light-emitting stage S2 are synchronously executed.

[0115] In other examples, such as Figure 7 As shown, for a large-sized display panel, the number of the first gate driving circuit 11a, the second gate driving circuit 11b, the third gate driving circuit 11c, the fourth gate driving circuit 11d and the fifth gate driving circuit 11e are, for example, two. For example, along the row direction X of the multiple rows of sub-pixels P, on both sides outside the display area AA, a first gate driving circuit 11a, a second gate driving circuit 11b, a third gate driving circuit 11c, a fourth gate driving circuit 11d and a fifth gate driving circuit 11e are arranged on each side. Each gate driving circuit 11 adopts a bilateral driving method.

[0116] in, Figure 7 The corresponding relationship between the shift register and the sub-pixel P in each gate drive circuit 11 is shown in FIG. Figure 6 The same as shown, please refer to the relevant instructions in the above text, and will not be repeated here.

[0117] That is to say, every two rows of sub-pixels P need to be driven by twelve shift registers.

[0118] For the above two display panels, although such a setting can achieve better display effects and power consumption benefits, more gate drive circuits 11 or shift registers will bring additional power consumption, hindering further reduction of power consumption; moreover, the above five types of gate drive circuits 11 will occupy a larger space, resulting in a larger border size of the display panel, making it difficult to achieve a narrow border design.

[0119] Figure 8 Also shown is an equivalent circuit diagram of a sub-pixel. Figure 8In the sub-pixel shown, the pixel circuit is an LTPO pixel circuit.

[0120] In some embodiments, Figure 8 As shown, the pixel circuit 21 in the sub-pixel P is electrically connected to the light-emitting device 22. The pixel circuit 21 may include a data writing circuit 211, a driving circuit 212, a compensation circuit 213, a first reset circuit 214, a light-emitting control circuit 215, an energy storage sub-circuit 216 and a second reset circuit 217.

[0121] For example, in Figure 8 The structures and connection relationships of the data writing circuit 211, the driving circuit 212, the compensation circuit 213, the light emitting control circuit 215, the energy storage sub-circuit 216 and the second reset circuit 217 can be referred to. Figure 4 , and see above for Figure 4 The relevant instructions will not be repeated here.

[0122] The first reset circuit 214 in the pixel circuit 21 may also be connected in other ways. Figure 8 As shown, the second electrode of the fourth transistor T4 in the first reset circuit 214 is electrically connected to the third node N3, and the control electrode of the fourth transistor T4 is electrically connected to the second scan signal terminal SC2(n-5); the control electrode of the seventh transistor T7 in the second reset circuit 217 is electrically connected to the first scan signal terminal SC1(n+1). Here, n≥5, and n is an integer.

[0123] In some embodiments, in order to optimize power consumption and achieve a set of frame rates compatible with 1 Hz, 10 Hz, 30 Hz, 60 Hz and 120 Hz, the driving circuit 1 includes, for example, three types of gate driving circuits 11. The three types of gate driving circuits 11 are, for example, a first gate driving circuit 11a, a second gate driving circuit 11b and a fourth gate driving circuit 11d.

[0124] In some examples, such as Fig. 9 As shown, for a display panel of small or medium size, the number of the first gate driving circuit 11a, the second gate driving circuit 11b and the fourth gate driving circuit 11d is, for example, two. Along the row direction X of the multiple rows of sub-pixels P, a first gate driving circuit 11a, a second gate driving circuit 11b and a fourth gate driving circuit 11d are arranged on each side outside the display area AA.

[0125] Continue reading Fig. 9 The first gate driving circuit 11a, the second gate driving circuit 11b and the fourth gate driving circuit 11d all adopt a bilateral driving method.

[0126] Among them, combined Figure 8and Fig. 9 , a first shift register GP-GOA in each first gate driving circuit 11a is, for example, electrically connected to the data writing circuit 211 of each pixel circuit 21 in the nth row of sub-pixels P through the first scanning signal terminal SC1(n), and is electrically connected to the second reset circuit 217 of each pixel circuit 21 in the n+1th row of sub-pixels P through the first scanning signal terminal SC1(n+1), so as to provide the first scanning signal for the corresponding pixel circuit 21. A second shift register GN-GOA in each second gate driving circuit 11b is, for example, electrically connected to the compensation circuit 213 of each pixel circuit 21 in the nth row of sub-pixels P through the second scanning signal terminal SC2(n), and is electrically connected to the first reset circuit 214 of each pixel circuit 21 in the n-5th row of sub-pixels P through the second scanning signal terminal SC2(n-5), so as to provide the second scanning signal for the corresponding pixel circuit 21. Here, the second shift register GN-GOA can also be electrically connected to the nth row of sub-pixels P, and other rows of sub-pixels P except the n-5th row of sub-pixels P. A fourth shift register EM-GOA in each fourth gate driving circuit 11d is electrically connected to each pixel circuit 21 in two rows of sub-pixels P through a fourth scanning signal terminal SC4, so as to provide a fourth scanning signal to the corresponding pixel circuit 21. Every two rows of sub-pixels P are driven by eight shift registers.

[0127] For the above-mentioned display panel, although such a setting can achieve better display effects and power consumption benefits, more gate drive circuits 11 or shift registers will bring additional power consumption, hindering further reduction of power consumption; moreover, the above-mentioned three types of gate drive circuits 11 will occupy a larger space, resulting in a larger border size of the display panel, making it difficult to achieve a narrow border design.

[0128] Based on this, some embodiments of the present application provide a display panel, which can be applied to the above-mentioned display module or electronic device. Optionally, the display panel can be used as Figure 2 The display panel in the embodiment of the present invention improves the structure of the pixel circuit 21, and accordingly improves the arrangement between the pixel circuit 21 and the shift register or gate drive circuit electrically connected thereto. Fig.10 , Fig.12 and Fig.15 The equivalent circuit diagrams of a sub-pixel are shown respectively. Fig.11 , Fig.13 , Fig.14 , Fig.16 and Fig.17 A partial structural diagram of a display panel is shown respectively.

[0129] In some embodiments, Figure 2As shown, the display panel 10 may include a plurality of sub-pixels P, which are located in the display area AA, for example, arranged in an array, specifically, the plurality of sub-pixels P are arranged in a plurality of rows and columns, each row of sub-pixels P includes a plurality of sub-pixels P spaced apart along a row direction X, and each column of sub-pixels includes a plurality of sub-pixels P spaced apart along a column direction Y. Of course, the arrangement of the plurality of sub-pixels P is not limited thereto.

[0130] In some examples, such as Fig.10 , Fig.12 and Fig.15 As shown, each sub-pixel P includes a pixel circuit 21 and a light-emitting device 22 connected to each other. The pixel circuit 21 includes a data writing circuit 211, a driving circuit 212 and a compensation circuit 213. The data writing circuit 211 is electrically connected to the data signal terminal Data and the driving circuit 212, and the junction point where the data writing circuit 211 and the driving circuit 212 are electrically connected is, for example, the first node N1. The driving circuit 212 is also electrically connected to the compensation circuit 213, and the junction point where the two are electrically connected is, for example, the second node N2 and the third node N3. For example, the data signal from the data signal terminal Data can be transmitted to the third node N3 via the data writing circuit 211, the first node N1, the driving circuit 212, the second node N2, and the compensation circuit 213 in sequence.

[0131] Exemplarily, the transistors included in the data writing circuit 211 and the compensation circuit 213 are all metal oxide thin film transistors. Correspondingly, the transistors included in the data writing circuit 211 and the compensation circuit 213 are all N-type transistors. The material of the active layer of the metal oxide thin film transistor includes but is not limited to metal oxides such as IGZO. In this way, the leakage of the data writing circuit 211 can be reduced, which is convenient for maintaining the potential of the first node N1 and reducing power consumption, and the leakage of the compensation circuit 213 can be reduced, which is convenient for maintaining the potential of the third node N3.

[0132] In some examples, such as Fig.11 and Fig.13 As shown, the display panel 10 may further include a first shift register 111, and the first shift register 111 is located outside the display area AA, that is, located in the frame area BB. The number of the first shift registers 111 is, for example, multiple, and the multiple first shift registers 111 located on the same side of the display area AA are cascaded in sequence to form a first gate drive circuit 11a. The first gate drive circuit 11a is located in the frame area BB.

[0133] Each first shift register 111 is, for example, electrically connected to a data writing circuit 211 of each pixel circuit 21 in a row of pixel circuits 21. Further, the first shift register 111 is configured to provide a first scanning signal to the data writing circuit 211 of the pixel circuit 21 connected to the first shift register 111. This helps to reduce the load of each first shift register 111, and can more flexibly control the display panel 10 to display a picture.

[0134] For example, the first shift register 111 and the data writing circuit 211 of each pixel circuit 21 in the above-mentioned row of pixel circuits 21 can be electrically connected through the first scanning signal terminal SC1. Each data writing circuit 211 can receive the first scanning signal through the first scanning signal terminal SC1. The data writing circuit 211 is configured to be turned on in response to the first scanning signal, and transmit the data signal from the data signal terminal Data to the compensation circuit 213. Specifically, the data signal can be transmitted to the compensation circuit 213 or the second node N2 via the data writing circuit 211, the first node N1, and the driving circuit 212 in sequence.

[0135] In some examples, such as Fig.11 and Fig.13 As shown, the display panel 10 may further include a second shift register 112, and the second shift register 112 is located outside the display area AA, that is, located in the frame area BB. The number of the second shift registers 112 is, for example, multiple, and the multiple second shift registers 112 located on the same side of the display area AA are cascaded in sequence to form a second gate drive circuit 11b. The second gate drive circuit 11b is located in the frame area BB.

[0136] Each second shift register 112 is, for example, electrically connected to the compensation circuit 213 of each pixel circuit 21 in at least one row of pixel circuits 21. Furthermore, the second shift register 112 is configured to provide a second scanning signal to the compensation circuit 213 of the pixel circuit 21 connected to the second shift register 112. For example, each second shift register 112 can be electrically connected to the compensation circuit 213 of each pixel circuit 21 in a row of pixel circuits 21. This helps to reduce the load of each second shift register 112, and can more flexibly control the display panel 10 to display a picture. For another example, Fig.13 As shown, each second shift register 112 can be electrically connected to the compensation circuit 213 of each pixel circuit 21 in two rows of pixel circuits 21. This is conducive to reducing the number of second shift registers 112 and simplifying the structure of the second gate drive circuit 11b and the display panel 10. Here, the number of rows of pixel circuits 21 connected to the second shift register 112 can be selected and set according to actual needs.

[0137] For example, the second shift register 112 and the compensation circuit 213 of each pixel circuit 21 in the at least one row of pixel circuits 21 may be electrically connected via the second scan signal terminal SC2. Each compensation circuit 213 may receive the second scan signal via the second scan signal terminal SC2. The compensation circuit 213 is configured to be turned on in response to the second scan signal and transmit the data signal to the driving circuit 212 or the third node N3.

[0138] It is understandable that since the transistors included in the data writing circuit 211 and the compensation circuit 213 are metal oxide thin film transistors, in small and medium-sized display panels, the first shift register 111 and the second shift register 112 can be set in a unilateral driving manner.

[0139] Take the case where the second shift register 112 is electrically connected to two adjacent rows of pixel circuits 21 as an example.

[0140] For example, Fig.13 and Fig.16 As shown, when the display panel 10 is a small or medium-sized display panel, a row of pixel circuits 21 can be electrically connected to a first shift register 111 , and two adjacent rows of pixel circuits 21 can be electrically connected to a second shift register 112 .

[0141] In this case, two adjacent rows of pixel circuits 21 are electrically connected to, for example, two first shift registers 111 and one second shift register 112. Figure 6 In the embodiment shown, two adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA and one second shift register GN-GOA, which means that Figure 6 In comparison, in the embodiment of the present application, the number of shift registers used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 is reduced by two, and accordingly, the number of gate driving circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 is reduced by one.

[0142] Furthermore, if Fig.14 and Fig.17 As shown, when the display panel 10 is a large-size display panel, one row of pixel circuits 21 can be electrically connected to two first shift registers 111 , and two adjacent rows of pixel circuits 21 can be electrically connected to two second shift registers 112 .

[0143] In this case, two adjacent rows of pixel circuits 21 are electrically connected to, for example, four first shift registers 111 and two second shift registers 112. Figure 7In the embodiment shown, two adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA and two second shift registers GN-GOA. That is, in the embodiment of the present application, the number of shift registers and gate drive circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 remains unchanged and does not increase.

[0144] Therefore, the display panel 10 provided in some embodiments of the present application, by setting the first shift register 111 and the second shift register 112, makes the first shift register 111 electrically connected to the data writing circuit 211 in each pixel circuit 21 located in the same row, makes the second shift register 112 electrically connected to the compensation circuit 213 in each pixel circuit 21 located in at least one row, and sets the transistors included in the data writing circuit 211 and the compensation circuit 213 to be metal oxide transistors, so that, on the one hand, leakage can be reduced by the data writing circuit 211 and the compensation circuit 213, the potential of the relevant nodes inside the pixel circuit 21 is maintained, and the power consumption caused by leakage is reduced; on the other hand, it is beneficial to reduce the first shift register 111 and the second shift register 112. On the other hand, in the case where the display panel 10 is a small or medium-sized display panel, the first shift register 111 can be set in a unilateral driving manner to reduce the number of shift registers used to drive the pixel circuit 21, for example, the number of first shift registers 111 used to drive the data writing circuit 211 is reduced, and accordingly, the number of gate driving circuits is reduced. In this way, the space occupied by the gate driving circuit can be reduced on the basis of reducing the power consumption caused by the large number of gate driving circuits, and the frame size of the display panel 10 can be reduced, so as to facilitate the realization of a narrow frame design of the display panel 10.

[0145] In some embodiments, at least one of the first shift register 111 and the second shift register 112 is located outside the display area AA. In other words, the first shift register 111 is located outside the display area AA, and / or the second shift register 112 is located outside the display area AA.

[0146] Optionally, the first shift register 111 is located at a side outside the display area AA, for example Fig.13 The second shift register 112 is located on a side outside the display area AA, for example Fig.13 Alternatively, the first shift register 111 is located on both sides outside the display area AA, for example Fig.14The second shift register 112 is located on both sides outside the display area AA, for example Fig.14 The left and right sides of the .

[0147] In this way, the flexibility of setting the first shift register 111 and the second shift register 112 can be improved, and the display panels 10 of more types can be applied.

[0148] In some embodiments, Fig.13 and Fig.16 As shown, in the case where the display panel 10 is a small or medium-sized display panel, a row of pixel circuits 21 can be electrically connected to a first shift register 111, and accordingly, the first shift register 111 is located on a side outside the display area AA, and the first shift register 111 adopts a single-sided drive setting mode. In addition, at least one row of pixel circuits 21 can be electrically connected to a second shift register 112, and accordingly, the second shift register 112 is located on a side outside the display area AA, and the second shift register 112 adopts a single-sided drive setting mode.

[0149] In some examples, along the row direction X of the multiple rows of pixel circuits 21, the first shift register 111 and the second shift register 112 are respectively located on two sides outside the display area AA, that is, on the left and right sides. Accordingly, one side of the multiple rows of pixel circuits P is provided with a first gate driving circuit 11a including the first shift register 111, and the other side is provided with a second gate driving circuit 11b including the second shift register 112.

[0150] Optionally, in Fig.13 and Fig.16 In the embodiment, two adjacent rows of pixel circuits 21 are electrically connected to a second shift register 112. Furthermore, the second shift register 112 is located at Fig.13 and Fig.16 The two first shift registers 111 connected to the two adjacent rows of pixel circuits 21 are arranged along the column direction Y, and the two first shift registers 111 are located Fig.13 and Fig.16 For example, along the row direction X, the size of the space occupied by the two first shift registers 111 is the same or substantially the same as the size of the space occupied by the second shift register 112.

[0151] In this way, along the row direction X of the multiple rows of pixel circuits 21, the number of gate drive circuits belonging to the shift registers on both sides of the display area AA can be balanced, so that the widths of the border areas BB on both sides of the display area AA are the same or approximately the same, and it is beneficial to the wiring arrangement of the border area BB.

[0152] In other embodiments, Fig.14 and Fig.17 As shown, in the case where the display panel 10 is a large-size display panel, a row of pixel circuits 21 can be electrically connected to two first shift registers 111, and at least one row of pixel circuits 21 is electrically connected to two second shift registers 112. Wherein, along the row direction X of the multiple rows of pixel circuits 21, the two first shift registers 111 are respectively located on both sides outside the display area AA, and the two second shift registers 112 are respectively located on both sides outside the display area AA. Accordingly, each side outside the display area AA is provided with a first gate driving circuit 11a including a first shift register 111, and a second gate driving circuit 11b including a second shift register 112.

[0153] In this way, the load of the first shift register 111 and the second shift register 112 is reduced, and the display panel 10 can be controlled more flexibly to display images.

[0154] For some examples, see Fig.14 , the second shift register 112 is farther away from the display area AA than the first shift register 111 located on the same side. That is, of the first shift register 111 and the second shift register 112 located on the same side of the display area AA, the first shift register 111 is closer to the display area AA. Accordingly, the two first gate driving circuits 11a are located between the two second gate driving circuits 11b.

[0155] Since each first shift register 111 is electrically connected to a row of pixel circuits 21, and each second shift register 112 is electrically connected to one or more rows of pixel circuits 21, the first gate drive circuit 11a and the multiple rows of pixel circuits 21 may have more wiring and more complicated wiring conditions than the second gate drive circuit 11b. The above-mentioned configuration is conducive to optimizing the wiring space of the display panel 10, reducing the winding between the first gate drive circuit 11a and the multiple rows of pixel circuits 21, reducing the wiring difficulty, and improving the yield of the display panel 10. In addition, the use of a bilateral drive method is conducive to improving the display uniformity of the display panel 10.

[0156] Of course, if Fig.17 As shown, the positions of the first shift register 111 and the second shift register 112 located on the same side can be interchanged.

[0157] The structures of the above-mentioned data writing circuit 211, driving circuit 212 and compensation circuit 213 include various types. The structures of the data writing circuit 211, driving circuit 212 and compensation circuit 213 are schematically illustrated below in conjunction with the accompanying drawings, but the structures of the data writing circuit 211, driving circuit 212 and compensation circuit 213 are not limited to this.

[0158] In some examples, such as Fig.10 , Fig.12 and Fig.15 As shown, the data writing circuit 211 includes a first transistor T1, the driving circuit 212 includes a second transistor T2, and the compensation circuit 213 includes a third transistor T3. The first transistor T1 and the third transistor T3 are both metal oxide thin film transistors.

[0159] The control electrode of the first transistor T1 is electrically connected to the first shift register 111, the first electrode of the first transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2, that is, the first node N1.

[0160] For example, when the level of the first scan signal transmitted from the first shift register 111 to the first transistor T1 through the first scan signal terminal SC1 is high, the first transistor T1 may be turned on under the control of the first scan signal to receive and transmit the data signal to the first node N1.

[0161] The control electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, ie, the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3, ie, the second node N2.

[0162] For example, when the potential of the third node N3 is an effective potential, the second transistor T2 can be turned on under the control of the potential of the third node N3 to transmit the electrical signal at the first node N1, such as a data signal, to the second node N2. Here, the effective potential of the potential of the third node N3 is, for example, a low level.

[0163] The control electrode of the third transistor T3 is electrically connected to the second shift register 112 .

[0164] For example, when the level of the second scan signal transmitted to the third transistor T3 by the second shift register 112 through the second scan signal terminal SC2 is high, the third transistor T3 can be turned on under the control of the second scan signal to transmit the electrical signal at the second node N2, such as a data signal, to the third node N3.

[0165] The above configuration is helpful to simplify the structures of the data writing circuit 211 , the driving circuit 212 and the compensation circuit 213 , and reduce the structural complexity and manufacturing difficulty of the display panel 10 .

[0166] Exemplarily, the second transistor T2 may be a metal oxide thin film transistor, or the second transistor T2 may be a low temperature polysilicon thin film transistor.

[0167] Wherein, when the second transistor T2 is a low temperature polysilicon thin film transistor, the second transistor T2 can have a higher electron mobility. When the second transistor T2 is a metal oxide thin film transistor, the crystallization uniformity of the active layer of the second transistor T2 can be improved, and the uniformity of the characteristics of the second transistor T2 can be improved.

[0168] In some embodiments, Fig.10 and Fig.12 As shown, the pixel circuit 21 may further include: a first reset circuit 214. The first reset circuit 214 is electrically connected to the driving circuit 212, the compensation circuit 213 and the first initial signal terminal Vinit1. Specifically, the first reset circuit 214 is electrically connected to the electrical connection junction of the driving circuit 212 and the compensation circuit 213, that is, the second node N2.

[0169] Exemplarily, the transistor included in the first reset circuit 214 is a metal oxide thin film transistor. Accordingly, the transistor included in the first reset circuit 214 is an N-type transistor. This can reduce the leakage of the first reset circuit 214 and facilitate maintaining the potential of the second node N2.

[0170] In some examples, since the transistors included in the first reset circuit 214 and the data write circuit 211 are both metal oxide thin film transistors, both can be turned on under the control of a high-level electrical signal, the first scan signal received by the data write circuit 211 can be multiplexed to the first reset circuit 214. Fig.13 and Fig.14 As shown, the first shift register 111 included in the display panel 10 is also electrically connected to the first reset circuit 214 of each pixel circuit 21 in a row of pixel circuits 21. Further, the first shift register 111 is also configured to provide a first scanning signal to the first reset circuit 214 of the pixel circuit 21 connected to the first shift register 111. This is conducive to reducing the load of each first shift register 111, and the display panel 10 can be more flexibly controlled to display a picture.

[0171] For example, the first shift register 111 and the first reset circuit 214 of each pixel circuit 21 in the above-mentioned row of pixel circuits 21 can be electrically connected through the first scan signal terminal SC1. Each first reset circuit 214 can receive the first scan signal through the first scan signal terminal SC1. The first reset circuit 214 is configured to be turned on in response to the first scan signal, and transmit the first initial signal from the first initial signal terminal Vinit1 to the driving circuit 212 and the compensation circuit 213, specifically the second node N2 and the third node N3.

[0172] Exemplarily, the first reset circuit 214 and the pixel circuit 21 to which the data writing circuit 211 are connected to the same first shift register 111 are located in different rows. In other words, the same first shift register 111 is not electrically connected to the first reset circuit 214 and the data writing circuit 211 of the same pixel circuit 21 at the same time. Fig.10 , Fig.12 , Fig.13 and Fig.14 The same first shift register 111 is electrically connected to the data writing circuit 211 of each pixel circuit 21 in the n-th row of pixel circuits 21 through the first scanning signal terminal SC1(n), and is electrically connected to the first reset circuit 214 of each pixel circuit 21 in the ni-th row of pixel circuits 21 through the first scanning signal terminal SC1(ni).

[0173] Optionally, i=1, the same first shift register 111 is electrically connected to the data writing circuit 211 of each pixel circuit 21 in the n-th row of pixel circuits 21 through the first scanning signal terminal SC1(n), and is electrically connected to the first reset circuit 214 of each pixel circuit 21 in the n-1-th row of pixel circuits 21 through the first scanning signal terminal SC1(n-1). Correspondingly, the pixel circuit 21 to which the first reset circuit 214 connected to the same first shift register 111 belongs is located in the previous row of the pixel circuit 21 to which the data writing circuit 211 connected to the same first shift register 111 belongs. In other words, the same first shift register 111 provides the first scanning signal for the pixel circuits 21 in two adjacent rows. This facilitates the coordination with other shift registers to realize the driving of the pixel circuit 21, and is also conducive to simplifying the design of the driving timing of the pixel circuit 21.

[0174] Of course, on the basis of the same first shift register 111 being electrically connected to the data writing circuit 211 of each pixel circuit 21 in the nth row of pixel circuits 21, it can also be electrically connected to the first reset circuit 214 of each pixel circuit 21 in the n-3rd row or the n-5th row of pixel circuits 21, and the embodiment of the present application is not limited thereto, and can be selected and set according to actual needs. Wherein, n and i are both integers, n≠i, i≠0, and n>1.

[0175] Take the above-mentioned electrical connection between the second shift register 112 and two adjacent rows of pixel circuits 21 as an example.

[0176] For example, Fig.13 As shown, when the display panel 10 is a small or medium-sized display panel, two adjacent rows of pixel circuits 21 are electrically connected to, for example, two first shift registers 111 and one second shift register 112. Figure 6It can also be considered that two adjacent rows of pixel circuits 21 are electrically connected to a second shift register GN-GOA and two third shift registers Rst-NGOA. Figure 6 In the embodiment shown, two adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA, one second shift register GN-GOA and one third shift register Rst-NGOA. Figure 6 In comparison, in the embodiment of the present application, the four first shift registers GP-GOA electrically connected to the data write circuit 211 are omitted, and the number of shift registers used to drive the data write circuit 211, the compensation circuit 213 and the first reset circuit 214 in the pixel circuit 21 is reduced by three. Correspondingly, the number of gate drive circuits used to drive the data write circuit 211, the compensation circuit 213 and the first reset circuit 214 in the pixel circuit 21 is reduced by two.

[0177] For example, Fig.14 As shown, when the display panel 10 is a large-size display panel, two adjacent rows of pixel circuits 21 are electrically connected to, for example, four first shift registers 111 and two second shift registers 112. Figure 7 It can also be considered that two adjacent rows of pixel circuits 21 are electrically connected to two second shift registers GN-GOA and two third shift registers Rst-NGOA. Figure 7 In the embodiment shown, two adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA, two second shift registers GN-GOA, and two third shift registers Rst-NGOA. That is, in the embodiment of the present application, the number of shift registers used to drive the data writing circuit 211, the compensation circuit 213, and the first reset circuit 214 in the pixel circuit 21 is reduced by two, and accordingly, the number of gate driving circuits used to drive the data writing circuit 211, the compensation circuit 213, and the first reset circuit 214 in the pixel circuit 21 is reduced by two.

[0178] Therefore, the first reset circuit 214 and the first shift register 111 are arranged in the above-mentioned manner. On the one hand, it is beneficial to reduce the leakage of the first reset circuit 214 and maintain the potential of the corresponding node in the pixel circuit 21; on the other hand, no matter the display panel 10 is a large-size display panel or a small or medium-sized display panel, the number of shift registers electrically connected to the pixel circuit 21 can be further reduced, and correspondingly, the number of gate drive circuits electrically connected to the pixel circuit 21 can be further reduced. In this way, on the basis of further reducing the power consumption caused by the large number of gate drive circuits, the space occupied by the gate drive circuit can be further reduced, and the border size of the display panel 10 can be reduced, so as to facilitate the realization of a narrow border design of the display panel 10.

[0179] In some examples, such as Fig.10 and Fig.12 As shown, the first reset circuit 214 includes, for example, a fourth transistor T4, which is a metal oxide thin film transistor.

[0180] The control electrode of the fourth transistor T4 is electrically connected to the first shift register 111, the first electrode of the fourth transistor T4 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the fourth transistor T4 is electrically connected to the driving circuit 212 and the compensation circuit 213. Correspondingly, the second electrode of the fourth transistor T4 is electrically connected to the second node N2.

[0181] For example, when the level of the first scan signal transmitted from the first shift register 111 to the fourth transistor T4 through the first scan signal terminal SC1(n-1) is high, the fourth transistor T4 can be turned on under the control of the first scan signal, receive and transmit the first initial signal to the second node N2. The first initial signal can also be transmitted to the third node N3 through the compensation circuit 213 to reset the third node N3.

[0182] The above configuration is helpful to simplify the structure of the first reset circuit 214 and reduce the structural complexity and manufacturing difficulty of the display panel 10 .

[0183] It is understandable that the display panel 10 and the pixel circuit 21 may also include other circuit structures, which are schematically described below with reference to the accompanying drawings.

[0184] In some embodiments, Fig.10 and Fig.12 As shown, the pixel circuit 21 may further include: a light emitting control circuit 215, an energy storage subcircuit 216, and a second reset circuit 217. The light emitting control circuit 215 is electrically connected to the first voltage signal terminal ELVDD, the driving circuit 212, and the light emitting device 22. The junction point where the light emitting control circuit 215 and the light emitting device 22 are electrically connected is, for example, the fourth node N4. The energy storage subcircuit 216 is electrically connected to the first voltage signal terminal ELVDD and the third node N3, and is used to maintain the potential of the third node N3. The second reset circuit 217 is electrically connected to the second initial signal terminal Vinit2 and the light emitting device 22, and specifically, the second reset circuit 217 is electrically connected to the second initial signal terminal Vinit2 and the fourth node N4.

[0185] In this case, if Fig.11 , Fig.13 and Fig.14As shown, the display panel 10 may further include a third shift register 113 and a fourth shift register 114 located outside the display area AA. The number of the third shift register 113 is, for example, multiple, and the multiple third shift registers 113 located on the same side of the display area AA are cascaded in sequence to form a third gate drive circuit 11c. The number of the fourth shift register 114 is, for example, multiple, and the multiple fourth shift registers 114 located on the same side of the display area AA are cascaded in sequence to form a fourth gate drive circuit 11d. The third gate drive circuit 11c and the fourth gate drive circuit 11d are both located in the border area BB.

[0186] Continue reading Fig.13 and Fig.14 , each third shift register 113 is, for example, electrically connected to the second reset circuit 217 of each pixel circuit 21 in at least one row of pixel circuits 21. Further, the third shift register 113 is configured to provide a third scanning signal to the second reset circuit 217 of the pixel circuit 21 connected to the third shift register 113. For example, each third shift register 113 can be electrically connected to the second reset circuit 217 of each pixel circuit 21 in a row of pixel circuits 21. This helps to reduce the load of each third shift register 113, and can more flexibly control the display panel 10 to display the picture. For another example, Fig.13 and Fig.14 As shown, each third shift register 113 can be electrically connected to the second reset circuit 217 of each pixel circuit 21 in two rows of pixel circuits 21. This is conducive to reducing the number of third shift registers 113 and simplifying the structure of the third gate drive circuit 11c and the display panel 10. Here, the number of rows of pixel circuits 21 connected to the third shift register 113 can be selected and set according to actual needs.

[0187] For example, the third shift register 113 and the second reset circuit 217 of each pixel circuit 21 in the at least one row of pixel circuits 21 may be electrically connected via the third scan signal terminal SC3. Each second reset circuit 217 may receive the third scan signal via the third scan signal terminal SC3. The second reset circuit 217 is configured to be turned on in response to the third scan signal, and transmit the second initial signal from the second initial signal terminal Vinit2 to the light emitting device 22.

[0188] Continue reading Fig.13 and Fig.14, each fourth shift register 114 is, for example, electrically connected to the light emitting control circuit 215 of each pixel circuit 21 in at least one row of pixel circuits 21. Further, the fourth shift register 114 is configured to provide a fourth scanning signal to the light emitting control circuit 215 of the pixel circuit connected to the fourth shift register 114. For example, each fourth shift register 114 can be electrically connected to the light emitting control circuit 215 of each pixel circuit 21 in a row of pixel circuits 21. This helps to reduce the load of each fourth shift register 114, and can more flexibly control the display panel 10 to display the picture. For another example, Fig.13 and Fig.14 As shown, each fourth shift register 114 can be electrically connected to the light emitting control circuit 215 of each pixel circuit 21 in two rows of pixel circuits 21. This is conducive to reducing the number of fourth shift registers 114 and simplifying the structure of the fourth gate driving circuit 11d and the display panel 10. Here, the number of rows of pixel circuits 21 connected to the fourth shift register 114 can be selected and set according to actual needs.

[0189] For example, the fourth shift register 114 and the light emitting control circuit 215 of each pixel circuit 21 in the at least one row of pixel circuits 21 may be electrically connected through the fourth scanning signal terminal SC4. Each light emitting control circuit 215 may receive a fourth scanning signal through the fourth scanning signal terminal SC4. The light emitting control circuit 215 is configured to be turned on in response to the fourth scanning signal to connect the path between the first voltage signal terminal ELVDD and the light emitting device 22.

[0190] Here, the data write circuit 211 and the second reset circuit 217 are connected to different shift registers respectively, so that the conduction conditions of the data write circuit 211 and the second reset circuit 217 can be controlled respectively, and then on the basis of meeting the control requirements of the data write circuit 211, the conduction frequency of the second reset circuit 217 can be increased, which is conducive to achieving flicker-free frame rate switching within a higher frame rate range, such as 90Hz-120Hz.

[0191] It is understood that in some embodiments, Fig.10 As shown, the pixel circuit 21 may be composed of the above-mentioned data writing circuit 211 , driving circuit 212 , compensation circuit 213 , first reset circuit 214 , light emitting control circuit 215 , energy storage subcircuit 216 and second reset circuit 217 .

[0192] In other embodiments, the pixel circuit 21 may also be composed of other circuits. Fig.15As shown, the pixel circuit 21 may be composed of the above-mentioned data writing circuit 211, driving circuit 212, compensation circuit 213, light emitting control circuit 215, energy storage subcircuit 216, second reset circuit 217 and third reset circuit 218. Fig.12 As shown, the pixel circuit 21 can be composed of the above-mentioned data writing circuit 211, driving circuit 212, compensation circuit 213, first reset circuit 214, light emitting control circuit 215, energy storage subcircuit 216, second reset circuit 217 and third reset circuit 218.

[0193] The third reset circuit 218 is schematically described below in conjunction with the accompanying drawings. In some examples, such as Fig.12 and Fig.15 As shown, the third reset circuit 218 is electrically connected to the third initial signal terminal Vinit3 and the driving circuit 212. Specifically, the third reset circuit 218 is electrically connected to the third initial signal terminal Vinit3 and the second node N2.

[0194] Optionally, the third reset circuit 218 is, for example, also electrically connected to the third shift register 113 .

[0195] Combination Fig.12 and Fig.13 Each third shift register 113 is, for example, electrically connected to the third reset circuit 218 of each pixel circuit 21 in the at least one row of pixel circuits 21. Further, the third shift register 113 is configured to provide a third scan signal to the third reset circuit 218 of the pixel circuit 21 connected to the third shift register 113.

[0196] For example, the third shift register 113 and the third reset circuit 218 of each pixel circuit 21 in the above-mentioned at least one row of pixel circuits 21 can be electrically connected through the third scan signal terminal SC3. Each third reset circuit 218 can receive the third scan signal through the third scan signal terminal SC3. Among them, the third reset circuit 218 is configured to be turned on in response to the third scan signal, and transmit the third initial signal from the third initial signal terminal Vinit3 to the driving circuit 212 and the compensation circuit 213. Of course, the third reset circuit 218 can also be electrically connected to the third initial signal terminal Vinit3 and the first node N1, and can transmit the third initial signal to the first node N1, which is not limited in the embodiment of the present application.

[0197] Here, in the case that the pixel circuit 21 includes both the second reset circuit 217 and the third reset circuit 218 , each third shift register 113 is electrically connected to the second reset circuit 217 and the third reset circuit 218 in the same pixel circuit 21 .

[0198] By setting the third reset circuit 218, the voltage difference between the output end of the third reset circuit 218 and the third node N3 can be adjusted by using the third initial signal. The output end of the third reset circuit 218 is, for example, the second node N2, so that the driving circuit 212 is in a biased state. When the display panel 10 displays a low-brightness picture, the problem of low frame rate flickering is improved. In addition, by using the same third shift register 113 to synchronously drive the second reset circuit 217 and the third reset circuit 218 of each pixel circuit 21 in at least one row of pixel circuits 21, it is possible to avoid increasing the number of shift registers and avoid increasing power consumption and frame size.

[0199] The relative position relationship between the third shift register 113, the fourth shift register 114, the pixel circuit 21, the first shift register 111 and the second shift register 112 includes various types, which can be selected and set according to actual needs.

[0200] In some embodiments, Fig.13 , Fig.14 , Fig.16 and Fig.17 As shown, at least one of the third shift register 113 and the fourth shift register 114 is located on a side outside the display area AA. It can also be said that the third shift register 113 is located on a side outside the display area AA, and / or the fourth shift register 114 is located on a side outside the display area AA.

[0201] Optionally, the third shift register 113 is located at a side outside the display area AA, for example Fig.13 The fourth shift register 114 is located on a side outside the display area, such as the left side, right side, upper side or lower side of the display area. Fig.13 Alternatively, the third shift register 113 is located on both sides outside the display area AA, for example Fig.14 The fourth shift register 114 is located on both sides outside the display area AA, for example Fig.14 The left and right sides of the .

[0202] Exemplarily, the above-mentioned at least one row of pixel circuits 21 can be electrically connected to a third shift register 113, and the third shift register 113 is located on a side outside the display area AA. The third shift register 113 adopts a unilateral driving method. Accordingly, the multiple rows of pixel circuits P in the display panel 10 are electrically connected to a third gate drive circuit 11c, and the third gate drive circuit 11c is located on a side outside the display area AA. Alternatively, the above-mentioned at least one row of pixel circuits 21 can also be electrically connected to two third shift registers 113, and the two third shift registers 113 are respectively located on both sides outside the display area AA. The third shift register 113 adopts a bilateral driving method. Accordingly, the multiple rows of pixel circuits P in the display panel 10 are electrically connected to two third gate drive circuits 11c, and the two third gate drive circuits 11c are respectively located on both sides outside the display area AA.

[0203] Exemplarily, the above-mentioned at least one row of pixel circuits 21 can be electrically connected to a fourth shift register 114, and the fourth shift register 114 is located on a side outside the display area AA. The fourth shift register 114 adopts a unilateral drive mode. Accordingly, the multiple rows of pixel circuits P in the display panel 10 are electrically connected to a fourth gate drive circuit 11d, and the fourth gate drive circuit 11d is located on a side outside the display area AA. Alternatively, the above-mentioned at least one row of pixel circuits 21 can also be electrically connected to two fourth shift registers 114, and the two fourth shift registers 114 are respectively located on both sides outside the display area AA. The fourth shift register 114 adopts a bilateral drive mode. Accordingly, the multiple rows of pixel circuits P in the display panel 10 are electrically connected to two fourth gate drive circuits 11d, and the two fourth gate drive circuits 11d are respectively located on both sides outside the display area AA.

[0204] When the third shift register 113 and / or the fourth shift register 114 are located on one side outside the display area AA, it is helpful to reduce the number of gate driving circuits in the display panel 10, and reduce the power consumption and frame size of the display panel 10. When the third shift register 113 and / or the fourth shift register 114 are located on both sides outside the display area AA, it is helpful to reduce the load of the corresponding gate driving circuit.

[0205] In some examples, the display panel 10 is, for example, a small or medium-sized display panel. Fig.13 and Fig.16 As shown, the at least one row of pixel circuits 21 can be electrically connected to a third shift register 113 and a fourth shift register 114. Along the row direction X of the multiple rows of pixel circuits 21, the third shift register 113 and the fourth shift register 114 are respectively located on both sides outside the display area AA.

[0206] Continue reading Fig.13and Fig.16 Correspondingly, along the row direction X of the multiple rows of pixel circuits 21, the third gate driving circuit 11c and the fourth gate driving circuit 11d are respectively located on both sides outside the display area AA.

[0207] In this way, along the row direction X of multiple rows of pixel circuits 21, the number of shift registers and their gate drive circuits on both sides of the display area AA can be balanced, so that the widths of the partial border areas BB on both sides outside the display area AA are the same or approximately the same, and it is beneficial to the wiring arrangement within the border area BB.

[0208] Furthermore, if Fig.13 and Fig.16 As shown, along the row direction X of the multiple rows of pixel circuits 21, the third shift register 113 is, for example, located on one side outside the display area AA together with the second shift register 112, and the fourth shift register 114 is, for example, located on the other side outside the display area AA together with the first shift register 111. Among them, the third shift register 113 is farther away from the pixel circuit 21 than the second shift register 112 located on the same side. And / or, the fourth shift register 114 is farther away from the pixel circuit 21 than the first shift register 111 located on the same side. That is, in the case where the third shift register 113 and the second shift register 112 are located on the same side outside the display area AA, the third shift register 113 is located on the side of the second shift register 112 away from the display area AA. In the case where the fourth shift register 114 and the first shift register 111 are located on the same side outside the display area AA, the fourth shift register 114 is located on the side of the first shift register 111 away from the display area AA.

[0209] This helps to reduce the voltage drop generated by the first scanning signal output by the first shift register 111 and the second scanning signal output by the second shift register 112 during the process of being transmitted to the pixel circuit 21, so that the data writing circuit 211 and the compensation circuit 213 can be fully opened in the corresponding working stage, thereby improving the speed of writing data signals to the display panel 10 and improving the accuracy of the data voltage written to the third node N3.

[0210] Of course, the locations of the third shift register 113 and the fourth shift register 114 can be interchanged, which is not limited in the embodiment of the present application.

[0211] In other examples, the display panel 10 is, for example, a large-sized display panel. Fig.14 and Fig.17As shown, the above-mentioned at least one row of pixel circuits 21 can be electrically connected to two third shift registers 113 and two fourth shift registers 114. Along the row direction X of the multiple rows of pixel circuits 21, the two third shift registers 113 are respectively located on both sides outside the display area AA, and the two fourth shift registers 114 are respectively located on both sides outside the display area AA. The third shift register 113 and the fourth shift register 114 are both set in a bilateral driving manner.

[0212] Continue reading Fig.14 and Fig.17 , the fourth shift register 114 is farther from the display area AA than the third shift register 113 located on the same side. That is, among the third shift register 113 and the fourth shift register 114 located on the same side, the fourth shift register 114 is located on the side of the third shift register away from the display area AA.

[0213] Of course, the locations of the third shift register 113 and the fourth shift register 114 on the same side may be swapped, which is not limited in the embodiment of the present application.

[0214] Here, contrast Fig.13 and Figure 6 , or contrast Fig.16 and Figure 6 In the case where the display panel 10 is a small or medium-sized display panel, the number of shift registers connected to every two rows of pixel circuits 21 is reduced from eight to five, for example. Fig.14 and Figure 7 , or contrast Fig.17 and Figure 7 In the case where the display panel 10 is a large-size display panel, the number of shift registers connected to every two rows of pixel circuits 21 is reduced from twelve to ten, for example. According to the test, the frame size of the display panel 10 is greater than or equal to 150 μm, and the power consumption is greater than or equal to 20 mW.

[0215] The structures of the above-mentioned light emitting control circuit 215, energy storage sub-circuit 216, second reset circuit 217 and third reset circuit 218 include various types. The structures of the light emitting control circuit 215, energy storage sub-circuit 216, second reset circuit 217 and third reset circuit 218 are schematically illustrated below in conjunction with the accompanying drawings, but the structures of the light emitting control circuit 215, energy storage sub-circuit 216, second reset circuit 217 and third reset circuit 218 are not limited to this.

[0216] In some examples, such as Fig.12 and Fig.15As shown, the light emitting control circuit 215 includes a fifth transistor T5 and a sixth transistor T6, the energy storage sub-circuit 216 includes a storage capacitor Cst, the second reset circuit 217 includes a seventh transistor T7, and the third reset circuit 218 includes an eighth transistor T8.

[0217] The control electrode of the fifth transistor T5 is electrically connected to the fourth shift register 114, the first electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected to the driving circuit 212. Specifically, the second electrode of the fifth transistor T5 is electrically connected to the first node N1. The control electrode of the sixth transistor T6 is electrically connected to the fourth shift register 114, the first electrode of the sixth transistor T6 is electrically connected to the driving circuit 212, and the second electrode of the sixth transistor T6 is electrically connected to the light emitting device 22. Specifically, the first electrode of the sixth transistor T6 is electrically connected to the second node N2.

[0218] For example, when the fourth scan signal transmitted by the fourth shift register 114 to the fifth transistor T5 and the sixth transistor T6 through the fourth scan signal terminal SC4 is at an effective working level, the fifth transistor T5 and the sixth transistor T6 can be turned on under the control of the fourth scan signal, connecting the path between the first voltage signal terminal ELVDD and the light emitting device 22. The effective working circuit here is, for example, a low level.

[0219] One end of the storage capacitor Cst is electrically connected to the first voltage signal terminal ELVDD, and the other end is electrically connected to the third node N3. The storage capacitor Cst is used to maintain the potential of the third node N3.

[0220] The control electrode of the seventh transistor T7 is electrically connected to the third shift register 113 , the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2 , and the second electrode of the seventh transistor T7 is electrically connected to the light emitting device 22 .

[0221] For example, when the third scan signal transmitted from the third shift register 113 to the seventh transistor T7 through the third scan signal terminal SC3 is at an effective working level, the seventh transistor T7 can be turned on under the control of the third scan signal, receive and transmit the second initial signal to the fourth node N4, and reset the anode of the light emitting device 22. The effective working level here is, for example, a low level.

[0222] The control electrode of the eighth transistor T8 is electrically connected to the third shift register 113, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal terminal Vinit3, and the second electrode of the eighth transistor T8 is electrically connected to the driving circuit 212. Specifically, the second electrode of the eighth transistor T8 is electrically connected to the second node N2 or the first node N1.

[0223] For example, when the third scan signal transmitted from the third shift register 113 to the eighth transistor T8 through the third scan signal terminal SC3 is at an effective working level, the eighth transistor T8 can be turned on under the control of the third scan signal, and receive and transmit the third initial signal to the second node N2 or the first node N1. The effective working level here is, for example, a low level.

[0224] The above configuration is helpful to simplify the structures of the light emitting control circuit 215 , the energy storage subcircuit 216 , the second reset circuit 217 and the third reset circuit 218 , and reduce the structural complexity and manufacturing difficulty of the display panel 10 .

[0225] The fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 and the eighth transistor T8 may be of various types and may be selected and set according to actual needs.

[0226] Optionally, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are all low-temperature polysilicon thin film transistors. In this way, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can all have higher electron mobility, thereby improving the electrical performance of the pixel circuit 21. Of course, the seventh transistor T7 and the eighth transistor T8 can also be metal oxide thin film transistors.

[0227] It is understandable that during the display process of the display panel 10, at least two refresh frame rates may be included. For example, the display panel 10 may include a first refresh frame rate and a second refresh frame rate, and the first refresh frame rate is greater than the second refresh frame rate. At the first refresh frame rate, a frame may include only a refresh frame period, and at the second refresh frame rate, a frame may include a refresh frame period and a hold frame period. Among them, the display panel 10 may include multiple refresh frame rates, and different refresh frame rates may be achieved by controlling the length of the hold frame period, which is not specifically limited in the embodiments of the present application.

[0228] Exemplarily, the display panel 10 includes a first refresh frame rate. Fig.18 A timing diagram is shown, which can be applied to sub-pixels of various structures. In the embodiment of the present application, the timing diagram is applied to Fig.12 The following takes the pixel circuit 21 of the nth row as an example, where n is a positive integer. Fig.18 and Fig.12 , the working process of the pixel circuit 21 is schematically described. Fig.18In the figure, SC1(n-1) represents the first scanning signal received by the data writing circuit 211 of the pixel circuit 21 of the n-1th row, SC1(n) represents the first scanning signal received by the data writing circuit 211 of the pixel circuit 21 of the nth row, SC1(n+1) represents the first scanning signal received by the data writing circuit 211 of the pixel circuit 21 of the n+1th row, SC2(n) represents the second scanning signal received by the compensation circuit 213 of the pixel circuit 21 of the nth row, SC3(n) represents the third scanning signal received by the second reset circuit 217 of the pixel circuit 21 of the nth row, and SC4(n) represents the fourth scanning signal received by the light emitting control circuit 215 of the pixel circuit 21 of the nth row.

[0229] like Fig.18 As shown, the working process of the pixel circuit 21 includes: a non-luminous stage S1 and a luminous stage S2. The non-luminous stage S1 includes a first reset stage t1, a data writing and compensation stage t2, and a second reset stage t3.

[0230] In the non-light-emitting stage S1, the level of the fourth scanning signal is high, the fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0231] In the first reset stage t1 of the non-light-emitting stage S1, the level of the second scanning signal transmitted to the n-th row pixel circuit 21 is high, and the first scanning signal transmitted to the n-1-th row pixel circuit 21 is synchronously transmitted to the first reset circuit 214 of the n-th row pixel circuit 21, and the level is high. The third transistor T3 and the fourth transistor T4 are both turned on, and the first initial signal from the first initial signal terminal Vinit1 is sequentially transmitted to the third node N3 through the fourth transistor T4, the second node N2, and the third transistor T3, and the third node N3 is reset.

[0232] Regarding the data writing in the non-light-emitting stage S1 and the compensation stage t2, reference may be made to the above related descriptions, which will not be described again here.

[0233] In the second reset stage t3 of the non-luminous stage S1, the level of the third scanning signal is low. The seventh transistor T7 and the eighth transistor T8 are both turned on, and the second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 via the seventh transistor T7, and the fourth node N4, that is, the anode of the light-emitting device 22, is reset. The third initial signal from the third initial signal terminal Vinit3 is transmitted to the second node N2 via the eighth transistor T8, and the second node N2 is reset. In addition, the third initial signal is also used to adjust the voltage difference between the third node N3 and the second node N2, alleviate or offset the drift of the threshold voltage of the second transistor T2, adjust the bias state of the second transistor T2, and improve the display uniformity of the display panel 10.

[0234] Regarding the light-emitting stage S2, please refer to the relevant description above, which will not be repeated here.

[0235] Among them, based on Fig.18 It can be seen from the timing diagram shown that when the third transistor T3 of the pixel circuit 21 in the nth row is turned on, the first transistor T1 of the pixel circuit 21 in the n-1th row, the nth row and the n+1th row can all be turned on to write data and compensate for the threshold voltage. Accordingly, each second shift register 112 can be electrically connected to the third transistor T3 of the pixel circuit 21 in three rows, that is, the compensation circuit 213, at the same time.

[0236] Exemplarily, the display panel 10 includes a first refresh frame rate and a second refresh frame rate. Fig.19 It also shows a corresponding Fig.15 The timing diagram of the sub-pixel shown in FIG. 1 is shown in FIG. 2 . Next, taking the pixel circuit 21 in the nth row as an example, n is a positive integer, and combining Fig.19 and Fig.15 , the working process of the pixel circuit 21 is schematically described. Fig.19 , SC1(n) represents the first scanning signal received by the pixel circuit 21 of the nth row, SC1(n+1) represents the first scanning signal received by the pixel circuit 21 of the n+1th row, SC2(n) represents the second scanning signal received by the pixel circuit 21 of the nth row, SC3(n) represents the third scanning signal received by the pixel circuit 21 of the nth row, SC4(n) represents the fourth scanning signal received by the pixel circuit 21 of the nth row, and Vinit3 represents the third initial signal received by the pixel circuit 21 of the nth row.

[0237] like Fig.19 As shown, the working process of the pixel circuit 21 includes: a refresh frame period and a hold frame period. In the refresh frame period, the working process of the pixel circuit 21 includes a non-luminous stage S1 and a luminous stage S2, and the non-luminous stage S1 includes a first reset stage t1, a data writing and compensation stage t2, and a second reset stage t3. In the hold frame period, the working process of the pixel circuit 21 includes a bias stage TK.

[0238] In the non-light-emitting stage S1, the level of the fourth scanning signal is high, the fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0239] In the first reset stage t1 of the non-luminous stage S1, the level of the second scanning signal is high, and the level of the third scanning signal is low. The third transistor T3 and the eighth transistor T8 are both turned on, and the third initial signal from the third initial signal terminal Vinit3 is transmitted to the third node N3 via the eighth transistor T8, the second node N2, and the third transistor T3 in sequence, and the third node N3 is reset; the seventh transistor T7 is turned on, and the second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N3 via the seventh transistor T7, and the anode of the light-emitting device 22 is reset.

[0240] Regarding the data writing in the non-light-emitting stage S1 and the compensation stage t2, reference may be made to the above related descriptions, which will not be described again here.

[0241] In the second reset stage t3 of the non-luminous stage S1, the level of the third scanning signal is a low level. The seventh transistor T7 and the eighth transistor T8 are both turned on, and the second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 via the seventh transistor T7, and the fourth node N4, that is, the anode of the light-emitting device 22, is reset. The third initial signal from the third initial signal terminal Vinit3 is transmitted to the second node N2 via the eighth transistor T8, and the second node N2 is reset. In addition, the third initial signal is also used to adjust the voltage difference between the third node N3 and the second node N2, alleviate or offset the drift of the threshold voltage of the second transistor T2, adjust the bias state of the second transistor T2, improve the problem of low frame rate flicker under low brightness, and improve the display uniformity of the display panel 10. In this example, the third initial signal is, for example, a variable frequency voltage signal, and the voltage value of the third initial signal in the second reset stage t3 is greater than its voltage value in the first reset stage t1. Furthermore, the voltage value of the third initial signal in the first reset stage t1, for example, is Fig.18 The voltage value of the first initial signal in the first reset phase t1 is the same as shown; the voltage value of the third initial signal in the second reset phase t3 is, for example, Fig.18 The voltage value of the third initial signal in the second reset phase t3 is the same.

[0242] Regarding the light-emitting stage S2, please refer to the relevant description above, which will not be repeated here.

[0243] In the bias stage TK, the potential at the control electrode of the second transistor T2, that is, the third node N3, maintains the potential of the previous stage, which is, for example, the potential after data writing and threshold voltage compensation. The eighth transistor T8 is turned on, and the third initial signal with a higher voltage value is transmitted to the second node N2 through the eighth transistor T8, so that the second transistor T2 is in a bias state.

[0244] Among them, based on Fig.19It can be seen from the timing diagram shown that when the third transistor T3 of the pixel circuit 21 in the nth row is turned on, the first transistor T1 of the pixel circuit 21 in the nth row and the n+1th row can be turned on to write data and compensate the threshold voltage. Accordingly, each second shift register 112 can be electrically connected to the third transistor T3 of the pixel circuit 21 in two rows, that is, the compensation circuit 213, at the same time.

[0245] Some embodiments of the present application also provide a display panel, and the structure and setting method of the multiple pixel circuits included in the display panel are, for example, the same as the structure and setting method of the multiple pixel circuits 21 in the display panel provided in some of the above embodiments. For details, please refer to the relevant description above, and no further description is given here. The difference between this display panel and the display panel provided in some of the above embodiments, for example, lies in: the setting method between the partial circuit structure included in the pixel circuit and the shift register. The difference is schematically explained below in conjunction with the accompanying drawings.

[0246] Fig. 20 , Fig.21 , Fig. 22 and Fig.25 The equivalent circuit diagrams of a sub-pixel are shown respectively. Fig.23 , Fig.24 , Fig.26 and Fig. 27 The partial structure diagrams of a display panel are shown respectively. Figure 20-Figure 27 The data writing circuit 211 and the compensation circuit 213 in the same pixel circuit 21 are electrically connected to the first shift register 111 and the second shift register 112 respectively. Fig.23 , Fig.24 , Fig.26 and Fig. 27 In the structure shown, the first shift register 111 is electrically connected to the data writing circuit 211 and the compensation circuit 213 of each pixel circuit 21 in a row of pixel circuits 21. That is, the data writing circuit 211 and the compensation circuit 213 in the same pixel circuit 21 are both electrically connected to the first shift register 111. For example, the first shift register 111 is configured to provide a first scanning signal to the data writing circuit 211 and the compensation circuit 213 of the pixel circuit 21 connected to the first shift register 111.

[0247] That is, the data writing circuit 211 and the compensation circuit 213 in the same pixel circuit 21 can both be electrically connected to the first scanning signal terminal SC1, and receive the first scanning signal from the same first shift register 111. The data writing circuit 211 and the compensation circuit 213 are configured to be turned on in response to the first scanning signal, and transmit the data signal from the data signal terminal Data to the driving circuit 212.

[0248] It is understandable that, since the transistors included in the data writing circuit 211 and the compensation circuit 213 are metal oxide thin film transistors, in a small or medium-sized display panel, the first shift register 111 can be set in a unilateral driving manner.

[0249] For example, the display panel 10 is a small or medium-sized display panel. Fig.23 and Fig.26 As shown, a row of pixel circuits 21 can be electrically connected to a first shift register 111, and the first shift register 111 is located on a side outside the display area AA. Correspondingly, the data writing circuit 211 and the compensation circuit 213 in the multiple rows of pixel circuits P in the display panel 10 are electrically connected to a first gate driving circuit 11a, and the first gate driving circuit 11a is located on a side outside the display area AA.

[0250] And in Figure 6 In the embodiment shown, the data writing circuit 211 of each row of pixel circuits 21 is electrically connected to two first shift registers GP-GOA, and the compensation circuit 213 of every two rows of pixel circuits 21 is electrically connected to a second shift register GN-GOA, which means that Figure 6 In comparison, in the embodiment of the present application, the number of shift registers electrically connected to the data writing circuit 211 and the compensation circuit 213 of every two rows of pixel circuits 21 is reduced by three, and accordingly, the number of gate driving circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 is reduced by two.

[0251] In addition, Fig. 9 In the embodiment shown, the data writing circuit 211 of each row of pixel circuits 21 is electrically connected to two first shift registers GP-GOA, and the compensation circuit 213 of every two rows of pixel circuits 21 is electrically connected to two second shift registers GN-GOA, which means that Fig. 9 In comparison, in the embodiment of the present application, the number of shift registers electrically connected to the data writing circuit 211 and the compensation circuit 213 of every two rows of pixel circuits 21 is reduced by four, and accordingly, the number of gate driving circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 is reduced by three.

[0252] For another example, the display panel 10 is a large-size display panel. Fig.24 and Fig. 27 As shown, a row of pixel circuits 21 can also be electrically connected to two first shift registers 111, and the two first shift registers 111 are respectively located on both sides outside the display area AA. Correspondingly, multiple rows of pixel circuits P in the display panel 10 are electrically connected to two first gate drive circuits 11a, and the two first gate drive circuits 11a are respectively located on both sides outside the display area AA.

[0253] And in Figure 7 In the embodiment shown, the data writing circuit 211 of each row of pixel circuits 21 is electrically connected to two first shift registers GP-GOA, and the compensation circuit 213 of every two rows of pixel circuits 21 is electrically connected to two second shift registers GN-GOA, which means that Figure 7 In comparison, in the embodiment of the present application, the number of shift registers electrically connected to the data writing circuit 211 and the compensation circuit 213 of every two rows of pixel circuits 21 is reduced by two, and accordingly, the number of gate driving circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 is reduced by two.

[0254] Therefore, the display panel 10 provided in some embodiments of the present application, by setting the transistors included in the data writing circuit 211 and the compensation circuit 213 to be metal oxide transistors, and setting the first shift register 111, so that the first shift register 111 is electrically connected to the data writing circuit 211 and the compensation circuit 213 in each pixel circuit 21 located in the same row, so that not only can the leakage be reduced through the data writing circuit 211 and the compensation circuit 213, the potential of the relevant nodes inside the pixel circuit 21 is maintained, and the power consumption caused by leakage is reduced; the first shift register 111 can also be shared to reduce the number of shift registers electrically connected to the pixel circuit 21, and correspondingly reduce the number of gate driving circuits, thereby reducing the space occupied by the gate driving circuit on the basis of reducing the power consumption caused by the large number of gate driving circuits, reducing the border size of the display panel 10, and facilitating the realization of a narrow border design of the display panel 10.

[0255] In some embodiments, Figure 20-22 As shown, in the case where the pixel circuit 21 includes the first reset circuit 214, the first reset circuit 214 and the data writing circuit 211 of the pixel circuits 21 located in different rows are electrically connected to the first shift register 111. Fig.23 and Fig.24 In the structure shown, the display panel 10 further includes a second shift register 112 located outside the display area AA, that is, located in the border area BB, and the second shift register 112 is electrically connected to the first reset circuit 214 of each pixel circuit 21 in at least one row of pixel circuits 21. Accordingly, the first reset circuits 214 and the data writing circuits 211 of the pixel circuits 21 located in different rows are electrically connected to different shift registers, respectively.

[0256] Further, the second shift register 112 is configured to provide a second scanning signal to a first reset circuit 214 of the pixel circuit 21 connected to the second shift register 112. The first reset circuit 214 is configured to be turned on in response to the second scanning signal, and transmit the first initial signal from the first initial signal terminal Vinit1 to the driving circuit 212 and the compensation circuit 213.

[0257] By arranging the second shift register 112 to be electrically connected to the first reset circuit 214 , it is beneficial to reduce the load of the second shift register 112 , and the display panel 10 can be controlled more flexibly to display images.

[0258] In this example, there are various connection relationships between the first reset circuit 214 and the drive circuit 212 and the compensation circuit 213, which can be selected and set according to actual needs.

[0259] For example, Fig. 22 As shown, the first reset circuit 214 is electrically connected to the second node N2. Correspondingly, the second electrode of the fourth transistor T4 included in the first reset circuit 214 is electrically connected to the second node N2. At this time, after the first reset circuit 214 is turned on in response to the second scan signal, the first initial signal is transmitted to the second node N2, and can be transmitted to the third node N3 via the compensation circuit 213 to reset the third node N3.

[0260] like Fig. 20 and Fig.21 As shown, the first reset circuit 214 is electrically connected to the third node N3. Correspondingly, the second electrode of the fourth transistor T4 included in the first reset circuit 214 is electrically connected to the third node N3. At this time, after the first reset circuit 214 is turned on in response to the second scan signal, the first initial signal is transmitted to the third node N3 to reset the third node N3.

[0261] For example, Figure 20-22 As shown, in the case where the data writing circuit 211 includes the first transistor T1, the driving circuit 212 includes the second transistor T2, and the compensation circuit 213 includes the third transistor T3, the connection mode between the first transistor T1, the second transistor T2 and the third transistor T3 is different from that of some of the above embodiments in that the control electrode of the first transistor T1 and the control electrode of the third transistor T3 are both electrically connected to the first shift register 111. In the case where the first reset circuit 214 includes the fourth transistor T4, the connection mode of the fourth transistor T4 is different from that of some of the above embodiments in that the control electrode of the fourth transistor T4 is electrically connected to the second shift register 112. For other details, please refer to the relevant description above, which will not be repeated here.

[0262] In some examples, such as Fig.23 and Fig.24 As shown, the second shift register 112 is located at a side outside the display area AA.

[0263] For example, Fig.23 As shown, at least one row of pixel circuits 21 may be electrically connected to a second shift register 112, and the second shift register 112 may be located on a side outside the display area AA along the row direction X of the multiple rows of pixel circuits 21. Correspondingly, the first reset circuit 214 in the multiple rows of pixel circuits P in the display panel 10 is electrically connected to a second gate drive circuit 11b, and the second gate drive circuit 11b is located on a side outside the display area AA.

[0264] At this time, the second shift register 112 is configured in a unilateral driving manner, and the display panel 10 is, for example, a small or medium-sized display panel.

[0265] This helps to reduce the load of the second shift register 112 and more flexibly control the display panel 10 to display images.

[0266] For example, Fig.24 As shown, at least one row of pixel circuits 21 can be electrically connected to two second shift registers 112, and the two second shift registers 112 are respectively located on both sides outside the display area AA along the row direction X of the multiple rows of pixel circuits 21. Correspondingly, the multiple rows of pixel circuits P in the display panel 10 are electrically connected to the two second gate driving circuits 11b, and the two second gate driving circuits 11b are respectively located on both sides outside the display area AA.

[0267] At this time, the second shift register 112 is configured in a double-sided driving manner, and the display panel 10 is, for example, a large-size display panel.

[0268] This helps to reduce the voltage drop generated when the second scanning signal output by the second shift register 112 is transmitted to the pixel circuit 21, so that the first reset circuit 214 can be fully opened in the corresponding working phase, thereby improving the writing speed of the first initial signal.

[0269] In some embodiments, Fig.23 As shown, in the case where the display panel 10 is a small or medium-sized display panel, a row of pixel circuits 21 can be electrically connected to a first shift register 111, and at least one row of pixel circuits 21 can be electrically connected to a second shift register 112. Wherein, along the row direction X of the multiple rows of pixel circuits 21, the first shift register 111 and the second shift register 112 are respectively located on both sides outside the display area AA. Specifically, please refer to the above description of the relative positions between the first shift register 111, the second shift register 112, and the pixel circuit 21, which will not be repeated here.

[0270] In other embodiments, Fig.24 As shown, in the case where the display panel 10 is a large-size display panel, a row of pixel circuits 21 can be electrically connected to two first shift registers 111, and at least one row of pixel circuits 21 is electrically connected to two second shift registers 112. Wherein, along the row direction X of the multiple rows of pixel circuits 21, the two first shift registers 111 are respectively located on both sides outside the display area AA, and the two second shift registers 112 are respectively located on both sides outside the display area AA. Accordingly, each side outside the display area AA is provided with a first gate driving circuit 11a including a first shift register 111, and a second gate driving circuit 11b including a second shift register 112.

[0271] For example, see Fig.24 , the second shift register 112 is closer to the display area AA than the first shift register 111 located on the same side. That is, among the first shift register 111 and the second shift register 112 located on the same side of the multiple rows of pixel circuits P, the first shift register 111 is farther away from the display area AA. Accordingly, the two second gate driving circuits 11b are located between the two first gate driving circuits 11a.

[0272] In this way, along the row direction X of the multiple rows of pixel circuits 21, it is beneficial to balance the number of shift registers and gate driving circuits on both sides of the display area AA, so that the frame sizes on both sides of the display area AA are substantially equal.

[0273] In some embodiments, in combination Figure 21-24 In the case where the pixel circuit 21 further includes a light emitting control circuit 215, a second reset circuit 217 and a third reset circuit 218, and includes a first reset circuit 214, the display panel 10 further includes a third shift register 113 and a fourth shift register 114, and the connection relationship, relative position relationship, etc. between the third shift register 113 and the fourth shift register 114 and the pixel circuit 21 are similar to those in some of the above embodiments, for example Fig.12 Same as shown. Fig.25 As shown, in the case where the light emitting control circuit 215, the second reset circuit 217 and the third reset circuit 218 are included but the first reset circuit 214 is not included, as shown in FIG. Fig.26 and Fig. 27 As shown, the display panel 10 further includes a third shift register 113 and a fourth shift register 114. The connection relationship, relative position relationship, etc. between the third shift register 113 and the fourth shift register 114 and the pixel circuit 21 are similar to those in some of the above embodiments, for example Fig.15 For details, please refer to the above description, which will not be repeated here.

[0274] Wherein, for the third reset circuit 218, as Fig.21 As shown, the third reset circuit 218 may be electrically connected to the first node N1, and correspondingly, the second electrode of the eighth transistor T8 in the third reset circuit 218 is electrically connected to the first node N1. Fig. 22 and Fig.25 As shown, the third reset circuit 218 may be electrically connected to the second node N2, and correspondingly, the second electrode of the eighth transistor T8 in the third reset circuit 218 is electrically connected to the second node N2.

[0275] Fig.28 A timing diagram is shown, which can be applied to sub-pixels of various structures. In the embodiment of the present application, the timing diagram is applied to Fig. 20 The following takes the pixel circuit 21 of the nth row as an example, where n is a positive integer. Fig.28 and Fig. 20 , the working process of the pixel circuit 21 is schematically described. Fig.28 , SC1(n) represents the first scanning signal received by the pixel circuit 21 of the nth row, SC1(n+1) represents the first scanning signal received by the pixel circuit 21 of the n+1th row, SC2(n) represents the second scanning signal received by the pixel circuit 21 of the nth row, SC3(n) represents the third scanning signal received by the pixel circuit 21 of the nth row, and SC4(n) represents the fourth scanning signal received by the pixel circuit 21 of the nth row.

[0276] like Fig.28 As shown, the working process of the pixel circuit 21 includes: a non-luminous stage S1 and a luminous stage S2. The non-luminous stage S1 includes a first reset stage t1, a data writing and compensation stage t2, and a second reset stage t3.

[0277] In the non-light-emitting stage S1, the level of the fourth scanning signal is high, the fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0278] In the first reset stage t1 of the non-luminous stage S1, the level of the second scanning signal is high, and the fourth transistor T4 is turned on, and the first initial signal from the first initial signal terminal Vinit1 is transmitted to the first node N1 through the fourth transistor T4 to reset the first node N1.

[0279] In the data writing and compensation phase t2 of the non-luminous phase S1, the level of the first scanning signal is high. The first transistor T1 and the third transistor T3 are both turned on, and the data signal from the data signal terminal Data is sequentially transmitted to the third node N3 through the first transistor T1, the first node N1, the second transistor T2, the second node N2, and the third transistor T3, so as to realize the writing of the data signal and the compensation of the threshold voltage of the second transistor T2. During this period, the storage capacitor Cst is also charged to maintain the potential of the third node N3.

[0280] In the second reset stage t3 of the non-luminous stage S1, the level of the third scanning signal is low. The seventh transistor T7 and the eighth transistor T8 are both turned on, and the second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 via the seventh transistor T7, and the fourth node N4, that is, the anode of the light-emitting device 22, is reset. The third initial signal from the third initial signal terminal Vinit3 is transmitted to the first node N1 via the eighth transistor T8, and the first node N1 is reset. In addition, the third initial signal is also used to adjust the voltage difference between the third node N3 and the first node N1, alleviate or offset the drift of the threshold voltage of the second transistor T2, adjust the bias state of the second transistor T2, and improve the display uniformity of the display panel 10.

[0281] Regarding the light-emitting stage S2, please refer to the relevant description above, which will not be repeated here.

[0282] Among them, based on Fig.28 It can be seen from the timing diagram shown that before the seventh transistor T7 and the eighth transistor T8 of the n-th row of pixel circuits 21 are turned on, the first transistor T1 and the third transistor T3 of the n-th row of pixel circuits 21, and the first transistor T1 and the third transistor T3 of the n+1-th row of pixel circuits 21 are turned on in time division to perform data writing and threshold voltage compensation. Accordingly, each third shift register 113 can be electrically connected to the seventh transistor T7 and the eighth transistor T8 of the two rows of pixel circuits 21, that is, the second reset circuit 217 and the third reset circuit 218 at the same time.

[0283] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a frame area, wherein the frame area is located on at least two sides outside the display area; the display panel includes: A plurality of rows of pixel circuits are located in the display area; each row of pixel circuits comprises a data writing circuit, a driving circuit and a compensation circuit, the data writing circuit is electrically connected to the driving circuit and the data signal terminal, and the driving circuit is electrically connected to the compensation circuit; the transistors included in the data writing circuit and the compensation circuit are metal oxide thin film transistors; a first shift register, located in the frame area; the first shift register is electrically connected to a data writing circuit of a row of pixel circuits; the first shift register is configured to provide a first scanning signal to the data writing circuit of the pixel circuit connected to the first shift register; the data writing circuit is configured to be turned on in response to the first scanning signal, and transmit the data signal from the data signal terminal to the compensation circuit; A second shift register is located in the border area; the second shift register is electrically connected to the compensation circuit of at least one row of pixel circuits; the second shift register is configured to provide a second scanning signal to the compensation circuit of the pixel circuit connected to the second shift register; the compensation circuit is configured to be turned on in response to the second scanning signal to transmit the data signal to the driving circuit.

2. The display panel according to claim 1, characterized in that: The first shift register is located at a side outside the display area, and / or the second shift register is located at a side outside the display area.

3. The display panel according to claim 2, characterized in that: A row of pixel circuits is electrically connected to a first shift register, and a second shift register is electrically connected to at least one row of pixel circuits; Along the row direction of the multiple rows of pixel circuits, the first shift register and the second shift register are respectively located on two sides outside the display area.

4. The display panel according to claim 2, characterized in that: A row of pixel circuits is electrically connected to two of the first shift registers, and at least one row of pixel circuits is electrically connected to two of the second shift registers; Along the row direction of the plurality of rows of pixel circuits, the two first shift registers are respectively located at two sides outside the display area, and the two second shift registers are respectively located at two sides outside the display area.

5. The display panel according to any one of claims 1 to 4, characterized in that: The data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor; the first transistor and the third transistor are both metal oxide thin film transistors; The control electrode of the first transistor is electrically connected to the first shift register, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor; The control electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; The control electrode of the third transistor is electrically connected to the second shift register.

6. The display panel according to any one of claims 1 to 5, characterized in that: The pixel circuit further includes a first reset circuit, which is electrically connected to the drive circuit, the compensation circuit and the first initial signal terminal; the transistor included in the first reset circuit is a metal oxide thin film transistor; The first shift register is also electrically connected to a first reset circuit of a row of pixel circuits; the first shift register is also configured to provide the first scanning signal to the first reset circuit of the pixel circuit connected to the first shift register; the first reset circuit is configured to be turned on in response to the first scanning signal, and transmit the first initial signal from the first initial signal terminal to the driving circuit and the compensation circuit; The pixel circuits to which the first reset circuit and the data writing circuit connected to the same first shift register belong are located in different rows.

7. The display panel according to claim 6, characterized in that: The pixel circuit to which the first reset circuit connected to the same first shift register belongs is located in a previous row to which the pixel circuit to which the data writing circuit connected to the same first shift register belongs belongs.

8. The display panel according to claim 6 or 7, characterized in that: The first reset circuit includes a fourth transistor, and the fourth transistor is the metal oxide thin film transistor; The control electrode of the fourth transistor is electrically connected to the first shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the driving circuit and the compensation circuit.

9. A display panel, characterized in that: The display panel comprises a display area and a frame area, wherein the frame area is located on at least two sides outside the display area; the display panel comprises: A plurality of rows of pixel circuits are located in the display area; a row of pixel circuits comprises a data writing circuit, a driving circuit and a compensation circuit, the data writing circuit is electrically connected to the driving circuit and the data signal terminal, the driving circuit is electrically connected to the compensation circuit; the transistors included in the data writing circuit and the compensation circuit are both metal oxide thin film transistors; A first shift register is located in the border area; the first shift register is electrically connected to a data writing circuit and a compensation circuit of a row of pixel circuits; the first shift register is configured to provide a first scanning signal to the data writing circuit and the compensation circuit of the pixel circuit connected to the first shift register; the data writing circuit and the compensation circuit are configured to be turned on in response to the first scanning signal, and transmit the data signal from the data signal end to the driving circuit.

10. The display panel according to claim 9, characterized in that: The data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor; the first transistor and the third transistor are both metal oxide thin film transistors; The control electrode of the first transistor is electrically connected to the first shift register, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor; The control electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; The control electrode of the third transistor is electrically connected to the first shift register.

11. The display panel according to claim 9 or 10, characterized in that: The pixel circuit further includes a first reset circuit, which is electrically connected to the drive circuit, the compensation circuit and the first initial signal terminal; the transistor included in the first reset circuit is a metal oxide thin film transistor; The display panel also includes a second shift register located in the border area, and the second shift register is electrically connected to the first reset circuit of at least one row of pixel circuits; the second shift register is configured to provide a second scanning signal to the first reset circuit of the pixel circuit connected to the second shift register; the first reset circuit is configured to be turned on in response to the second scanning signal, and transmit the first initial signal from the first initial signal terminal to the drive circuit and the compensation circuit.

12. The display panel according to claim 11, characterized in that: The first shift register is located at a side outside the display area, and / or the second shift register is located at a side outside the display area.

13. The display panel according to claim 12, characterized in that: A row of pixel circuits is electrically connected to one of the first shift registers, and a second shift register is electrically connected to at least one row of pixel circuits; Along the row direction of the multiple rows of pixel circuits, the first shift register and the second shift register are respectively located on two sides outside the display area.

14. The display panel according to claim 12, characterized in that: A row of pixel circuits is electrically connected to two of the first shift registers, and at least one row of pixel circuits is electrically connected to two of the second shift registers; Along the row direction of the plurality of rows of pixel circuits, the two first shift registers are respectively located at two sides outside the display area, and the two second shift registers are respectively located at two sides outside the display area.

15. The display panel according to any one of claims 11 to 14, characterized in that: The first reset circuit includes a fourth transistor, and the fourth transistor is the metal oxide thin film transistor; The control electrode of the fourth transistor is electrically connected to the second shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the driving circuit and the compensation circuit.

16. The display panel according to any one of claims 1 to 15, characterized in that: The second transistor is the metal oxide thin film transistor, or the second transistor is a low temperature polysilicon thin film transistor.

17. The display panel according to any one of claims 1 to 16, characterized in that: The display panel further comprises a light emitting device, a third shift register and a fourth shift register, wherein the light emitting device is located in the display area, and the third shift register and the fourth shift register are located outside the display area; the pixel circuit further comprises a light emitting control circuit, a second reset circuit and a third reset circuit; The light emitting control circuit is electrically connected to the first voltage signal terminal, the driving circuit, and the light emitting device; the second reset circuit is electrically connected to the second initial signal terminal and the light emitting device; and the third reset circuit is electrically connected to the third initial signal terminal and the driving circuit; The third shift register is electrically connected to the second reset circuit and the third reset circuit of at least one row of pixel circuits; the third shift register is configured to provide a third scan signal to the second reset circuit and the third reset circuit of the pixel circuit connected to the third shift register; the second reset circuit is configured to be turned on in response to the third scan signal, and transmit the second initial signal from the second initial signal terminal to the light emitting device; The third reset circuit is configured to be turned on in response to the third scanning signal, and transmit the third initial signal from the third initial signal terminal to the driving circuit; The fourth shift register is electrically connected to the light emitting control circuit of at least one row of pixel circuits; the fourth shift register is configured to provide a fourth scanning signal to the light emitting control circuit of the pixel circuit connected to the fourth shift register; the light emitting control circuit is configured to be turned on in response to the fourth scanning signal, thereby connecting the path between the first voltage signal terminal and the light emitting device.

18. The display panel according to claim 17, characterized in that: The third shift register is located at a side outside the display area, and / or the fourth shift register is located at a side outside the display area.

19. The display panel according to claim 18, characterized in that: At least one row of pixel circuits is electrically connected to one of the third shift registers and one of the fourth shift registers; Along the row direction of the multiple rows of pixel circuits, the third shift register and the fourth shift register are respectively located on two sides outside the display area.

20. The display panel according to claim 18, characterized in that: At least one row of pixel circuits is electrically connected to the two third shift registers and the two fourth shift registers; Along the row direction of the plurality of rows of pixel circuits, the two third shift registers are respectively located at two sides outside the display area, and the two fourth shift registers are respectively located at two sides outside the display area.

21. The display panel according to any one of claims 17 to 20, characterized in that: The light emitting control circuit includes a fifth transistor and a sixth transistor, the second reset circuit includes a seventh transistor, and the third reset circuit includes an eighth transistor; The control electrode of the fifth transistor is electrically connected to the fourth shift register, the first electrode of the fifth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the driving circuit; The control electrode of the sixth transistor is electrically connected to the fourth shift register, the first electrode of the sixth transistor is electrically connected to the driving circuit, and the second electrode of the sixth transistor is electrically connected to the light emitting device; The control electrode of the seventh transistor is electrically connected to the third shift register, the first electrode of the seventh transistor is electrically connected to the second initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the light emitting device; The control electrode of the eighth transistor is electrically connected to the third shift register, the first electrode of the eighth transistor is electrically connected to the third initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the driving circuit.

22. The display panel according to claim 21, characterized in that: The fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all low-temperature polysilicon thin film transistors.

23. A display module, characterized in that: The display module comprises: The display panel as claimed in any one of claims 1 to 22; The display driver is electrically connected to the display panel.

24. An electronic device, characterized in that: The electronic device comprises: The display module as claimed in claim 23; The driving controller is coupled to the display module.

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