Packaging structure, packaging method, chip stacking structure and electronic device

Abstract

The present disclosure relates to a packaging structure, a packaging method, a chip stacking structure, and an electronic device. The packaging structure includes a first chip of the packaging structure and a second chip stacked with the first chip. The first chip is provided with a first element. The second chip is arranged opposite to the active surface of the first chip. The second chip includes a shielding element, which is arranged on a side of the second chip close to the first chip. The shielding element is used to reduce the signal interference of the second chip on the first element. The packaging structure of the present disclosure, by providing a shielding element on the second chip and arranging the shielding element on the side of the second chip close to the first chip, can reduce or even avoid the signal interference generated by the second chip on the first element by the shielding element, thereby improving the signal quality of the first element and the signal quality of the packaging structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure, a packaging method, a chip stacking structure, and an electronic device. Background Art

[0002] Three-dimensional stacked chips not only enable high-density vertical interconnection between chips through methods like hybrid bonding, increasing the equivalent two-dimensional integration density of the chip, but also enable heterogeneous integration at different process nodes, increasing system functional density and meeting the growing demand for computing power. However, stacking chips with high integration density reduces the distance between them, causing interference between high-speed signals within different chips and affecting their integrity. Summary of the Invention

[0003] In a first aspect, the present disclosure provides a packaging structure to improve the signal quality of the packaging structure.

[0004] The packaging structure disclosed herein includes a first chip and a second chip stacked with the first chip, wherein the first chip is provided with a first element; wherein the second chip is arranged opposite to the active surface of the first chip; the second chip includes a shielding element, wherein the shielding element is arranged on a side of the second chip close to the first chip, and the shielding element is used to reduce signal interference of the second chip on the first element.

[0005] Optionally, an orthographic projection of the shielding element in a direction toward the first chip at least partially covers the first element.

[0006] Optionally, an area of ​​an orthographic projection of the shielding element in a direction toward the first chip is larger than an area of ​​a region where the first element is located.

[0007] Optionally, the second chip includes a first circuit, and the first circuit is arranged on a side of the shielding element away from the first element in a thickness direction of the package structure.

[0008] Optionally, the first chip includes multiple first wiring layers, and the multiple first wiring layers are arranged along the thickness direction of the packaging structure. At least one first wiring layer is a first top layer, and the first top layer is arranged closer to the second chip than the other first wiring layers in the thickness direction of the packaging structure. The first element is at least partially arranged in the first top layer.

[0009] Optionally, the second chip includes multiple second wiring layers, and the multiple second wiring layers are arranged along the thickness direction of the packaging structure. At least one second wiring layer is a second top layer, and the second top layer is arranged closer to the first chip than the remaining second wiring layers in the thickness direction of the packaging structure, and the shielding element is arranged on the second top layer.

[0010] Optionally, the first chip is provided with a plurality of first electrical connectors, the second chip is provided with a plurality of second electrical connectors, and the second electrical connectors are interconnected with the first electrical connectors; an electrical connection area and a clearance area are provided between the first chip and the second chip, the first electrical connectors and the second electrical connectors are provided in the electrical connection area, and the orthographic projection of the clearance area in the direction toward the first element at least partially covers the first element.

[0011] Optionally, an area of ​​a positive projection of the clearance zone in a direction toward the first element is larger than an area of ​​a region where the first element is located.

[0012] Optionally, a minimum distance between an edge of a positive projection of the clearance area in a direction toward the first element and the first element is at least greater than or equal to 5 μm.

[0013] Optionally, the orthographic projection of the first element in the direction toward the second chip is polygonal, and the clearance area is polygonal.

[0014] Optionally, there are multiple first elements and multiple clearance areas, and each clearance area is provided corresponding to at least one first element.

[0015] Optionally, the distance between two adjacent clearance areas is greater than or equal to 20 μm.

[0016] Optionally, the area of ​​the clearance zone is less than or equal to 0.08 mm 2 .

[0017] Optionally, the shielding element comprises a metal layer.

[0018] Optionally, the metal density of the area where the metal layer is located is 30% to 50%.

[0019] Optionally, the shielding element is grounded or connected to a power supply.

[0020] Optionally, the shielding element includes a first shielding part and a second shielding part, both of which are comb-shaped; the first shielding part includes a plurality of first metal strips arranged side by side, and the second shielding part includes a plurality of second metal strips arranged side by side, and the first metal strips and the second metal strips are arranged alternately and at intervals.

[0021] Optionally, the first chip includes a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

[0022] Optionally, the first element includes at least one of an inductor, a sensor and a capacitor.

[0023] In a second aspect, the present disclosure provides a packaging method.

[0024] The packaging method disclosed herein is used to form any of the above-mentioned packaging structures, and the packaging method includes:

[0025] Disposing a first component on the first chip;

[0026] providing a shielding element on the second chip;

[0027] The first chip and the second chip are stacked, wherein the shielding element is arranged on a side of the second chip close to the first chip, and the second chip is arranged opposite to the active surface of the first chip, and the shielding element is used to reduce signal interference of the second chip on the first element.

[0028] Optionally, providing a first component on the first chip includes:

[0029] forming at least one first wiring layer on the active surface of the first chip, wherein the first wiring layer is arranged along the thickness direction of the package structure;

[0030] The first element is formed by at least one of the first wiring layers.

[0031] Optionally, the packaging method includes:

[0032] At least one of the first wiring layers is a first top layer, which is arranged closer to the second chip than the other first wiring layers in the thickness direction of the package structure, and the first component is at least partially arranged on the first top layer.

[0033] Optionally, providing a shielding element on the second chip includes:

[0034] forming at least one second wiring layer on the active surface of the second chip, wherein the second wiring layer is arranged along the thickness direction of the package structure;

[0035] The shielding element is formed by at least one second wiring layer.

[0036] Optionally, at least one of the second wiring layers is a second top layer, which is arranged closer to the first chip than the other second wiring layers in the thickness direction of the package structure, and the shielding element is arranged on the second top layer.

[0037] In the present disclosure, the formation of the first top layer, the second top layer or the shielding layer can be achieved through relevant processes, such as a patterning process, which is not elaborated in the present disclosure.

[0038] In a third aspect, the present disclosure proposes a chip stacking structure.

[0039] The chip stacking structure disclosed in the present invention includes a substrate and a packaging structure provided on the substrate, and the packaging structure is any one of the packaging structures described above.

[0040] In a fourth aspect, the present disclosure provides an electronic device.

[0041] The electronic device disclosed in the present invention comprises a printed circuit board and any one of the above-mentioned packaging structures, wherein the printed circuit board is connected to the packaging structure.

[0042] The packaging structure disclosed herein provides a shielding element on the second chip, and the shielding element is provided on the side of the second chip close to the first chip, so that the shielding element can reduce or even avoid the signal interference caused by the second chip to the first element, thereby improving the signal quality of the first element and the signal quality of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 FIG. 4 is a cross-sectional view of a packaging structure in one embodiment of the present disclosure.

[0044] Figure 2 It is a partial cross-sectional view of a packaging structure according to an embodiment of the present disclosure.

[0045] Figure 3 is a cross-sectional view of a packaging structure according to another embodiment of the present disclosure.

[0046] Figure 4 yes Figure 3 Enlarged view of point A in the middle.

[0047] Figure 5 It is a structural schematic diagram of a shielding element of a packaging structure according to another embodiment of the present disclosure.

[0048] Figure 6 It is a structural schematic diagram of the shielding element and the first element of the packaging structure of another embodiment of the present disclosure.

[0049] Figure 7 It is a structural schematic diagram of a shielding element of a packaging structure according to another embodiment of the present disclosure.

[0050] Figure 8 It is a structural schematic diagram of a shielding element of a packaging structure according to another embodiment of the present disclosure.

[0051] Figure 9It is a structural schematic diagram of a shielding element of a packaging structure according to another embodiment of the present disclosure.

[0052] Figure 10 3 is a schematic structural diagram of the electrical connection area and clearance area of ​​a packaging structure according to another embodiment of the present disclosure.

[0053] Figure 11 3 is a schematic structural diagram of an electrical connection area, a clearance area, and a first element of a packaging structure according to another embodiment of the present disclosure.

[0054] Figure 12 and Figure 13 This is a simulation diagram provided by yet another embodiment of the present disclosure.

[0055] Reference numerals:

[0056] 10. Package chip;

[0057] 1. First chip; 11. First component; 12. Second circuit; 13. First electrical connector; 14. First through-hole; 101. First wiring layer; 1011. First top layer; 102. Electrical connection area; 103. Clearance area;

[0058] 2. Second chip; 21. Shielding element; 211. First shielding portion; 2111. First metal strip; 212. Second shielding portion; 2121. Second metal strip; 213. Shielding portion; 2131. Metal strip; 22. First circuit; 23. Third circuit; 24. Second electrical connector; 25. Second via; 201. Second wiring layer; 2011. Second top layer;

[0059] 100. Packaging structure; 1001. First chip; 1002. Second chip; 1003. Inductor element; 1004. Circuit. DETAILED DESCRIPTION

[0060] The embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present disclosure, but should not be understood as limiting the present disclosure.

[0061] like Figure 1 and Figure 2 A package structure 100 is disclosed in one embodiment of the present disclosure. Figure 1 and Figure 2In the example, the inductor element 1003 needs to be provided with a clearance area of ​​a certain size to prevent other traces from affecting the Q value and inductance of the inductor element 1003. Since the active surfaces of the first chip 1001 and the second chip 1002 in the package structure 100 are connected by a hybrid bonding method, the distance L between the first chip 1001 and the second chip 1002 is only a few microns. The inductor element 1003 of the first chip 1001 cannot achieve the required clearance area, and the line 1004 on the second chip 1002 will interfere with the inductor element 1003 of the first chip 1001, reducing the signal quality of the inductor element 1003 and further affecting the operation of the first chip 1001. Especially in high-speed scenarios, such as when the transmission speed reaches 10BPS or more, the inductor element 1003 is more susceptible to the influence of the second chip 1002. Therefore, how to improve the signal quality of the inductor element 1003 in the first chip 1001 is a technical problem that needs to be solved urgently.

[0062] like Figure 3 and Figure 4 As shown, the package structure 10 of the embodiment of the present disclosure includes a first chip 1 and a second chip 2. The second chip 2 is stacked with the first chip 1, and the second chip 2 is arranged opposite the active surface of the first chip 1. The first chip 1 includes a first element 11, and the second chip 2 includes a shielding element 21. The shielding element 21 is arranged on a side of the second chip 2 close to the first chip 1. The shielding element 21 is used to reduce signal interference from the second chip 2 to the first element 11.

[0063] The shielding element 21 is arranged on a side of the second chip 2 close to the first chip 1 , which means that the second chip 2 has a first side facing the first chip 1 and a second side facing away from the first chip 1 , and the shielding element 21 is arranged on the first side.

[0064] It should be noted that the chip in the embodiment of the present disclosure can be a grain (also referred to as a particle or a bare chip) (die) or a chip wafer. It is understandable that after the epitaxial layer is grown on the wafer, the chip wafer is formed, and the chip wafer is cut to obtain a bare chip (die). Grains can be bonded to each other (die-to-die bonding, D2D bonding). The chip wafer bonding is called wafer-to-wafer bonding (wafer-to-wafer bonding, W2W bonding). Multiple grains are stacked on a chip wafer, and such a structure can be called grain-to-wafer bonding (die-to-wafer bonding, D2W bonding). The package disclosed in the present disclosure can also be at least one of chip to wafer (C2W) bonding, die to wafer (D2C) bonding, and chip to chip (C2C) bonding.

[0065] The present disclosure does not limit the number of chips stacked in the chip stacking structure, and the number of stacked chips can be set according to application needs. In addition, the above-mentioned chips can be memory chips, logic chips, or chips with other functions.

[0066] The packaging structure 10 of the embodiment of the present disclosure provides a shielding element 21 on the second chip 2, and the shielding element 21 is provided on the side of the second chip 2 close to the first chip 1, so that the shielding element 21 can reduce or even avoid the signal interference caused by the second chip 2 to the first element 11, thereby improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0067] Optionally, the first chip 1 includes a logic chip, and the second chip 2 includes a memory chip; or, both the first chip 1 and the second chip 2 are logic chips.

[0068] The logic chip may be an application chip, and the memory chip may be a dynamic random access memory chip DRAM.

[0069] The first elements of the present disclosure include elements for realizing specific functions, which may be referred to as functional elements.

[0070] Optionally, the first component 11 includes an inductor. It is understandable that the first component can also be other functional devices affected by the second chip, such as a sensor, a capacitor, etc.

[0071] In the present disclosure, the inductor element is very susceptible to the influence of the second chip 2 , and the present application solution can be preferably used in the scenario where the first element 11 is an inductor.

[0072] By providing the shielding element 21 , the signal interference of the second chip 2 on the inductor, sensor or capacitor can be reduced or even avoided, thereby improving the signal quality of the package structure 10 .

[0073] In order to make the technical solution of the present disclosure easier to understand, the following takes the thickness direction of the packaging structure 10 as an example to further describe the technical solution of the present disclosure. Figure 3 and Figure 4 shown.

[0074] For example, the first chip 1 is disposed on a lower side of the second chip 2 , the first element 11 is disposed on a lower side of the shielding element 21 , and the shielding element 21 is disposed on a lower side of the second chip 2 .

[0075] Optionally, the second chip 2 includes a first circuit, and the first circuit 22 is provided on a side of the shielding element 21 away from the first element 11 in the thickness direction of the package structure 10 .

[0076] For example, the first element 11 is provided on the lower side of the shielding element 21 , and the first line 22 is provided on the upper side of the shielding element 21 .

[0077] By arranging the first circuit 22 on the side of the shielding element 21 away from the first element 11, the shielding element 21 can be used to shield the signal of the first element 11, reducing or even avoiding the signal interference caused by the first circuit 22 to the first element 11, and improving the signal quality of the packaging structure 10.

[0078] Alternatively, as Figure 3 and Figure 4 As shown, the first chip 1 includes multiple first wiring layers 101, which are arranged along the thickness direction of the package structure 10. At least one first wiring layer 101 is a first top layer 1011, which is arranged closer to the second chip 2 than the remaining first wiring layers 101 in the thickness direction of the package structure 10. The first component 11 is at least partially arranged on the first top layer 1011.

[0079] Among them, the first element 11 is at least partially arranged on the first top layer 1011, which can be understood as: a part of the first element 11 is arranged on the first top layer 1011, and another part of the first element 11 is arranged on other first wiring layers 101 except the first top layer 1011; or, the first element 11 is entirely arranged on the first top layer 1011.

[0080] For example, a plurality of first wiring layers 101 are arranged in an up-down direction, wherein one of the first wiring layers 101 is a first top layer 1011 , and the first top layer 1011 is located at the uppermost side among the plurality of first wiring layers 101 .

[0081] In the embodiment of the present disclosure, among the plurality of first wiring layers 101 , the first wiring layer 101 closer to the second chip 2 has a greater thickness and a lower resistance.

[0082] By disposing at least a portion of the first element 11 on the first top layer 1011 , the parasitic resistance of the first element 11 can be reduced, thereby increasing the Q value of the first element 11 , further improving the signal quality of the first element 11 , and improving the signal quality of the package structure 10 .

[0083] Alternatively, as Figure 3 As shown, the first chip 1 further includes a second circuit 12 . The second circuit 12 is arranged on at least one side of the first element 11 in a preset direction. The preset direction is perpendicular to the thickness direction of the package structure 10 .

[0084] In order to make the technical solution of the present disclosure easier to understand, the following takes the preset direction and the left and right directions as an example to further describe the technical solution of the present disclosure. Figure 3 and Figure 4 shown.

[0085] For example, the second lines 12 are located on both left and right sides of the first element 11 in the left-right direction.

[0086] By arranging the second line 12 on at least one side of the first element 11 in a preset direction, compared with arranging the second line 12 on a side of the first element 11 away from the shielding element 21 in the preset direction, the interference of the second line 12 on the first element 11 can be reduced, thereby further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0087] Alternatively, as Figure 3 As shown, the second chip 2 includes multiple second wiring layers 201, which are arranged along the thickness direction of the package structure 10. At least one second wiring layer 201 is a second top layer 2011, which is arranged closer to the first chip 1 than the remaining second wiring layers 201 in the thickness direction of the package structure 10. The shielding element 21 is arranged on the second top layer 2011.

[0088] For example, the plurality of second wiring layers 201 are arranged in an up-down direction, wherein one of the second wiring layers 201 is a second top layer 2011 , and the second top layer 2011 is located at the bottom of the plurality of second wiring layers 201 .

[0089] It can be understood that, among the plurality of second top layers 2011 , the second wiring layer 201 closer to the first chip 1 has a greater thickness.

[0090] By setting the shielding element 21 on the second top layer 2011, on the one hand, the signal shielding effect of the shielding element 21 can be improved, thereby further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10; on the other hand, the remaining second wiring layer 201 away from the first element 11 can be used as the first line 22, thereby improving the integration of the second chip 2 and thus improving the integration of the packaging structure 10.

[0091] Alternatively, as Figure 3 As shown, the second chip 2 further includes a third circuit 23 . The third circuit 23 is arranged on at least one side of the shielding element 21 in a preset direction. The preset direction is perpendicular to the thickness direction of the package structure 10 .

[0092] For example, the third lines 23 are located on both left and right sides of the first element 11 in the left-right direction.

[0093] By arranging the third circuit 23 on at least one side of the shielding element 21 in a preset direction, the integration level of the second chip 2 can be further improved, thereby improving the integration level of the package structure 10 .

[0094] Alternatively, as Figure 3 and Figure 4 As shown, the first chip 1 is provided with a plurality of first electrical connectors 13, and the second chip 2 is provided with a plurality of second electrical connectors 24, wherein the second electrical connectors 24 are interconnected with the first electrical connectors 13. The first chip 1 includes a first wiring layer 101, and the shielding element 21 is electrically connected to the first wiring layer 101 via the second electrical connectors 24 and the first electrical connectors 13.

[0095] like Figure 3 As shown, the first chip 1 is provided with a first through-hole 14, through which the first electrical connector 13 extends to the circuit of the first chip 1. The second chip 2 is provided with a second through-hole 25, through which the second electrical connector 24 extends to the circuit of the second chip 2. In other words, the first chip 1 and the second chip 2 are connected by hybrid bonding.

[0096] The shielding element 21 is electrically connected to the first wiring layer 101 via the second electrical connector 24 and the first electrical connector 13 .

[0097] Optionally, the shielding element 21 includes a shielding layer made of electromagnetic shielding material.

[0098] Optionally, the shielding element 21 comprises a metal layer.

[0099] It can be understood that the shielding element 21 in the present disclosure is not limited to a metal layer or an electromagnetic shielding layer, but may also be other elements having an electromagnetic shielding function.

[0100] By configuring the shielding element 21 to include a metal layer, the signal shielding effect of the shielding element 21 can be improved, and the signal quality of the first element 11 and the signal quality of the packaging structure 10 can be further improved.

[0101] Optionally, the metal density of the area where the metal layer is located is 30% to 50%.

[0102] For example, Figure 5 As shown, the area in the dotted box is the area where the metal layer is located, and the ratio of the area of ​​the metal layer to the area of ​​the dotted box is the metal density of the area where the metal layer is located.

[0103] By setting the metal density of the metal layer to 30% to 50%, the metal content of the shielding element 21 can be reduced while ensuring the shielding effect of the shielding element 21, thereby reducing the cost of the packaging structure 10. Optionally, the shielding element 21 is grounded or connected to a power line.

[0104] For example, the shielding element 21 is electrically connected to the first wiring layer 101 , and the first wiring layer 101 is grounded or connected to a power line, thereby enabling the shielding element 21 to be grounded or connected to a power line.

[0105] By grounding the shielding element 21 , the signal shielding effect of the shielding element 21 can be improved, the signal interference generated by the second chip 2 on the first element 11 can be reduced, and the signal quality of the package structure 10 can be further improved.

[0106] Alternatively, as Figures 5 to 7 As shown, the shielding element 21 includes at least one shielding portion 213 , and the shielding portion 213 is in a comb-teeth shape.

[0107] For example, Figure 5 and Figure 6 As shown, the shielding element 21 includes two shielding parts 213 , and both shielding parts 213 are in a comb-teeth shape.

[0108] By configuring the shielding portion 213 of the shielding element 21 to be comb-shaped, the shielding element 21 can effectively improve the signal shielding effect of the shielding element 21 , reduce signal interference to the first element 11 , and further improve the signal quality of the packaging structure 10 .

[0109] Alternatively, as Figure 5 and Figure 6 As shown, the shielding element 21 includes multiple shielding portions 213, at least one of which is a first shielding portion 211, and at least one of which is a second shielding portion 212. The first shielding portion 211 includes multiple first metal strips 2111 arranged side by side, and the second shielding portion 212 includes multiple second metal strips 2121 arranged side by side. The first metal strips 2111 and the second metal strips 2121 are arranged alternately and at intervals.

[0110] For example, Figure 5 and Figure 6 As shown, the first shielding portion 211 is arranged in front of the second shielding portion 212, and a plurality of first metal strips 2111 and a plurality of second metal strips 2121 are arranged alternately and spaced apart in the left-right direction. Figure 5 and Figure 6 As shown, the left and right directions are as follows Figure 5 and Figure 6 shown.

[0111] By setting the shielding element 21 to the above structure, the signal shielding effect of the shielding element 21 can be effectively improved, the signal interference generated on the first element 11 can be reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0112] Alternatively, as Figure 5 and Figure 6 As shown, the width of the first metal strip 2111 and the second metal strip 2121 is 0.4 μm to 12.5 μm.

[0113] For example, Figure 5 As shown, the width of the first metal strip 2111 and the second metal strip 2121 are both K1, and K1 is 1.8 μm.

[0114] By setting the width of the first metal strip 2111 and the second metal strip 2121 to 0.4 μm to 12.5 μm, the processing and manufacturing of the shielding element 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which helps to reduce the cost of the packaging structure 10 .

[0115] Alternatively, as Figure 5 and Figure 6 As shown, the distance between the first metal strip 2111 and the second metal strip 2121 is 0.4 μm to 25 μm.

[0116] For example, Figure 5 As shown, the distance between the first metal strip 2111 and the second metal strip 2121 is K2, and K2 is 2.7 μm.

[0117] By setting the distance between the first metal strip 2111 and the second metal strip 2121 to 0.4 μm to 25 μm, the processing and manufacturing of the shielding element 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which helps to reduce the cost of the packaging structure 10 .

[0118] Alternatively, as Figure 8As shown, the shielding element 21 includes multiple shielding parts 213, which are evenly arranged along the circumference of a preset rectangular frame. The shielding part 213 includes multiple V-shaped metal strips 2131. The multiple metal strips 2131 of the same shielding part 213 are arranged in an inner and outer direction at intervals, and the length of the metal strips 2131 located on the outer side is shorter than the length of the metal strips 2131 located on the inner side. Figure 8 The dotted box in the figure is a preset rectangular box.

[0119] Here, inward can be understood as: a direction close to the center of the rectangular frame within the plane where the shielding element 21 is located; outward can be understood as: a direction away from the center of the rectangular frame within the plane where the shielding element 21 is located.

[0120] By setting the shielding element 21 to the above structure, the signal shielding effect of the shielding element 21 can be effectively improved, the signal interference generated on the first element 11 can be reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0121] Alternatively, as Figure 8 As shown, there are four shielding parts 213 , and the angle between the metal strips 2131 is 90°.

[0122] By setting the number of shielding parts 213 to four and the inner angle of the metal strip 2131 to 90°, the processing and manufacturing of the shielding element 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10, which helps to reduce the cost of the packaging structure 10.

[0123] Alternatively, as Figure 9 As shown, the shielding element 21 has a rectangular pulse signal waveform.

[0124] By configuring the shielding element 21 with the aforementioned structure, the signal shielding effect of the shielding element 21 can be effectively improved, reducing signal interference with the first element 11, further improving the signal quality of the first element 11, and thus improving the signal quality of the package structure 10. Furthermore, configuring the shielding element 21 to have a rectangular pulse signal waveform can facilitate the processing and manufacturing of the shielding element 21, thereby facilitating the processing and manufacturing of the package structure 10 and helping to reduce the cost of the package structure 10.

[0125] Alternatively, as Figure 6 As shown, the orthographic projection of the shielding element 21 in the direction toward the first chip 1 at least partially covers the first element 11 .

[0126] The orthographic projection of the shielding element 21 in the direction toward the first chip 1 at least partially covers the first element 11, which can be understood as: the orthographic projection of the shielding element 21 in the direction toward the first chip 1 covers the first element 11 as a whole; or, a part of the orthographic projection of the shielding element 21 in the direction toward the first chip 1 covers the first element 11, and the other part of the orthographic projection of the shielding element 21 in the direction toward the first chip 1 does not cover the first element 11.

[0127] By setting the orthographic projection of the shielding element 21 toward the first chip 1 to at least partially cover the first element 11 , the signal shielding effect of the shielding element 21 can be improved, further improving the signal quality of the first element 11 and the signal quality of the package structure 10 .

[0128] Alternatively, as Figure 6 As shown, the area of ​​the orthographic projection of the shielding element 21 in the direction toward the first chip 1 is larger than the area of ​​the region where the first element 11 is located. In other words, the orthographic projection of the shielding element 21 in the direction toward the first chip 1 not only covers the first element 11, but also covers the edge of the first element 11, thereby providing more coverage for the signal generated by the first element 11.

[0129] By making the area of ​​the orthographic projection of the shielding element 21 in the direction toward the first chip 1 larger than the area of ​​the region where the first element 11 is located, the signal shielding effect of the shielding element 21 can be further improved, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0130] Alternatively, as Figure 3 and Figure 11 As shown, an electrical connection area 102 and a clearance area 103 are provided between the first chip 1 and the second chip 2. The first electrical connector 13 and the second electrical connector 24 are provided in the electrical connection area 102. The orthographic projection of the clearance area 103 in the direction toward the first element 11 covers the first element 11.

[0131] It is understandable that the first electrical connector 13 and the second electrical connector 24 are both conductive members and will also interfere with the first element 11 .

[0132] By covering the first element 11 with the orthographic projection of the clearance area 103 in the direction toward the first element 11, the orthographic projections of the first electrical connector 13 and the second electrical connector 24 in the direction toward the first element 11 will not cover the first element 11, thereby reducing the interference of the first electrical connector 13 and the second electrical connector 24 on the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0133] Optionally, at an edge of the orthographic projection of the clearance area 103 in a direction toward the first elements 11 , a minimum distance between the first elements 11 is greater than or equal to 5 μm.

[0134] In the present disclosure, the minimum distance between the edge of the orthographic projection of the clearance area 103 in the direction toward the first element 11 and the first element 11 is greater than or equal to: the shortest straight line distance between the orthographic projections of the clearance area 103 and the first element 11 on the plane where the first element 11 is located. Figure 11 As shown, the shortest distance J between the first element 11 and the clearance area 103 is 5 μm.

[0135] Taking the first element 11 as an inductor as an example, the distance between the edge of the positive projection of the clearance area 103 on the first element 11 and the first element 11 will affect the inductance value (L value) and Q value of the inductor element. Figure 12 As shown, the horizontal axis is the minimum distance between the edge of the positive projection of the clearance area 103 on the first element 11 and the first element 11, and the vertical axis is the inductance value (L value) of the inductor element. Figure 13 As shown, the abscissa represents the shortest straight-line distance between the orthographic projections of clearance area 103 and first element 11 on the plane where first element 11 lies, and the ordinate represents the Q value of the inductor. It can be seen that the minimum distance between the edge of the orthographic projection of clearance area 103 on first element 11 and first element 11 is greater than 5 μm, effectively reducing the signal from second chip 2 and ensuring the performance of first element 11.

[0136] Alternatively, as Figure 10 and Figure 11 As shown, there are multiple first elements 11 and multiple clearance areas 103 , and the clearance area 103 is provided corresponding to at least one first element 11 .

[0137] For example, Figure 11 As shown, there are nine first elements 11 and five clearance areas 103. A portion of the clearance areas 103 is provided corresponding to two first elements 11, and a portion of the clearance areas 103 is provided corresponding to one first element 11.

[0138] By providing a plurality of first elements 11 and a plurality of clearance areas 103 , the plurality of first elements 11 can be integrated on the same first chip 1 , thereby improving the integration level of the packaging structure 10 .

[0139] Alternatively, as Figure 10 As shown, the orthographic projection of the first element 11 in the direction toward the second chip 2 is polygonal, and the clearance area 103 is polygonal.

[0140] For example, Figure 11As shown, when the orthographic projection of the first element 11 in the direction toward the second chip 2 is rectangular, the corresponding clearance area 103 is also rectangular. When the first element 11 is octagonal, the corresponding clearance area 103 is also octagonal.

[0141] It can be understood that the first electrical connector 13 and the second electrical connector 24 are not provided in the clearance area 103, resulting in that the first chip 1 and the second chip 2 cannot be connected through the first electrical connector 13 and the second electrical connector 24 in the clearance area 103, thereby reducing the connection area of ​​the first chip 1 and the second chip 2 and reducing the connection stability of the first chip 1 and the second chip 2.

[0142] By configuring both the orthographic projection of the first element 11 in the direction toward the second chip 2 and the clearance area 103 to be polygonal, the clearance area 103 can cover the corresponding first element 11 even when the area is relatively small. This improves the connection stability between the first chip 1 and the second chip 2, and enhances the reliability of the package structure 10.

[0143] Alternatively, as Figure 11 As shown, the area of ​​the orthographic projection of the clearance zone 103 in the direction toward the first element 11 is larger than the area of ​​the region where the first element 11 is located.

[0144] By setting the orthographic projection coverage of the clearance area 103 in the direction toward the first element 11 to be larger than the area where the first element 11 is located, the signal shielding effect of the shielding element 21 can be improved, further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0145] Alternatively, as Figure 10 As shown, the distance D between two adjacent clearance areas 103 is greater than or equal to 50 μm.

[0146] As described above, the clearance area 103 is not provided with the first electrical connector 13 and the second electrical connector 24 , which reduces the connection area of ​​the first chip 1 and the second chip 2 in the clearance area 103 and reduces the connection stability of the first chip 1 and the second chip 2 .

[0147] By setting the distance between two adjacent clearance areas 103 to be greater than or equal to 20 μm, preferably, the distance between two adjacent clearance areas 103 is 100 μm, it is possible to avoid excessive density between the clearance areas 103, which affects the connection stability between the first chip 1 and the second chip 2, and improve the reliability of the packaging structure 10.

[0148] Optionally, the area of ​​the clearance zone 103 is less than or equal to 0.08 mm 2 Preferably, the area of ​​the clearance area 103 is 0.0625mm 2When the clearance area 103 is smaller than the value described in the embodiment of the present disclosure, the connection stability between the first chip 1 and the second chip 2 can be better ensured.

[0149] As described above, the clearance area 103 is not provided with the first electrical connector 13 and the second electrical connector 24, resulting in that the first chip 1 and the second chip 2 cannot be connected by hybrid bonding in the clearance area 103, affecting the connection stability of the first chip 1 and the second chip 2.

[0150] By setting the area of ​​the clearance area 103 to be less than or equal to 0.08 mm 2 , the area of ​​the unconnected region between the first chip 1 and the second chip 2 can be reduced, the connection stability between the first chip 1 and the second chip 2 can be improved, and the reliability of the packaging structure 10 can be improved.

[0151] The packaging structure 10 of the embodiment of the present disclosure can reduce the signal interference caused by the first circuit 22 of the second chip 2 to the first element 11, and the interference of the first element 11 to the first circuit 22 by the first circuit 22 of the second chip 2, thereby improving the signal quality of the first element 11 and the signal quality of the packaging structure 10 by providing the first component 11 on the first chip 1, providing the shielding component 21 on the second chip 2, and providing the first circuit 22 of the second chip 2 on the side of the shielding component 21 away from the first component 11.

[0152] The packaging method of the embodiment of the present disclosure is used to form the packaging structure 10 described in any of the above embodiments.

[0153] The packaging method of the embodiment of the present disclosure includes:

[0154] A first component 11 is provided on the first chip 1;

[0155] A shielding element 21 is provided on the second chip 2;

[0156] The first chip 1 and the second chip 2 are stacked, wherein the shielding element 21 is arranged on a side of the second chip 2 close to the first chip 1. The second chip 2 is arranged opposite to the active surface of the first chip 1. The shielding element 21 is used to reduce the signal interference of the second chip 2 on the first element 11.

[0157] In some embodiments, a first component 11 is provided on the first chip 1, including:

[0158] At least one first wiring layer 101 is formed on the active surface of the first chip 1, and the first wiring layer 101 is arranged along the thickness direction of the package structure 10;

[0159] The first element 11 is formed by at least one first wiring layer 101 .

[0160] The chip stacking structure of the embodiment of the present disclosure includes a substrate and a package structure 10 disposed on the substrate. The package structure 10 is the package structure 10 of any embodiment.

[0161] In some embodiments, the packaging method includes:

[0162] At least one first wiring layer 101 is a first top layer 1011 . The first top layer 1011 is arranged closer to the second chip 2 than the other first wiring layers 101 in the thickness direction of the package structure 10 . The first component 11 is at least partially arranged in the first top layer 1011 .

[0163] In some embodiments, a shielding element 21 is provided on the second chip 2, including:

[0164] At least one second wiring layer 201 is formed on the active surface of the second chip 2 , and the second wiring layer 201 is arranged along the thickness direction of the package structure 10 ;

[0165] The shielding member 21 is formed by at least one second wiring layer 201 .

[0166] In some embodiments, at least one second wiring layer 201 is a second top layer 2011 . The second top layer 2011 is arranged closer to the first chip 1 than the other second wiring layers 201 in the thickness direction of the package structure 10 . The shielding element 21 is arranged in the second top layer 2011 .

[0167] The chip stacking structure of the embodiment of the present disclosure includes a substrate and a packaging structure 10 disposed on the substrate. The packaging structure is the packaging structure 10 described in any of the above embodiments.

[0168] The electronic device of the embodiment of the present disclosure includes a printed circuit board and a packaging structure 10, and the packaging structure 10 is the packaging structure 10 described in any of the above embodiments, and the printed circuit board is connected to the packaging structure 10. In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present disclosure.

[0169] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0170] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication between them; direct connections or indirect connections through an intermediate medium; and internal communication between two elements or interaction between two elements, unless otherwise expressly limited. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on specific circumstances.

[0171] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0172] In the present disclosure, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0173] Although the embodiments of the present disclosure have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present disclosure. Any changes, modifications, substitutions and variations of the above embodiments by those skilled in the art are all within the scope of protection of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: a first chip, wherein the first chip is provided with a first component; a second chip stacked with the first chip, wherein the second chip is arranged opposite to the active surface of the first chip; The second chip includes a shielding element, which is arranged on a side of the second chip close to the first chip. The shielding element is used to reduce the signal interference of the second chip on the first element. A clearance area is provided between the first chip and the second chip, and the orthographic projection of the clearance area in the direction toward the first element at least partially covers the first element. The first chip includes multiple first wiring layers, and the multiple first wiring layers are arranged along the thickness direction of the packaging structure. Among the multiple first wiring layers, the closer the first wiring layer is to the second chip, the thicker it is. At least one first wiring layer is a first top layer, and the first top layer is arranged closer to the second chip in the thickness direction of the packaging structure relative to the other first wiring layers. The first element is at least partially arranged on the first top layer.

2. The packaging structure according to claim 1, wherein: An orthographic projection of the shielding element in a direction toward the first chip at least partially covers the first element.

3. The packaging structure according to claim 2, wherein: The area of ​​the orthographic projection of the shielding element in the direction toward the first chip is larger than the area of ​​the region where the first element is located.

4. The packaging structure according to claim 1, wherein: The second chip includes a first circuit, and the first circuit is arranged on a side of the shielding element away from the first element in a thickness direction of the package structure.

5. The packaging structure according to claim 1, wherein: The second chip includes multiple second wiring layers, which are arranged along the thickness direction of the packaging structure. At least one second wiring layer is a second top layer, and the second top layer is arranged closer to the first chip than the other second wiring layers in the thickness direction of the packaging structure. The shielding element is arranged on the second top layer.

6. The packaging structure according to claim 1, wherein: The first chip is provided with a plurality of first electrical connectors, the second chip is provided with a plurality of second electrical connectors, and the second electrical connectors are connected to the first electrical connectors; An electrical connection area is provided between the first chip and the second chip, and the first electrical connection member and the second electrical connection member are provided in the electrical connection area.

7. The packaging structure according to claim 6, wherein: An area of ​​a positive projection of the clearance zone in a direction toward the first element is larger than an area where the first element is located.

8. The packaging structure according to claim 7, wherein: A minimum distance between an edge of a positive projection of the clearance area in a direction toward the first element and the first element is greater than or equal to 5 μm.

9. The packaging structure according to claim 6, wherein: The orthographic projection of the first element in a direction toward the second chip is a polygon, and the clearance area is a polygon.

10. The packaging structure according to claim 6, wherein: There are multiple first elements and multiple clearance areas, and each clearance area is provided corresponding to at least one first element.

11. The packaging structure according to claim 10, wherein: The distance between two adjacent clearance areas is greater than or equal to 20 μm.

12. The packaging structure according to claim 6, wherein: The area of ​​the clearance zone is less than or equal to 0.08 mm 2 .

13. The packaging structure according to any one of claims 1 to 12, characterized in that: The shielding element comprises a metal layer.

14. The packaging structure according to claim 13, wherein: The metal density of the area where the metal layer is located is 30% to 50%.

15. The packaging structure according to claim 13, wherein: The shielding element is grounded or connected to a power source.

16. The packaging structure according to claim 13, wherein: The shielding element comprises a first shielding portion and a second shielding portion, wherein the first shielding portion and the second shielding portion are in a comb-teeth shape; and / or, The shielding element comprises a first shielding portion and a second shielding portion, The first shielding portion includes a plurality of first metal strips arranged side by side, and the second shielding portion includes a plurality of second metal strips arranged side by side, wherein the first metal strips and the second metal strips are alternately arranged in sequence.

17. The packaging structure according to claim 13, wherein: The first chip includes a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

18. The packaging structure according to claim 13, wherein: The first element includes at least one of an inductor, a sensor, and a capacitor.

19. A packaging method, characterized in that: The packaging method is used to form the packaging structure according to any one of claims 1 to 18, and the packaging method includes: Disposing a first component on the first chip; providing a shielding element on the second chip; The first chip and the second chip are stacked, wherein the shielding element is arranged on a side of the second chip close to the first chip, and the second chip is arranged opposite to the active surface of the first chip, and the shielding element is used to reduce signal interference of the second chip on the first element.

20. The packaging method according to claim 19, wherein: The first component is provided on the first chip, comprising: forming at least one first wiring layer on the active surface of the first chip, wherein the first wiring layer is arranged along the thickness direction of the package structure; The first element is formed by at least one of the first wiring layers.

21. The packaging method according to claim 20, characterized in that: include: At least one of the first wiring layers is a first top layer, which is arranged closer to the second chip than the other first wiring layers in the thickness direction of the package structure, and the first component is at least partially arranged on the first top layer.

22. The packaging method according to claim 19, wherein: The shielding element is provided on the second chip, comprising: forming at least one second wiring layer on the active surface of the second chip, wherein the second wiring layer is arranged along the thickness direction of the package structure; The shielding element is formed by at least one second wiring layer.

23. The packaging method according to claim 22, characterized in that: At least one of the second wiring layers is a second top layer, which is arranged closer to the first chip than the other second wiring layers in the thickness direction of the package structure, and the shielding element is arranged on the second top layer.

24. A chip stacking structure, characterized in that: include: substrate; A packaging structure is provided on the substrate, wherein the packaging structure is the packaging structure according to any one of claims 1 to 18.

25. An electronic device, characterized in that: include: printed circuit boards; A packaging structure, wherein the packaging structure is the packaging structure according to any one of claims 1 to 18, and the printed circuit board is connected to the packaging structure.

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