A current integration modulus phase interpolator and method
By integrating a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module, the current integrating-mode phase interpolator solves the problem of traditional phase interpolators being susceptible to environmental interference, achieving high-precision and high-stability phase interpolation to meet engineering requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XI AN JIAOTONG UNIV
- Filing Date
- 2025-01-07
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional phase interpolators are susceptible to environmental interference, such as temperature changes and power supply voltage fluctuations, which can lead to insufficient phase linearity, affecting data transmission quality and system stability.
A current integrating modulus phase interpolator is adopted, including a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module. It integrates an anti-interference unit and a self-reset feedback unit. The clock signal is divided by the multi-mode frequency divider, the pulse generation module generates a phase interpolation pulse and a reset signal, the phase interpolator array generates an output signal, and the reset module performs efficient reset. The anti-interference unit isolates clock interference and the self-reset feedback unit improves the charge reset rate.
It improves the phase linearity and accuracy of the phase interpolator, enhances its resistance to environmental interference, ensures the synchronization, integrity and stability of data transmission, and meets the stringent requirements of practical engineering.
Smart Images
Figure CN119945388B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a current integral modulus phase interpolator and method. Background Technology
[0002] In the field of integrated circuits, phase interpolators are a key component, typically used to precisely adjust the delay of data or clock signals. This function is crucial for ensuring the synchronization and integrity of data transmission. Therefore, the performance of a phase interpolator, especially its phase linearity, directly determines the overall performance of the system.
[0003] Taking clock and data recovery systems as an example, phase interpolators play a crucial role in adjusting clock latency. To minimize jitter introduced during clock and data recovery, phase interpolators need to possess excellent accuracy and extremely high phase linearity. Only in this way can the stability and accuracy of data during transmission be ensured.
[0004] However, traditional phase interpolators face a series of challenges in practical applications. They are often susceptible to environmental factors such as temperature variations and power supply voltage fluctuations, which can degrade their performance, particularly leading to insufficient phase linearity. This deficiency directly affects the quality of data transmission and the stability of the system, thus failing to meet the stringent requirements of real-world engineering projects. Summary of the Invention
[0005] This invention provides a current integral modulus phase interpolator and method to solve the technical problem that existing phase interpolators are easily affected by environmental factors, resulting in insufficient linearity of the phase interpolator.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] In a first aspect, the present invention provides a current integral modulus phase interpolator, comprising: a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module;
[0008] The multi-mode frequency divider is used to divide the input clock signal.
[0009] The pulse generation module is used to receive the clock signal after frequency division by the multi-mode frequency divider, and generate a pulse signal for phase interpolation and a reset signal for reset based on the frequency division clock signal.
[0010] The phase interpolator array is used to receive the pulse signal from the pulse generation module and generate an output signal based on the pulse signal;
[0011] The reset module is used to receive the reset signal from the pulse generation module and the output signal from the phase interpolator array, and simultaneously reset the phase interpolator according to the reset signal and the output signal.
[0012] The reset module includes an anti-interference unit for isolating clock interference and a self-reset feedback unit for improving the charge reset rate.
[0013] A further improvement of the present invention is that the output terminal of the multi-mode frequency divider is connected to the first input terminal of the pulse generation module; the input terminal of the multi-mode frequency divider and the second input terminal of the pulse generation module are connected in parallel; the first output terminal of the pulse generation module is connected to the first input terminal of the reset module; the second output terminal of the pulse generation module is connected to the second input terminal of the reset module; the third output terminal of the pulse generation module is connected to the first input terminal of the phase interpolator array; the fourth output terminal of the pulse generation module is connected to the second input terminal of the phase interpolator array; and the output terminal of the phase interpolator array is connected to the third input terminal of the reset module.
[0014] A further improvement of the present invention is that the pulse generation module includes a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, a fourth flip-flop DFF4, a fifth flip-flop DFF5, and a sixth flip-flop DFF6;
[0015] The input terminals of the multimode divider, the clock input terminals of the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected in parallel.
[0016] A further improvement of the present invention is that the pulse generation module further includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor array C0, and a second capacitor array C1;
[0017] The output terminal of the multimode frequency divider is connected to the data input terminal of the first flip-flop DFF1 and the data input terminal of the third flip-flop DFF3, respectively.
[0018] The output of the first flip-flop DFF1 is connected to the data input of the second flip-flop DFF2 and the input of the first inverter INV1, respectively.
[0019] The output of the second flip-flop DFF2 is connected to the input of the second inverter INV2;
[0020] The output terminal of the third flip-flop DFF3 is connected to the data input terminal of the fourth flip-flop DFF4 and the data input terminal of the fifth flip-flop DFF5, respectively.
[0021] The output terminal of the fourth flip-flop DFF4 is connected to the data input terminal of the sixth flip-flop DFF6;
[0022] The output of the fifth flip-flop DFF5 is connected to the upper plate of the first capacitor array C0 and the input of the third inverter INV3, respectively.
[0023] The output of the sixth flip-flop DFF6 is connected to the upper plate of the second capacitor array C1 and the input of the fourth inverter INV4, respectively.
[0024] The output terminal of the first inverter INV1 is connected to the first input terminal of the reset module;
[0025] The output of the second inverter INV2 is connected to the second input of the reset module;
[0026] The output terminal of the third inverter INV3 is connected to the first input terminal of the phase interpolator array;
[0027] The output of the fourth inverter INV4 is connected to the second input of the phase interpolator array.
[0028] A further improvement of the present invention is that the pulse generation module further includes: the lower plate of the first capacitor array C0 is connected to GND; and the lower plate of the second capacitor array C1 is connected to GND.
[0029] A further improvement of the present invention is that the phase interpolator array includes multiple phase interpolator core modules connected in parallel;
[0030] The core module of the phase interpolator includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M4, a first PMOS transistor M3, a two-to-one switch SEL, a fifth inverter INV5, and a sixth inverter INV6.
[0031] The gate terminal and input terminal EN of the first NMOS transistor M1 are connected, the source terminal and input terminal Vbn of the first NMOS transistor M1 are connected, and the drain terminal of the first NMOS transistor M1 is connected to the gate terminal of the second NMOS transistor M2.
[0032] The source terminal of the second NMOS transistor M2 is connected to the drain terminal of the first PMOS transistor M3 and the drain terminal of the third NMOS transistor M4, respectively, and the drain terminal of the second NMOS transistor M2 is connected to the third input terminal of the reset module.
[0033] The source terminal of the first PMOS transistor M3 is connected to VDD, and the gate terminal of the first PMOS transistor M3 is connected to the gate terminal of the third NMOS transistor M4 and the output terminal of the two-to-one switch SEL.
[0034] The source terminal of the third NMOS transistor M4 is connected to GND;
[0035] The input terminal of the two-to-one switch SEL can be selectively connected to the output terminal of the fifth inverter INV5 or the output terminal of the sixth inverter INV6, respectively.
[0036] The input terminal of the fifth inverter INV5 is connected to the output terminal of the third inverter INV3; the input terminal of the sixth inverter INV6 is connected to the output terminal of the fourth inverter INV4.
[0037] A further improvement of the present invention is that the reset module includes a second PMOS transistor M5, a third PMOS transistor M7, a fourth NMOS transistor M6, a fifth NMOS transistor M8, a capacitor C2, and a seventh inverter INV7; wherein, the anti-interference unit is the fifth NMOS transistor M8; and the self-reset feedback unit is the fourth NMOS transistor M6.
[0038] The gate terminal of the second PMOS transistor M5 is connected to the first output terminal of the pulse generation module, the source terminal of the second PMOS transistor M5 is connected to VDD, and the drain terminal of the second PMOS transistor M5 is connected to the output terminal of the phase interpolator array.
[0039] The upper plate of capacitor C2 is connected to VDD, and the lower plate of capacitor C2 is connected to the output terminal of the phase interpolator array.
[0040] The gate terminal of the fourth NMOS transistor M6 is connected to the output terminal of the seventh inverter INV7, the drain terminal of the fourth NMOS transistor M6 is connected to VDD, and the source terminal of the fourth NMOS transistor M6 is connected to the output terminal of the phase interpolator array.
[0041] The gate terminal of the third PMOS transistor M7 is connected to the second output terminal of the pulse generation module, the source terminal of the third PMOS transistor M7 is connected to VDD, and the drain terminal of the third PMOS transistor M7 is connected to the source terminal of the fifth NMOS transistor M8 and the input terminal of the seventh inverter INV7, respectively.
[0042] The gate terminal of the fifth NMOS transistor M8 is connected to the VBN port, and the drain terminal of the fifth NMOS transistor M8 is connected to the output terminal of the phase interpolator array.
[0043] Secondly, the present invention provides a method for operating a current integral modulus phase interpolator, based on the above-mentioned current integral modulus phase interpolator, comprising:
[0044] A multi-mode frequency divider divides the input clock signal.
[0045] The pulse generation module generates a pulse signal for phase interpolation and a reset signal for resetting based on the received frequency-divided clock signal.
[0046] The phase interpolator array generates an output signal based on the received pulse signal;
[0047] The reset module resets the phase interpolator based on the received reset signal and the output signal;
[0048] Among them, the anti-interference unit is used to isolate clock interference, and the self-reset feedback unit is used to improve the charge reset rate.
[0049] A further improvement of the present invention is that,
[0050] The pulse generation module generates two clock signals with a phase difference of 2π and two reset signals based on the received frequency-divided clock signal.
[0051] A further improvement of the present invention is that,
[0052] The self-reset feedback unit starts working according to the working signal and uses a node charging method to cancel the discharge current of the phase interpolator array, thereby improving the charge reset rate.
[0053] Compared with the prior art, the present invention has the following beneficial effects:
[0054] This invention provides a current integrating modulus phase interpolator. This phase interpolator integrates a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module including an anti-interference unit and a self-reset feedback unit. This achieves effective frequency division of the input clock signal, accurate generation of the phase interpolation pulse signal, and efficient reset operation. Its anti-interference unit effectively isolates the phase interpolator's performance from environmental changes, such as temperature variations and power supply voltage fluctuations. Simultaneously, the self-reset feedback unit significantly improves the charge reset rate, thereby jointly enhancing the phase linearity and accuracy of the phase interpolator. This ensures the synchronization, integrity, and stability of data transmission, meeting the stringent requirements for data transmission quality and system stability in practical engineering. Compared to traditional phase interpolators, this phase interpolator improves the linearity of the current integrating modulus phase interpolator, enhances its resistance to environmental interference, and reduces power consumption, offering advantages for engineering applications.
[0055] Preferably, in this invention, the pulse generation module incorporates multiple triggers to achieve precise control and processing of the clock signal, thus ensuring the generation of high-quality phase interpolation pulse signals.
[0056] Preferably, in this invention, by introducing an inverter and a capacitor array, the functionality and flexibility of the pulse generation module are further enhanced, and the accuracy and stability of phase interpolation are improved.
[0057] Preferably, in this invention, the lower plate of the capacitor array is grounded to ensure the normal operation of the capacitors and the stable transmission of signals.
[0058] Preferably, in this invention, multiple parallel phase interpolator core modules are used to achieve parallel processing of the input signal, thereby improving the efficiency and accuracy of phase interpolation.
[0059] Preferably, in this invention, the anti-interference unit and the self-reset feedback unit in the reset module improve the system's resistance to clock interference and charge reset rate, respectively, thereby ensuring the stability and accuracy of the phase interpolator.
[0060] This invention provides a method for operating a current integrating modulus phase interpolator. Based on the aforementioned current integrating modulus phase interpolator, this method utilizes a multi-mode frequency divider to effectively divide the input clock signal; a pulse generation module generates precise phase interpolation pulses and a reset signal based on the divided signal; a phase interpolator array generates an output signal based on the pulse signal; and a reset module, combined with an anti-interference unit and a self-reset feedback unit, achieves efficient reset. This method not only enhances the phase interpolator's resistance to clock interference but also significantly improves the charge reset rate, thereby effectively improving the phase linearity and accuracy of the phase interpolator. It ensures the synchronization and integrity of data transmission, meeting the stringent requirements for high-performance phase interpolators in practical engineering, and performs particularly well in dealing with environmental interference such as temperature changes and power supply voltage fluctuations.
[0061] Preferably, in this invention, by generating two clock signals with a phase difference of 2π and two reset signals, a wealth of control signals are provided for the phase interpolator, thereby improving the flexibility and accuracy of phase interpolation.
[0062] Preferably, in this invention, the self-reset feedback unit cancels the discharge current of the phase interpolator array through node charging, which significantly improves the charge reset rate, thereby ensuring the fast response and stability of the phase interpolator. Attached Figure Description
[0063] Figure 1 This is a schematic diagram of the structure of a current integrating modulus phase interpolator provided in an embodiment of the present invention;
[0064] Figure 2This is a schematic diagram illustrating the working principle of the phase interpolator array provided in an embodiment of the present invention.
[0065] Figure 3 A circuit diagram of a reset module provided in an embodiment of the present invention;
[0066] Figure 4 A schematic diagram of the reset module provided in an embodiment of the present invention;
[0067] Figure 5 This is a schematic diagram of the linearity performance of the current integral modulus phase interpolator provided in an embodiment of the present invention; wherein, (a) is the differential nonlinearity (DNL) performance diagram of the phase interpolator; and (b) is the integral nonlinearity (INL) performance diagram of the phase interpolator. Detailed Implementation
[0068] To further understand the content of this invention, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not limiting of the invention.
[0069] As described in the background section, traditional phase interpolators currently face a series of challenges in practical applications. They are often susceptible to environmental factors such as temperature variations and power supply voltage fluctuations, which can lead to performance degradation, particularly insufficient phase linearity. This deficiency directly affects the quality of data transmission and system stability, thus failing to meet the stringent requirements of practical engineering.
[0070] To address the aforementioned issues, this embodiment provides a current integrating modulus phase interpolator. This embodiment employs two-phase clock phase interpolation, adds a calibration module, designs the phase interpolation unit using a transistor-resistor stacked structure, and adds an NMOS switch and a self-resetting feedback transistor to the phase interpolator reset circuit. Compared to traditional phase interpolators, this design improves the linearity of the current integrating modulus phase interpolator, enhances its resistance to environmental interference, reduces power consumption, and offers advantages for engineering applications.
[0071] This embodiment provides a current integrating modulus phase interpolator, including: a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module; the multi-mode frequency divider is used to divide the input clock signal; the pulse generation module is used to receive the clock signal after frequency division by the multi-mode frequency divider, and generate a pulse signal for phase interpolation and a reset signal for reset based on the divided clock signal; the phase interpolator array is used to receive the pulse signal from the pulse generation module, and generate an output signal based on the pulse signal; the reset module is used to receive the reset signal from the pulse generation module and the output signal from the phase interpolator array, and simultaneously reset the phase interpolator based on the reset signal and the output signal; wherein, the reset module includes an anti-interference unit for isolating clock interference and a self-reset feedback unit for improving the charge reset rate.
[0072] The output terminal of the multimode frequency divider is connected to the first input terminal of the pulse generation module; the input terminal of the multimode frequency divider and the second input terminal of the pulse generation module are connected in parallel; the first output terminal of the pulse generation module is connected to the first input terminal of the reset module; the second output terminal of the pulse generation module is connected to the second input terminal of the reset module; the third output terminal of the pulse generation module is connected to the first input terminal of the phase interpolator array; the fourth output terminal of the pulse generation module is connected to the second input terminal of the phase interpolator array; and the output terminal of the phase interpolator array is connected to the third input terminal of the reset module.
[0073] Therefore, this phase interpolator, by integrating a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module including an anti-interference unit and a self-reset feedback unit, achieves effective frequency division of the input clock signal, accurate generation of phase interpolation pulse signals, and efficient reset operation. Its anti-interference unit can effectively isolate the interference of environmental changes, such as temperature changes and power supply voltage fluctuations, on the performance of the phase interpolator. At the same time, the self-reset feedback unit significantly improves the charge reset rate, thereby jointly improving the phase linearity and accuracy of the phase interpolator, ensuring the synchronization, integrity, and stability of data transmission, and meeting the stringent requirements for data transmission quality and system stability in practical engineering.
[0074] The current integral modulus phase interpolator provided in this embodiment will be further explained below with reference to the accompanying drawings:
[0075] like Figure 1As shown, this application provides a current integrating modulus phase interpolator, including: a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module; the output terminal of the multi-mode frequency divider is connected to the first input terminal of the pulse generation module; the second input terminal of the multi-mode frequency divider is connected to the second input terminal of the pulse generation module; the first and second output terminals of the pulse generation module are connected to the first and second input terminals of the reset module; the third and fourth output terminals of the pulse generation module are connected to the first and second input terminals of the phase interpolator array; and the output terminal of the phase interpolator array is connected to the third input terminal of the reset module.
[0076] The pulse generation module includes: a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, a fourth flip-flop DFF4, a fifth flip-flop DFF5, a sixth flip-flop DFF6, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor array C0, and a second capacitor array C1. The output of the multi-mode divider is connected to the data inputs of the first flip-flop DFF1 and the third flip-flop DFF3, respectively. The inputs of the multi-mode divider, the clock inputs of the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected in parallel. The output of the first flip-flop DFF1 is connected to the data input of the second flip-flop DFF2 and the input of the first inverter INV1, respectively. The output of the second flip-flop DFF2 is connected to the input of the second inverter INV2. The output of the third flip-flop DFF3 is connected to the data inputs of the fourth flip-flop DFF4 and the fifth flip-flop DFF5, respectively. The output of the fourth flip-flop DFF4 is connected to the data input of the sixth flip-flop DFF6. The output of the fifth flip-flop DFF5 is connected to the upper plate of the first capacitor array C0 and the input of the third inverter INV3, respectively. The output of the sixth flip-flop DFF6 is connected to the upper plate of the second capacitor array C1 and the input of the fourth inverter INV4, respectively. The lower plate of the first capacitor array C0 is connected to GND. The lower plate of the second capacitor array C1 is connected to GND. The output of the first inverter INV1 is connected to the first input of the reset module. The output of the second inverter INV2 is connected to the second input of the reset module. The output of the third inverter INV3 is connected to the first input of the phase interpolator array. The output of the fourth inverter INV4 is connected to the second input of the phase interpolator array.
[0077] The phase interpolator array includes N parallel-connected phase interpolator core modules, where N≥2. Each phase interpolator core module includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M4, a first PMOS transistor M3, a 2-to-1 switch SEL, a fifth inverter INV5, and a sixth inverter INV6. The gate and input terminals EN of the first NMOS transistor M1 are connected, as are its source and input terminals Vbn. The drain of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2. The source of the second NMOS transistor M2 is connected to the drain of the first PMOS transistor M3 and the drain of the third NMOS transistor M4. The drain terminal of the first PMOS transistor M3 is connected to the third input terminal of the reset module; the source terminal of the first PMOS transistor M3 is connected to VDD, and the gate terminal of the first PMOS transistor M3 is connected to the gate terminal of the third NMOS transistor M4 and the output terminal of the two-to-one switch SEL; the source terminal of the third NMOS transistor M4 is connected to GND; the input terminal of the two-to-one switch SEL can be selectively connected to the output terminal of the fifth inverter INV5 or the output terminal of the sixth inverter INV6; the input terminal of the fifth inverter INV5 is connected to the output terminal of the third inverter INV3; the input terminal of the sixth inverter INV6 is connected to the output terminal of the fourth inverter INV4.
[0078] The reset module includes: a second PMOS transistor M5, a third PMOS transistor M7, a fourth NMOS transistor M6, a fifth NMOS transistor M8, a capacitor C2, and a seventh inverter INV7. The gate of the second PMOS transistor M5 is connected to the output of the first inverter INV1, the source of the second PMOS transistor M5 is connected to VDD, and the drain of the second PMOS transistor M5 is connected to the drain of the second NMOS transistor M2. The upper plate of capacitor C2 is connected to VDD, and the lower plate of capacitor C2 is connected to the drain of the second NMOS transistor M2. The gate of the fourth NMOS transistor M6 is connected to the output of the seventh inverter INV7, the drain of the fourth NMOS transistor M6 is connected to VDD, and the source of the fourth NMOS transistor M6 is connected to the drain of the second NMOS transistor M2. The gate of the third PMOS transistor M7 is connected to the output of the second INV2, the source of the third PMOS transistor M7 is connected to VDD, and the drain of the third PMOS transistor M7 is connected to the source of the fifth NMOS transistor M8 and the input of the seventh inverter INV7. The gate of the fifth NMOS transistor M8 is connected to the VBN port, and the drain of the fifth NMOS transistor M8 is connected to the drain of the second NMOS transistor M2.
[0079] The current integrating modulus phase interpolator provided in this embodiment has the following advantages: it uses only two-phase clocks for phase interpolation, which reduces power consumption and also eliminates the phase nonlinearity caused by the transmission delay mismatch of different phases at the output of the phase selector in traditional phase interpolators, thereby improving phase linearity.
[0080] A variable capacitor array was added after the pulse generation module to calibrate the phase difference between the two-phase clocks, which improved the accuracy of the phase difference between the two-phase clocks and enhanced the circuit's ability to resist environmental interference.
[0081] The phase interpolation unit is designed with a transistor + resistor stack structure, which reduces the impact of environmental changes on linearity;
[0082] The gate of the current source in the phase interpolation unit has no voltage bias requirement and is a single-edge phase interpolation. There is no need to consider the intensity mismatch between PMOS and NMOS in the phase interpolation unit, which reduces the phase nonlinearity caused by current mismatch.
[0083] An NMOS switch was added to the reset circuit to reduce the impact of the phase interpolator linearity on the inverter threshold voltage variation, thereby enhancing the circuit's ability to resist environmental interference.
[0084] Adding a self-reset feedback transistor to the reset circuit to construct a negative feedback loop reduces the discharge time of the phase interpolator output node, lowers power consumption, and at the same time weakens the slope instability of the phase interpolator output waveform, improves circuit robustness, and enhances the circuit's ability to resist environmental interference.
[0085] This embodiment provides a current integral modulus phase interpolator, the specific working principle of which is as follows:
[0086] A multi-mode frequency divider divides the input clock signal; a pulse generation module generates a pulse signal for phase interpolation and a reset signal for resetting based on the received divided clock signal; a phase interpolator array generates an output signal based on the received pulse signal; and a reset module resets the phase interpolator based on the received reset signal and the output signal. An anti-interference unit isolates clock interference, while a self-reset feedback unit improves the charge reset rate. In this embodiment, adding a fifth NMOS transistor M8 to the reset module isolates clock interference, and adding a feedback transistor M6 improves the charge reset rate. This current-integrating-mode phase interpolator exhibits better linearity compared to traditional phase interpolators.
[0087] The working principle of this embodiment will be further described with reference to the accompanying drawings:
[0088] like Figure 1 As shown, the multi-mode frequency divider generates a divided clock signal; the pulse generation module generates two clock signals CK0 and CK1 with a phase difference of 2π, i.e., pulse signals, based on the divided clock signal; there are also two reset signals vslop_set1 and vslop_set2.
[0089] The phase interpolator array generates an interpolated clock signal based on two pulse signals with a phase difference of 2π. The phase offset of the interpolated clock is related to the number of current paths on CK0 and CK1, while the total number of current paths on CK0 and CK1 remains constant. The working principle of the phase interpolator array is as follows: Figure 2 As shown, the current drop rate in region I is related to the number of current paths on CK0 and CK1, while the current drop rate in region II is constant.
[0090] Combination Figure 3 and Figure 4 As shown, the reset module includes: PMOS transistor M5, third PMOS transistor M7, fourth NMOS transistor M6, fifth NMOS transistor M8, capacitor C2, and seventh inverter INV7.
[0091] vslop_set1 is the reset signal for node Vx, and vslop_set2 is the reset signal for node Vy. After the Vx signal passes through the NMOS switch, the variable slope operating region disappears, and the constant slope operating region becomes larger. The inverter threshold voltage Vth range expands from V1 to V2 to V1 to VDD, improving the circuit's PVT resistance and eliminating the need for threshold voltage calibration. When the Vo node signal jumps from 0 to 1, the self-reset feedback transistor, i.e., the fourth NMOS transistor M6, starts working, charging node Vx to offset the discharge current of the phase interpolator array, preventing the Vx node voltage from continuing to decrease, reducing the discharge time of the phase interpolator output node, and lowering power consumption. The slope fluctuation of the Vx node signal is greatest at the extreme value of the swing. Now, the negative feedback loop prevents the Vx node signal from having a zero swing, thus improving the circuit's robustness and enhancing its PVT resistance.
[0092] like Figure 5 As shown, specifically as follows Figure 5 (a) and Figure 5 As shown in (b), the differential nonlinearity (DNL) of the current integrating modulus phase interpolator varies from -0.045 to 0.033 LSB, with a peak-to-peak value of 0.078 LSB. The integral nonlinearity (INL) varies from -0.1 to 0.45 LSB, with a peak-to-peak value of 0.55 LSB. This is sufficient to prove that the current integrating modulus phase interpolator provided in this embodiment has excellent phase linearity.
[0093] In summary, this invention provides a current integrating modulus phase interpolator and method. By employing a reset module, adding NMOS switches and self-reset feedback transistors, it ultimately achieves excellent accuracy and linearity under different manufacturing processes. Compared with existing phase interpolators, it has the following advantages:
[0094] First, functional integration and high efficiency: This current integrating modulus phase interpolator integrates a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module, forming a complete and efficient phase adjustment system; this integrated design not only simplifies the circuit structure, but also improves the accuracy and efficiency of phase interpolation.
[0095] Secondly, it has strong anti-interference capabilities: the reset module includes an anti-interference unit to isolate clock interference, which can effectively reduce the interference of external clock signals on the phase interpolation process and ensure the stability and accuracy of phase interpolation.
[0096] Third, improved charge reset rate: The self-reset feedback unit in the reset module can offset the discharge current of the phase interpolator array through node charging, thereby significantly improving the charge reset rate. This helps to accelerate the phase adjustment process and improve overall performance.
[0097] Fourth, flexibility and scalability: The multi-mode frequency divider can handle clock signals of different frequencies, enabling the phase interpolator to adapt to various application scenarios; at the same time, the phase interpolator array is composed of multiple parallel phase interpolator core modules, which provides good scalability and makes it easy to adjust the accuracy and range of phase interpolation according to actual needs.
[0098] Fifth, optimization of the working method: This invention also provides an efficient working method. The clock signal is divided by a multi-mode frequency divider, the pulse generation module generates the pulse signal and reset signal required for phase interpolation, the phase interpolator array generates the output signal based on the pulse signal, and finally, the reset module performs the reset operation. This method not only has a clear process but also fully utilizes the functions of each module to achieve efficient phase interpolation.
[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A current integrating modulus phase interpolator, characterized in that, include: Multimode frequency divider, pulse generation module, phase interpolator array and reset module; The multi-mode frequency divider is used to divide the input clock signal. The pulse generation module is used to receive the clock signal after frequency division by the multi-mode frequency divider, and generate a pulse signal for phase interpolation and a reset signal for reset based on the frequency division clock signal. The phase interpolator array is used to receive the pulse signal from the pulse generation module and generate an output signal based on the pulse signal; The reset module is used to receive the reset signal from the pulse generation module and the output signal from the phase interpolator array, and simultaneously reset the phase interpolator according to the reset signal and the output signal. The reset module includes an anti-interference unit for isolating clock interference and a self-reset feedback unit for improving the charge reset rate. The reset module includes a second PMOS transistor M5, a third PMOS transistor M7, a fourth NMOS transistor M6, a fifth NMOS transistor M8, a capacitor C2, and a seventh inverter INV7; wherein, the anti-interference unit is the fifth NMOS transistor M8; and the self-reset feedback unit is the fourth NMOS transistor M6. The gate terminal of the second PMOS transistor M5 is connected to the first output terminal of the pulse generation module, the source terminal of the second PMOS transistor M5 is connected to VDD, and the drain terminal of the second PMOS transistor M5 is connected to the output terminal of the phase interpolator array. The upper plate of capacitor C2 is connected to VDD, and the lower plate of capacitor C2 is connected to the output terminal of the phase interpolator array. The gate terminal of the fourth NMOS transistor M6 is connected to the output terminal of the seventh inverter INV7, the drain terminal of the fourth NMOS transistor M6 is connected to VDD, and the source terminal of the fourth NMOS transistor M6 is connected to the output terminal of the phase interpolator array. The gate terminal of the third PMOS transistor M7 is connected to the second output terminal of the pulse generation module, the source terminal of the third PMOS transistor M7 is connected to VDD, and the drain terminal of the third PMOS transistor M7 is connected to the source terminal of the fifth NMOS transistor M8 and the input terminal of the seventh inverter INV7, respectively. The gate terminal of the fifth NMOS transistor M8 is connected to the VBN port, and the drain terminal of the fifth NMOS transistor M8 is connected to the output terminal of the phase interpolator array.
2. The current integrating modulus phase interpolator according to claim 1, characterized in that, The output terminal of the multimode frequency divider is connected to the first input terminal of the pulse generation module; the input terminal of the multimode frequency divider and the second input terminal of the pulse generation module are connected in parallel; the first output terminal of the pulse generation module is connected to the first input terminal of the reset module; the second output terminal of the pulse generation module is connected to the second input terminal of the reset module; the third output terminal of the pulse generation module is connected to the first input terminal of the phase interpolator array; the fourth output terminal of the pulse generation module is connected to the second input terminal of the phase interpolator array; and the output terminal of the phase interpolator array is connected to the third input terminal of the reset module.
3. The current integrating modulus phase interpolator according to claim 2, characterized in that, The pulse generation module includes a first trigger DFF1, a second trigger DFF2, a third trigger DFF3, a fourth trigger DFF4, a fifth trigger DFF5, and a sixth trigger DFF6; The input terminals of the multimode divider, the clock input terminals of the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected in parallel.
4. The current integrating modulus phase interpolator according to claim 3, characterized in that, The pulse generation module further includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor array C0, and a second capacitor array C1; The output terminal of the multimode frequency divider is connected to the data input terminal of the first flip-flop DFF1 and the data input terminal of the third flip-flop DFF3, respectively. The output of the first flip-flop DFF1 is connected to the data input of the second flip-flop DFF2 and the input of the first inverter INV1, respectively. The output of the second flip-flop DFF2 is connected to the input of the second inverter INV2; The output terminal of the third flip-flop DFF3 is connected to the data input terminal of the fourth flip-flop DFF4 and the data input terminal of the fifth flip-flop DFF5, respectively. The output terminal of the fourth flip-flop DFF4 is connected to the data input terminal of the sixth flip-flop DFF6; The output of the fifth flip-flop DFF5 is connected to the upper plate of the first capacitor array C0 and the input of the third inverter INV3, respectively. The output of the sixth flip-flop DFF6 is connected to the upper plate of the second capacitor array C1 and the input of the fourth inverter INV4, respectively. The output terminal of the first inverter INV1 is connected to the first input terminal of the reset module; The output of the second inverter INV2 is connected to the second input of the reset module; The output terminal of the third inverter INV3 is connected to the first input terminal of the phase interpolator array; The output of the fourth inverter INV4 is connected to the second input of the phase interpolator array.
5. The current integrating modulus phase interpolator according to claim 4, characterized in that, The pulse generation module further includes: the lower plate of the first capacitor array C0 is connected to GND; and the lower plate of the second capacitor array C1 is connected to GND.
6. A current integrating modulus phase interpolator according to claim 4, characterized in that, The phase interpolator array includes multiple phase interpolator core modules connected in parallel; The core module of the phase interpolator includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M4, a first PMOS transistor M3, a two-to-one switch SEL, a fifth inverter INV5, and a sixth inverter INV6. The gate terminal and input terminal EN of the first NMOS transistor M1 are connected, the source terminal and input terminal Vbn of the first NMOS transistor M1 are connected, and the drain terminal of the first NMOS transistor M1 is connected to the gate terminal of the second NMOS transistor M2. The source terminal of the second NMOS transistor M2 is connected to the drain terminal of the first PMOS transistor M3 and the drain terminal of the third NMOS transistor M4, respectively, and the drain terminal of the second NMOS transistor M2 is connected to the third input terminal of the reset module. The source terminal of the first PMOS transistor M3 is connected to VDD, and the gate terminal of the first PMOS transistor M3 is connected to the gate terminal of the third NMOS transistor M4 and the output terminal of the two-to-one switch SEL. The source terminal of the third NMOS transistor M4 is connected to GND; The input terminal of the two-to-one switch SEL can be selectively connected to the output terminal of the fifth inverter INV5 or the output terminal of the sixth inverter INV6, respectively. The input terminal of the fifth inverter INV5 is connected to the output terminal of the third inverter INV3; the input terminal of the sixth inverter INV6 is connected to the output terminal of the fourth inverter INV4.
7. A method for operating a current integrating modulus phase interpolator, based on the current integrating modulus phase interpolator according to any one of claims 1-6, characterized in that, include: A multi-mode frequency divider divides the input clock signal. The pulse generation module generates a pulse signal for phase interpolation and a reset signal for resetting based on the received frequency-divided clock signal. The phase interpolator array generates an output signal based on the received pulse signal; The reset module resets the phase interpolator based on the received reset signal and the output signal; Among them, the anti-interference unit is used to isolate clock interference, and the self-reset feedback unit is used to improve the charge reset rate.
8. The operating method of the current integrating modulus phase interpolator according to claim 7, characterized in that, The pulse generation module generates two clock signals with a phase difference of 2π and two reset signals based on the received frequency-divided clock signal.
9. The operating method of the current integrating modulus phase interpolator according to claim 7, characterized in that, The self-reset feedback unit starts working according to the working signal and uses a node charging method to cancel the discharge current of the phase interpolator array, thereby improving the charge reset rate.