Multi-protocol output driving circuit

Abstract

The invention provides a multi-protocol output driving circuit which comprises a logic control module, a bias generation module and an output driving module, and the output driving module comprises a plurality of output driving circuits of different transmission protocol types. According to the invention, the logic control module outputs the enable control signal to realize switching of the output driving circuits of different transmission protocols, and when the output driving circuit of the differential signal transmission protocol type is selected to enter a working state, the bias generation module outputs the corresponding bias voltage to the output driving circuit of the differential signal transmission protocol type. Therefore, the output swing of the output driving circuit is controlled, so that when the output driving circuit is switched to output driving circuits of different differential signal transmission protocol types, the performances such as driving capability, output swing and power consumption can be compromised, and the compatibility and reliability of the multi-protocol output driving circuit are improved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a multi-protocol output drive circuit. Background Art

[0002] IO (INPUT, OUTPUT) is a key module for direct input and output signals of the chip, and generally plays the role of level matching, impedance transformation, power amplification and protection. IO can be divided into input drive and output drive circuits. Among them, the output drive circuit generally outputs the signal of the corresponding level according to the standards specified by the communication protocol. The communication protocol specifies electrical characteristics such as signal swing and common mode level range. Common output signal protocols can be divided into single-ended signal standards such as CMOS (Complementary Metal Oxide Semiconductor), using PMOS and NMOS to implement logic functions, differential signal standards such as CML (Current Mode Logic), LVPECL (Low Voltage Positive Emitter Coupled Logic), LVDS (Low Voltage Differential Signaling), etc.

[0003] With the development of modern wireless communication technology, higher requirements are placed on signal transmission and interaction. For a communication system, it is necessary to be compatible with multi-channel and multi-level protocol outputs, such as CMOS, CML, LVPECL, LVDS, etc. Each output level protocol has different driving capabilities, signal swings, and common-mode voltage ranges. If you want to achieve compatibility with multiple output level protocols, you need to implement the corresponding drive circuit. In addition, for the output drive circuit, especially for multi-channel output chips, improving phase noise performance and output swing means a significant increase in power consumption. Therefore, it is necessary to design an output drive circuit that meets multiple level protocols and performance and power consumption compromise configurations to expand the working scenarios and application scope of integrated circuits. Summary of the invention

[0004] The main purpose of the present application is to provide a multi-protocol output drive circuit, which can at least solve the problem of poor compatibility of the multi-protocol output drive circuit in the related art.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a multi-protocol output drive circuit, including: a logic control module, a bias generation module and an output drive module, the output drive module including multiple output drive circuits of different transmission protocol types; wherein the transmission protocol type includes a differential signal transmission protocol and a single-ended signal transmission protocol; the logic control module is configured to: output an enable control signal to a target output drive circuit, and when the transmission protocol type of the target output drive circuit is the differential signal transmission protocol, output a selection control signal to the bias generation module; wherein the enable control signal is used to control the target output drive circuit to enter a working state; the bias generation module is configured to: according to the selection control signal, select and output a corresponding bias voltage to the target output drive circuit; wherein the bias voltage is used to control the output swing of the target output drive circuit.

[0006] Furthermore, the output driving module includes a CML mode driving circuit, an LVPECL mode driving circuit, an LVDS mode driving circuit and a CMOS mode driving circuit connected in parallel, and the bias generating module includes an LVDS bias generating circuit, an LVPECL bias generating circuit and a CML bias generating circuit; the bias generating module is configured to: according to the selection control signal, select the bias voltage generated by the corresponding bias generating circuit and transmit it to the corresponding output driving circuit.

[0007] From the above description, it can be seen that the present application switches the output driving circuits of different transmission protocols through the output enable control signal of the logic control module. When the output driving circuit of the differential signal transmission protocol type is selected to enter the working state, in order to meet the driving capability, signal swing and other performance requirements of the output driving circuit, while taking into account the power consumption requirements, a bias generation module is also provided to output the corresponding bias voltage to the output driving circuit of the differential signal transmission protocol type to control the output swing of this type of output driving circuit, so that when switching to the output driving circuit of different differential signal transmission protocol types, the driving capability, output swing and power consumption can be configured in a compromise, thereby improving the compatibility and reliability of the multi-protocol output driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 is a structural schematic diagram of a multi-protocol output drive circuit according to an embodiment of the present application;

[0010] Figure 2 is a circuit schematic diagram of a bias generation module according to an embodiment of the present application;

[0011] Figure 3 is a circuit schematic diagram of a CML mode driving circuit according to an embodiment of the present application;

[0012] Figure 4 is a circuit schematic diagram of an LVPECL mode driving circuit according to an embodiment of the present application;

[0013] Figure 5 is a circuit schematic diagram of an LVDS mode driving circuit according to an embodiment of the present application;

[0014] Figure 6 It is a circuit schematic diagram of a CMOS mode driving circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0015] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0016] In the related art, there is a problem of poor compatibility of multi-protocol output driving circuits. Therefore, an embodiment of the present application provides a multi-protocol output driving circuit.

[0017] like Figure 1 The structure diagram of a multi-protocol output driving circuit provided by the present embodiment is shown, and the multi-protocol output driving circuit includes: a logic control module, a bias generation module and an output driving module, and the output driving module includes a plurality of output driving circuits of different transmission protocol types; wherein the transmission protocol type includes a differential signal transmission protocol and a single-ended signal transmission protocol; the logic control module is configured to: output an enable control signal to a target output driving circuit according to a transmission protocol type selection instruction, and when the transmission protocol type of the target output driving circuit is a differential signal transmission protocol, output a selection control signal to the bias generation module; wherein the enable control signal is used to control the target output driving circuit to enter a working state; the bias generation module is configured to: select and output a corresponding bias voltage to the target output driving circuit according to the selection control signal; wherein the bias voltage is used to control the output swing of the target output driving circuit.

[0018] Specifically, the multi-protocol output driving circuit in the present embodiment switches the output driving circuits of different transmission protocols by outputting an enable control signal through a logic control module. When the output driving circuit of the differential signal transmission protocol type is selected to enter the working state, in order to meet the performance requirements of the output driving circuit, such as the driving capability and signal swing, while taking into account the power consumption requirements, a bias generation module is also provided to output a corresponding bias voltage to the output driving circuit of the differential signal transmission protocol type to control the output swing of this type of output driving circuit, so that when switching to the output driving circuit of the different differential signal transmission protocol type, the driving capability, output swing and power consumption can be configured in a compromise, thereby ensuring the driving performance of the output driving circuit when switching to different output driving circuits, thereby improving the compatibility and reliability of the multi-protocol output driving circuit.

[0019] Furthermore, if Figure 2 FIG. 1 is a circuit diagram of a bias generation module provided in this embodiment, see Figure 1 and Figure 2 The output driving module includes a CML mode driving circuit, an LVPECL mode driving circuit, an LVDS mode driving circuit and a CMOS mode driving circuit connected in parallel, and the bias generating module includes an LVDS bias generating circuit, an LVPECL bias generating circuit and a CML bias generating circuit; the bias generating module is configured to: according to a selection control signal, select the bias voltage generated by the corresponding bias generating circuit and transmit it to the corresponding output driving circuit.

[0020] Specifically, taking the common transmission protocols CMOS, CML, LVPECL, and LVDS as examples, the multi-protocol output driving circuit in this embodiment includes a CML mode driving circuit, an LVPECL mode driving circuit, an LVDS mode driving circuit, and a CMOS mode driving circuit connected in parallel, wherein CML is a high-speed differential signal transmission protocol, LVPECL is a low-voltage differential signal transmission protocol, and LVDS is a low-voltage differential signal transmission protocol. Therefore, the bias generation module in this embodiment includes an LVDS bias generation circuit, an LVPECL bias generation circuit, and a CML bias generation circuit. When the output driving circuit of the differential transmission protocol type is selected to enter the working state, the bias generation module selects the bias voltage generated by the corresponding bias generation circuit and transmits it to the target output driving circuit to adjust the output swing of the target output driving circuit, so that the performance indicators such as the driving capability, phase noise, and power consumption of the output driving circuit are compromised.

[0021] For further information, see Figure 2The LVDS bias generating circuit includes a seventh switch tube M30, an eighth switch tube M33, a ninth switch tube M35, a tenth switch tube M32, an eleventh switch tube M31, a twelfth switch tube M34, a first resistor R9 and a second control switch S9; the sources of the seventh switch tube M30, the eighth switch tube M33 and the ninth switch tube M35 are all electrically connected to the power supply, the drain of the seventh switch tube M30 is respectively electrically connected to the gate of the seventh switch tube M30, the gate of the eighth switch tube M33, the first resistor R9, the gate of the ninth switch tube M35 and the LVDS mode driving circuit, and the eighth switch tube M32 is electrically connected to the gate of the eighth switch tube M33, the first resistor R9, the gate of the ninth switch tube M35 and the LVDS mode driving circuit. The drain of the first switch tube M33 is electrically connected to the drain of the tenth switch tube M32, the gate of the eleventh switch tube M31 and the LVDS mode driving circuit respectively, the source of the tenth switch tube M32 is electrically connected to the drain of the eleventh switch tube M31, the gate of the twelfth switch tube M34 is electrically connected to the gate of the tenth switch tube M32, the drain of the twelfth switch tube M34 and the drain of the ninth switch tube M35 respectively, the sources of the twelfth switch tube M34 and the eleventh switch tube M31 are grounded, and the second control switch S9 is electrically connected to the first resistor R9, the logic control module and the source of the eleventh switch tube M31 respectively.

[0022] Further, see Figure 2 The CML bias generation circuit includes an LVPECL bias generation circuit, a thirteenth switch tube M47, a fourteenth switch tube M46 and a third control switch S16; the source of the thirteenth switch tube M47 and the first end of the third control switch S16 are electrically connected to the power supply, the gate of the thirteenth switch tube M47 is electrically connected to the LVPECL bias generation circuit and the second end of the third control switch S16 respectively, the drain of the thirteenth switch tube M47 is electrically connected to the drain and gate of the fourteenth switch tube M46 and the CML mode driving circuit respectively, the source of the fourteenth switch tube M46 is grounded, and the third end of the third control switch S16 is electrically connected to the logic control module.

[0023] The LVPECL bias generating circuit includes a fifteenth switch tube M48, a sixteenth switch tube M40, a seventeenth switch tube M41, an eighteenth switch tube M44, a nineteenth switch tube M43, a second resistor R10, a fourth control switch S10, a fifth control switch S12, a sixth control switch S13, a seventh control switch S14 and an eighth control switch S15; the second resistor R10 is electrically connected to the drain and gate of the fourth control switch S10, the fifteenth switch tube M48, and the gate of the sixteenth switch tube M40, respectively; the sources of the fifteenth switch tube M48 and the sixteenth switch tube M40 are both grounded; the drain of the sixteenth switch tube M40 is electrically connected to the fifth control switch S12; the gate of the seventeenth switch tube M41 is electrically connected to the gate of the seventeenth switch tube M41, respectively. The drain of the eighteenth switch tube M44 is electrically connected to the drain of the LVPECL mode driving circuit and the gate and drain of the nineteenth switch tube M43, respectively. The source of the eighteenth switch tube M44 is electrically connected to the gate of the thirteenth switch tube M47, and all the control switches are also electrically connected to the logic control module.

[0024] Specifically, in this embodiment, the bias generation module mainly provides a bias voltage for the output drive circuit. The bias generation module generates bias voltages VBP, VB1, VB2, VBN1, and VBN2 through diode-connected MOS devices M30 and M48, resistors R9 and R10, and control switches S9 and S10, and can mirror the current to the output drive circuit. By changing the resistance values ​​of resistors R9 and R10, the bias voltage can be changed. Corresponding to different transmission protocol modes, the control switch of the bias generation module can be controlled by the logic control module to turn on or off the bias voltage. Among them, when the control switches S10, S12, S14, and S15 are closed and the switches S9, S13, and S16 are opened, only the bias voltages VBN1 and VB2 are output normally, and the bias generation module is in CML mode; when the control switches S10, S12, S13, and S16 are closed and the switches S9, S14, and S15 are opened, only the bias voltages VBN1 and VB1 are output normally, and the bias generation module is in LVPECL mode; when the switches S9, S14, and S16 are closed and the switches S10, S12, S13, and S15 are opened, only the bias voltages VBP and VBN2 are output normally, and the bias generation module is in LVDS mode.

[0025] like Figure 3FIG. 1 is a schematic diagram of a CML mode driving circuit provided in this embodiment. Figure 3 The CML mode driving circuit includes a CML adjustable resistor array, an adjustable current array, a first differential driving unit, a first isolation tube unit and a CML bias control unit ( Figure 3 The first differential driving unit is electrically connected to the adjustable current array and the first isolation tube unit respectively, the CML adjustable resistance array is electrically connected to the logic control module, the first isolation tube unit and the power supply respectively, the adjustable current array is also electrically connected to the CML bias control unit and the logic control module, and the first isolation tube unit is also electrically connected to the CML bias control unit; the CML bias control unit is configured to: when receiving an enable control signal, transmit the bias voltage to the first isolation tube unit and the adjustable current array.

[0026] For further information, see Figure 3 The first differential driving unit includes a first driving tube M2 and a second driving tube M3, the first isolation tube unit includes a first switch tube M6 and a second switch tube M7, and the CML adjustable resistor array includes a first adjustable resistor array and a second adjustable resistor array; the control ends of the first driving tube M2 and the second driving tube M3 are both used to be electrically connected to an external clock control signal generator, the input ends of the first driving tube M2 and the second driving tube M3 are both electrically connected to the adjustable current array, the output end of the first driving tube M2 is electrically connected to the input end of the first switch tube M6, the output end of the second driving tube M3 is electrically connected to the input end of the second switch tube M7, the control ends of the first switch tube M6 and the second switch tube M7 are both electrically connected to the CML bias control unit, the output end of the first switch tube M6 is electrically connected to the first adjustable resistor array and is used to be electrically connected to an external load, the output end of the second switch tube M7 is electrically connected to the second adjustable resistor array and is used to be electrically connected to an external load, and the first adjustable resistor array and the second adjustable resistor array are also electrically connected to a logic control module.

[0027] Among them, the bias voltage is used to control the first isolation tube unit to enter the on state, and to control the total current of the adjustable current array in combination with the first digital control signal transmitted by the logic control module; the CML adjustable resistor array is configured to: adjust the number of resistors connected to the CML mode drive circuit according to the second digital control signal transmitted by the logic control module.

[0028] In this embodiment, when the logic control module outputs an enable control signal to the CML mode driving circuit, for example, when the enable terminal ENH_CML of the CML mode driving circuit is pulled high, the multi-protocol output driving circuit selects the CML mode, and the other modes are turned off. In the CML mode driving circuit, the clock control signals CLKINN and CLKINP are input through the driving tubes M2 and M3, and are connected to the CML adjustable resistor array through the isolation tubes M6 and M7. The CML adjustable resistor array serves as the internal load of the CML mode driving circuit, and is finally connected to the output ports CLKOUT and CLKOUTB through the isolation tubes M6 and M7 to connect to the external load (for example, a 100Ω resistor). Among them, when the multi-protocol output driving circuit selects the CML mode, the bias generation module selects to output the bias voltages VB2 and VBN1 generated by the CML bias generation circuit, that is, at this time VB2 and VBN1 are high level. At the same time, since the CML bias control unit receives a high level enable control signal, the high level VB2 and VBN1 are transmitted to the isolation tubes M6 and M7 and the adjustable current array, so that the isolation tubes M6 and M7 are in the on state, and the CML internal resistance array and current array are turned on.

[0029] In addition, for the standard CMOS process, since the speed performance of the high-voltage domain MOS device is limited, and the low-voltage domain MOS device has a higher cut-off frequency, in order to achieve a higher operating speed, the input differential pair tubes M2 and M3 of the CML output drive circuit are set as low-voltage domain drive tubes. However, there is a problem of device overvoltage in its application, that is, its maximum withstand voltage is less than the power supply voltage VDD. By superimposing a layer of isolation tubes such as MOS tubes M6 and M7 and applying a bias voltage VB2 to the gate of the isolation tube, the drain voltage of the drive tubes M2 and M3 can be reduced to VB2-V GS6 VB2-V GS7 , to avoid the low-voltage domain driver tube being in an overvoltage state for a long time when the circuit is working, causing circuit failure.

[0030] In addition, when the multi-protocol output drive circuit selects the CML mode, the digital control signals Rload_CML and PROG_I_CMLLVP can be output through the logic control module to respectively configure the resistor array and the current array, wherein the digital control signal Rload_CML is used to select different numbers of resistors to adjust the internal load resistance of the CML mode drive circuit, and the bias voltage VBN1 generated by the CML bias generation circuit is used to provide bias current for the CML mode drive circuit, and the number of current branches connected to the circuit is selected through the logic control module, thereby adjusting the tail current of the drive circuit. The current array and the resistor array determine the VOH and VOL of the CML mode output. Taking CLKINN as a high level and CLKINP as a low level as an example, at this time, almost all the current flows through the driver tube M2. If the total resistance of the internal adjustable resistor array is R L , the external connection resistance is 100Ω, the driving current provided by the adjustable current array is I0, then the voltage at CLKOUT is VOL, the voltage at CLKOUTB is VOH, and the calculation formula is as follows:

[0031] like Figure 4 FIG. 1 is a schematic diagram of a LVPECL mode driving circuit provided in this embodiment. Figure 3 and Figure 4 The LVPECL mode driving circuit includes a CML mode driving circuit, a second isolation tube unit, an LVPECL adjustable resistor array, a source follower and an LVPECL bias control unit (not shown in the figure); the second isolation tube unit is electrically connected to the first differential driving unit, the LVPECL adjustable resistor array and the input end of the source follower respectively, the output end of the source follower is used to be electrically connected to an external load, the LVPECL adjustable resistor array is also electrically connected to the logic control module, and the LVPECL bias control unit is electrically connected to the logic control module, the bias generation module, the second isolation tube unit and the adjustable current array respectively.

[0032] For further information, see Figure 3 and Figure 4The second isolation transistor unit includes a third switch transistor M4 and a fourth switch transistor M5, the LVPECL adjustable resistor array includes a third adjustable resistor array and a fourth adjustable resistor array, and the source follower includes a first MOS transistor M8 and a second MOS transistor M9; the input ends of the third switch transistor M4 and the fourth switch transistor M5 are both electrically connected to the first differential driving unit, the control ends of the third switch transistor M4 and the fourth switch transistor M5 are both electrically connected to the LVPECL bias control unit, the output end of the third switch transistor M4 is respectively connected to the gate of the third adjustable resistor array and the first MOS transistor M8, the output end of the fourth switch transistor M5 is respectively electrically connected to the gate of the fourth adjustable resistor array and the second MOS transistor M9, the third adjustable resistor array and the fourth adjustable resistor array are also electrically connected to the logic control module, the source electrodes of the first MOS transistor M8 and the second MOS transistor M9 are both used to be electrically connected to an external load, and the drain electrodes of the first MOS transistor M8 and the second MOS transistor M9 are both electrically connected to a power supply.

[0033] Among them, the LVPECL bias control unit is also configured to: when receiving an enable control signal, transmit the bias voltage to the second isolation tube unit and the adjustable current array; wherein the bias voltage is used to control the second isolation tube unit to enter the on state, and to control the total current of the adjustable current array in combination with the third digital control signal transmitted by the logic control module; the LVPECL adjustable resistor array is configured to: adjust the number of resistors connected to the LVPECL mode drive circuit according to the fourth digital control signal transmitted by the logic control module.

[0034] In this embodiment, the LVPECL mode driving circuit is divided into two stages, the first stage structure is similar to the common source structure of CML, and the second stage is a source follower structure. When the logic control module outputs an enable control signal to the LVPECL mode driving circuit, for example, when the enable terminal ENH_LVP of the LVPECL mode driving circuit is pulled high, the multi-protocol output driving circuit selects the LVPECL mode, and the other modes are turned off. In the LVPECL mode driving circuit, the clock control signals CLKINN and CLKINP are input through the driving tubes M2 and M3, and are connected to the LVPECL adjustable resistor array through the isolation tubes M4 and M5. The LVPECL adjustable resistor array serves as the internal load of the LVPECL mode driving circuit, and is connected to the gate of the MOS tubes M8 and M9 through the drain of the isolation tubes M4 and M5. The source of the MOS tubes M8 and M9 serves as the output of the source follower, and is connected to the output ports CLKOUT and CLKOUTB to connect to the external load, and the external load can be set according to actual needs. Among them, when the multi-protocol output driving circuit selects the LVPECL mode, the bias generation module selects to output the bias voltages VB1 and VBN1 generated by the LVPECL bias generation circuit, that is, at this time, VB1 and VBN1 are at a high level. At the same time, because the LVPECL bias control unit receives a high-level enable control signal, the high-level VB1 and VBN1 are transmitted to the isolation tubes M4 and M5 and the adjustable current array, so that the isolation tubes M4 and M5 are in a conductive state, and the LVPECL internal resistance array and current array are turned on. The LVPECL mode and the CML mode in this embodiment are multiplexed structures, that is, the multiplexed circuit can realize the LVPECL mode and the CML mode. Since the LVPECL mode and the CML mode share the low-voltage domain input differential pair tubes M2 and M3, in order to ensure the safety and reliability of the circuit components, a layer of withstand voltage isolation tubes M4 and M5 is added to the drain of the driving tubes M2 and M3, and the bias voltage VB1 is generated by the corresponding bias generation circuit, so that the drain voltages of the driving tubes M2 and M3 are reduced to VB1-V GS4 ,VB1-V GS5 , to include the low-voltage domain driver tube.

[0035] In addition, when the multi-protocol output drive circuit selects the LVPECL mode, the digital control signals Rload_LVP and PROG_I_CMLLVP can be output through the logic control module to respectively configure the resistor array and the current array, wherein the digital control signal Rload_CML is used to select different numbers of resistors to adjust the internal load resistance of the LVPECL mode drive circuit, and the bias voltage VBN1 generated by the LVPECL bias generation circuit is used to provide bias current for the LVPECL mode drive circuit, and the number of current branches connected to the circuit is selected through the logic control module, thereby adjusting the tail current of the drive circuit. Taking CLKINN as a high level and CLKINP as a low level as an example, at this time, the driving current of the current array almost all flows through the driver tube M2. If the total resistance of the internal adjustable resistor array is R L , the driving current provided by the adjustable current array is I0, then the gate voltage of MOS tube M8 is VDD-I0*R L , the gate voltage of MOS tube M9 is close to the power supply voltage. The second stage of the LVPECL mode driver circuit is a source follower structure, so the voltage at CLKOUT is VDD-I0*R L -V GS8 , the voltage at CLKOUTB is VDD-V GS9 .

[0036] like Figure 5 FIG. 1 is a schematic diagram of a LVDS mode driving circuit provided in this embodiment. Figure 5 The LVDS mode driving circuit includes a first LVDS adjustable current array, a second LVDS adjustable current array, a second differential driving unit, a first voltage conversion unit and a common mode feedback unit; the second differential driving unit is electrically connected to the first voltage conversion unit, the first LVDS adjustable current array, the second LVDS adjustable current array and the common mode feedback unit respectively, the first LVDS adjustable current array is also electrically connected to the logic control module, the bias generation module and the common mode feedback unit respectively, the second LVDS adjustable current array is also electrically connected to the logic control module and the bias generation module respectively, the first voltage conversion unit is electrically connected to the logic control module and is used to be electrically connected to an external clock control signal generator.

[0037] For further information, see Figure 5The common-mode feedback circuit includes a reference voltage supply circuit, a common-mode load, a comparator, a first control switch S4, a fifth switch tube M20, and a sixth switch tube M21; the common-mode load is electrically connected to the output end of the second differential drive unit and the first input end of the comparator, respectively; the reference voltage supply circuit is electrically connected to the second input end of the comparator, the first control switch S4 is electrically connected to the output end of the comparator, the gates of the fifth switch tube M20 and the sixth switch tube M21, and the logic control module, respectively; the source electrodes of the fifth switch tube M20 and the sixth switch tube M21 are electrically connected to the power supply, and the drain electrodes of the fifth switch tube M20 and the sixth switch tube M21 are electrically connected to the first LVDS adjustable current array. Among them, the reference voltage supply circuit can be a voltage divider circuit composed of resistors R2 and R1.

[0038] In this embodiment, when the logic control module outputs an enable control signal to the LVDS mode driving circuit, for example, when the enable terminal ENH_LVDS of the LVDS mode driving circuit is pulled high, the multi-protocol output driving circuit selects the LVDS mode, and the pull-up and pull-down current arrays of the LVDS mode driving circuit are turned on. In the LVDS mode driving circuit, the clock control signals CLKINN and CLKINP are converted into two sets of differential clock signals CLKNL / CLKNR and CLKPL / CLKPR through voltage conversion, and the four MOS tubes M14, M15, M16, and M17 in the differential driving unit are respectively controlled, so that the corresponding switch tubes are turned on to form a path from the power supply to the ground. The drain of the MOS tube in the differential driving unit is respectively connected to the output ports CLKOUT and CLKOUTB. When the output port is connected to an external resistor, a voltage drop is generated to form a differential level. Considering the working speed requirements of LVDS and the dual current source structure adopted in its driving circuit, the dual current source can be a PMOS current source and an NMOS current source. In order to avoid the mismatch problem that may exist between the PMOS current source and the NMOS current source, the LVDS mode driving circuit in this embodiment is also provided with a common mode feedback circuit. The common mode feedback circuit is connected to the output ports CLKOUT and CLKOUTB through a common mode load to obtain an output common mode level VCM. The operational amplifier AMP1 compares the common mode level VCM with the resistor voltage reference level VREF, and outputs VCMFB to adjust the conduction state of the MOS tubes M20 and M21 to form a common mode feedback loop, adjust the common mode level, and reduce the mismatch between the PMOS current source and the NMOS current source. Among them, when the circuit is in a low power consumption state, only the on and off of the MOS tube M20 can be controlled. When the circuit is in a high power consumption state, the on and off of the MOS tubes M20 and M21 are realized by closing the control switch S4.

[0039] When the multi-protocol output drive circuit selects the LVDS mode, the digital control signal Prog_I_lvds can be output through the logic control module to configure the current array, and the bias voltage VBP generated by the LVDS bias generation circuit is used to provide bias current for the LVDS mode drive circuit, and the number of current branches connected to the circuit is selected through the logic control module, so as to adjust the tail current of the drive circuit. Among them, when CLKPL and CLKNL are high level, CLKPR and CLKNR are low level, a path from the power supply to the ground is formed through the external 100Ω load, at this time, the switch tubes M17 and M14 are turned on, M16 and M15 are turned off, the output at CLKOUTB is high level, and the output at CLKOUT is low level; when CLKPL and CLKNL are low level, CLKPR and CLKNR are high level, the switch tubes M17 and M14 are turned off, M16 and M15 are turned on, the output at CLKOUTB is low level, and the output at CLKOUT is high level.

[0040] like Figure 6 FIG. 1 is a schematic diagram of a CMOS mode driving circuit provided in this embodiment. Figure 6 The CMOS mode driving circuit includes a driving unit and a second voltage conversion unit; the second voltage conversion unit is electrically connected to the logic control module and the driving tube unit respectively and is used to be electrically connected to an external clock control signal generator.

[0041] In this embodiment, when the multi-protocol output drive circuit selects the CMOS mode, ENH_CMOS is pulled high, and the other modes are closed. The clocks CLKINP and CLKINN are converted into CLKP_CMOS and CLKN_CMOS through voltage, and control the drive tubes M24, M25 and M22, M23 respectively. When the drive tubes M24 and M25 are turned on, the drive tubes M22 and M23 are turned off, and CLKOUT and CLKOUTB output a high level close to the power supply voltage. When the drive tubes M24 and M25 are turned off and the drive tubes M22 and M23 are turned on, CLKOUT and CLKOUTB output a low level close to 0V, and the output signal swing of CMOS is close to the power supply voltage VDD.

[0042] Therefore, in order to achieve a higher operating speed, the multi-protocol output drive circuit provided in this embodiment adopts a low-voltage domain driver tube (such as a MOS device) as a core working device, and designs a withstand voltage protection circuit for it, that is, a layer of withstand voltage isolation tube is superimposed on the drain of the core device, and the isolation characteristics of the cascode are used to isolate the high-voltage side close to the power supply to ensure the safety of the core device in the low-voltage domain. An adjustable current array is set. When the CML or LVPECL mode is selected, VBN1 outputs normally, which can be configured by the PROG_I_CMLLVP control word. When the LVDS mode is selected, VBN2 outputs normally, which can be configured by the PROG_I_LVDS control word. You can choose to increase or decrease the number of tail currents such as MOS tail current tubes connected, and then adjust the bias current of the drive circuit. An internal adjustable resistor array is set. When the CML and LVPECL modes are selected, the equivalent resistance value connected can also be adjusted by adjusting the internal adjustable resistor array. By configuring the current and resistance, low power consumption and high performance modes can be achieved. By adjusting the load resistance and the drive current, the drive circuits of different transmission protocols can be matched to achieve high flexibility and high reliability of the output drive circuit.

[0043] It should be noted that the various embodiments in the present application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0044] It should also be noted that, in the content of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0045] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A multi-protocol output drive circuit, characterized in that: include: A logic control module, a bias generation module and an output drive module, wherein the output drive module includes a plurality of output drive circuits of different transmission protocol types; wherein the transmission protocol types include a differential signal transmission protocol and a single-ended signal transmission protocol; The logic control module is configured to: output an enable control signal to the target output drive circuit, and when the transmission protocol type of the target output drive circuit is the differential signal transmission protocol, output a selection control signal to the bias generation module; wherein the enable control signal is used to control the target output drive circuit to enter a working state; The bias generation module is configured to: select and output a corresponding bias voltage to the target output drive circuit according to the selection control signal; wherein the bias voltage is used to control the output swing of the target output drive circuit.

2. The multi-protocol output driving circuit according to claim 1, characterized in that: The output driving module includes a CML mode driving circuit, an LVPECL mode driving circuit, an LVDS mode driving circuit and a CMOS mode driving circuit connected in parallel.

3. The multi-protocol output driving circuit according to claim 2, characterized in that: The bias generation module includes an LVDS bias generation circuit, an LVPECL bias generation circuit and a CML bias generation circuit; wherein, The bias generation module is configured to: select the bias voltage generated by the corresponding bias generation circuit and transmit it to the corresponding output drive circuit according to the selection control signal.

4. The multi-protocol output driving circuit according to claim 2, characterized in that: The CML mode driving circuit includes a CML adjustable resistance array, an adjustable current array, a first differential driving unit, a first isolation tube unit and a CML bias control unit; The first differential driving unit is electrically connected to the adjustable current array and the first isolation tube unit respectively, the CML adjustable resistance array is electrically connected to the logic control module, the first isolation tube unit and a power supply respectively, the adjustable current array is also electrically connected to the CML bias control unit and the logic control module, and the first isolation tube unit is also electrically connected to the CML bias control unit; The CML bias control unit is configured to: transmit the bias voltage to the first isolation tube unit and the adjustable current array when receiving the enable control signal; wherein the bias voltage is used to control the first isolation tube unit to enter a conducting state, and to control the total current of the adjustable current array in combination with the first digital control signal transmitted by the logic control module; The CML adjustable resistor array is configured to adjust the number of resistors connected to the CML mode driving circuit according to a second digital control signal transmitted by the logic control module.

5. The multi-protocol output driving circuit according to claim 4, characterized in that: The first differential driving unit includes a first driving transistor and a second driving transistor, the first isolation transistor unit includes a first switching transistor and a second switching transistor, and the CML adjustable resistor array includes a first adjustable resistor array and a second adjustable resistor array; The control ends of the first driver tube and the second driver tube are both electrically connected to an external clock control signal generator, the input ends of the first driver tube and the second driver tube are both electrically connected to the adjustable current array, the output end of the first driver tube is electrically connected to the input end of the first switch tube, the output end of the second driver tube is electrically connected to the input end of the second switch tube, the control ends of the first switch tube and the second switch tube are both electrically connected to the CML bias control unit, the output end of the first switch tube is electrically connected to the first adjustable resistor array and is used to be electrically connected to an external load, the output end of the second switch tube is electrically connected to the second adjustable resistor array and is used to be electrically connected to an external load, and the first adjustable resistor array and the second adjustable resistor array are also electrically connected to the logic control module.

6. The multi-protocol output driving circuit according to claim 4, characterized in that: The LVPECL mode driving circuit includes the CML mode driving circuit, a second isolation tube unit, an LVPECL adjustable resistor array, a source follower and an LVPECL bias control unit; The second isolation tube unit is electrically connected to the first differential driving unit, the LVPECL adjustable resistor array and the input end of the source follower respectively, the output end of the source follower is used to be electrically connected to an external load, the LVPECL adjustable resistor array is also electrically connected to the logic control module, and the LVPECL bias control unit is electrically connected to the logic control module, the bias generation module, the second isolation tube unit and the adjustable current array respectively; The LVPECL bias control unit is further configured to: transmit the bias voltage to the second isolation tube unit and the adjustable current array when receiving the enable control signal; wherein the bias voltage is used to control the second isolation tube unit to enter a conducting state, and to control the total current of the adjustable current array in combination with the third digital control signal transmitted by the logic control module; The LVPECL adjustable resistor array is configured to adjust the number of resistors connected to the LVPECL mode driving circuit according to a fourth digital control signal transmitted by the logic control module.

7. The multi-protocol output driving circuit according to claim 6, characterized in that: The second isolation transistor unit includes a third switch transistor and a fourth switch transistor, the LVPECL adjustable resistor array includes a third adjustable resistor array and a fourth adjustable resistor array, and the source follower includes a first MOS transistor and a second MOS transistor; The input ends of the third switch tube and the fourth switch tube are both electrically connected to the first differential driving unit, the control ends of the third switch tube and the fourth switch tube are both electrically connected to the LVPECL bias control unit, the output end of the third switch tube is respectively connected to the third adjustable resistor array and the gate of the first MOS tube, the output end of the fourth switch tube is respectively electrically connected to the fourth adjustable resistor array and the gate of the second MOS tube, the third adjustable resistor array and the fourth adjustable resistor array are also electrically connected to the logic control module, the source electrodes of the first MOS tube and the second MOS tube are both used to be electrically connected to an external load, and the drain electrodes of the first MOS tube and the second MOS tube are both electrically connected to a power supply.

8. The multi-protocol output driving circuit according to claim 2, characterized in that: The LVDS mode driving circuit includes a first LVDS adjustable current array, a second LVDS adjustable current array, a second differential driving unit, a first voltage conversion unit and a common mode feedback unit; The second differential driving unit is electrically connected to the first voltage conversion unit, the first LVDS adjustable current array, the second LVDS adjustable current array and the common-mode feedback unit, respectively; the first LVDS adjustable current array is also electrically connected to the logic control module, the bias generation module and the common-mode feedback unit, respectively; the second LVDS adjustable current array is also electrically connected to the logic control module and the bias generation module, respectively; the first voltage conversion unit is electrically connected to the logic control module and is used to be electrically connected to an external clock control signal generator.

9. The multi-protocol output driving circuit according to claim 8, characterized in that: The common-mode feedback circuit includes a reference voltage supply circuit, a common-mode load, a comparator, a first control switch, a fifth switch tube and a sixth switch tube; The common-mode load is electrically connected to the output end of the second differential driving unit and the first input end of the comparator, respectively; the reference voltage supply circuit is electrically connected to the second input end of the comparator; the first control switch is electrically connected to the output end of the comparator, the gates of the fifth switch tube and the sixth switch tube, and the logic control module, respectively; the sources of the fifth switch tube and the sixth switch tube are electrically connected to a power supply; and the drains of the fifth switch tube and the sixth switch tube are electrically connected to the first LVDS adjustable current array.

10. The multi-protocol output driving circuit according to claim 2, characterized in that: The CMOS mode driving circuit includes a driving tube unit and a second voltage conversion unit; the second voltage conversion unit is electrically connected to the logic control module and the driving tube unit respectively and is used to be electrically connected to an external clock control signal generator.

11. The multi-protocol output driving circuit according to claim 3, characterized in that: The LVDS bias generating circuit includes a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube, a first resistor and a second control switch; The sources of the seventh switch tube, the eighth switch tube and the ninth switch tube are all electrically connected to the power supply, the drain of the seventh switch tube is respectively electrically connected to the gate of the seventh switch tube, the gate of the eighth switch tube, the first resistor, the gate of the ninth switch tube and the LVDS mode driving circuit, the drain of the eighth switch tube is respectively electrically connected to the drain of the tenth switch tube, the gate of the eleventh switch tube and the LVDS mode driving circuit, the source of the tenth switch tube is electrically connected to the drain of the eleventh switch tube, the gate of the twelfth switch tube is respectively electrically connected to the gate of the tenth switch tube, the drain of the twelfth switch tube and the drain of the ninth switch tube, the sources of the twelfth switch tube and the eleventh switch tube are both grounded, and the second control switch is respectively electrically connected to the first resistor, the logic control module and the source of the eleventh switch tube.

12. The multi-protocol output driving circuit according to claim 3, characterized in that: The CML bias generating circuit includes the LVPECL bias generating circuit, a thirteenth switch tube, a fourteenth switch tube and a third control switch; The source of the thirteenth switch tube and the first end of the third control switch are electrically connected to a power supply, the gate of the thirteenth switch tube is electrically connected to the LVPECL bias generating circuit and the second end of the third control switch respectively, the drain of the thirteenth switch tube is electrically connected to the drain and gate of the fourteenth switch tube and the CML mode driving circuit respectively, the source of the fourteenth switch tube is grounded, and the third end of the third control switch is electrically connected to the logic control module.

13. The multi-protocol output driving circuit according to claim 12, characterized in that: The LVPECL bias generating circuit includes a fifteenth switch tube, a sixteenth switch tube, a seventeenth switch tube, an eighteenth switch tube, a nineteenth switch tube, a second resistor, a fourth control switch, a fifth control switch, a sixth control switch, a seventh control switch and an eighth control switch; The second resistor is electrically connected to the fourth control switch, the drain and gate of the fifteenth switch tube, and the gate of the sixteenth switch tube respectively. The sources of the fifteenth switch tube and the sixteenth switch tube are both grounded. The drain of the sixteenth switch tube is electrically connected to the fifth control switch. The gate of the seventeenth switch tube is electrically connected to the drain of the seventeenth switch tube, the fifth control switch, the sixth control switch, and the eighth control switch respectively. The gate of the eighteenth switch tube is electrically connected to the sixth control switch and the seventh control switch respectively. The sources of the seventeenth switch tube and the eighteenth switch tube are both electrically connected to a power supply. One end of the fourth control switch and the seventh control switch are both electrically connected to a power supply. The drain of the eighteenth switch tube is electrically connected to the LVPECL mode driving circuit and the gate and drain of the nineteenth switch tube respectively. The source of the nineteenth switch tube is grounded. One end of the eighth control switch is electrically connected to the gate of the thirteenth switch tube. All control switches are also electrically connected to the logic control module.

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