Digital signal amplifier developed based on radio frequency transceiver chip

Abstract

The invention discloses a digital signal amplifier developed based on a radio frequency transceiver chip. The digital signal amplifier comprises a user terminal, a first radio frequency transceiver chip, a second radio frequency transceiver chip and a main antenna, the user terminal is in signal connection with the second radio frequency transceiver chip, the second radio frequency transceiver chip is connected with the first radio frequency transceiver chip, the first radio frequency transceiver chip is wirelessly connected with the main antenna, and the main antenna is in signal wireless connection with the base station; the user terminal transmits a signal input by a user to the second radio frequency transceiver chip, and the second radio frequency transceiver chip converts the signal input by the user into a baseband signal and transmits the baseband signal to the first radio frequency transceiver chip; afterwards, the signal is enhanced by the first radio frequency transceiver chip and then sent to the main antenna, and the main antenna receives the enhanced signal input by the user and sends the signal to the base station. The logic chip is utilized to control the baseband signal forwarding between the first radio frequency transceiver chip and the second radio frequency transceiver chip, so that the same frequency can enter the system for baseband signal conversion.

Description

Technical Field

[0001] The present invention relates to the technical field of signal amplifiers, and in particular to a digital signal amplifier developed based on a radio frequency transceiver chip. Background Art

[0002] As the coverage of mobile networks becomes wider and wider, shopping malls, parking lots, schools, hotels and other places need mobile network coverage. There are two solutions adopted by the existing mobile communication low-power micro-distribution system, mobile phone companion, mobile phone signal amplifier, and Mangebao: one is that the RF link is composed of analog devices, which will enhance the background noise or signal outside the working frequency band after amplification, causing the scene very close to the out-of-band signal base station to interfere with other frequency band base stations. The advantage is low cost. The second is that the RF link is digital, but the logic chip uses FPGA, which can suppress the out-of-band signal very well and will not raise the out-of-band background noise or out-of-band signal, but the cost is several times that of analog products and cannot be used in the field of wireless communications. Summary of the invention

[0003] The present invention provides a digital signal amplifier developed based on a radio frequency transceiver chip, which is used to solve the problem raised in the technical background.

[0004] A digital signal amplifier developed based on a radio frequency transceiver chip of the present invention comprises a user terminal, a first radio frequency transceiver chip, a second radio frequency transceiver chip, a main antenna, and a base station;

[0005] The user terminal signal is connected to the second RF transceiver chip, the second RF transceiver chip is connected to the first RF transceiver chip, the first RF transceiver chip is wirelessly connected to the main antenna, and the main antenna signal is wirelessly connected to the base station;

[0006] The user terminal transmits the signal input by the user to the second RF transceiver chip, and the second RF transceiver chip converts the signal input by the user into a baseband signal and sends it to the first RF transceiver chip; the first RF transceiver chip restores the baseband signal to the signal input by the user, and then enhances it by the first RF transceiver chip and sends it to the main antenna, and the main antenna receives the enhanced user input signal and sends it to the base station.

[0007] Preferably, the second RF transceiver chip and the first RF transceiver chip are the same chip.

[0008] Preferably, the second RF transceiver chip and the first RF transceiver chip are both connected to an uplink signal input circuit;

[0009] The uplink signal input circuit includes a 40M crystal oscillator, which is electrically connected to the input of the second chip. The output of the second chip includes three paths, which are electrically connected to a first RF transceiver chip, a second RF transceiver chip, and a logic chip.

[0010] Preferably, the clock emitted by the 40M crystal oscillator is divided into three paths through the second chip, one clock is given to the second RF transceiver chip, another clock is given to the first RF transceiver chip, and another clock is given to the logic chip, so as to realize the same source of multiple clocks.

[0011] Preferably, the second RF transceiver chip and the first RF transceiver chip are both connected to a power management circuit.

[0012] Preferably, the power management circuit is electrically connected to the power supply circuit.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] The present invention converts the user input signal into a digital signal and then converts it into a baseband signal and sends it to the second RF transceiver chip and the first RF transceiver chip. Then, a low-cost logic chip is used to combine the first RF transceiver chip and the second RF transceiver chip to achieve digital low-cost signal amplification.

[0015] The logic chip is used to control the forwarding of baseband signals between the first RF transceiver chip and the second RF transceiver chip without demodulation and modulation. The control synchronization time is guaranteed at the same crystal frequency, the overall system delay is reduced, and the baseband signal conversion can be realized when the same frequency enters the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is an overall structural diagram of a digital signal amplifier developed based on a radio frequency transceiver chip of the present invention;

[0017] Figure 2 A circuit diagram of an uplink signal input circuit of the present invention;

[0018] Figure 3 A circuit diagram of a clock homology circuit of the present invention;

[0019] Figure 4 is a circuit diagram of a power management circuit of the present invention;

[0020] Figure 5 It is a circuit diagram of the power supply circuit of the present invention. DETAILED DESCRIPTION

[0021] The following will disclose multiple embodiments of the present invention with diagrams. For the purpose of clear description, many physical details will be described together in the following description. However, it should be understood that these physical details should not be used to limit the present invention. In other words, in some embodiments of the present invention, these physical details are not necessary. In addition, for the purpose of simplifying the diagram, some conventional structures and components will be depicted in a simple schematic manner in the diagram.

[0022] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0023] See also Figure 1-5 , the present invention is a digital signal amplifier developed based on a radio frequency transceiver chip, comprising a user terminal, a first radio frequency transceiver chip 1, a second radio frequency transceiver chip 2, a main antenna, and a base station;

[0024] The user terminal signal is connected to the second RF transceiver chip 2, the second RF transceiver chip 2 is connected to the first RF transceiver chip 1, the first RF transceiver chip 1 is wirelessly connected to the main antenna, and the main antenna signal is wirelessly connected to the base station;

[0025] The user terminal transmits the signal input by the user to the second RF transceiver chip 2, and the second RF transceiver chip 2 converts the signal input by the user into a baseband signal and sends it to the first RF transceiver chip 1; the first RF transceiver chip 1 restores the baseband signal to the signal input by the user, and then enhances it by the first RF transceiver chip 1 and sends it to the main antenna, and the main antenna receives the enhanced user input signal and sends it to the base station.

[0026] Furthermore, the second RF transceiver chip 2 is the same chip as the first RF transceiver chip 1, and the model of the second RF transceiver chip 2 and the first RF transceiver chip 1 is any one of ECR8665 / ECR8667 / ECR8668 / GC0802L. The first RF transceiver chip 1 and the second RF transceiver chip 2 can also adopt RF transceiver chips with similar functions such as ESV 8665, 8668, 8667, etc.

[0027] Furthermore, the second RF transceiver chip 2 and the first RF transceiver chip 1 are both connected to an uplink signal input circuit 3;

[0028] The uplink signal input circuit 3 includes a 40M crystal oscillator Y401, and the model of the 40M crystal oscillator Y401 is any one of DSB211 SDN38.400MHZ 1XXD38400MLC / DSB211 SDN 30.72MHZ 7EF03072A01. The 40M crystal oscillator Y401 is electrically connected to the input of the second chip U401, and the model of the second chip U401 is CDCV304TPWREP. The output of the second chip U401 includes three CLKs, and the three CLKs are electrically connected to a second RF transceiver chip 2, a first RF transceiver chip 1, and a logic chip.

[0029] Furthermore, the clock emitted by the 40M crystal oscillator Y401 is divided into three CLKs through the second chip U401, and the three CLKs are output as downlink signals, one of which is given to the second RF transceiver chip 2, another is given to the first RF transceiver chip 1, and another is given to the logic chip. The logic chip is the MCU controller. The first RF transceiver chip 1 is also connected to the logic chip at the same time to achieve multi-channel clock homology.

[0030] Furthermore, the second RF transceiver chip 2 and the first RF transceiver chip 1 are both connected to a power management circuit 4 .

[0031] Furthermore, the power management circuit 4 is electrically connected to the power supply circuit 5 .

[0032] Embodiment: The main antenna picks up the network signal of the mobile base station in the existing coverage area and sends it to the second RF transceiver chip 2; the second RF transceiver chip 2 converts the base station network signal into a baseband signal and sends it to the first RF transceiver chip 1; the first RF transceiver chip 1 restores the baseband signal to the base station network signal, which is enhanced by the first RF transceiver chip 1 and then sent to the main antenna in the coverage area, and then the main antenna transmits the enhanced user input signal to the area to be covered.

[0033] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A digital signal amplifier developed based on a radio frequency transceiver chip, characterized in that: It comprises a user terminal, a first radio frequency transceiver chip (1), a second radio frequency transceiver chip (2), a main antenna, and a base station; The user terminal signal is connected to the second radio frequency transceiver chip (2), the second radio frequency transceiver chip (2) is connected to the first radio frequency transceiver chip (1), the first radio frequency transceiver chip (1) is wirelessly connected to the main antenna, and the main antenna signal is wirelessly connected to the base station; The user terminal transmits the signal input by the user to the second radio frequency transceiver chip (2); the second radio frequency transceiver chip (2) converts the signal input by the user into a baseband signal and sends it to the first radio frequency transceiver chip (1); the first radio frequency transceiver chip (1) restores the baseband signal to the signal input by the user, and then enhances it by the first radio frequency transceiver chip (1) and sends it to the main antenna; the main antenna receives the enhanced signal input by the user and sends it to the base station.

2. The amplifier according to claim 1, characterized in that The second radio frequency transceiver chip (2) and the first radio frequency transceiver chip (1) are the same chip.

3. The amplifier according to claim 1, characterized in that The second radio frequency transceiver chip (2) and the first radio frequency transceiver chip (1) are both connected to an uplink signal input circuit (3); The uplink signal input circuit (3) includes a 40M crystal oscillator (Y401), the 40M crystal oscillator (Y401) is electrically connected to the input of the second chip (U401), the output of the second chip (U401) includes three paths (CLK), and the three paths (CLK) are electrically connected to a radio frequency transceiver chip (2), a first radio frequency transceiver chip (1), and a logic chip.

4. The amplifier according to claim 3, characterized in that The clock emitted by the 40M crystal oscillator (Y401) is divided into three paths (CLK) through the second chip (U401), one of which is sent to the second RF transceiver chip (2), another is sent to the first RF transceiver chip (1), and another is sent to the logic chip, thereby realizing the same source of multiple clocks.

5. The amplifier according to claim 3, characterized in that The second radio frequency transceiver chip (2) and the first radio frequency transceiver chip (1) are both connected to a power management circuit (4).

6. The amplifier according to claim 3, characterized in that The power management circuit (4) is electrically connected to the power supply circuit (5).

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