Clock path processing method and device based on fault and fault recovery
By obtaining clock topology diagrams and fault alarm information, quickly locate the fault source equipment and perform clock fault repair, the problem that clock fault repair requires manual confirmation and time is solved in the existing technology, and the fault repair efficiency is improved.
Patent Information
- Application Number
- CN202510117888.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2025-05-06
AI Technical Summary
In the prior art, when clock failure occurs in the network, repair requires manual confirmation, which takes a long time and is difficult to quickly confirm the common fault source of multiple network element devices, which extends the repair time.
By obtaining the clock topology diagram in advance, obtaining the clock alarm information of each faulty device, and determining whether the fault port is used as the sink node of the clock chain fiber. If so, find the clock topology diagram to locate the faulty device link, determine the fault source device and perform clock fault repair.
It can quickly locate the fault source equipment, and by repairing the clock fault of the fault source equipment, improve the clock fault repair efficiency of downstream fault equipment, and reduce manual intervention and repair time.
Smart Images
Figure CN119945884A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of clock path change, and in particular to a clock path processing method and device based on fault and fault recovery. Background Art
[0002] In order to ensure the smooth development of network services, all devices on the network need to synchronize their clocks. During synchronization, the clock source and clock path need to be specified. The clock source provides standard clock information; the clock path is a unidirectional path that starts from the clock source and connects all devices on the network. When synchronizing the clock, the clock of each device is determined by the clock of the upstream device connected to the device.
[0003] With the rapid development of 5G technology, the scale of the network is getting larger and larger, and the number of devices in the network is increasing. Clock information is the most basic information on each device. Once the clock information is wrong or deviated, it will cause unpredictable errors such as service interruption.
[0004] For the protection of the clock path, the existing technical means include the following process:
[0005] 1. Configure the master and slave clock paths of the device to make the configuration take effect. The paths are in locked state.
[0006] 2. If the main clock link fails, the device automatically switches to the backup path through detection.
[0007] 3. If the backup clock link fails, the device reports an alarm to the network manager, who then notifies the operation and maintenance personnel through alarm notifications and other means.
[0008] 4. The operation and maintenance personnel manually modify the clock configuration.
[0009] The main problems of existing technical means:
[0010] 1. When a clock failure occurs, the repair requires manual confirmation and the repair time is long.
[0011] 2. When a clock failure occurs, it often causes alarms for a large number of network elements. During manual repair, only the previous hop device on the clock path of each network element device is found and replaced, that is, the previous hop network element device of the current alarm network element device is regarded as the fault source. It cannot be considered from a global perspective, and the common fault source of multiple network element devices cannot be quickly confirmed, which also prolongs the repair time.
[0012] 3. After confirming the source of the fault, the manually selected path may not be the best one.
[0013] 4. After the faulty path is restored, the clock path cannot be adjusted to the original path in time. Summary of the invention
[0014] The present application provides a clock path processing method and device based on fault and fault recovery, which can solve the technical problem in the prior art that it is difficult to quickly repair the clock status of all faulty devices when a large number of network element devices in the network send out clock alarm information.
[0015] In a first aspect, an embodiment of the present application provides a clock path processing method based on fault and fault recovery, the method comprising:
[0016] Get the clock topology diagram containing all clock paths in advance;
[0017] Acquire clock alarm information issued by each faulty device, wherein the clock alarm information includes the faulty port and clock configuration information on the faulty port, wherein the clock configuration information includes information related to a source node and a sink node in a clock chain fiber corresponding to the faulty port;
[0018] Determine whether the faulty port serves as the sink node of the clock chain fiber and whether there is a physical link between the source and sink nodes in the clock chain fiber. If so, take the clock chain fiber as the fault path, search the clock topology diagram according to the fault path corresponding to each clock alarm information, obtain the faulty device link on each clock path, take the device most upstream in the faulty device link as the faulty source device, and repair the clock fault of the faulty source device; if not, repair the clock fault of the faulty device itself.
[0019] In combination with the first aspect, in one implementation, the method further includes:
[0020] After the clock fault of the fault source device is repaired, determine whether the clock status of all faulty devices downstream of the faulty source device in the faulty device link has returned to normal. If so, eliminate the clock alarm information; if not, take the first faulty device downstream of the faulty source device as the new faulty source device, and repair the clock fault of the new faulty source device.
[0021] In combination with the first aspect, in one implementation, the repairing the fault source device specifically includes the following steps:
[0022] Determine whether there are other paths besides the fault path between the fault source device and its adjacent upstream device in the fault device link. If so, select a path from the other paths to build a new clock chain fiber between the fault source device and its adjacent upstream device. If not, calculate the minimum ring or shortest chain between the fault source device and its adjacent upstream device in the network, and build a new clock chain fiber between the fault source device and its adjacent upstream device based on the minimum ring or shortest chain.
[0023] In combination with the first aspect, in one implementation, the method further includes:
[0024] After obtaining the fault source devices corresponding to each clock alarm information, the clock fault is repaired according to the priority order of the fault source devices; the priority order is that the priority of the core layer device is greater than the priority of the aggregation layer device, and the priority of the aggregation layer device is greater than the priority of the access layer device.
[0025] In combination with the first aspect, in one implementation, the method further includes:
[0026] After repairing the clock fault of the fault source device, a new clock path is obtained, and the new clock path is associated with the old clock path;
[0027] Path switching is performed between associated clock paths according to a preset switching strategy.
[0028] In a second aspect, an embodiment of the present application provides a clock path processing system based on fault and fault recovery, the system comprising:
[0029] A data acquisition module, which is used to pre-acquire a clock topology diagram containing all clock paths;
[0030] An alarm processing module, which is used to obtain clock alarm information sent by each faulty device, wherein the clock alarm information includes the faulty port and the clock configuration information on the faulty port, wherein the clock configuration information includes information related to the source node and the sink node in the clock chain fiber corresponding to the faulty port;
[0031] A fault repair module is used to determine whether the faulty port serves as a sink node of a clock chain fiber and whether there is a physical link between the source and sink nodes in the clock chain fiber. If so, the clock chain fiber is used as a fault path, and the clock topology diagram is searched according to the fault paths corresponding to each clock alarm information to obtain the faulty device links on each clock path. The device most upstream in the faulty device link is used as the faulty source device, and the clock fault of the faulty source device is repaired; if not, the clock fault of the faulty device itself is repaired.
[0032] In combination with the second aspect, in one embodiment, the fault repair module is also used to determine whether the clock status of all faulty devices downstream of the faulty source device in the faulty device link has returned to normal after the clock fault of the faulty source device is repaired. If so, the clock alarm information is eliminated; if not, the first faulty device downstream of the faulty source device is used as the new faulty source device, and the clock fault is repaired for the new faulty source device.
[0033] In combination with the second aspect, in one embodiment, when the fault repair module repairs the fault source device, it determines whether there are other paths other than the fault path in the fault device link between the fault source device and its adjacent upstream device. If so, a path is selected from the other paths to construct a new clock chain fiber between the fault source device and its adjacent upstream device; if not, the minimum ring or shortest chain of the fault source device in the network is calculated, and a new clock chain fiber is constructed based on the minimum ring or shortest chain.
[0034] In combination with the second aspect, in one embodiment, the fault repair module is also used to perform clock fault repair in the order of priority of the fault source devices after obtaining the fault source devices corresponding to each clock alarm information; the priority of the core layer device is greater than the priority of the aggregation layer device, and the priority of the aggregation layer device is greater than the priority of the access layer device.
[0035] In conjunction with the second aspect, in one implementation, the fault repair module is further used to obtain a new clock path after repairing the clock fault of the fault source device, and associate the new clock path with the old clock path;
[0036] Path switching is performed between associated clock paths according to a preset switching strategy.
[0037] The beneficial effects brought by the technical solution provided in the embodiments of the present application include:
[0038] It can quickly locate the fault source device according to the clock alarm information sent by each faulty device, and improve the clock fault repair efficiency of downstream faulty devices by repairing the clock fault of the fault source device. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 A flowchart of an embodiment of a clock path processing method based on fault and fault recovery of the present application;
[0040] Figure 2 This is an application diagram of a specific embodiment of a clock path processing method based on fault and fault recovery of the present application;
[0041] Figure 3 This is a functional module diagram of an embodiment of a clock path processing system based on fault and fault recovery of the present application. DETAILED DESCRIPTION
[0042] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0043] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0044] In a first aspect, an embodiment of the present application provides a clock path processing method based on fault and fault recovery.
[0045] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the clock path processing method based on fault and fault recovery of this application. Figure 1 As shown, the clock path processing method based on fault and fault recovery includes:
[0046] Step S1: pre-acquire a clock topology diagram including all clock paths.
[0047] Step S2: Acquire clock alarm information sent by each faulty device. The clock alarm information includes the faulty port and clock configuration information on the faulty port. The clock configuration information includes information related to the source node and the sink node in the clock chain fiber corresponding to the faulty port.
[0048] Step S3: Determine whether the faulty port is used as a sink node of a clock fiber chain and whether a physical link exists between the source and sink nodes in the clock fiber chain:
[0049] If yes, go to step S4.
[0050] If not, go to step S5.
[0051] Step S4: Take the clock chain fiber as the fault path, search the clock topology diagram according to the fault path corresponding to each clock alarm information, obtain the faulty device link on each clock path, take the upstream device in the faulty device link as the faulty source device, and repair the clock fault of the faulty source device.
[0052] Step S5: Repair the clock fault of the faulty device itself.
[0053] In this embodiment, the clock topology includes multiple clock paths, each clock path includes a clock source and multiple network element devices, there is at least one physical link between two adjacent devices in the clock path, and a clock chain fiber in the clock path is constructed based on one of the physical links. The clock path is a unidirectional path, starting from the clock source, and connected to multiple network element devices downstream. Therefore, the clock chain fiber is also a unidirectional path. In the clock chain fiber, the chain direction is determined by the source node and the sink node. The source node and the sink node are ports on the network element device.
[0054] When configuring the clock path for the device in the network for the first time, the clock configuration information is sent to the device to configure the clock of its port so that the port can be connected to the corresponding clock path. When a large number of devices in the network send out clock alarm information, only the faulty port and the clock configuration information of the faulty port can be extracted from the clock alarm information. Since the maintainers of different devices may be different, or the distance between different devices may be far, the maintainer will select the device that can be connected the fastest as the new clock information provider, that is, the previous hop device, in order to improve the efficiency of repairing the clock fault of the device. However, the new clock path selected for the faulty device at this time may not be the best. In addition, due to the lack of global coordination, repairing the clock faults of all devices that send out clock alarm information separately will greatly reduce the efficiency of clock state recovery of the entire network.
[0055] In order to solve the above problems, in the solution of the present invention, after obtaining the clock alarm information sent by each faulty device, the faulty port and the clock configuration information on the faulty port are extracted from each clock alarm information respectively. If the faulty port is used as the host node of a jump link fiber in its clock configuration information, and there is an actual physical link between the jump link fiber and the source node of the jump link fiber, it means that the jump link fiber is a faulty path. The pre-acquired clock topology diagram is searched in combination with the faulty paths corresponding to all clock alarm information, and several clock paths where clock failures occur in the clock topology can be located. On each clock path where a clock failure occurs, the faulty device link on the clock path is from the first faulty device that sends a clock alarm information to the last faulty device that sends a clock alarm information, wherein the first device that sends a clock alarm information is the faulty source device on the path. Subsequently, the clock failure of the downstream device on the faulty device link can be automatically restored after the clock failure of the faulty source device is repaired, thereby greatly improving the clock failure repair efficiency of all devices in the entire network.
[0056] In summary, the fault source device can be quickly located according to the clock alarm information issued by each faulty device, and the clock fault repair efficiency of the downstream faulty device can be improved by repairing the clock fault of the fault source device.
[0057] In a specific embodiment, referring to Figure 2 , Figure 2This is an application diagram of a specific embodiment of the clock path processing method based on fault and fault recovery of the present application, according to Figure 2 The network topology diagram shows the clock paths constructed in the network.
[0058] Clock source 1 → NE 1 → NE 3 → NE 5.
[0059] Clock source 2 → NE 2 → NE 4 → NE 6.
[0060] Clock source 2 → NE 2 → NE 1 → NE 3 → NE 5.
[0061] Clock source 2 → NE 2 → NE 3 → NE 5.
[0062] Clock source 2 → NE 2 → NE 3 → NE 4 → NE 6.
[0063] The main clock path of network element 3 is connected to network element 1, and the backup clock path is connected to network element 2. When the main clock path of network element 3 is disconnected, clock alarm information is generated, and the fault path is network element 1→network element 3. Then the clock path of network element 3 is switched to the backup clock path. After the backup clock path of network element 3 is disconnected, clock alarm information is generated, and the fault path is network element 2→network element 3. Network element 3 generates a total of two clock alarm information, corresponding to the main and backup clock paths respectively. Network element 5 generates one clock alarm information, and the corresponding fault path is network element 3→network element 5. After receiving the clock alarm information of network element 3 and network element 5, the clock topology diagram is searched in combination with the corresponding fault path, and the fault device link is obtained as network element 3→network element 5. The fault source device is network element 3. It is only necessary to repair the clock fault of network element 3 to automatically repair the clock fault of network element 5, thereby improving the fault source location accuracy and fault repair efficiency.
[0064] Further, in one embodiment, continue to refer to Figure 1 , the above method further comprises:
[0065] After step S4 and step S5 are completed, the process jumps to step S6.
[0066] Step S6: Check whether the clock status of all faulty devices downstream of the fault source device in the faulty device link has returned to normal:
[0067] If yes, go to step S7.
[0068] If not, go to step S8.
[0069] Step S7: Eliminate clock alarm information.
[0070] Step S8: Take the first faulty device downstream of the faulty source device as a new faulty source device, and perform clock fault repair on the new faulty source device.
[0071] In this embodiment, after the new clock configuration information is sent, the clock state of the fault source device is restored, the clock path of the downstream faulty network element of the fault source device should also be automatically restored, and all fault port alarms still exist. After waiting for a period of time, if the links of multiple network elements are restored at the same time, the alarm is cleared. If not, the downstream device of the fault source device is used as the new fault source device, and the new clock configuration information is sent to the new fault source device to repair its clock fault, ensuring that all clock paths are restored to normal.
[0072] In a specific embodiment, continue to refer to Figure 2 If the clock status of network element 5 does not automatically return to normal after network element 3 is repaired, network element 5 is taken as the new fault source and its clock fault is repaired.
[0073] Furthermore, in one embodiment, the above-mentioned fault repairing of the fault source device specifically includes the following steps:
[0074] Determine whether there are other paths between the fault source device and its adjacent upstream device in the faulty device link except the faulty path. If so, select a path from the other paths to build a new clock chain fiber between the fault source device and its adjacent upstream device. If not, calculate the minimum ring or shortest chain of the fault source device in the network, and build a new clock chain fiber based on the minimum ring or shortest chain.
[0075] In this embodiment, when repairing the clock failure of the fault source device, it is necessary to connect a new clock chain fiber. If there are other physical links between the previous hop device corresponding to the original clock chain fiber and the current device, one of these physical links is preferentially selected to establish a new clock chain fiber. If there are no other physical links, the minimum ring or shortest link of the fault source device in the network is calculated, and a network element device is selected based on the minimum ring or shortest link as the new previous hop device, and a new clock chain fiber is constructed between the previous device and the current device.
[0076] In a specific embodiment, continue to refer to Figure 2 There is no other physical link between NE 3 and NE 1 except the physical link where the clock fiber is located, and there is no other physical link between NE 3 and NE 2 except the physical link where the clock fiber is located. When repairing the clock failure of NE 3, after building a new physical link between NE 4 and NE 3, build a new clock fiber based on the new physical link, thereby forming a new clock path: clock source 2→NE 2→NE 4→NE 3→NE 5.
[0077] Furthermore, in one embodiment, the above method further includes:
[0078] After obtaining the fault source devices corresponding to each clock alarm information, the clock fault is repaired according to the priority order of the fault source devices. The priority of the core layer device is higher than that of the aggregation layer device, and the priority of the aggregation layer device is higher than that of the access layer device.
[0079] In this embodiment, if there are multiple fault source devices to be repaired, the network layers of these devices are first determined before repairing the clock fault. The priorities of the network layers are: core>aggregation>access.
[0080] If multiple fault source devices have the same priority, these devices perform clock fault repair at the same time.
[0081] If multiple fault source devices have different priorities, the clock fault repair is performed on the device with a higher priority first, and then on the device with a lower priority.
[0082] Furthermore, in one embodiment, the above method further includes:
[0083] After the clock fault of the fault source device is repaired, a new clock path is obtained, and the new clock path is associated with the old clock path.
[0084] Path switching is performed between associated clock paths according to a preset switching strategy.
[0085] In this embodiment, after the clock fault of the fault source device is repaired, the fault source device is connected to a new clock path. If the original clock path returns to normal after the new clock path runs for a period of time, for example, the original faulty port returns to normal or the clock chain fiber connected to the original faulty port returns to normal, then the faulty source device can be reconnected to the original clock path, that is, the current path is switched back to the original path.
[0086] In a second aspect, an embodiment of the present application also provides a clock path processing system based on fault and fault recovery.
[0087] In one embodiment, referring to Figure 3 , Figure 3 This is a functional module diagram of an embodiment of a clock path processing system based on fault and fault recovery of the present application. Figure 3 As shown, the clock path processing system based on fault and fault recovery includes:
[0088] The data acquisition module 1 is used to pre-acquire a clock topology diagram including all clock paths.
[0089] The alarm processing module 2 is used to obtain the clock alarm information sent by each faulty device. The clock alarm information includes the faulty port and the clock configuration information on the faulty port. The clock configuration information includes the source node and the sink node related information in the clock chain fiber corresponding to the faulty port.
[0090] Fault repair module 3 is used to determine whether the faulty port is a sink node of the clock fiber chain and whether there is a physical link between the source and sink nodes in the clock fiber chain. If so, the clock fiber chain is used as the fault path, and the clock topology diagram is searched according to the fault path corresponding to each clock alarm information to obtain the faulty device link on each clock path. The device most upstream in the faulty device link is used as the faulty source device, and the clock fault of the faulty source device is repaired. If not, the clock fault of the faulty device itself is repaired.
[0091] In this embodiment, the clock topology includes multiple clock paths, each clock path includes a clock source and multiple network element devices, there is at least one physical link between two adjacent devices in the clock path, and a clock chain fiber in the clock path is constructed based on one of the physical links. The clock path is a unidirectional path, starting from the clock source, and connected to multiple network element devices downstream. Therefore, the clock chain fiber is also a unidirectional path. In the clock chain fiber, the chain direction is determined by the source node and the sink node. The source node and the sink node are ports on the network element device.
[0092] When configuring the clock path for the device in the network for the first time, the clock configuration information is sent to the device to configure the clock of its port so that the port can be connected to the corresponding clock path. When a large number of devices in the network send out clock alarm information, only the faulty port and the clock configuration information of the faulty port can be extracted from the clock alarm information. Since the maintainers of different devices may be different, or the distance between different devices may be far, the maintainer will select the device that can be connected the fastest as the new clock information provider, that is, the previous hop device, in order to improve the efficiency of repairing the clock fault of the device. However, the new clock path selected for the faulty device at this time may not be the best. In addition, due to the lack of global coordination, repairing the clock faults of all devices that send out clock alarm information separately will greatly reduce the efficiency of clock state recovery of the entire network.
[0093] In order to solve the above problems, in the solution of the present invention, after obtaining the clock alarm information sent by each faulty device, the faulty port and the clock configuration information on the faulty port are extracted from each clock alarm information respectively. If the faulty port is used as the host node of a jump link fiber in its clock configuration information, and there is an actual physical link between the jump link fiber and the source node of the jump link fiber, it means that the jump link fiber is a faulty path. The pre-acquired clock topology diagram is searched in combination with the faulty paths corresponding to all clock alarm information, and several clock paths where clock failures occur in the clock topology can be located. On each clock path where a clock failure occurs, the faulty device link on the clock path is from the first faulty device that sends a clock alarm information to the last faulty device that sends a clock alarm information, wherein the first device that sends a clock alarm information is the faulty source device on the path. Subsequently, the clock failure of the downstream device on the faulty device link can be automatically restored after the clock failure of the faulty source device is repaired, thereby greatly improving the clock failure repair efficiency of all devices in the entire network.
[0094] In summary, the fault source device can be quickly located according to the clock alarm information issued by each faulty device, and the clock fault repair efficiency of the downstream faulty device can be improved by repairing the clock fault of the fault source device.
[0095] Furthermore, in one embodiment, the fault repair module 3 is also used to determine whether the clock status of all faulty devices downstream of the faulty source device in the faulty device link has returned to normal after the clock fault of the faulty source device is repaired. If so, the clock alarm information is eliminated. If not, the first faulty device downstream of the faulty source device is used as a new faulty source device, and the clock fault of the new faulty source device is repaired.
[0096] In this embodiment, after the new clock configuration information is sent, the clock state of the fault source device is restored, the clock path of the downstream faulty network element of the fault source device should also be automatically restored, and all fault port alarms still exist. After waiting for a period of time, if the links of multiple network elements are restored at the same time, the alarm is cleared. If not, the downstream device of the fault source device is used as the new fault source device, and the new clock configuration information is sent to the new fault source device to repair its clock fault, ensuring that all clock paths are restored to normal.
[0097] Furthermore, in one embodiment, when the fault repair module 3 performs fault repair on the fault source device, it determines whether there are other paths between the fault source device and its adjacent upstream device in addition to the fault path in the fault device link. If so, a path is selected from the other paths to build a new clock chain fiber between the fault source device and its adjacent upstream device. If not, the minimum ring or shortest chain of the fault source device in the network is calculated, and a new clock chain fiber is built based on the minimum ring or shortest chain.
[0098] In this embodiment, when repairing the clock failure of the fault source device, it is necessary to connect a new clock chain fiber. If there are other physical links between the previous hop device corresponding to the original clock chain fiber and the current device, one of these physical links is preferentially selected to establish a new clock chain fiber. If there are no other physical links, the minimum ring or shortest link of the fault source device in the network is calculated, and a network element device is selected based on the minimum ring or shortest link as the new previous hop device, and a new clock chain fiber is constructed between the previous device and the current device.
[0099] Furthermore, in one embodiment, the fault repair module 3 is also used to repair the clock fault according to the priority order of the fault source devices after obtaining the fault source devices corresponding to the clock alarm information. The priority of the core layer device is higher than the priority of the aggregation layer device, and the priority of the aggregation layer device is higher than the priority of the access layer device.
[0100] In this embodiment, if there are multiple fault source devices to be repaired, the network layers of these devices are first determined before repairing the clock fault. The priorities of the network layers are: core>aggregation>access.
[0101] If multiple fault source devices have the same priority, these devices perform clock fault repair at the same time.
[0102] If multiple fault source devices have different priorities, the clock fault repair is performed on the device with a higher priority first, and then on the device with a lower priority.
[0103] Furthermore, in one embodiment, the fault repair module 3 is further configured to obtain a new clock path after repairing the clock fault of the fault source device, and associate the new clock path with the old clock path.
[0104] Path switching is performed between associated clock paths according to a preset switching strategy.
[0105] In this embodiment, after the clock fault of the fault source device is repaired, the fault source device is connected to a new clock path. If the original clock path returns to normal after the new clock path runs for a period of time, for example, the original faulty port returns to normal or the clock chain fiber connected to the original faulty port returns to normal, then the faulty source device can be reconnected to the original clock path, that is, the current path is switched back to the original path.
[0106] In this embodiment, after the clock fault of the fault source device is repaired, the fault source device is connected to a new clock path. If the original clock path returns to normal after the new clock path runs for a period of time, for example, the original faulty port returns to normal or the clock chain fiber connected to the original faulty port returns to normal, then the faulty source device can be reconnected to the original clock path, that is, the current path is switched back to the original path.
[0107] In a specific embodiment, after the alarm processing module 2 obtains the clock alarm information sent by the faulty device, the fault repair module 3 can choose whether to perform clock fault processing, and there are the following scenarios:
[0108] Scenario 1: No fault processing is performed. The user can set the system to exit directly without performing additional processing when a fault occurs.
[0109] Scenario 2: Perform troubleshooting whenever there is a fault.
[0110] Scenario 3: Fault handling is performed only after both the primary and backup paths fail.
[0111] After the fault repair module 3 repairs the clock faults of all devices, you can choose whether to perform fault recovery processing. There are the following scenarios:
[0112] Scenario 1: No failure recovery is performed.
[0113] Scenario 2: Restore to the original path.
[0114] Scenario 3: Restore to the last normal path.
[0115] Scenario 4: Restore to a normal path.
[0116] When a clock link fails, multiple network elements may generate alarms at the same time. Here, clock failure alarms within a certain period of time are collected and the network element, single disk, port and other information in the alarm are analyzed. Among them, a port of a single disk on the network element is connected to the clock link.
[0117] When the information in the alarm is the input source information of the network element, that is, the sink node information in a chain fiber, the corresponding chain fiber is found according to the input source information, and the source node information of the chain fiber is found. The found source and sink information is used to form the fault path of the alarm.
[0118] Collect a list of all faulty network elements and combine it with the clock topology diagram to build the faulty device link of the faulty network element.
[0119] According to the faulty equipment link, find out the faulty source network element in the link as the network element to be repaired.
[0120] Prioritize the path with the same source as the fault path, that is, in Example 1, there are other paths from NE 1->NE 3 that have not caused any faults, or there are other paths from NE 2->NE 3 that have not caused any faults. If there are, directly select the path as the planning result. If there is no path with the same source, perform incremental planning on the faulty NE. After planning the path, send the configuration to the NE to make the configuration take effect. There are the following scenarios:
[0121] Scenario 1: After the path is planned, it is automatically delivered and the configuration takes effect immediately.
[0122] Scenario 2: After planning the path, save the planned path as a temporary path and send it after manual confirmation.
[0123] After the clock configuration is delivered, the clock status of the faulty NE is restored, but the faulty port alarm still exists. The alarm is cleared when the links of multiple NEs are restored at the same time.
[0124] If the path is planned, save the original path and the changed path and associate them. There are the following scenarios:
[0125] Scenario 1: When no fault recovery is performed, the path is not saved.
[0126] Scenario 2: When restoring to the original path, only the original path is saved as the restored path and associated with the current clock path.
[0127] Scenario 3: When the path that was previously normal is restored, the faulty path is saved as the restored path and associated with the current clock path.
[0128] In summary, the fault and fault recovery method implemented by the present invention can minimize the scope of clock path changes and reduce the impact on the existing network. It can quickly determine the fault path that needs to be repaired and provide a repair plan. After the fault is cleared, it can be restored to the original path.
[0129] Among them, the functional implementation of each module in the above-mentioned clock path processing system based on fault and fault recovery corresponds to the steps in the above-mentioned clock path processing method embodiment based on fault and fault recovery, and its functions and implementation process will not be repeated here one by one.
[0130] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.
[0131] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.
[0132] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.
[0133] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B. "And / or" in the text is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.
[0134] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.
[0135] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.
[0136] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A clock path processing method based on fault and fault recovery, characterized in that: The method comprises: Get the clock topology diagram containing all clock paths in advance; Acquire clock alarm information issued by each faulty device, wherein the clock alarm information includes the faulty port and clock configuration information on the faulty port, wherein the clock configuration information includes information related to a source node and a sink node in a clock chain fiber corresponding to the faulty port; Determine whether the faulty port serves as the sink node of the clock chain fiber and whether there is a physical link between the source and sink nodes in the clock chain fiber. If so, take the clock chain fiber as the fault path, search the clock topology diagram according to the fault path corresponding to each clock alarm information, obtain the faulty device link on each clock path, take the device most upstream in the faulty device link as the faulty source device, and repair the clock fault of the faulty source device; if not, repair the clock fault of the faulty device itself.
2. The clock path processing method based on fault and fault recovery according to claim 1, characterized in that: The method further comprises: After the clock fault of the fault source device is repaired, determine whether the clock status of all faulty devices downstream of the faulty source device in the faulty device link has returned to normal. If so, eliminate the clock alarm information; if not, take the first faulty device downstream of the faulty source device as the new faulty source device, and repair the clock fault of the new faulty source device.
3. The clock path processing method based on fault and fault recovery according to claim 1, characterized in that: The fault repairing of the fault source device specifically comprises the following steps: Determine whether there are other paths besides the fault path between the fault source device and its adjacent upstream device in the fault device link. If so, select a path from the other paths to build a new clock chain fiber between the fault source device and its adjacent upstream device. If not, calculate the minimum ring or shortest chain between the fault source device and its adjacent upstream device in the network, and build a new clock chain fiber between the fault source device and its adjacent upstream device based on the minimum ring or shortest chain.
4. The clock path processing method based on failure and failure recovery according to claim 1, characterized in that: The method further comprises: After obtaining the fault source devices corresponding to each clock alarm information, the clock fault is repaired according to the priority order of the fault source devices; the priority order is that the priority of the core layer device is greater than the priority of the aggregation layer device, and the priority of the aggregation layer device is greater than the priority of the access layer device.
5. The clock path processing method based on failure and failure recovery according to claim 1, characterized in that: The method further comprises: After repairing the clock fault of the fault source device, a new clock path is obtained, and the new clock path is associated with the old clock path; Path switching is performed between associated clock paths according to a preset switching strategy.
6. A clock path processing system based on failure and failure recovery, characterized in that: The system comprises: A data acquisition module, which is used to pre-acquire a clock topology diagram containing all clock paths; An alarm processing module, which is used to obtain clock alarm information sent by each faulty device, wherein the clock alarm information includes the faulty port and the clock configuration information on the faulty port, wherein the clock configuration information includes information related to the source node and the sink node in the clock chain fiber corresponding to the faulty port; A fault repair module is used to determine whether the faulty port serves as a sink node of a clock chain fiber and whether there is a physical link between the source and sink nodes in the clock chain fiber. If so, the clock chain fiber is used as a fault path, and the clock topology diagram is searched according to the fault paths corresponding to each clock alarm information to obtain the faulty device links on each clock path. The device most upstream in the faulty device link is used as the faulty source device, and the clock fault of the faulty source device is repaired; if not, the clock fault of the faulty device itself is repaired.
7. The clock path processing system based on failure and failure recovery as claimed in claim 6, characterized in that: The fault repair module is also used to determine whether the clock status of all faulty devices downstream of the faulty source device in the faulty device link has returned to normal after the clock fault of the faulty source device has been repaired. If so, the clock alarm information is eliminated; if not, the first faulty device downstream of the faulty source device is used as the new faulty source device, and the clock fault of the new faulty source device is repaired.
8. The clock path processing system based on failure and failure recovery as claimed in claim 6, characterized in that: When repairing the fault source device, the fault repair module determines whether there are other paths between the fault source device and its adjacent upstream device in addition to the fault path in the fault device link. If so, a path is selected from the other paths to build a new clock chain fiber between the fault source device and its adjacent upstream device; if not, the minimum ring or shortest chain of the fault source device in the network is calculated, and a new clock chain fiber is built based on the minimum ring or shortest chain.
9. The clock path processing system based on failure and failure recovery as claimed in claim 6, characterized in that: The fault repair module is also used to repair clock faults according to the priority order of the fault source devices after obtaining the fault source devices corresponding to each clock alarm information; the priority of the core layer device is greater than the priority of the aggregation layer device, and the priority of the aggregation layer device is greater than the priority of the access layer device.
10. The clock path processing system based on failure and failure recovery as claimed in claim 6, characterized in that: The fault repair module is also used to obtain a new clock path after repairing the clock fault of the fault source device, and associate the new clock path with the old clock path; Path switching is performed between associated clock paths according to a preset switching strategy.