Serial communication circuit capable of automatically allocating addresses and communication equipment

Abstract

The invention is applicable to the technical field of communication, and provides a serial communication circuit and communication equipment capable of automatically allocating addresses, comprising a host circuit, a serial expansion circuit, a serial communication interface circuit and a slave circuit, the host circuit is electrically connected with the serial expansion circuit, the serial expansion circuit is electrically connected with the serial communication interface circuit, and the slave circuit is electrically connected with the serial communication interface circuit. The serial communication interface circuit is electrically connected with the slave circuit; the host circuit generates a communication signal and an address signal, the communication signal communicates with a slave after passing through the serial port expansion circuit and the serial port communication interface circuit, and the address signal is used for controlling the serial port expansion circuit to allocate a slave communication address; the serial port expansion circuit is used for carrying out slave communication address automatic allocation on communication between the host and the slave through a time division multiplexing polling mode; the serial communication interface circuit comprises at least one serial communication interface; the slave circuit comprises at least one slave, and the slave is electrically connected with the serial communication interface. The communication efficiency between the master and the slave can be improved.

Description

Technical Field

[0001] The invention belongs to the field of communication technology, and in particular relates to a serial communication circuit and communication equipment for automatically allocating addresses. Background Art

[0002] The existing master-slave communication method generally adopts a one-master-multiple-slave mode for serial communication. The main method of slave communication address allocation in the existing technology is to connect multiple slaves in series, control them one level at a time, and allocate addresses one by one. The master-slave structure is complex, slow, and inefficient. Moreover, the address is directly configured through the IO port of the MCU inside the slave, and the configuration of each slave is different. The slave hardware may not be unified and prone to errors, resulting in the communication port being unable to communicate. In addition, the method of using software to compete for addresses may fail. As a result, the communication speed of the existing master-slave communication method becomes slow, the communication reliability is low, and other problems, which in turn affects the communication efficiency of the existing master-slave communication method. Summary of the invention

[0003] In view of the problem of low communication efficiency between master and slave machines in the prior art, the embodiment of the present application provides a serial communication circuit with automatic address allocation, aiming to improve the communication efficiency between master and slave machines in the prior art.

[0004] According to one aspect of an embodiment of the present application, the present application provides a serial port communication circuit for automatically assigning addresses, comprising: a host circuit, a serial port expansion circuit, a serial port communication interface circuit, and a slave circuit, wherein the host circuit is electrically connected to the serial port expansion circuit, the serial port expansion circuit is electrically connected to the serial port communication interface circuit, and the serial port communication interface circuit is electrically connected to the slave circuit;

[0005] The host circuit is used to generate a communication signal and an address signal, wherein the communication signal is used to realize the communication between the host circuit and the slave after passing through the serial port expansion circuit and the serial port communication interface circuit, and the address signal is used to control the serial port expansion circuit to allocate a slave communication address;

[0006] The serial port expansion circuit is used to automatically allocate the communication address of the slave machine through the round-robin mode of time-division multiplexing for the communication between the host machine and the slave machine;

[0007] The serial communication interface circuit includes at least one serial communication interface;

[0008] The slave circuit includes at least one slave, and the slave is electrically connected to the serial communication interface.

[0009] Furthermore, the serial port expansion circuit includes: a sending module and a receiving module, the sending module is electrically connected to the host circuit and the serial port communication interface circuit respectively, and the receiving module is electrically connected to the host circuit and the serial port communication interface circuit respectively.

[0010] Furthermore, the sending module includes: a first decoder and a first OR gate unit, the first decoder is electrically connected to the host circuit and the first OR gate unit respectively, and the first OR gate unit is also electrically connected to the host circuit and the serial communication interface circuit respectively.

[0011] Furthermore, the sending module further includes: a first AND gate unit, wherein the first AND gate unit is electrically connected to the host circuit, the first decoder and the first OR gate unit respectively.

[0012] Furthermore, the receiving module includes a signal receiving chip, and the signal receiving chip is electrically connected to the host circuit and the serial communication interface circuit respectively.

[0013] Furthermore, the serial port expansion circuit includes: a second decoder and an analog switch, the second decoder is electrically connected to the host circuit and the analog switch respectively, and the analog switch is also electrically connected to the host circuit and the serial port communication interface circuit respectively.

[0014] Furthermore, the serial port expansion circuit includes an FPGA chip or a CPLD chip and a field programmable logic device, and the field programmable logic device is communicatively connected with the FPGA chip or the CPLD chip.

[0015] Furthermore, the serial communication interface circuit includes any one of an RS232 chip, an RS485 chip and an RS422 chip.

[0016] Furthermore, when the serial communication interface circuit is the RS485 chip, the serial communication circuit for automatically assigning addresses further comprises: an RS485 chip sending control circuit and an RS485 chip receiving control circuit, wherein the RS485 chip sending control circuit comprises a third decoder and a second AND gate unit, wherein the third decoder is electrically connected to the host circuit and the second AND gate unit respectively, and the second AND gate unit is also electrically connected to the host circuit and the RS485 chip respectively;

[0017] Alternatively, the RS485 chip transmission control circuit includes a third AND gate unit, and the third AND gate unit is electrically connected to the host circuit, the third decoder and the second AND gate unit respectively;

[0018] The RS485 chip receiving control circuit comprises a fourth decoder and a second OR gate unit. The fourth decoder is electrically connected to the host circuit and the second OR gate unit respectively. The second OR gate unit is also electrically connected to the RS485 chip.

[0019] According to another aspect of the embodiments of the present application, the present application provides a communication device, which communicates based on the serial port communication circuit that automatically allocates addresses.

[0020] The beneficial effect achieved by the present invention is that the communication address of the slave machine is automatically allocated directly on the host machine through the host circuit, the circuit is simple, and at the same time, the high-speed communication is maintained in the time-sharing multiplexing round-robin mode through the serial port expansion circuit, and the interface serial port in the serial port communication interface circuit connected to each slave machine in the slave circuit can be flexibly configured to ensure the reliability of communication and improve the communication speed, thereby improving the communication efficiency between the master and slave machines. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technology descriptions are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can also be obtained based on these drawings without paying creative labor.

[0022] Figure 1 is a schematic diagram of a serial communication circuit for automatically allocating addresses provided in an embodiment of the present application;

[0023] Figure 2 It is a specific circuit diagram of a sending module of an optional serial port expansion circuit in an embodiment of the present application;

[0024] Figure 3 It is a specific circuit diagram of a receiving module of an optional serial port expansion circuit in an embodiment of the present application;

[0025] Figure 4 is a circuit diagram of another optional serial port expansion circuit in an embodiment of the present application;

[0026] Figure 5 Schematic diagram of the pin layout of an optional RS485 chip provided in an embodiment of the present application;

[0027] Figure 6 It is a specific circuit diagram of an optional RS485 chip sending control circuit provided in an embodiment of the present application;

[0028] Figure 7 It is a specific circuit diagram of an optional RS485 chip receiving control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0030] The present application automatically allocates the slave communication address directly on the host through the host circuit, and the circuit is simple. At the same time, the serial port expansion circuit maintains high-speed communication in the time-sharing multiplexing round-robin mode, and the interface serial port in the serial communication interface circuit connected to each slave in the slave circuit can be flexibly configured to ensure the reliability of communication and improve the communication speed, thereby improving the communication efficiency between the master and slave machines.

[0031] Embodiment 1

[0032] Combination Figure 1 As shown, Figure 1 The schematic diagram of the serial communication circuit for automatically assigning addresses provided in the embodiment of the present application is shown. The serial communication circuit for automatically assigning addresses provided in the embodiment includes a host circuit 1, a serial port expansion circuit 2, a serial communication interface circuit 3 and a slave circuit 4, wherein the host circuit 1 is electrically connected to the serial port expansion circuit 2, the serial port expansion circuit 2 is electrically connected to the serial communication interface circuit 3, and the serial communication interface circuit 3 is electrically connected to the slave circuit 4;

[0033] The host circuit 1 is used to generate a communication signal and an address signal. The communication signal is used to realize the communication between the host circuit 1 and the slave after passing through the serial port expansion circuit 2 and the serial port communication interface circuit 3. The address signal is used to control the serial port expansion circuit 2 to allocate the slave communication address.

[0034] The serial port expansion circuit 2 is used to automatically allocate the communication address of the slave through the round-robin mode of time-division multiplexing for the communication between the host and the slave;

[0035] The serial communication interface circuit 3 includes at least one serial communication interface;

[0036] The slave circuit 4 includes at least one slave, and the slave is electrically connected to the serial communication interface.

[0037] In this embodiment, the host circuit 1 can be used as the host MCU (Micro Control Unit), as the main control circuit of the entire serial communication circuit for automatically assigning addresses, and mainly provides a serial communication interface. The host circuit 1 can be used to generate communication signals and address signals, wherein the communication signal is used to realize the communication between the host circuit 1 and the slave after passing through the serial port expansion circuit 2, and the address signal is used to control the serial port expansion circuit 2 to assign the slave communication address. Among them, the address signal includes a first address signal A0~A5 sent through the first address interface and a second address signal B0 sent through the second address interface. The first address signals A0~A5 sent by the host circuit 1 correspond to the communication addresses of each slave, thereby realizing the automatic assignment of the slave communication address. The second address interface is a super address line, which is used to send a super address signal B0, wherein the super address signal B0 is used for address mode selection, and the address mode includes a one-to-one address mode and a one-to-many address mode.

[0038] In this embodiment, the serial port expansion circuit 2, by constructing a circuit system, automatically allocates the slave communication address through a time-division multiplexing round-robin mode for communication between the host and the slave, thereby realizing normal communication functions. The serial port expansion circuit 2 is electrically connected to the serial communication interface of the communication host circuit 1, and is used to connect the communication signal of the host circuit 1, wherein the communication signal includes a sending signal MCU_TXD and a receiving signal MCU_RXD, and the serial communication interface includes a sending interface and a receiving interface, the sending interface is used to send the above-mentioned sending signal MCU_TXD, and the receiving interface is used to receive the above-mentioned receiving signal MCU_RXD.

[0039] Furthermore, the serial port expansion circuit 2 is also electrically connected to the address interface of the host circuit 1 for transmitting the address signal of the slave, wherein the address interface includes a first address interface and a second address interface, the first address interface is used to send the first address signal of each slave, and the second address interface is used to send the second address signal.

[0040] Furthermore, the serial port expansion circuit 2 controls the host MCU's sending signal MCU_TXD and receiving signal MCU_RXD to connect to a pair of signals in the sending data TXD1~TXDn and receiving data RXD1~RXDn outputted by the host MCU through the first address signal A0~A5 and the second address signal B0, so as to realize the function of communicating with the corresponding slave. The sending data TXD1~TXDn corresponds to the receiving data RXD1~RXDn to control n slaves, for example, the sending data TXD1 and the receiving data RXD1 correspond to control the first slave, the sending data TXD2 and the receiving data RXD2 correspond to control the second slave, and so on, the sending data TXDn and the receiving data RXDn correspond to control the nth slave. The number of slaves can be configured according to actual needs, and the corresponding number of sending data TXD and receiving data RXD is also set accordingly.

[0041] In the present embodiment, the serial communication interface circuit 3 is connected to the receiving interface and the sending interface of the serial port expansion circuit 2, and data is sent based on the receiving interface and data is received based on the receiving interface. Specifically, the serial communication interface circuit 3 includes at least one serial communication interface, and the serial communication interface circuit 3 can be freely configured according to actual needs, and can be configured as an RS232 chip, an RS485 chip, an RS422 chip, etc., and can be made isolated or not isolated. The communication process can realize full-duplex or half-duplex communication according to the actual configured circuit. The number of serial communication interfaces can be configured according to actual needs to ensure that each slave can have a serial communication interface connection.

[0042] In this embodiment, each slave in the slave circuit 4 is electrically connected to the serial communication interface in the serial communication interface circuit 3 to communicate with each slave. The slave circuit 4 includes at least one slave, which is a communication object of the host. The number of slaves can be selected according to actual needs. The slave is electrically connected to the serial communication interface.

[0043] It should be noted that the host circuit 1 , the serial port expansion circuit 2 , the serial port communication interface circuit 3 and the slave circuit 4 are all electrically connected to the power circuit to provide power for each circuit.

[0044] In an embodiment of the present invention, the slave communication address is automatically allocated directly on the host through the host circuit 1, the circuit is simple, and at the same time, the serial port expansion circuit 2 maintains high-speed communication in the time-sharing multiplexing round-robin mode, and the interface serial port in the serial communication interface circuit 3 connected to each slave in the slave circuit 4 can be flexibly configured to ensure the reliability of communication and improve the communication speed, thereby improving the communication efficiency between the master and the slave.

[0045] Example 2

[0046] In this embodiment, the serial port expansion circuit 2 includes: a sending module and a receiving module, the sending module is electrically connected to the host circuit 1 and the serial port communication interface circuit 3 respectively, and the receiving module is electrically connected to the host circuit 1 and the serial port communication interface circuit 3 respectively.

[0047] Specifically, the sending module sends the sending signal to the serial communication interface circuit 3, and the receiving module receives the data sent by the slave to the serial communication interface circuit 3 and then sent to the serial port expansion circuit 2, thereby realizing the communication between the master and the slave. Only by using the sending module and the receiving module, high-speed communication can be maintained with each slave in the round-robin mode of time-division multiplexing, which not only makes the circuit simpler, but also makes the communication data faster, which is conducive to improving the communication reliability and efficiency between the master and the slave.

[0048] Example 3

[0049] In this embodiment, the sending module includes: a first decoder and a first OR gate unit, the first decoder is electrically connected to the host circuit 1 and the first OR gate unit respectively, and the first OR gate unit is electrically connected to the host circuit 1 and the serial communication interface circuit 3 respectively.

[0050] In this embodiment, the first decoder can be a 38 decoder, including a 74HC138 chip, a 74LVC138 chip, a 74HCT138 chip, etc., which can be selected according to actual conditions. The first OR gate unit can be a 74HC32 chip. Specifically, the first decoder is electrically connected to the first address interface of the host circuit 1, and is used to receive the first address signal sent by the host MCU. The output serial port of the first decoder is correspondingly connected to the OR gate of the first OR gate unit; the first OR gate unit is electrically connected to the second address interface of the host MCU, and is used to receive the second address signal B0 of the host MCU; the first OR gate unit is also electrically connected to the sending interface of the host MCU, and is used to send the sending signal of the host MCU; the first OR gate unit can provide multiple serial ports to connect with the serial communication interface circuit 3.

[0051] In this embodiment, the number of the first decoder and the first OR gate unit in the sending module can be configured according to actual needs. If there are more slaves that need to communicate, the number of configured first decoders and first OR gate units will also increase, so that it can communicate with more slaves and improve the communication efficiency between the master and slaves.

[0052] Example 4

[0053] Combination Figure 2 As shown, in this embodiment, the sending module further includes: a first AND gate unit, and the first AND gate unit is electrically connected to the host circuit 1, the first decoder and the first OR gate unit respectively.

[0054] The first AND gate unit is electrically connected to the second address interface of the host MCU; the AND gate of the first AND gate unit is correspondingly connected to the OR gate in the first OR gate unit. The first AND gate unit can be a 74HC08 chip, and the first AND gate unit is optional in the serial port expansion circuit 2.

[0055] In this embodiment, when the second address signal B0=0, all the AND gate outputs of the first AND gate unit are 0, all the OR gates in the first OR gate unit of the subsequent stage are opened, and the host MCU can send signals to all slaves, realizing a one-to-many mode and a broadcast function. When the second address signal B0 is 1, or the optional first AND gate unit is not installed, the first decoder may have only one output of 0 at a certain moment, so only one AND gate in the first OR gate unit of the subsequent stage can be opened, and the host MCU can only send signals to one slave and can only communicate with one slave, realizing a one-to-one mode.

[0056] Combination Figure 2 As shown, Figure 2 A specific circuit diagram of 16 slave interfaces is provided for the sending module of the serial port expansion circuit. In actual application, it can be increased or decreased according to the on-site situation. When only 8 interfaces are needed, part of the circuit of U6~U10 can be deleted; when more than 16 interfaces are needed, it can be expanded by adding a first decoder to control the first address signal A0~A5 to determine the address of the slave. In terms of software, the address status of the first address signal A0~A5 can be sent to the serial port communication interface circuit 3 in the communication protocol, and then sent to the corresponding slave, so that the slave can obtain its own address, which is convenient for product maintenance, can improve the reliability of the communication circuit, and can increase the communication speed, thereby improving the communication efficiency.

[0057] In this embodiment, the communication mode between the master and slave machines can be flexibly switched by setting the first AND gate unit. When only one-to-one communication control is required, the one-to-one mode can be selected to ensure data reliability and communication speed, thereby improving the one-to-one communication efficiency. When one-to-many communication control is required, the one-to-many mode can also be selected to communicate with multiple slave machines at the same time to achieve data transmission, thereby improving the one-to-many communication efficiency.

[0058] Example 5

[0059] Combination Figure 3 As shown, in this embodiment, the receiving module includes a signal receiving chip, and the signal receiving chip is electrically connected to the host circuit 1 and the serial communication interface circuit 3 respectively.

[0060] The signal receiving chip can be an eight-choice chip, which includes a 74HC151 chip, and the eight-choice chip is electrically connected to the first address interface and the transmission interface of the host MCU. Specifically, the receiving module uses the 74HC151 chip in the eight-choice chip to build a circuit, each 74HC151 chip can generate 8 signals from the serial port of the slave in a round-robin manner, and the first address signals A0-A2 generate the first level of channel selection.

[0061] In some possible embodiments, combined with Figure 3 As shown, Figure 3 This is a specific circuit diagram of the receiving module of the serial port expansion circuit in the embodiment of the present invention providing 16 slaves. If 16 slaves are needed, three 74HC151 chips can be used to form a cascade solution; if nine 74HC151 chips are used to form a cascade solution, there will be 64 slave serial ports when fully equipped, and the on-site use can be configured according to actual needs.

[0062] In this embodiment, the receiving module adopts an eight-to-one chip to adapt to the situation of multiple slaves. When the number of slaves is large, the number of eight-to-one chips can be increased to meet the needs of each slave. At the same time, the eight-to-one chip circuit is easy to install and occupies a small space. At the same time, the communication speed is improved in hardware, thereby improving the communication efficiency between the master and slaves.

[0063] Example 6

[0064] Combination Figure 4 As shown, in this embodiment, the serial port expansion circuit 2 includes: a second decoder and an analog switch, the second decoder is electrically connected to the host circuit 1 and the analog switch respectively, and the analog switch is electrically connected to the host circuit 1 and the serial port communication interface circuit 3 respectively.

[0065] The second decoder is electrically connected to the first address interface of the host MCU, and the analog switch is electrically connected to the sending interface, the receiving interface and the first address interface of the host MCU respectively. An output serial port of the second decoder is electrically connected to an analog switch. The second decoder can be a 38 decoder, and can also include a 74HC138 chip, a 74LVC138 chip, a 74HCT138 chip, etc. The specific use can be selected according to the actual situation.

[0066] The analog switch may be a 74CBTLV3251 chip or a 74HC4051 chip. Specifically, since the analog switch is in a high impedance state when the channel is not selected, the output of the analog switch can be directly connected in parallel. In some examples, the analog switch may select a 74CBTLV3251 chip with a small on-resistance and a fast switching speed to meet the requirements of high-speed switching. In practical applications, the analog switch may also select a chip such as 74HC4051.

[0067] Combination Figure 4 As shown, Figure 4 This is another circuit diagram of supporting 16 slaves provided by the serial port expansion circuit in the embodiment of the present application. The second decoder takes the 74HC138 chip as an example, and the analog switch takes the 74CBTLV3251 chip as an example. If only 8 or less slaves are needed, there is no need to use the 74HC138 chip to increase the address lines, and the first address lines A0-A2 of the host MCU can be directly used for control. One 74HC138 chip can generate 8 address control signals, and each address control signal can expand the serial port of 8 slaves. In this way, one 74HC138 chip can generate up to 64 slave interfaces. Of course, if more slave interfaces are needed, the number of second decoders and the number of analog switches can be increased.

[0068] In this embodiment, the serial port expansion circuit 2 adopts the structure of the second decoder and the analog switch, which can further improve the communication reliability and communication efficiency from the hardware perspective.

[0069] Example 7

[0070] In this embodiment, the serial port expansion circuit 2 includes an FPGA chip or a CPLD chip and a field programmable logic device, and the field programmable logic device is communicatively connected with the FPGA chip or the CPLD chip.

[0071] Among them, the serial port expansion circuit 2 includes an FPGA (Field Programmable Gate Array) chip or a CPLD (Complex Programmable logic device) chip and a field programmable logic device. The FPGA chip or CPLD and the field programmable logic device are used, and the circuit can be implemented with the field programmable logic device, with consistent functions and effects, and can save the loss of circuit hardware. At the same time, the serial port expansion situation can be flexibly modified and maintained by programming, so that the hardware circuit of the serial port expansion circuit 2 is simple and stable, thereby improving the stability of the entire serial port communication circuit that automatically allocates addresses, and further improving the communication reliability and communication efficiency between the master and slave machines.

[0072] Example 8

[0073] like Figure 5-Figure 7As shown, in this embodiment, when the serial communication interface circuit 3 is an RS485 chip, the serial communication circuit for automatically assigning addresses also includes: an RS485 chip sending control circuit and an RS485 chip receiving control circuit, the RS485 chip sending control circuit includes a third decoder and a second AND gate unit, the third decoder is electrically connected to the host circuit 1 and the second AND gate unit, respectively, and the second AND gate unit is electrically connected to the host circuit 1 and the RS485 chip, respectively;

[0074] Alternatively, the RS485 chip sending control circuit includes a third AND gate unit, which is electrically connected to the host circuit 1, the third decoder and the second AND gate unit respectively; the RS485 chip receiving control circuit includes a fourth decoder and a second OR gate unit, which is electrically connected to the host circuit 1 and the second OR gate unit respectively, and the second OR gate unit is also electrically connected to the RS485 chip.

[0075] Specifically, the third decoder is electrically connected to the first address interface of the host MCU, the output serial port of the third decoder is electrically connected to the AND gate corresponding to the second AND gate unit, and the second AND gate unit is electrically connected to the second address interface and the communication address RTS of the host MCU. The fourth decoder is electrically connected to the first address interface of the host MCU, the serial ports generated by the fourth decoder are connected to each OR gate of the second OR gate unit, and the second OR gate unit is electrically connected to the communication address RTS of the host MCU; the output serial port of the fourth decoder is electrically connected to the AND gate corresponding to the third AND gate unit. Among them, the AND gate of the second AND gate unit is connected to the AND gate of the third AND gate unit.

[0076] The third decoder and the fourth decoder can also be 38 decoders, including 74HC138 chip, 74LVC138 chip, 74HCT138 chip, etc., which can be selected according to actual conditions. The second and third AND gate units can be 74HC08 chips, and the second OR gate unit can be 74HC32 chips.

[0077] In this embodiment, when the serial communication interface circuit 3 is an RS485 chip, it is equivalent to that the serial port expansion circuit 2 needs to be used for RS485 chip output. In this regard, the serial communication circuit with automatic address allocation needs to add an RS485 chip sending control circuit and an RS485 chip receiving control circuit to provide a sending and receiving control signal for the RS485 chip.

[0078] like Figure 5-Figure 7 As shown, Figure 5 Provides a pin layout diagram of an optional RS485 chip. Figure 6 Provides a specific circuit diagram of an optional RS485 chip transmission control circuit. Figure 7A specific circuit diagram of an optional RS485 chip receiving control circuit is provided. Specifically, for a single RS485 chip receiving and transmitting control, nRE and DE can be connected together and controlled by an RTS signal. If multiple RS485 chip circuits are extended, multiple nRE and DE need to be uniformly controlled, otherwise they will interfere with each other. For the receiving control of the RS485 chip, only one channel can be valid at a time; for the sending control circuit of the RS485 chip outside the broadcast mode, only one channel can be valid.

[0079] In this embodiment, when the serial communication interface circuit 3 is an RS485 chip, the serial communication circuit that automatically assigns an address adds a transceiver control signal circuit, including an RS485 chip sending control circuit and an RS485 chip receiving control circuit, thereby being able to adapt to the serial communication interface of the RS485 chip, ensuring the communication accuracy and reliability with the corresponding slave machine, and further improving the communication efficiency between the master and slave machines.

[0080] Example 9

[0081] In this embodiment, a communication device is further provided, and the communication device communicates based on the serial communication circuit with automatic address allocation in the above embodiment.

[0082] In this embodiment, the communication device provided can be a single device in the communication process, or a combined device composed of a full communication link. The communication device can include a serial communication circuit that automatically assigns addresses, and the communication between the host and the slave is realized through the serial communication circuit that automatically assigns addresses. Among them, the serial communication circuit that automatically assigns addresses automatically assigns the slave communication address directly on the host through the host circuit 1, and the circuit is simple. At the same time, the serial port expansion circuit 2 maintains high-speed communication in the time-sharing multiplexing round-robin mode, and the interface serial port in the serial communication interface circuit 3 of each slave in the slave circuit 4 can be flexibly configured to ensure the reliability of communication, and improve the communication speed, thereby improving the communication efficiency between the master and the slave. Therefore, the communication device provided by the present application can also realize the above-mentioned embodiments and achieve the corresponding technical effects, which will not be repeated here.

[0083] The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. The reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0084] It is understandable that those skilled in the art can, under the guidance of the above embodiments, combine various implementation methods in the above embodiments to obtain technical solutions of multiple implementation methods.

[0085] The above is only a preferred specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features applied for herein, and any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A serial communication circuit for automatically allocating addresses, characterized in that: include: A host circuit, a serial port expansion circuit, a serial port communication interface circuit and a slave circuit, wherein the host circuit is electrically connected to the serial port expansion circuit, the serial port expansion circuit is electrically connected to the serial port communication interface circuit, and the serial port communication interface circuit is electrically connected to the slave circuit; / the host circuit is used to generate a communication signal and an address signal, wherein the communication signal is used to realize the communication between the host circuit and the slave after passing through the serial port expansion circuit and the serial port communication interface circuit, and the address signal is used to control the serial port expansion circuit to allocate a slave communication address; The serial port expansion circuit is used to automatically allocate the communication address of the slave machine through the round-robin mode of time-division multiplexing for the communication between the host machine and the slave machine; The serial communication interface circuit includes at least one serial communication interface; The slave circuit includes at least one slave, and the slave is electrically connected to the serial communication interface.

2. The serial communication circuit for automatically assigning addresses according to claim 1, characterized in that: The serial port expansion circuit includes: a sending module and a receiving module, the sending module is electrically connected to the host circuit and the serial port communication interface circuit respectively, and the receiving module is electrically connected to the host circuit and the serial port communication interface circuit respectively.

3. The serial communication circuit for automatically assigning addresses as claimed in claim 2, characterized in that: The sending module includes: a first decoder and a first OR gate unit, the first decoder is electrically connected to the host circuit and the first OR gate unit respectively, and the first OR gate unit is also electrically connected to the host circuit and the serial communication interface circuit respectively.

4. The serial communication circuit for automatically assigning addresses as claimed in claim 3, characterized in that: The sending module further includes: a first AND gate unit, wherein the first AND gate unit is electrically connected to the host circuit, the first decoder and the first OR gate unit respectively.

5. The serial communication circuit for automatically allocating addresses according to any one of claims 2 to 4, characterized in that: The receiving module includes a signal receiving chip, and the signal receiving chip is electrically connected to the host circuit and the serial communication interface circuit respectively.

6. The serial communication circuit for automatically assigning addresses according to claim 1, characterized in that: The serial port expansion circuit includes: a second decoder and an analog switch, the second decoder is electrically connected to the host circuit and the analog switch respectively, and the analog switch is also electrically connected to the host circuit and the serial port communication interface circuit respectively.

7. The serial communication circuit for automatically assigning addresses according to claim 1, characterized in that: The serial port expansion circuit comprises an FPGA chip or a CPLD chip and a field programmable logic device, and the field programmable logic device is communicatively connected with the FPGA chip or the CPLD chip.

8. The serial communication circuit for automatically assigning addresses according to claim 1, characterized in that: The serial communication interface circuit includes any one of an RS232 chip, an RS485 chip and an RS422 chip.

9. The serial communication circuit for automatically assigning addresses as claimed in claim 8, characterized in that: When the serial communication interface circuit is the RS485 chip, the serial communication circuit for automatically assigning addresses further comprises: an RS485 chip sending control circuit and an RS485 chip receiving control circuit; The RS485 chip transmission control circuit includes a third decoder and a second AND gate unit, wherein the third decoder is electrically connected to the host circuit and the second AND gate unit respectively, and the second AND gate unit is also electrically connected to the host circuit and the RS485 chip respectively; Alternatively, the RS485 chip transmission control circuit includes a third AND gate unit, and the third AND gate unit is electrically connected to the host circuit, the third decoder and the second AND gate unit respectively; The RS485 chip receiving control circuit comprises a fourth decoder and a second OR gate unit. The fourth decoder is electrically connected to the host circuit and the second OR gate unit respectively. The second OR gate unit is also electrically connected to the RS485 chip.

10. A communication device, characterized in that: The communication device communicates based on the serial communication circuit for automatically assigning addresses according to any one of claims 1 to 9.

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