Semiconductor device including bit line

Abstract

A semiconductor device including bit lines is provided. The semiconductor device includes: a substrate including a first active region; a bit line on the substrate across the first active region; a bit line contact between the bit line and the first active region and in a bit line contact hole, the bit line contact hole extending into the substrate; a bit line contact spacer on a sidewall of the bit line contact within the bit line contact hole; bit line spacers on sidewalls of the bit lines; an anti-oxidation layer between a sidewall of the bit line and the bit line spacer and between a sidewall of the bit line contact and the bit line spacer; and a buried contact in the buried contact hole, contacting the spacer through the bit line, and contacting the first active region, where the anti-oxidation layer includes a silicon-containing material, the silicon-containing material including SiOx, where 0 lt; x < = 2.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0149279 filed on November 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a bit line. Background Art

[0003] As semiconductor devices continue to shrink, the size of individual microcircuit patterns used to implement semiconductor devices is further reduced. In addition, as integrated circuit devices become highly integrated, the line width of bit lines decreases, and the spacing between bit lines also decreases. Therefore, the process for forming contacts between bit lines becomes increasingly complex and difficult. In addition, it is a challenge to maintain low resistance for bit lines with reduced line width and / or to provide good electrical connections between components for contacts formed with small spacing between bit lines. Summary of the invention

[0004] The inventive concept provides a semiconductor device capable of reducing the difficulty of a process of forming a contact between bit lines.

[0005] According to an embodiment of the inventive concept, there is provided a semiconductor device, comprising: a substrate, comprising a first active region; a bit line, arranged on the substrate, crossing the first active region, and extending in a first direction parallel to a top surface of the substrate; a bit line contact, arranged between the bit line and the first active region, and arranged in a bit line contact hole, the bit line contact hole extending into the substrate; a bit line contact spacer, arranged on a sidewall of the bit line contact in the bit line contact hole; a bit line spacer, arranged on a sidewall of the bit line; an anti-oxidation layer, arranged between the sidewall of the bit line and the bit line spacer and between the sidewall of the bit line contact and the bit line spacer; and a buried contact, arranged in the buried contact hole, passing through the bit line contact spacer, and contacting the first active region, wherein the anti-oxidation layer comprises a silicon-containing material, and the silicon-containing material comprises SiO x , where 0 <X≤2。

[0006] According to an embodiment of the inventive concept, a semiconductor device is provided, including: a substrate including a plurality of first active regions; a plurality of bit lines placed on the substrate, spanning the plurality of first active regions, and extending in a first direction parallel to the top surface of the substrate; a bit line contact disposed between a first bit line among the plurality of bit lines and a first active region among the plurality of first active regions, the first active region corresponding to the first bit line, and the bit line contact being disposed within a bit line contact hole extending into the substrate; an antioxidant layer including a first portion disposed on a sidewall of the first bit line and a second portion disposed on an inner wall of the bit line contact hole; a bit line contact spacer disposed on the second portion of the antioxidant layer and filling the bit line contact hole; and a buried contact disposed between the first bit line and a second bit line among the plurality of bit lines, the second bit line being adjacent to the first bit line, the buried contact being disposed within a buried contact hole passing through the bit line contact spacer and the second portion of the antioxidant layer and contacting the first active region, wherein the antioxidant layer includes a silicon-containing material, and the silicon-containing material includes SiO x , where 0 < X ≤ 2.

[0007] According to an embodiment of the inventive concept, a semiconductor device is provided, including: a substrate including a plurality of first active regions; a plurality of bit lines placed on the substrate, spanning the plurality of first active regions, and extending in a first direction parallel to the top surface of the substrate; a bit line contact disposed between a first bit line among the plurality of bit lines and a first active region among the plurality of first active regions, the first active region corresponding to the first bit line, and the bit line contact being disposed within a bit line contact hole extending into the substrate; an antioxidant layer including a first portion disposed on a sidewall of the first bit line and a second portion disposed on an inner wall of the bit line contact hole; a bit line contact spacer disposed on the second portion of the antioxidant layer and filling the bit line contact hole; a buried contact disposed between the first bit line and a second bit line among the plurality of bit lines, the second bit line being adjacent to the first bit line, the buried contact being disposed within a buried contact hole passing through the bit line contact spacer and the second portion of the antioxidant layer and contacting the first active region; a bit line spacer disposed on a sidewall of the first bit line, the bit line spacer including a first spacer layer and a second spacer layer, the first spacer layer being disposed on a sidewall of the first portion of the antioxidant layer and including silicon oxide, and the second spacer layer being disposed on a sidewall of the first spacer layer and including silicon nitride; and a landing pad disposed on the buried contact, wherein the antioxidant layer includes a silicon-containing material, and the silicon-containing material contains SiO x , where 0 < x ≤ 2, and the first portion of the antioxidant layer includes silicon oxide (SiO2). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a layout diagram showing a semiconductor device according to an embodiment of the inventive concept;

[0010] Figure 2 yes Figure 1 An enlarged layout diagram of Part II;

[0011] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA';

[0012] Figure 4 It is along Figure 2 A cross-sectional view taken along line BB';

[0013] Figure 5 It is along Figure 2 A cross-sectional view taken along line CC';

[0014] Figure 6 yes Figure 3 A magnified view of a portion of CX1;

[0015] Figure 7 and Figure 8 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept;

[0016] Fig. 9 and Fig.10 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept; and

[0017] Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Figures 15 to 21 , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A and Fig. 24B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept, wherein: Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Figures 15 to 21 , Fig.22A , Fig.23A and Fig.24A is along with Figure 2The cross-sectional view corresponds to the cross-sectional view taken along the line AA', and Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 22B , Fig. 23B and Fig. 24B is along with Figure 2 The cross-sectional view corresponds to the cross-sectional view taken along the line BB'.

[0018] because Figures 1 to 24B The drawings in the drawings are intended for illustrative purposes, and therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for the purpose of clarity. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 is a layout diagram illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 2 yes Figure 1 An enlarged layout diagram of part II. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 It is along Figure 2 A cross-sectional view taken along line BB'. Figure 5 It is along Figure 2 A cross-sectional view taken along line CC'. Figure 6 yes Figure 3 An enlarged view of a portion of CX1.

[0021] Reference Figures 1 to 6 , the semiconductor device 100 may include a substrate 110 including a cell array area MCA and a peripheral circuit area PCA. Each of the cell array areas MCA may be a memory cell area of ​​a dynamic random access memory (DRAM) device, and each of the peripheral circuit areas PCA may be a core area or a peripheral circuit area of ​​the DRAM device. For example, each of the cell array areas MCA may include a cell transistor and a capacitor structure CAP connected to the cell transistor, and each of the peripheral circuit areas PCA may include a peripheral circuit transistor PTR for transmitting signals and / or power to the cell transistor included in each of the cell array areas MCA. In an embodiment of the inventive concept, the peripheral circuit transistor PTR may configure various circuits (such as, with a command decoder, control logic, address buffer, row decoder, column decoder, sense amplifier, data input / output circuit, etc.).

[0022] A device isolation trench 112T may be formed in the substrate 110, and a first device isolation layer 112 and a second device isolation layer 112P may be formed in the device isolation trench 112T. A plurality of first active regions AC1 may be defined in each cell array region MCA of the substrate 110 by the first device isolation layer 112, and a plurality of second active regions AC2 may be defined in each peripheral circuit region PCA by the second device isolation layer 112P. For example, the device isolation trench 112T may be arranged on the substrate 110 to surround the plurality of first active regions AC1 in each cell array region MCA and the plurality of second active regions AC2 in each peripheral circuit region PCA.

[0023] like Figure 2 As shown in, in each cell array region MCA, each of the plurality of first active regions AC1 may be arranged to have a long axis in a first diagonal direction D1 that is inclined relative to the first horizontal direction X and the second horizontal direction Y. Therefore, the second horizontal direction Y is orthogonal to the first horizontal direction X. As shown in the figure, the plurality of first active regions AC1 may be arranged in a diagonal or oblique strip form, and by depositing the plurality of first active regions AC1 in the diagonal or oblique direction, the maximum possible distance between contacts may be provided for the semiconductor device 100. The plurality of word lines WL may be spaced apart from each other in the second horizontal direction Y, and may extend through the plurality of first active regions AC1 in parallel with each other in the first horizontal direction X. The plurality of word lines WL may be arranged at a consistent spacing. The plurality of bit lines BL may extend in parallel with each other in the second horizontal direction Y above the plurality of word lines WL, and may be arranged at a consistent spacing. The plurality of bit lines BL may be connected to the plurality of first active regions AC1 respectively through bit line contacts DC. The bit line contacts DC may each be arranged on the central region of the first active region AC1. In an embodiment of the inventive concept, a plurality of bit lines BL may cross a plurality of first active regions AC1 .

[0024] A plurality of buried contacts BC may be formed between two bit lines BL adjacent to each other among the plurality of bit lines BL, and may be disposed at both ends of the plurality of first active regions AC1. A plurality of landing pads LP may be formed on the plurality of buried contacts BC, respectively. The plurality of buried contacts BC and the plurality of landing pads LP may connect the lower electrode 182 of the capacitor structure CAP formed above the plurality of bit lines BL to the first active region AC1. For example, the plurality of landing pads LP may be arranged between the plurality of buried contacts BC and the lower electrode 182 of the capacitor structure CAP. The plurality of landing pads LP may be arranged to partially overlap the buried contacts BC and the bit lines BL, respectively.

[0025] The substrate 110 may include silicon (Si) (e.g., single crystal silicon (sc-Si), polycrystalline silicon (pc-Si), or amorphous silicon (a-Si)). The substrate 110 may be a bulk silicon (Si) substrate or a silicon on insulator (SOI) substrate. In an embodiment of the present invention, the substrate 110 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), lead telluride (PbTe), gallium phosphide (GaP), gallium antimonide (GaSb), and indium phosphide (InP). In an embodiment of the present invention, the substrate 110 may include a conductive region (such as an impurity-doped well or an impurity-doped structure).

[0026] The first device isolation layer 112 may include, for example, an oxide layer, a nitride layer, or a combination thereof. For example, the first device isolation layer 112 may include, for example, silicon oxide (SiO 2 ) film, silicon nitride (Si 3 N 4 ) film or a combination thereof. The first buffer insulating layer 114 and the second buffer insulating layer 116 may be sequentially arranged on the top surface of the substrate 110. Each of the first buffer insulating layer 114 and the second buffer insulating layer 116 may include, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON) or silicon nitride (Si 3 N 4 ).

[0027] A plurality of word line trenches 120T extending in the first horizontal direction X may be arranged on the substrate 110, and a buried gate structure 120 may be arranged in the plurality of word line trenches 120T. The buried gate structure 120 may include a gate dielectric layer 122, a gate electrode 124, and a word line capping layer 126 arranged in each of the plurality of word line trenches 120T. The gate dielectric layer 122 may conformally cover the inner surface of the word line trench 120T to contact the first active region AC1 and the first device isolation layer 112, and may extend along the sidewall and bottom surface of the word line trench 120T. The plurality of gate electrodes 124 may correspond to the first active region AC1 and the first device isolation layer 112, respectively. Figure 2 The multiple word lines WL shown in FIG.

[0028] The plurality of gate dielectric layers 122 may each include, for example, silicon oxide (SiO 2 ) layer, silicon nitride (Si 3 N 4 ) layer, a silicon oxynitride (SiON) layer, an oxide / nitride / oxide (ONO) layer, or a layer having a ratio of greater than silicon oxide (SiO 2 The high-k dielectric film may include, for example, hafnium oxide (HfO 2), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO 3 ), Tantalum Oxide (Ta 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), zirconium oxide (ZrO 2 ), yttrium oxide (Y 2 O 3 ) or titanium oxide (TiO 2 ), but the inventive concept is not limited thereto. The plurality of gate electrodes 124 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. The plurality of word line capping layers 126 may each include, for example, silicon oxide (SiO 2 ) layer, silicon nitride (Si 3 N 4 ) layer, a silicon oxynitride (SiON) layer, or a combination thereof.

[0029] A plurality of bit line contact holes DCH may extend into the substrate 110 by penetrating the first buffer insulating layer 114 and the second buffer insulating layer 116, and a plurality of bit line contacts DC may be respectively formed in the plurality of bit line contact holes DCH. The plurality of bit line contacts DC may be respectively connected to the plurality of first active regions AC1. The plurality of bit line contacts DC may include, for example, titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide (WSi2), doped polysilicon (p-Si), or a combination thereof.

[0030] The plurality of bit lines BL may longitudinally extend on the substrate 110 and on the plurality of bit line contacts DC in the second horizontal direction Y. Each of the plurality of bit lines BL may be connected to the first active region AC1 through each of the bit line contacts DC.

[0031] Each of the plurality of bit lines BL may include a lower conductive layer 132, a metal silicide layer 134, and an upper conductive layer 136. Figure 3 and Figure 4 Each of the plurality of bit lines BL is shown to have a three-layer structure including a lower conductive layer 132, a metal silicide layer 134, and an upper conductive layer 136, but the inventive concept is not limited thereto. For example, each of the plurality of bit lines BL may have a single-layer structure, a double-layer structure, or a stacked structure of multiple layers including four or more layers.

[0032] like Figure 3As shown in , the lower conductive layer 132 may extend along the second horizontal direction Y on the second buffer insulating layer 116, and the lower conductive layer 132 may cover both sidewalls of the bit line contact DC. Figure 4 , a top surface of the lower conductive layer 132 may be arranged on the same plane as a top surface of the bit line contact DC, and both sidewalls of the bit line contact DC may contact the lower conductive layer 132. The lower conductive layer 132 may include, for example, silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof.

[0033] In an example embodiment of the inventive concept, in a process of forming the bit line contact hole DCH, a portion of the lower conductive layer 132, a portion of the second buffer insulating layer 116, a portion of the first buffer insulating layer 114, and a portion of the substrate 110 may be removed, and a bit line contact DC may be formed in the bit line contact hole DCH. Therefore, an upper side of the bit line contact DC may contact the metal silicide layer 134, and a lower side of the bit line contact DC may contact the substrate 110 (e.g., the first active region AC1).

[0034] The metal silicide layer 134 may be arranged on the top surface of the lower conductive layer 132 and the top surface of the bit line contact DC to extend in the second horizontal direction Y. In an embodiment of the present invention, the metal silicide layer 134 may include, for example, at least one of cobalt silicide (CoSi2), nickel silicide (NiSi2), titanium silicide (TiSi2), tantalum silicide (TaSi2), and tungsten silicide (WSi2). In an embodiment of the present invention, optionally, a conductive barrier layer of at least one of titanium (Ti), titanium nitride (TiN), niobium nitride (NbN), tungsten nitride (WN), and tantalum nitride (TaN) may also be arranged on the metal silicide layer 134.

[0035] The upper conductive layer 136 may be disposed on the top surface of the metal silicide layer 134 and extend in the second horizontal direction Y. In an embodiment of the present inventive concept, the upper conductive layer 136 may include, for example, any one of tungsten (W), ruthenium (Ru), molybdenum (Mo), titanium (Ti), rhodium (Ro), iridium (Ir), and alloys thereof.

[0036] A plurality of bit line capping layers 140 may be respectively disposed on a plurality of bit lines BL. Each of the bit line capping layers 140 may include a first capping layer 142, a second capping layer 144, and a third capping layer 146 that are sequentially disposed on the top surface of each of the plurality of bit lines BL. The first capping layer 142, the second capping layer 144, and the third capping layer 146 may include, for example, silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), and at least one of silicon oxynitride (SiON).

[0037] An antioxidant layer 138 may be conformally disposed on the sidewalls of each of the plurality of bit lines BL, on the sidewalls of each of the plurality of bit line capping layers 140, and on the inner walls of each of the bit line contact holes DCH. In an embodiment of the inventive concept, the antioxidant layer 138 may be disposed on the sidewalls of each of the bit line contacts DC, and each of the bit line contacts DC is disposed to be aligned with the sidewalls of each of the plurality of bit lines BL. Here, as Figure 6 shown, a portion of the antioxidant layer 138 disposed on the sidewall of the upper conductive layer 136 of the bit line BL is referred to as a first portion P1, and a portion of the antioxidant layer 138 disposed on the inner wall of the bit line contact hole DCH is referred to as a second portion P2.

[0038] In an embodiment of the inventive concept, the antioxidant layer 138 may prevent the sidewall portions of the upper conductive layer 136 of each of the plurality of bit lines BL from being oxidized during the patterning process of the bit lines BL and / or the cleaning process after the patterning process. For example, the antioxidant layer 138 may supply a silicon (Si) precursor to the exposed sidewalls of the plurality of bit lines BL after the patterning process of the plurality of bit lines BL, and may include a silicon-containing material formed by a reduction reaction between the supplied silicon (Si) precursor and a metal oxide on the surface of the upper conductive layer 136. For example, the metal oxide may be reduced by the silicon (Si) precursor to regenerate the metal.

[0039] In an embodiment of the inventive concept, each of the antioxidant layers 138 may have a thickness of about 0.1 nm to about 2 nm. When the term "about" is used in combination with a numerical value in this specification, it is intended that the associated numerical value includes a tolerance of up to ±10% centered on the stated numerical value. In an embodiment of the inventive concept, the antioxidant layer 138 may include a silicon-containing material, and the silicon-containing material may be represented by the chemical formula SiO x (0 < x ≤ 2). In an embodiment of the inventive concept, the antioxidant layer 138 may further include impurities of chlorine (Cl) and / or carbon (C). For example, the impurities may be residues of chlorine (Cl) atoms and / or carbon (C) atoms included in the silicon (Si) precursor supplied during the formation process of the antioxidant layer 138.

[0040] In an embodiment of the inventive concept, a portion of the antioxidant layer 138 (e.g., a first portion P1 of the antioxidant layer 138 disposed on the sidewall of the upper conductive layer 136) may include silicon oxide (SiO 2 ) formed by a reduction reaction between a supplied silicon precursor and a metal oxide on the surface of the upper conductive layer 136.

[0041] For example, the first portion P1 of the antioxidant layer 138 may include a material formed by a reduction reaction according to Chemical Formula 1 below.

[0042] MO x + Si → M + SiO y -(Chemical Formula 1)

[0043] Here, M may correspond to an element including a metal material in the bit line BL. The antioxidant layer 138 including the silicon-containing material SiO y (0 < y ≤ 2) may be formed on the sidewall of the bit line BL. In Chemical Formula 1, x may be equal to y. The upper conductive layer 136 may include a metal material represented by M.

[0044] For example, when the upper conductive layer 136 included in the bit line BL includes tungsten (W), the first portion P1 of the antioxidant layer 138 including silicon oxide (SiO 2 ) may be formed on the sidewall of the upper conductive layer 136 by a reduction reaction according to Chemical Formula 2 below.

[0045] 2WO 3 + 3Si → 2W + 3SiO 2 -(Chemical Formula 2)

[0046] In an embodiment of the inventive concept, although the sidewall portions of the upper conductive layer 136 of each of the plurality of bit lines BL are oxidized during the patterning process of the bit line BL and / or during the cleaning process after the patterning process of the bit line BL to locally form tungsten oxide (WO 3 ) on the sidewall portions of the upper conductive layer 136, during the process of forming the antioxidant layer 138 by supplying silicon (Si) precursor, the tungsten oxide (WO 3 ) formed on the sidewall of the upper conductive layer 136 may be reduced to metallic tungsten (W) by a reduction reaction of the tungsten oxide (WO 3 ). Accordingly, the upper conductive layer 136 may have a relatively small resistance.

[0047] In an embodiment of the inventive concept, according to the amount of the metal oxide formed on the sidewall of the bit line BL, when a sufficient amount of silicon (Si) precursor is supplied to form the antioxidant layer 138 to reduce the tungsten oxide (WO 3 ), the reduction reaction may be represented by Chemical Formula 3 below.

[0048] 2WO 3 +zSi→2W+zSiO 6 / z -(Chemical Formula 3)

[0049] In Chemical Formula 3, z is equal to or greater than 3.

[0050] The bit line spacer 150 may be disposed on both sidewalls of each bit line BL. The anti-oxidation layer 138 may be disposed between the bit line spacer 150 and the bit line BL and between the bit line spacer 150 and the bit line capping layer 140, respectively. The bit line spacer 150 may include a first spacer layer 152 and a second spacer layer 154. In an embodiment of the present inventive concept, the first spacer layer 152 may include silicon oxide (SiO 2 ), and the second spacer layer 154 may include silicon nitride (Si 3 N 4 ). The first spacer layer 152 may be in contact with the anti-oxidation layer 138, and thus, the first spacer layer 152 may not be in contact with the sidewall of the bit line BL.

[0051] The second portion P2 of the anti-oxidation layer 138 may conformally extend onto the inner wall of the bit line contact hole DCH to cover or contact the sidewall of the bit line contact DC and the surface of the substrate 110, and the bit line contact spacer 160 may be arranged on the second portion P2 of the anti-oxidation layer 138 in the bit line contact hole DCH.

[0052] The bit line contact spacer 160 may include an insulating liner 162 and a buried spacer 164. The insulating liner 162 may contact the second portion P2 of the anti-oxidation layer 138 and may be conformally arranged inside the bit line contact hole DCH. The buried spacer 164 on the insulating liner 162 may fill the inside of the bit line contact hole DCH. In an embodiment of the present inventive concept, the insulating liner 162 may include silicon oxide (SiO 2 ), and the buried spacer 164 may include silicon nitride (Si 3 N 4 For example, the first spacer layer 152 of the bit line spacer 150 and the insulating liner 162 of the bit line contact spacer 160 may include the same material. The second spacer layer 154 of the bit line spacer 150 and the buried spacer 164 of the bit line contact spacer 160 may include the same material.

[0053] A plurality of buried contacts BC may be respectively arranged between the plurality of bit lines BL. For example, the upper side of each of the plurality of buried contacts BC may be placed between two adjacent bit line spacers 150, and the upper side of each of the plurality of buried contacts BC may contact the two adjacent bit line spacers 150. The lower side of each of the plurality of buried contacts BC may be arranged in a buried contact hole BCH, pass through the bit line contact spacer 160 and extend into the substrate 110. For example, each of the plurality of buried contacts BC and the corresponding buried contact hole BCH may pass through the bit line contact spacer 160. The bottom of each of the plurality of buried contacts BC may contact the first active region AC1. In an embodiment of the inventive concept, the plurality of buried contacts BC may include doped polysilicon (p-Si).

[0054] In an embodiment of the inventive concept, the buried contact hole BCH may extend in a direction toward the sidewall of the bit line contact hole DCH to penetrate the bit line contact spacer 160, and the bottom of the buried contact hole BCH may be arranged to overlap with the sidewall of the bit line contact hole DCH. Figure 6 As shown in , when the buried contact hole BCH extends in a direction toward the sidewall of the bit line contact hole DCH to penetrate the bit line contact spacer 160, the bottom of the buried contact BC may have a curved profile that protrudes laterally in a direction toward the first active region AC1 relative to the sidewall of the bit line contact hole DCH. In an embodiment of the inventive concept, the bottom of the buried contact BC arranged adjacent to the first active region AC1 may be surrounded by the second portion P2 of the anti-oxidation layer 138 and the insulating liner 162. For example, the bottom of the buried contact BC may be covered by the buried spacer 164, the insulating liner 162, and the anti-oxidation layer 138. One bit line contact DC and a pair of buried contacts BC facing each other between which the one bit line contact DC is arranged may be respectively connected to first active regions AC1 different from each other among a plurality of first active regions AC1.

[0055] A plurality of insulating fences may be arranged between two adjacent bit lines BL in the second horizontal direction Y. A plurality of insulating fences may be arranged at positions vertically overlapping with a plurality of word line trenches 120T. In a plan view, a plurality of buried contacts BC and a plurality of insulating fences may be alternately arranged between two bit lines BL extending along the second horizontal direction Y. Each of the plurality of insulating fences may have a column shape extending along a vertical direction Z between the plurality of bit lines BL and may include silicon nitride (SiN). 3 N 4 ) film. For example, silicon oxide (SiO 2 ) film or other insulating films such as a silicon oxynitride (SiON) film may also be used for each of the plurality of insulating barriers.

[0056] A plurality of landing pads LP may be arranged on a plurality of buried contacts BC, respectively. Each of the plurality of landing pads LP may include a conductive barrier layer and a landing pad conductive layer. The conductive barrier layer may include, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof. The landing pad conductive layer may include, for example, a metal, a metal nitride, conductive polysilicon (p-Si), or a combination thereof. For example, the landing pad conductive layer may include tungsten (W). In a plan view, the plurality of landing pads LP may have a plurality of island pattern shapes.

[0057] The plurality of landing pads LP may be electrically insulated from each other by an insulating pattern 170 surrounding the plurality of landing pads LP. The insulating pattern 170 may include, for example, silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ) and at least one of silicon oxynitride (SiON).

[0058] The etch stop layer 180 may be disposed on the insulating pattern 170 and may include openings 180H. The openings 180H may be disposed at positions corresponding to the respective landing pads LP, and a top surface of each landing pad LP may be disposed on a bottom of each opening 180H.

[0059] The capacitor structure CAP may be arranged on the etch stop layer 180 and the landing pad LP to store charge in, for example, a semiconductor memory element. For example, the capacitor structure CAP may be connected to a portion of the upper surface of each landing pad LP that is not blocked by the etch stop layer 180. The capacitor structure CAP may include a lower electrode 182, a capacitor dielectric layer 184, and an upper electrode 186. The lower electrode 182 may be arranged so that the bottom of the lower electrode 182 is arranged in each of the openings 180H of the etch stop layer 180, and thus the bottom of the lower electrode 182 is placed on each landing pad LP. The capacitor dielectric layer 184 may be arranged very thin to conformally cover the lower electrode 182, and the upper electrode 186 may be arranged on the capacitor dielectric layer 184. The capacitor structure CAP may store charge in the capacitor dielectric layer 184 by a potential difference generated between the lower electrode 182 and the upper electrode 186.

[0060] The peripheral circuit transistor PTR may be arranged on the second active area AC2 in the peripheral circuit area PCA. Figure 2 and Figure 5 As shown in , the peripheral circuit transistor PTR may include a gate dielectric layer 118 , a peripheral circuit gate stack PGS, and a gate capping pattern 142P sequentially stacked on the second active region AC2 .

[0061] The gate dielectric layer 118 may be disposed on the top surface of the substrate 110. The gate dielectric layer 118 may include, for example, silicon oxide (SiO 2 ) layer, silicon nitride (Si 3 N 4 ) layer, silicon oxynitride (SiON) layer, oxide / nitride / oxide (ONO) layer and silicon oxide (SiO 2 The high-k dielectric film may include, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO 3 ), tantalum oxide (Ta2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), or titanium oxide (TiO2), but the inventive concept is not limited thereto. The gate capping pattern 142P may be arranged to cover the top surface of the peripheral circuit gate stack PGS. In an embodiment of the inventive concept, the gate capping pattern 142P may include silicon nitride (Si 3 N 4 )layer.

[0062] The peripheral gate stack PGS may include a peripheral lower conductive layer 132P, a peripheral metal silicide layer 134P, and a peripheral upper conductive layer 136P.

[0063] The peripheral lower conductive layer 132P may be disposed on the gate dielectric layer 118 and may include, for example, at least one of silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), and combinations thereof. The peripheral metal silicide layer 134P may be disposed on the top surface of the peripheral lower conductive layer 132P. In an embodiment of the present inventive concept, the peripheral metal silicide layer 134P may include, for example, at least one of cobalt silicide (CoSi2), nickel silicide (NiSi2), titanium silicide (TiSi2), tantalum silicide (TaSi2), and tungsten silicide (WSi2). In an embodiment of the present inventive concept, optionally, at least one conductive barrier layer such as titanium (Ti), titanium nitride (TiN), niobium nitride (NbN), tungsten nitride (WN) or tantalum nitride (TaN) may also be disposed on the peripheral metal silicide layer 134P.

[0064] In an embodiment of the inventive concept, the upper peripheral conductive layer 136P may include, for example, at least one of tungsten (W), ruthenium (Ru), molybdenum (Mo), titanium (Ti), rhodium (Ro), iridium (Ir), and alloys thereof.

[0065] In an embodiment of the present inventive concept, the constituent material of each of the peripheral lower conductive layer 132P, the peripheral metal silicide layer 134P, and the peripheral upper conductive layer 136P may be respectively the same as the constituent materials of the lower conductive layer 132, the metal silicide layer 134, and the upper conductive layer 136 in each bit line BL included in the cell array area MCA. For example, the peripheral gate stack PGS may be formed simultaneously in the process of forming the bit line BL. However, the present inventive concept is not limited thereto.

[0066] The two side walls of the peripheral circuit gate stack PGS and the gate capping pattern 142P may be covered by an insulating spacer 150P. For example, the insulating spacer 150P may be formed on the substrate 110 and may extend on the top surface of the gate dielectric layer 118 and the side walls of the peripheral circuit gate stack PGS and the gate capping pattern 142P in the second horizontal direction Y. The insulating spacer 150P may include, for example, an oxide layer, a nitride layer, or a combination thereof. The peripheral circuit transistor PTR and the insulating spacer 150P may be covered by a protective layer 144P, and a first interlayer insulating layer 148 may be arranged on the protective layer 144P to fill the space between two adjacent peripheral circuit transistors PTR. The capping insulating layer 146P may be arranged on the first interlayer insulating layer 148 and the protective layer 144P.

[0067] like Figure 2 and Figure 5 As shown in , the contact plugs PCT may be respectively formed in the contact holes PCTH, which penetrate the first interlayer insulating layer 148 and the capping insulating layer 146P in the peripheral circuit area PCA along the vertical direction Z to connect to the substrate 110. For example, the contact plugs PCT may be disposed adjacent to the peripheral gate stack PGS and may be connected to the source region and the drain region of the substrate 110. The contact plugs PCT may include a conductive barrier layer and a landing pad conductive layer in the same manner as a plurality of landing pads LP are formed in the cell array area MCA. A metal silicide layer may be arranged between the second active area AC2 and each contact plug PCT. An upper interlayer insulating layer 190 covering the contact plugs PCT may be arranged on the capping insulating layer 146P.

[0068] Generally, as the line width of the bit line BL decreases and the interval between the bit lines BL decreases, it is difficult to accurately control the process of patterning the bit line contact DC and / or forming the contact buried hole BCH. 3 N 4)When an internal spacer is formed on the side wall of the bit line contact DC, in the process of forming the buried contact hole BCH, the internal spacer may not be sufficiently removed from the bottom of the buried contact hole BCH to penetrate the bit line contact spacer, resulting in defects such as the surface of the substrate not being exposed or the surface of the substrate being exposed in a relatively small area.

[0069] According to the above embodiment, an anti-oxidation layer 138 may be formed on the sidewall of each bit line BL by a silicon (Si) precursor supply process to prevent undesired oxidation of the sidewall of each bit line BL (such as the upper conductive layer 136). For example, as shown in the above chemical formula 1, the metal oxide (MO) formed on the sidewall of the bit line BL x ) can be reduced by a silicon (Si) precursor to regenerate the metal (M) of the bit line BL. In addition, since silicon nitride (Si) is not formed on the sidewall of the bit line contact DC, 3 N 4 ), so the bit line contact spacer 160 can be sufficiently removed in the process of forming the buried contact hole BCH so as to penetrate the bit line contact spacer 160, and a sufficiently large contact area between the buried contact BC and the first active region AC1 can be ensured.

[0070] Figure 7 and Figure 8 is a cross-sectional view illustrating a semiconductor device 100A according to an embodiment of the inventive concept.

[0071] Reference Figure 7 and Figure 8 The bit line spacer 150 may further include a third spacer layer 156 , and the third spacer layer 156 may be disposed between the first spacer layer 152 and the anti-oxidation layer 138 .

[0072] The third spacer layer 156 may be conformally disposed on the sidewall of the anti-oxidation layer 138 and have one end extending to the top surface of the insulating liner 162 of the bit line contact spacer 160. The first spacer layer 152 and the second spacer layer 154 may be sequentially disposed on the third spacer layer 156.

[0073] In an embodiment of the present inventive concept, the third spacer layer 156 may include silicon nitride (Si 3 N 4 ). In an embodiment of the inventive concept, the third spacer layer 156 may have a thickness of about 0.5 nm to about 2 nm.

[0074] Fig. 9 and Fig.10 is a cross-sectional view illustrating a semiconductor device 100B according to an embodiment of the inventive concept.

[0075] Reference Fig. 9 and Fig.10 The bit line spacer 150 may further include a third spacer layer 156A, and the third spacer layer 156A may be disposed between the first spacer layer 152 and the antioxidant layer 138.

[0076] In an embodiment of the inventive concept, the third spacer layer 156A may include a silicon-containing material (e.g., the silicon-containing material may be represented by the formula SiO x (0 < x ≤ 2)). For example, the silicon-containing material may be represented by the formula SiO q (0 < q < 2). In an embodiment of the inventive concept, the third spacer layer 156A may further include impurities of chlorine (Cl) and / or carbon (C). For example, the impurities may be residues of chlorine (Cl) atoms and / or carbon (C) atoms included in the silicon (Si) precursor supplied in the process of forming the third spacer layer 156A.

[0077] In an embodiment of the inventive concept, the third spacer layer 156A may include a silicon-containing material formed by a process of supplying a silicon (Si) precursor onto the top surface of the antioxidant layer 138. For example, the third spacer layer 156A may be formed by forming the antioxidant layer 138, and then forming the bit line contact spacer 160 in the bit line contact hole DCH, and then performing an additional silicon precursor supply process on the surface of the antioxidant layer 138 placed on the sidewalls of each bit line BL.

[0078] In an embodiment of the inventive concept, since both the third spacer layer 156A and the antioxidant layer 138 are formed by the silicon precursor supply process, the boundary between the third spacer layer 156A and the antioxidant layer 138 may not be visually distinguishable.

[0079] In an embodiment of the inventive concept, the third spacer layer 156A may have a thickness of about 0.5 nm to about 2 nm.

[0080] Fig.11A and Fig. 11B and Fig. 12A and Fig. 12B and Fig.13A and Fig. 13B and Fig.14A and Fig. 14B and Figures 15 to 21 and Fig.22A and Fig. 22B and Fig.23A and Fig. 23B and Fig.24A and Fig. 24B are cross-sectional views showing a method of manufacturing a semiconductor device 100 according to an embodiment of the inventive concept. For example, Fig.11A and Fig. 12A and Fig.13A and Fig.14A , Figures 15 to 21 , Fig.22A , Fig.23A and Fig.24A is along with Figure 2 The cross-sectional view corresponds to the cross-sectional view taken along the line AA', and Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 22B , Fig. 23B and Fig. 24B is along with Figure 2 The cross-sectional view corresponds to the cross-sectional view taken along the line BB'.

[0081] Reference Fig.11A and Fig. 11B , a plurality of device isolation trenches 112T may be formed in the substrate 110 .

[0082] Afterwards, a first device isolation layer 112 filling the plurality of device isolation trenches 112T may be formed. By forming the first device isolation layer 112, a plurality of first active regions AC1 may be defined in the substrate 110. In a plan view, the plurality of first active regions AC1 may be arranged in a first diagonal direction D1 (see FIG. 1 ) that is inclined at a predetermined angle to the first horizontal direction X and the second horizontal direction Y. Figure 2 In addition, the plurality of first active regions AC1 may be in the form of a plurality of strips extending parallel to each other, and a substantially central portion of one of the plurality of first active regions AC1 may be disposed adjacent to an end portion of another first active region AC1.

[0083] In an embodiment of the present inventive concept, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof to form the first device isolation layer 112. In an embodiment of the inventive concept, the first device isolation layer 112 may be formed to have silicon oxide (SiO 2 ) layer and silicon nitride (Si 3 N 4 ) layers, but the present invention is not limited thereto.

[0084] A mask pattern may be formed on the substrate 110, and a portion of the substrate 110 may be removed by using the mask pattern as an etching mask to form the word line trench 120T. The mask pattern may be formed by a photolithography process and an etching process. For example, a double patterning technique (DPT) or a quadruple patterning technique (QPT) may be used to form a mask pattern for forming the word line trench 120T, but the inventive concept is not limited thereto.

[0085] Thereafter, a gate dielectric layer 122 , a gate electrode 124 , and a word line capping layer 126 constituting a buried gate structure 120 may be sequentially formed in each word line trench 120T.

[0086] The gate dielectric layer 122 may be conformally arranged on the inner wall of the word line trench 120T. The gate electrode 124 may be formed by filling the word line trench 120T with a conductive layer, and then etching back the upper portion of the conductive layer to expose a portion of the upper side of the word line trench 120T again. The etching back process may be performed until a conductive layer having a desired thickness is formed in the lower portion of the word line trench 120T.

[0087] Reference Fig. 12A and Fig. 12B , a first buffer insulating layer 114 and a second buffer insulating layer 116 may be formed on the first active region AC1 and the first device isolation layer 112. Thereafter, a lower conductive layer 132 may be formed on the first buffer insulating layer 114 and the second buffer insulating layer 116. The lower conductive layer 132, the first buffer insulating layer 114 and the second buffer insulating layer 116, and a portion of the substrate 110 may be removed to form a bit line contact hole DCH. For example, in a plan view, the bit line contact holes DCH may each be formed at a substantially central portion of each of the first active regions AC1, and may be formed between two adjacent buried gate structures 120. Thereafter, a bit line contact DC may be formed in the bit line contact hole DCH by using a conductive material.

[0088] In an embodiment of the present inventive concept, the lower conductive layer 132 may be formed using, for example, at least one of silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), and a combination thereof. In an embodiment of the present inventive concept, the bit line contact DC may be formed using, for example, titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide (WSi2), doped polysilicon (p-Si), or a combination thereof.

[0089] Reference Fig.13A and Fig. 13B , a metal silicide layer 134 may be formed on the bit line contact DC and the lower conductive layer 132. The metal silicide layer 134 may be formed using, for example, at least one of cobalt silicide (CoSi2), nickel silicide (NiSi2), titanium silicide (TiSi2), tantalum silicide (TaSi2), and tungsten silicide (WSi2). Alternatively, a conductive barrier layer may be further formed on the metal silicide layer 134 using, for example, at least one of titanium (Ti), titanium nitride (TiN), niobium nitride (NbN), tungsten nitride (WN), and tantalum nitride (TaN).

[0090] Thereafter, an upper conductive layer 136 may be formed on the metal silicide layer 134. In an embodiment of the present inventive concept, the upper conductive layer 136 may include, for example, at least one of tungsten (W), ruthenium (Ru), molybdenum (Mo), titanium (Ti), rhodium (Ro), iridium (Ir), and alloys thereof. The upper conductive layer 136 may be formed using, for example, at least one of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process.

[0091] Thereafter, a bit line capping layer 140 may be formed on the upper conductive layer 136. The bit line capping layer 140 may include a first capping layer 142, a second capping layer 144, and a third capping layer 146 sequentially disposed on the upper conductive layer 136. The first capping layer 142, the second capping layer 144, and the third capping layer 146 may be formed using, for example, silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ) and at least one of silicon oxynitride (SiON).

[0092] Reference Fig.14A and Fig. 14B , a plurality of bit lines BL may be formed by patterning the upper conductive layer 136, the metal silicide layer 134, and the lower conductive layer 132 using the bit line capping layer 140 as an etching mask. The first buffer insulating layer 114 and the second buffer insulating layer 116 may function as an etching stopper film.

[0093] In the patterning process for forming the plurality of bit lines BL, the portion of the bit line contact DC disposed in the bit line contact hole DCH may also be removed. Fig.14A As shown in , the sidewall of each bit line contact DC may be formed to be aligned with the sidewall of each bit line BL, and the inner wall of each bit line contact hole DCH (e.g., the surface of the substrate 110) may be exposed on both sides of each bit line contact DC. For example, after the patterning process, the bit line BL and the bit line contact DC may be formed on and connected to the substrate 110, and may extend in the second horizontal direction in the cell array area MCA.

[0094] Alternatively, a cleaning process may be performed after the patterning process of the bit line BL. The cleaning process may be performed to remove etching residues from the patterning process, and, for example, may be performed by a rinsing process using a wet cleaning solution.

[0095] Reference Fig.15 , an anti-oxidation layer 138 may be formed on sidewalls of the bit line BL, the bit line capping layer 140 , and the bit line contact DC.

[0096] In an embodiment of the inventive concept, an antioxidant layer 138 may be formed by performing a silicon (Si) precursor supply process. In an embodiment of the inventive concept, the silicon (Si) precursor supplied in the silicon (Si) precursor supply process may include, but is not limited to, for example, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (DCS), trichlorosilane (TCS), diisopropylaminosilane (DIPAS), etc.

[0097] In an embodiment of the inventive concept, the silicon (Si) precursor supply process may include supplying a silicon (Si) precursor onto a reaction chamber in which a substrate is disposed, and removing or purging the silicon (Si) precursor from the reaction chamber. In an embodiment of the inventive concept, the silicon (Si) precursor supply process may be implemented by repeating a unit supply cycle including a silicon (Si) precursor supply step and a purge step one to dozens of times. The silicon (Si) precursor supply process may be performed until a silicon-containing material having a thickness of about 0.1 nm to about 2 nm is formed.

[0098] In an embodiment of the inventive concept, the antioxidant layer 138 may include a silicon-containing material, and the silicon-containing material may be represented by the chemical formula SiO x (0 < x ≤ 2). In an embodiment of the inventive concept, the antioxidant layer 138 may further include impurities containing chlorine (Cl) and / or carbon (C). For example, the impurities may be residues of chlorine (Cl) atoms and / or carbon (C) atoms included in the silicon (Si) precursor supplied during the formation process of the antioxidant layer 138.

[0099] In an embodiment of the inventive concept, silicon oxide (SiO 2 ) may be formed by a reduction reaction between a silicon precursor supplied on the sidewall of the upper conductive layer 136 and a metal oxide (for example, a metal oxide formed on the surface of the upper conductive layer 136 as a result of a previous patterning process and / or a selectively performed cleaning process). For example, the metal oxide may be reduced by the silicon (Si) precursor to regenerate the metal of the upper conductive layer 136. For example, a reduction reaction according to Chemical Formula 1 below may occur on the surface of the upper conductive layer 136, and at least a part (for example, a first part P1 of the antioxidant layer 138) of the antioxidant layer 138 may include a material formed by Chemical Formula 1 below.

[0100] MO x + Si → M + SiO y -(Chemical Formula 1)

[0101] Here, M may correspond to an element including a metal material in the bit line BL. Including the silicon-containing material SiO yThe antioxidant layer 138 where (0 < y ≤ 2) can be formed on the sidewalls of the bit lines BL. In Chemical Formula 1, x can be equal to y. The upper conductive layer 136 can include a metal material represented by M.

[0102] For example, when the upper conductive layer 136 included in each bit line BL includes tungsten (W), a first portion P1 of the antioxidant layer 138 placed on the sidewalls of the upper conductive layer 136 through the reduction reaction of the following Chemical Formula 2 can include silicon oxide (SiO 2 ).

[0103] 2WO 3 + 3Si → 2W + 3SiO 2 -(Chemical Formula 2)

[0104] In an embodiment of the inventive concept, according to the amount of metal oxide formed on the sidewalls of the bit lines BL, when a sufficient amount of a silicon (Si) precursor is supplied to form the antioxidant layer 138 such that tungsten oxide (WO 3 ) is reduced, the reduction reaction can be represented by the following Chemical Formula 3.

[0105] 2WO 3 + zSi → 2W + zSiO 6 / z -(Chemical Formula 3)

[0106] In Chemical Formula 3, z is equal to or greater than 3.

[0107] In an embodiment of the inventive concept, the antioxidant layer 138 can be conformally disposed on the sidewalls of each of the plurality of bit lines BL, on the sidewalls of each of the plurality of bit line capping layers 140, and on the inner walls of each bit line contact hole DCH. In an embodiment of the inventive concept, the antioxidant layer 138 can be disposed on the sidewalls of each bit line contact DC, and each bit line contact DC is disposed to be aligned with the sidewalls of each of the plurality of bit lines BL.

[0108] Referring to Fig.16 , an insulating liner 162 can be conformally formed on the plurality of bit lines BL, the plurality of bit line capping layers 140, and the inner walls of the bit line contact holes DCH. The insulating liner 162 can be disposed in contact with the antioxidant layer 138.

[0109] In an embodiment of the inventive concept, the insulating liner 162 can include silicon oxide (SiO 2 ).

[0110] Referring to Fig.17 , a buried spacer 164 can be formed on the plurality of bit lines BL, the plurality of bit line capping layers 140, and the inner walls of the bit line contact holes DCH. The buried spacer 164 can be in contact with the insulating liner 162 and can be formed thick enough to completely fill the interior of the bit line contact hole DCH.

[0111] In an embodiment of the present inventive concept, the buried spacer 164 may include silicon nitride (Si 3 N 4 ).

[0112] Reference Fig.18 , the buried spacers 164 arranged on the sidewalls of the plurality of bit lines BL and the plurality of bit line capping layers 140 may be removed, and only portions of the buried spacers 164 arranged inside the bit line contact holes DCH may remain.

[0113] In an embodiment of the present inventive concept, the process of removing a portion of the buried spacer 164 may be an etching process using an etchant having an etching selectivity with respect to the insulating liner 162. For example, under the etching conditions using the etchant, the etching rate of the buried spacer 164 is substantially higher than the etching rate of the insulating liner 162. For example, in the process of removing a portion of the buried spacer 164, a portion of the insulating liner 162 disposed on the sidewalls of the plurality of bit lines BL and the plurality of bit line capping layers 140 may remain due to not being removed. For example, phosphoric acid (H 2 O) may be used in the wet etching process. 3 PO 4 ) or using oxygen (O 2 ), nitrogen (N 2 ) and a fluorine source gas (such as carbon tetrafluoride (CF4) or nitrogen trifluoride (NF3)) on the silicon oxide (SiO 2 ) is selectively removed from the buried spacer 164. 3 N 4 ). However, the present inventive concept is not limited thereto.

[0114] Reference Fig.19 , portions of the insulating liner 162 disposed on sidewalls of the plurality of bit lines BL and the plurality of bit line capping layers 140 may be removed, and only portions of the insulating liner 162 disposed inside the bit line contact holes DCH may remain.

[0115] In an embodiment of the inventive concept, in the process of removing a portion of the insulating liner 162 , the sidewall of the bit line BL may be covered by the anti-oxidation layer 138 so as not to be exposed to the etching atmosphere.

[0116] Here, the insulating liner 162 and the buried spacer 164 disposed in the bit line contact hole DCH may be referred to as a bit line contact spacer 160 .

[0117] Reference Fig. 20, a first spacer layer 152 may be formed on the sidewalls of the bit line BL and the bit line capping layer 140. In an embodiment of the inventive concept, the first spacer layer 152 may be disposed on the sidewalls of the anti-oxidation layer 138 and include silicon oxide (SiO 2 ) or using silicon oxide (SiO 2 The first spacer layer 152 may be in contact with the anti-oxidation layer 138, and the anti-oxidation layer 138 may be disposed between the first spacer layer 152 and the bit line BL. The first spacer layer 152 may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0118] Thereafter, a second spacer layer 154 may be formed on the sidewalls of the first spacer layer 152. In an embodiment of the present inventive concept, the second spacer layer 154 may include silicon nitride (Si 3 N 4 ) or silicon nitride (Si 3 N 4 The second spacer layer 154 may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0119] Thereafter, a portion of the bit line contact spacer 160 disposed between the bit lines BL may be removed to expose the top of the first active region AC1 and form a buried contact hole BCH.

[0120] In an embodiment of the present inventive concept, the process of forming the buried contact hole BCH may include a wet etching process, a dry etching process, or a combination thereof. In the etching process for forming the buried contact hole BCH, a portion of the upper side of the bit line capping layer 140 may also be removed, thereby reducing the top surface height of the bit line capping layer 140.

[0121] In an embodiment of the present inventive concept, the process of forming the buried contact hole BCH may include a first etching process for removing a portion of the buried spacer 164, a second etching process for removing a portion of the insulating liner 162, and a third etching process for removing a portion of the anti-oxidation layer 138. A portion of the first active region AC1 may also be removed in the process of forming the buried contact hole BCH.

[0122] In an embodiment of the present inventive concept, the buried contact hole BCH may extend in a direction toward the sidewall of the bit line contact hole DCH to penetrate the bit line contact spacer 160, and the bottom of the buried contact hole BCH may have a curved profile that protrudes laterally relative to the sidewall of the bit line contact hole DCH in a direction toward the first active region AC1.

[0123] Reference Fig.21, a buried contact BC filling the inside of the buried contact hole BCH may be formed. In an embodiment of the inventive concept, the buried contact BC may be formed using doped polysilicon (p-Si).

[0124] In an embodiment of the present inventive concept, the buried contact hole BCH is formed to have a linear planar shape placed between adjacent bit lines BL (e.g., between adjacent bit line spacers 150), and then a pre-contact layer having a linear planar shape may be formed in the buried contact hole BCH, and the pre-contact layer may be patterned to form a buried contact BC. Thereafter, an insulating fence may be formed using an insulating material in a space between the buried contacts BC (e.g., a space from which a portion of the pre-contact layer is removed).

[0125] In an embodiment of the present inventive concept, before forming the buried contact hole BCH, a plurality of insulating fences (see FIG. 1 ) may be formed at the intersection of the space between two adjacent bit lines BL and the word line trench 120T using an insulating material. Fig. 22B ), a buried contact hole BCH may be formed by removing a portion of the substrate 110 disposed between the plurality of bit lines BL and between the plurality of insulating barriers, and then a buried contact BC may be formed in the buried contact hole BCH.

[0126] Reference Fig.22A and Fig. 22B A landing pad conductive layer LPL may be formed on top surfaces of the plurality of buried contacts BC. The landing pad conductive layer LPL may be formed to have a sufficient thickness to contact the buried contacts BC and cover the top surface of the bit line capping layer 140.

[0127] Reference Fig.23A and Fig. 23B , a mask pattern may be formed on the landing pad conductive layer LPL, and the landing pad conductive layer LPL may be patterned using the mask pattern as an etching mask to form a landing pad opening LPH. A plurality of landing pads LP respectively arranged on a plurality of buried contacts BC may be formed through the landing pad opening LPH. Then, each of the plurality of landing pads LP may be disposed on a portion of the upper surface of the bit line capping layer 140 and the upper surface of the buried contact BC. Similar to the buried contact BC, the landing pad LP may form a plurality of isolation regions spaced apart from each other.

[0128] Reference Fig.24A and Fig. 24B , an insulating pattern 170 may be formed in the landing pad opening LPH by using an insulating material. The insulating pattern 170 may be arranged to cover the sidewalls of the plurality of landing pads LP. For example, the insulating pattern 170 may separate the landing pads LP from each other.

[0129] Return to reference Figure 3And Figure 4 , an etch stop layer 180 may be formed on the insulating pattern 170, and the etch stop layer 180 may include an opening 180H. The opening 180H may be disposed at a position corresponding to each landing pad LP, and the top surface of each landing pad LP may be disposed on the bottom of each opening 180H.

[0130] Return to reference Figure 3 And Figure 4 , a plurality of lower electrodes 182 connected to the landing pads LP may be formed, and a capacitor dielectric layer 184 and an upper electrode 186 may be sequentially formed on the sidewalls of each of the plurality of lower electrodes 182. The lower electrodes 182 may be arranged such that the bottom of the lower electrodes 182 is disposed in each opening 180H of the etch stop layer 180, and thus the bottom of the lower electrodes 182 is placed on each landing pad LP.

[0131] The semiconductor device 100 may be completely formed by performing the above-described method.

[0132] According to an embodiment of the inventive concept, an antioxidant layer 138 may be formed on the sidewalls of each bit line BL through a silicon (Si) precursor supply process to prevent undesired oxidation of the sidewalls of each bit line BL (e.g., the upper conductive layer 136). Additionally, since an inner spacer using silicon nitride (Si 3 N 4 ) is not formed on the sidewalls of the bit line contacts DC, the bit line contact spacer 160 may be sufficiently removed in the process of forming the buried contact hole BCH to penetrate the bit line contact spacer 160, and a sufficiently large contact area between the buried contact BC and the first active region AC1 may be ensured.

[0133] In an embodiment of the inventive concept, after performing the process described with reference to FIG. 11A to FIG. 19 , a silicon (Si) precursor supply process may be performed on the sidewalls of the bit lines BL (e.g., on the top surface of the antioxidant layer 138 disposed on the sidewalls of each bit line BL) to form a third spacer layer 156A, and then a first spacer layer 152 and a second spacer layer 154 covering the third spacer layer 156A may be sequentially formed. The third spacer layer 156A may include a silicon-containing material. For example, the silicon-containing material may be represented by the formula SiO x (0 < x ≤ 2). In this case, the semiconductor device 100B described with reference to Fig. 9 And Fig.10 may be formed.

[0134] In an embodiment of the inventive concept, after performing the process described with reference to FIG. 11A to FIG. 19 , silicon nitride (Si 3 N 4) A third spacer layer 156 is formed on the sidewall of each bit line BL (for example, formed on the top surface of the anti-oxidation layer 138 arranged on the sidewall of each bit line BL), and then a first spacer layer 152 and a second spacer layer 154 covering the third spacer layer 156 may be sequentially formed. In this case, a reference Figure 7 and Figure 8 A semiconductor device 100A is described.

[0135] According to the semiconductor device of the present invention, an anti-oxidation layer can be formed on the sidewall of each bit line by a silicon (Si) precursor supply process to prevent undesired oxidation of the sidewall of each bit line (e.g., an upper conductive layer including a metal material). In addition, since a silicon nitride (Si) layer is not formed on the sidewall of the bit line contact, 3 N 4 ), so the bit line contact spacer can be sufficiently removed in the process of forming the buried contact hole to penetrate the bit line contact spacer, and a sufficiently large contact area between the buried contact and the first active region can be ensured. Therefore, the electrical connection between the buried contact and the first active region can be ensured, and the occurrence of resistance defects can be prevented.

[0136] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a first active region; A bit line disposed on the substrate, crossing the first active region, and extending in a first direction parallel to a top surface of the substrate; a bit line contact disposed between the bit line and the first active region and disposed in a bit line contact hole extending into the substrate; a bit line contact spacer disposed on a sidewall of the bit line contact in the bit line contact hole; A bit line spacer disposed on a sidewall of the bit line; an anti-oxidation layer disposed between a sidewall of the bit line and the bit line spacer and between a sidewall of the bit line contact and the bit line spacer; as well as a buried contact disposed in the buried contact hole, passing through the bit line contact spacer, and contacting the first active region, The anti-oxidation layer includes a silicon-containing material, and the silicon-containing material includes SiO x , where 0 <X≤2。 2. The semiconductor device according to claim 1, wherein The bit line includes an upper conductive layer including a metal material, The anti-oxidation layer includes a first portion disposed on a sidewall of the upper conductive layer, and The first portion includes silicon oxide.

3. The semiconductor device according to claim 1, wherein The silicon-containing material also includes impurities, and The impurities include at least one of carbon and chlorine.

4. The semiconductor device according to claim 1, wherein The anti-oxidation layer includes a second portion disposed on an inner wall of the bit line contact hole, and The bit line contact spacer comprises: an insulating liner disposed on an inner wall of the bit line contact hole and on a second portion of the anti-oxidation layer; and A buried spacer is disposed on an inner wall of the bit line contact hole and on an insulating liner.

5. The semiconductor device according to claim 4, wherein: The insulating spacer includes silicon oxide, and The buried spacers include silicon nitride.

6. The semiconductor device according to claim 4, wherein: An insulating liner is disposed between the buried spacer and the anti-oxidation layer, and The bottom of the buried contact is covered by a buried spacer, an insulating liner and an anti-oxidation layer.

7. The semiconductor device according to claim 4, wherein: A bottom of the buried contact protrudes laterally toward the first active region relative to a sidewall of the bit line contact hole.

8. The semiconductor device according to claim 4, wherein: A second portion of the anti-oxidation layer contacts a sidewall of the bit line contact.

9. The semiconductor device according to claim 1, wherein: The bit line spacer includes: a first spacer layer disposed on a sidewall of the anti-oxidation layer and including silicon oxide; and The second spacer layer is disposed on the sidewalls of the first spacer layer and includes silicon nitride.

10. The semiconductor device according to claim 9, wherein: The first spacer layer contacts a sidewall of the anti-oxidation layer.

11. The semiconductor device according to claim 9, wherein The bit line spacer further includes a third spacer layer disposed between a sidewall of the anti-oxidation layer and the first spacer layer, and The third spacer layer includes silicon nitride.

12. The semiconductor device according to claim 9, wherein: The bit line spacer further includes a third spacer layer disposed between a sidewall of the anti-oxidation layer and the first spacer layer, and The third spacer layer includes a silicon-containing material, and the silicon-containing material includes SiO x (0 <X≤2)。 13. A semiconductor device comprising: A substrate including a plurality of first active regions; a plurality of bit lines disposed on the substrate, crossing the plurality of first active regions, and extending in a first direction parallel to a top surface of the substrate; A bit line contact is arranged between a first bit line among the plurality of bit lines and a first active region corresponding to the first bit line among the plurality of first active regions, and is arranged in a bit line contact hole, the bit line contact hole extending into the substrate; an anti-oxidation layer, comprising a first portion disposed on a sidewall of the first bit line and a second portion disposed on an inner wall of the bit line contact hole; a bit line contact spacer disposed on the second portion of the anti-oxidation layer and filling the bit line contact hole; as well as a buried contact disposed between a first bit line among the plurality of bit lines and a second bit line adjacent to the first bit line, disposed in the buried contact hole, passing through the bit line contact spacer and the second portion of the anti-oxidation layer, and contacting the first active region, The anti-oxidation layer includes a silicon-containing material, and the silicon-containing material includes SiO x , where 0 <X≤2。 14. The semiconductor device according to claim 13, wherein: The first portion of the anti-oxidation layer includes silicon oxide.

15. The semiconductor device according to claim 13, wherein: Silicon-containing materials also contain impurities, and The impurities include at least one of carbon and chlorine.

16. The semiconductor device according to claim 13, wherein: The bit line contact spacer comprises: an insulating liner disposed on an inner wall of the bit line contact hole and on a second portion of the anti-oxidation layer; and A buried spacer is disposed on an inner wall of the bit line contact hole and on an insulating liner.

17. The semiconductor device according to claim 16, wherein: The insulating spacer includes silicon oxide, and The buried spacers include silicon nitride.

18. The semiconductor device according to claim 16, wherein: An insulating liner is disposed between the buried spacer and the anti-oxidation layer, and A second portion of the anti-oxidation layer contacts a sidewall of the bit line contact.

19. A semiconductor device comprising: A substrate including a plurality of first active regions; a plurality of bit lines disposed on the substrate, crossing the plurality of first active regions, and extending in a first direction parallel to a top surface of the substrate; A bit line contact is arranged between a first bit line among the plurality of bit lines and a first active region corresponding to the first bit line among the plurality of first active regions, and is arranged in a bit line contact hole, the bit line contact hole extending into the substrate; an anti-oxidation layer, comprising a first portion disposed on a side wall of the first bit line and a second portion disposed on an inner wall of the bit line contact hole; a bit line contact spacer disposed on the second portion of the anti-oxidation layer and filling the bit line contact hole; a buried contact disposed between a first bit line among the plurality of bit lines and a second bit line adjacent to the first bit line, disposed in the buried contact hole, passing through the bit line contact spacer and the second portion of the anti-oxidation layer, and contacting the first active region; A bit line spacer disposed on a sidewall of the first bit line, the bit line spacer comprising a first spacer layer and a second spacer layer, the first spacer layer being disposed on a sidewall of the first portion of the anti-oxidation layer and comprising silicon oxide, the second spacer layer being disposed on a sidewall of the first spacer layer and comprising silicon nitride; and Landing pads, arranged on buried contacts, Among them, the antioxidant layer includes a silicon-containing material, and the silicon-containing material contains SiO x , where 0 < x ≤ 2, and The first portion of the anti-oxidation layer includes silicon oxide.

20. The semiconductor device according to claim 19, wherein The bit line contact spacer comprises: an insulating liner disposed on an inner wall of the bit line contact hole and on a second portion of the anti-oxidation layer; and a buried spacer disposed on an inner wall of the bit line contact hole and disposed on an insulating liner, wherein the bottom of the buried contact is covered by the buried spacer, the insulating liner and the second portion of the anti-oxidation layer, and A bottom of the buried contact protrudes laterally toward the first active region relative to a sidewall of the bit line contact hole.

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