Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel and the display device solve the problem that in the prior art, due to the fact that stress in a display panel cannot be released in time, a circuit is damaged, and display is poor. The display panel comprises a substrate, a first semiconductor wire and a first conductive wire, the first semiconductor wire comprises a first edge part; the first conductive wire and the first semiconductor wire are stacked in the thickness direction of the substrate, the first conductive wire comprises a second edge part, and a first overlapping area exists between the orthographic projection of the first conductive wire on the substrate and the orthographic projection of the first semiconductor wire on the substrate; the orthographic projection of the second edge portion of the first conductive wire on the substrate is overlapped with the orthographic projection of the first edge portion of the first semiconductor wire on the substrate, and a first included angle between the orthographic projection of the second edge portion of the first conductive wire and the orthographic projection of the first edge portion of the first semiconductor wire is larger than or equal to 90 degrees. When the display panel deforms, stress can be released in time when a local area is repeatedly stressed, and poor display caused by circuit damage is almost avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display panel related technologies, there are more and more types of display panels, among which flexible display panels, such as fixed bend screens, flexible folding screens, flexible sliding screens and flexible curling screens, are becoming more and more common. Flexible display panels have high requirements for stress release of their film layer stacking structure. Because local areas of flexible display panels are repeatedly stressed, failure to release stress in time will cause damage to the circuit and cause poor display. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a display panel and a display device, which solve the problem in the prior art that stress in the display panel cannot be released in time, which may cause circuit damage and lead to poor display.

[0004] In a first aspect, the present application provides a display panel, comprising:

[0005] substrate;

[0006] A first semiconductor trace, located on the substrate, the first semiconductor trace comprising a first edge;

[0007] A first conductive trace, the first conductive trace and the first semiconductor trace are stacked along the thickness direction of the substrate, the first conductive trace includes a second edge, and an orthographic projection of the first conductive trace on the substrate and an orthographic projection of the first semiconductor trace on the substrate have a first overlapping area; the orthographic projection of the second edge of the first conductive trace on the substrate overlaps with the orthographic projection of the first edge of the first semiconductor trace on the substrate, and a first angle between the two is greater than or equal to 90°, and the first angle is located outside the orthographic projections of the first semiconductor trace and the first conductive trace on the substrate.

[0008] In one embodiment, the first semiconductor trace further includes a third side portion; the first side portion and the third side portion are located on opposite sides of the first semiconductor trace;

[0009] The first conductive trace further includes a fourth side, the second side is connected to the fourth side, the second side and the fourth side are located on the same side of the first conductive trace, an orthographic projection of the fourth side of the first conductive trace on the substrate overlaps with an orthographic projection of the third side of the first semiconductor trace on the substrate, and a second angle between the two is greater than or equal to 90°, and the second angle is located outside the orthographic projections of the first semiconductor trace and the first conductive trace on the substrate;

[0010] Optionally, the fourth side portion extends along the first direction;

[0011] Optionally, the orthographic projection of the fourth side portion on the substrate coincides with an edge of the orthographic projection of the first overlapping region on the substrate.

[0012] In one embodiment, it further comprises: a second conductive trace and a third conductive trace, wherein the second conductive trace and the third conductive trace are stacked along the thickness direction of the substrate;

[0013] The second conductive trace includes a fifth side portion, and the third conductive trace includes a sixth side portion;

[0014] There is a second overlapping region between the orthographic projection of the second conductive trace on the substrate and the orthographic projection of the third conductive trace on the substrate; at the second overlapping region, an angle between the orthographic projection of the fifth side of the second conductive trace on the substrate and the orthographic projection of the sixth side of the third conductive trace on the substrate is equal to 90°;

[0015] Optionally, the second conductive trace includes a seventh side portion, and the fifth side portion and the seventh side portion are located on two opposite sides of the second conductive trace;

[0016] The third conductive trace includes an eighth side; the sixth side and the eighth side are located on two opposite sides of the third conductive trace;

[0017] At the second overlapping region, an angle between an orthographic projection of the seventh side of the second conductive trace on the substrate and an orthographic projection of the eighth side of the third conductive trace on the substrate is equal to 90°;

[0018] At the second overlapping region, an angle between an orthographic projection of the seventh side of the second conductive trace on the substrate and an orthographic projection of the sixth side of the third conductive trace on the substrate is equal to 90°;

[0019] At the second overlapping region, an angle between an orthographic projection of a fifth side of the second conductive trace on the substrate and an orthographic projection of an eighth side of the third conductive trace on the substrate is equal to 90°;

[0020] Optionally, the second conductive trace is connected to a first initialization voltage;

[0021] Optionally, the third conductive trace is a first scan line.

[0022] In one embodiment, the display panel further includes a second semiconductor trace, and an orthographic projection of the second semiconductor trace on the substrate overlaps an orthographic projection of the third conductive trace on the substrate at a second overlapping region;

[0023] Optionally, the display panel further includes a pixel circuit, the pixel circuit includes a driving transistor and a first initialization transistor, the first initialization transistor is connected to a gate of the driving transistor, and the second semiconductor trace and the third conductive trace form at least a portion of the first initialization transistor at the second overlapping region;

[0024] Optionally, the first initialization transistor includes a first sub-transistor and a second sub-transistor connected in series, and the second semiconductor trace and the third conductive trace form the second sub-transistor at the second overlapping region;

[0025] Optionally, the pixel circuit further includes a second initialization transistor,

[0026] In two adjacent rows of pixel circuits, the second initialization transistors in the pixel circuits in the previous row and the first initialization transistors in the pixel circuits in the current row share the same scanning line;

[0027] The second sub-transistor is located between the first sub-transistor and the second initialization transistor;

[0028] Optionally, the second conductive trace extends along the first direction, the third conductive trace extends along the second direction, and the first direction and the second direction intersect;

[0029] Optionally, the second semiconductor trace extends along the first direction;

[0030] The orthographic projection of the second semiconductor trace on the substrate overlaps with the orthographic projection of the second conductive trace on the substrate at a second overlapping region;

[0031] Optionally, the second conductive trace is located on a side of the third conductive trace away from the substrate;

[0032] Optionally, the second conductive trace is disposed on the same layer as the first conductive trace, and the first semiconductor trace is disposed on the same layer as the second semiconductor trace;

[0033] Optionally, the fifth side portion and / or the seventh side portion extend along the first direction; the sixth side portion and / or the eighth side portion extend along the second direction;

[0034] Optionally, a second insulating layer is provided between the second conductive trace and the third conductive trace.

[0035] In one embodiment, the display panel further comprises: an organic layer located on a side of the first conductive trace and the first semiconductor trace away from the substrate;

[0036] Optionally, at the second overlapping region, a second groove is provided on a surface of the organic layer away from the substrate;

[0037] Optionally, in a direction parallel to the substrate, a width of the second groove is greater than or equal to 0.5 μm and less than or equal to 1 μm; in a direction perpendicular to the substrate, a depth of the second groove is greater than or equal to 0.2 μm and less than or equal to 0.5 μm;

[0038] Optionally, the second groove comprises a side wall portion and a groove bottom that are connected to each other, and an area of ​​a cross section of the second groove parallel to the substrate gradually increases along a direction from the substrate to the organic layer;

[0039] Optionally, the angle between the side wall portion of the second groove and the bottom of the groove is an obtuse angle;

[0040] Optionally, the angle between the side wall portion of the second groove and the groove bottom is greater than or equal to 155° and less than or equal to 165°;

[0041] Optionally, the display panel further comprises: a pixel defining layer, the pixel defining layer is provided with a pixel opening, and an orthographic projection of the pixel opening on the substrate is located outside the second overlapping region and / or an orthographic projection of the second groove on the substrate;

[0042] Optionally, the pixel defining layer is located on a side of the organic layer away from the substrate, the pixel defining layer covers the second groove, and a side of the pixel defining layer away from the second groove is recessed.

[0043] In one embodiment, the first conductive trace is a data line;

[0044] Optionally, the display panel further includes a pixel circuit, the pixel circuit includes a driving transistor and a data writing transistor, and the data writing transistor is connected between the data line and the first electrode of the driving transistor;

[0045] Optionally, the first conductive trace extends along a first direction.

[0046] In one embodiment, the first conductive trace is located on a side of the first semiconductor trace away from the substrate;

[0047] and / or, the first conductive trace is connected to the first semiconductor trace through a first via at the first overlapping region;

[0048] And / or, a first insulating layer is disposed between the first conductive wiring and the first semiconductor wiring.

[0049] In one embodiment, it further includes: an organic layer located on a side of the first conductive trace and the first semiconductor trace away from the substrate;

[0050] Optionally, at the first overlapping region, a first groove is provided on a surface of the organic layer away from the substrate;

[0051] Optionally, in a direction parallel to the substrate, a width of the first groove is greater than or equal to 0.5 μm and less than or equal to 1 μm; in a direction perpendicular to the substrate, a depth of the first groove is greater than or equal to 0.2 μm and less than or equal to 0.5 μm;

[0052] Optionally, the first groove includes a side wall portion and a groove bottom that are connected to each other, and an area of ​​a cross section of the first groove parallel to the substrate gradually increases along a direction from the substrate to the organic layer;

[0053] Optionally, the angle between the side wall portion of the first groove and the bottom of the groove is an obtuse angle;

[0054] Optionally, the angle between the side wall portion of the first groove and the bottom of the groove is greater than or equal to 155° and less than or equal to 165°;

[0055] Optionally, the display panel further comprises: a pixel defining layer, the pixel defining layer is provided with a pixel opening, and an orthographic projection of the pixel opening on the substrate is located outside the first overlapping region and / or an orthographic projection of the first groove on the substrate;

[0056] Optionally, the pixel defining layer is located on a side of the organic layer away from the substrate, the pixel defining layer covers the first groove, and a side of the pixel defining layer away from the first groove is recessed.

[0057] In one embodiment, it further includes: an inorganic layer located between the substrate and the first semiconductor trace;

[0058] Optionally, the inorganic layer includes a first inorganic layer and a second inorganic layer which are stacked, and the first inorganic layer is located on a side of the second inorganic layer close to the substrate;

[0059] Optionally, the first inorganic layer comprises silicon nitride, and the second inorganic layer comprises silicon oxide;

[0060] Optionally, the substrate is a flexible substrate;

[0061] Optionally, the display panel includes at least one of a curved screen, a flexible folding screen, a flexible sliding screen and a flexible curling screen.

[0062] A second aspect of the present application provides a display device, comprising the aforementioned display panel.

[0063] In the display panel of the embodiment of the present application, when the first angle between the orthographic projection of the second edge of the first conductive trace on the substrate and the orthographic projection of the first edge of the first semiconductor trace on the substrate is greater than or equal to 90°, the stress concentration in the first conductive trace and the first semiconductor trace can be reduced, and then when the display panel is deformed, the stress in the local area can be released in time when it is repeatedly subjected to force, and the circuit will not be damaged and cause poor display. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 It is a schematic diagram of the cross-sectional structure of a display panel in one embodiment of the present application.

[0065] Figure 2 This is a schematic diagram of a partial top view of the structure of the first conductive trace and the first semiconductor trace in one embodiment of the present application.

[0066] Figure 3 This is a schematic diagram of a partial top view of the structure of the first conductive trace and the first semiconductor trace in another embodiment of the present application.

[0067] Figure 4This is a schematic diagram of the pixel circuit structure in one embodiment of the present application.

[0068] Figure 5 The figure is a schematic diagram of a top view of the structure of a display panel in one embodiment of the present application.

[0069] Figure 6 This is a schematic diagram of the top view of the second semiconductor trace and the third conductive trace in one embodiment of the present application.

[0070] Figure 7 This is a schematic diagram of the cross-sectional structure of a display panel in another embodiment of the present application.

[0071] Figure 8 This is a schematic diagram of the cross-sectional structure of a display panel in another embodiment of the present application.

[0072] Fig. 9 This is a schematic diagram of the cross-sectional structure of a display panel in another embodiment of the present application.

[0073] Fig.10 This is a structural schematic diagram of the orthographic projection of a pixel opening, a first groove, and a second groove on a substrate in one embodiment of the present application.

[0074] Fig.11 This is a schematic diagram of the cross-sectional structure of a display panel in another embodiment of the present application.

[0075] Fig.12 This is a schematic diagram of the cross-sectional structure of a display panel in another embodiment of the present application. DETAILED DESCRIPTION

[0076] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0077] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0078] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0079] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0080] The present application provides a display panel according to a first aspect. Figure 1 The cross-sectional structure diagram of the display panel shown in FIG. Figure 2 and Figure 3 The display panel shown is a schematic diagram of a top view structure. The display panel includes: a substrate 100 , a first semiconductor wiring 200 and a first conductive wiring 300 .

[0081] The first semiconductor trace 200 is located on the substrate 100, and the first semiconductor trace 200 includes a first edge 210; the first conductive trace 300 and the first semiconductor trace 200 are stacked along the thickness direction of the substrate 100, and the first conductive trace 300 includes a second edge 310, and the orthographic projection of the first conductive trace 310 on the substrate 100 and the orthographic projection of the first semiconductor trace 200 on the substrate have a first overlapping area A; the orthographic projection of the second edge 310 of the first conductive trace 300 on the substrate 100 overlaps with the orthographic projection of the first edge 210 of the first semiconductor trace 200 on the substrate 100, and a first angle α1 between the two is greater than or equal to 90° (for example, it can be 90°, 95°, 100°, 105°, 110°, 115°, 120°, etc.), and the first angle α1 is located outside the orthographic projections of the first semiconductor trace 200 and the first conductive trace 300 on the substrate 100.

[0082] It is understandable that, referring to Figure 2 and Figure 3 , at the first overlapping area A, the orthographic projections of part of the first side portion 210 and part of the second side portion 310 on the substrate 100 form the edge of the orthographic projection of the overlapping area A on the substrate 100; the remaining part of the first side portion 210 extends in a direction away from the first overlapping area A, and the remaining part of the second side portion 310 extends in a direction away from the first overlapping area A, and the angle between the extended second side portion 310 and the orthographic projection of the first side portion 210 on the substrate 100 is α1.

[0083] There are differences in the performance of the first semiconductor trace 200 and the first conductive trace 300, such as differences in ductility and bending resistance, etc., which leads to the risk of breakage when the angle between the first semiconductor trace 200 and the first conductive trace 300 at the first overlapping area A of the orthographic projection on the substrate 100 is acute; while in the display panel of the embodiment of the present application, at the first overlapping area A, when the first angle α1 of the orthographic projection of the first edge 210 of the first semiconductor trace 200 and the second edge 310 of the first conductive trace 300 is greater than or equal to 90°, the concentration of stress in the first semiconductor trace 200 and the first conductive trace 300 can be reduced, and then when the display panel is deformed, the stress in the local area can be released in time when it is repeatedly subjected to force, and the circuit will not be damaged to cause poor display.

[0084] For example, the first semiconductor trace 200 may be located in an active layer, such as a polysilicon layer or a semiconductor metal oxide layer, and the first conductive trace 300 may be a metal trace.

[0085] In one embodiment, referring to Figure 3 , the first semiconductor routing 200 also includes a third side 220; the first side 210 and the third side 220 are located on opposite sides of the first semiconductor routing 200; the first conductive routing 300 also includes a fourth side 320, the second side 310 and the fourth side 320 are connected, the second side 310 and the fourth side 320 are located on the same side of the first conductive routing 300, the orthographic projection of the fourth side 320 of the first conductive routing 300 on the substrate 100 overlaps with the orthographic projection of the third side 220 of the first semiconductor routing 200 on the substrate 100, and the angle α2 between the two is greater than or equal to 90° (for example, it can be 90°, 95°, 100°, 105°, 110°, 115°, 120°, etc.), and the second angle α2 is located outside the orthographic projections of the first semiconductor routing 200 and the first conductive routing 300 on the substrate 100.

[0086] Exemplarily, the orthographic projection of the fourth side portion 320 on the substrate 100 coincides with the edge of the orthographic projection of the first overlapping region A on the substrate 100. It can be understood that, referring to Figure 3 , at the first overlapping area A, the orthographic projection of the fourth side 320 on the substrate 100 forms the edge of the orthographic projection of the first overlapping area A on the substrate 100, the third side 220 extends in a direction away from the first overlapping area A, and the angle between the orthographic projection of the third side 220 extending in the direction away from the first overlapping area A on the substrate 100 and the orthographic projection of the fourth side 320 on the substrate 100 is α2.

[0087] An angle α2 greater than or equal to 90° can reduce the concentration of stress in the first semiconductor wiring 200 and the first conductive wiring 300. When the display panel is deformed, the stress in the local area can be released in time when it is repeatedly stressed, and the line will not be damaged to cause poor display.

[0088] In one embodiment, the fourth side portion 320 extends along the first direction x.

[0089] In a specific embodiment, the first conductive trace 300 is located on a side of the first semiconductor trace 200 away from the substrate 100 ; a first insulating layer is disposed between the first conductive trace 300 and the first semiconductor trace 200 .

[0090] In other embodiments, the first conductive trace 300 is located on a side of the first semiconductor trace 200 close to the substrate 100. A first insulating layer is disposed between the first conductive trace 300 and the first semiconductor trace 200.

[0091] In one embodiment, the first conductive trace 300 is connected to the first semiconductor trace 200 through the first via 111 at the first overlapping region A. Exemplarily, the first via 111 is opened in the first insulating layer (not shown in the figure), and the first conductive trace 300 is connected to the first semiconductor trace 200 after filling the first via 111.

[0092] In one embodiment, the first conductive trace 300 is a data line (used to transmit a data voltage Vdata).

[0093] In one embodiment, referring to Figure 4 As shown in the structural diagram of the pixel circuit, the display panel further includes a pixel circuit 700. The pixel circuit 700 includes T1 and a data writing transistor T2. The data writing transistor T2 is connected between the data line and the first electrode of the driving transistor T1.

[0094] Optionally, the first conductive trace 300 extends along a first direction x. For example, a plurality of data lines may be arranged along a second direction y. The first direction x intersects with the second direction y, for example, perpendicularly.

[0095] In one embodiment, referring to Figure 5The schematic diagram of the top view structure of the display panel shown in the figure, the display panel also includes: a second conductive trace 400 and a third conductive trace 500, the second conductive trace 400 and the third conductive trace 500 are stacked along the thickness direction Z of the substrate 100; the second conductive trace 400 includes a fifth edge 410, and the third conductive trace 500 includes a sixth edge 510; the orthographic projection of the second conductive trace 400 on the substrate 100 and the orthographic projection of the third conductive trace 500 on the substrate 100 have a second overlapping area B; at the second overlapping area B, the angle α3 between the orthographic projection of the fifth edge 410 of the second conductive trace 400 on the substrate 100 and the orthographic projection of the sixth edge 510 of the third conductive trace 500 on the substrate 100 is equal to 90°. This helps to avoid the risk of film breakage caused by the sharp angle between the second conductive trace 400 and the third conductive trace 500. When the display panel is deformed, the stress in the second overlapping area B can be released in time when it is repeatedly stressed, and the line will not be damaged to cause poor display.

[0096] In one embodiment, the second conductive trace 400 includes a seventh side 420, and the fifth side 410 and the seventh side 420 are located on opposite sides of the second conductive trace 400; the third conductive trace 500 includes an eighth side 520; the sixth side 510 and the eighth side 520 are located on opposite sides of the third conductive trace 500; at the second overlapping region B, the angle α4 between the orthographic projection of the seventh side 420 of the second conductive trace 400 on the substrate 100 and the orthographic projection of the eighth side 520 of the third conductive trace 500 on the substrate 100 is equal to 90°. Thus, the risk of film fracture caused by the sharp angle between the second conductive trace 400 and the third conductive trace 500 can be further avoided, and when the display panel is deformed, the stress in the second overlapping region B can be released in time when repeatedly subjected to force, and the circuit will not be damaged to cause poor display.

[0097] For example, at the second overlapping region B, the angle α5 between the orthographic projection of the seventh side 420 of the second conductive trace 400 on the substrate 100 and the orthographic projection of the sixth side 510 of the third conductive trace 500 on the substrate 100 is equal to 90°. Thus, the risk of film breakage caused by the sharp angle between the second conductive trace 400 and the third conductive trace 500 can be further avoided, and when the display panel is deformed, the stress in the second overlapping region B can be released in time when repeatedly subjected to force, and the circuit will not be damaged to cause poor display.

[0098] For example, at the second overlapping region B, the angle α6 between the orthographic projection of the fifth side 410 of the second conductive trace 400 on the substrate 100 and the orthographic projection of the eighth side 520 of the third conductive trace 500 on the substrate 100 is equal to 90°. Thus, the risk of film breakage caused by the sharp angle between the second conductive trace 400 and the third conductive trace 500 can be further avoided, and when the display panel is deformed, the stress in the second overlapping region B can be released in time when repeatedly subjected to force, and the circuit will not be damaged to cause poor display.

[0099] Optionally, the second conductive line 400 is connected to the first initialization voltage Vref1; the third conductive line 500 is the first scan line S1.

[0100] In one embodiment, referring to Figure 5 The display panel further includes a second semiconductor trace 600 , and an orthographic projection of the second semiconductor trace 600 on the substrate 100 overlaps with an orthographic projection of the third conductive trace 500 on the substrate 100 at a second overlapping region B.

[0101] In one embodiment, referring to Figure 4 The display panel also includes a pixel circuit 700, which includes a driving transistor T1 and a first initialization transistor T4, the first initialization transistor T4 is connected to the gate of the driving transistor T1, and the second semiconductor wiring 600 and the third conductive wiring 500 form at least a portion of the first initialization transistor T4 (for example, the second sub-transistor T4-2) at the second overlapping area B.

[0102] Optionally, the pixel circuit 700 further includes a driving transistor T1 and a first initialization transistor T4, the driving transistor is connected between the first power line 604 (which can be used to transmit the first power supply voltage VDD) and the first electrode of the light-emitting device D1, the gate of the first initialization transistor T4 is connected to the first scan line S1, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line (which can be used to transmit the first initialization voltage Vrfe1), and the second electrode of the first initialization transistor T4 is connected to the gate or the second electrode of the driving transistor T1. The first initialization transistor T4 can be a dual-gate transistor, for example, including a first sub-transistor T4-1 and a second sub-transistor T4-2 connected in series.

[0103] Optionally, the pixel circuit 700 includes a second initialization transistor T7, a gate of the second initialization transistor T7 is connected to the third scan line S3, a first electrode of the second initialization transistor T7 is connected to a second initialization signal line 601 (which can be used to transmit a second initialization voltage Vrfe2), and a second electrode of the second initialization transistor T7 is connected to a first electrode of the light-emitting device D1. The second initialization signal line 601 is connected to a connection line 602 through a fifth via 115, and the connection line 602 is connected to the second initialization transistor T7 through a sixth via 116. For example, the fifth via 115 and the sixth via 116 are located on opposite sides of the first scan line S1 along the first direction x.

[0104] Optionally, the pixel circuit 700 further includes a data writing transistor T2, a gate of the data writing transistor T2 is connected to the second scanning line S2, a first electrode of the data writing transistor T2 is connected to the data line Vdata, and a second electrode of the data writing transistor T2 is connected to the first electrode of the driving transistor T1.

[0105] Optionally, the pixel circuit 700 further includes a storage capacitor C, a first electrode of the storage capacitor C is connected to the gate of the driving transistor T1, and a second electrode of the storage capacitor C is connected to a first power line (which can be used to transmit a first power voltage VDD).

[0106] Optionally, the pixel circuit 700 further includes a threshold compensation transistor T3, the gate of the threshold compensation transistor T3 is connected to the second scan line S2, the first electrode of the threshold compensation transistor T3 is connected to the second electrode of the driving transistor T1, and the second electrode of the threshold compensation transistor T3 is connected to the gate of the driving transistor T1. The threshold compensation transistor T3 may be a dual-gate transistor, for example, including a third sub-transistor T3-1 and a fourth sub-transistor T3-2 connected in series.

[0107] Optionally, the pixel circuit 700 also includes a first light-emitting control transistor T5 and / or a second light-emitting control transistor T6, the gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM, the first electrode of the first light-emitting control transistor T5 is connected to the first power line (which can be used to transmit the first power supply voltage VDD), the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1, the gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM, the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the second light-emitting control transistor T6 is connected to the first electrode (for example, the anode) of the light-emitting device D1.

[0108] Optionally, the second electrode (eg, cathode) of the light emitting device D1 may be connected to a second power line (which may be used to transmit a second power voltage VSS).

[0109] For example, in two adjacent rows of pixel circuits 700, the second initialization transistors T7 in the previous row of pixel circuits 700 and the first initialization transistors T4 in the current row of pixel circuits 700 share the same scan line. For example, the row direction is parallel to the second direction y or the extension direction of the first scan line S1.

[0110] For example, refer to Figure 5 The second initialization transistor T7 in the pixel circuit 700 of the nth row and the first initialization transistor T4 in the pixel circuit 700 of the (n+1)th row share the same scan line, where n is an integer greater than or equal to 1.

[0111] For example, the second sub-transistor T4-2 is located between the first sub-transistor T4-1 and the second initialization transistor T7. For example, the second sub-transistor T4-2 in the n+1th row pixel circuit 700 is located between the first sub-transistor T4-1 in the n+1th row pixel circuit 700 and the second initialization transistor T7 in the nth row pixel circuit 700.

[0112] For example, the second sub-transistor T4 - 2 is connected to the second conductive trace 400 through the fourth via 114 .

[0113] For example, one of the first power supply voltage VDD and the second power supply voltage VSS is a high voltage, and the other is a low voltage. Exemplarily, the pixel circuit 700 may adopt a 7T1C circuit, where "T" refers to TFT (thin film transistor) and "C" refers to capacitor.

[0114] For example, refer to Figure 5 There is a second insulating layer (not shown in the figure) between the second conductive trace 400 and the third conductive trace 500.

[0115] In one embodiment, the second conductive trace 400 extends along a first direction x, and the third conductive trace 500 extends along a second direction y, and the first direction x intersects with the second direction y. Exemplarily, the first direction x and the second direction y are perpendicular to each other.

[0116] In one embodiment, referring to Figure 5 and Figure 6 , the second semiconductor trace 600 extends along the first direction x; the orthographic projection of the second semiconductor trace 600 on the substrate 100 overlaps with the orthographic projection of the second conductive trace 400 on the substrate 100 at the second overlapping region B. Figure 6 Can Figure 5 The second semiconductor wiring 600 and the third conductive wiring 500 form a second sub-transistor T4-2 at the second overlapping region B.

[0117] In one embodiment, the second conductive trace 400 is located on a side of the third conductive trace 500 away from the substrate 100 .

[0118] Exemplarily, the second conductive trace 400 and the first conductive trace 300 are disposed on the same layer, and the first semiconductor trace 200 and the second semiconductor trace 600 are disposed on the same layer.

[0119] In other embodiments, the second conductive trace 400 is located on a side of the third conductive trace 500 close to the substrate 100 .

[0120] Exemplarily, the fifth side portion 410 and / or the seventh side portion 420 extend along the first direction x; and / or the sixth side portion 510 and / or the eighth side portion 520 extend along the second direction y.

[0121] For example, refer to Figure 5 The display panel further includes part or all of the second via hole 112, the third via hole 113, the fourth via hole 114, the fifth via hole 115, and the sixth via hole 116, wherein the third via hole 113, the fourth via hole 114, and the sixth via hole 116 are used to connect the conductive traces with the semiconductor traces, and the second via hole 112 and the fifth via hole 115 are used to connect the conductive traces. It can be understood that the second via hole 112, the third via hole 113, the fourth via hole 114, the fifth via hole 115, and the sixth via hole 116 can be via holes opened in the insulating layer between the film layers to be connected. Figure 5 The insulating layer is not shown, and only the relative positions of the second via hole 112 , the third via hole 113 , the fourth via hole 114 , the fifth via hole 115 and the sixth via hole 116 are indicated by dotted lines, which should not be construed as a limitation to the present application.

[0122] In one embodiment, referring to Figure 7 and Figure 8 The cross-sectional structure diagram of the display panel shown in the figure further includes: an organic layer 800 located on a side of the first conductive wiring 300 and the first semiconductor wiring 200 away from the substrate 100 .

[0123] In one embodiment, at the first overlapping region A, a first groove 810 is provided on the surface of the organic layer 800 away from the substrate 100. As a result, the stress is mainly concentrated in the region outside the first groove 810 in the organic layer 800, and the stress shared in the organic layer 800 corresponding to the first groove 810 is less, which effectively avoids the concentration of stress in the first overlapping region A, and further effectively avoids the display failure caused by the breakage of the film layer and the damage of the circuit. It should be noted that Figure 5 The positions of the first groove 810 and the second groove 820 are indicated by dashed lines only, which are only used to explain the present application and should not be construed as limiting the present application.

[0124] In one embodiment, in a direction parallel to the substrate 100, the width of the first groove 810 is greater than or equal to 0.5 μm and less than or equal to 1 μm, for example, it may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm, etc.; in a direction perpendicular to the substrate 100, the depth of the first groove 810 is greater than or equal to 0.2 μm and less than or equal to 0.5 μm, for example, it may be 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm, etc.; the size of the first groove 810 is appropriate, and the effect of avoiding stress concentration is better.

[0125] It should be noted that the width of the first groove 810 indicates the maximum distance between any two points in the first groove 810 in a direction parallel to the substrate 100, and the depth of the first groove 810 refers to the maximum distance between any two points in the first groove 810 in a direction perpendicular to the substrate 100.

[0126] It is understandable that the cross-sectional shape of the first groove 810 perpendicular to the substrate can be a regular shape such as an inverted trapezoid, a semicircle, a triangle, etc., or an irregular shape. As long as the requirements can be met, technicians in this field can flexibly choose according to actual conditions.

[0127] In one embodiment, the first groove 810 includes a sidewall portion 811 and a groove bottom 812 connected to each other, and the area of ​​the cross section of the first groove 810 parallel to the substrate 100 gradually increases in the direction from the substrate 100 to the organic layer 800. Thus, the cross-sectional shape of the first groove 810 is an inverted trapezoid, and the effect of relieving stress concentration in the groove area is better.

[0128] In one embodiment, the angle β between the side wall portion 811 of the first groove 810 and the groove bottom 812 is an obtuse angle; optionally, the angle β between the side wall portion 811 of the first groove 810 and the groove bottom 812 is greater than or equal to 155° and less than or equal to 165°, for example, it can be 155°, 157°, 160°, 162° or 165°, etc.; thus, the slope of the inclined portion of the first groove 810 is smaller, which is more conducive to alleviating stress concentration.

[0129] In one embodiment, at the second overlapping region B, a second groove 820 is disposed on a surface of the organic layer 800 away from the substrate 100 .

[0130] In one embodiment, in a direction parallel to the substrate 100, the width of the second groove 820 is greater than or equal to 0.5 μm and less than or equal to 1 μm, for example, it can be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm, etc.; in a direction perpendicular to the substrate 100, the depth of the second groove is greater than or equal to 0.2 μm and less than or equal to 0.5 μm, for example, it can be 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm, etc. Therefore, the size of the second groove 820 is appropriate, and the effect of avoiding stress concentration is better.

[0131] It should be noted that the width of the second groove 820 indicates the maximum distance between any two points in the second groove 820 in a direction parallel to the substrate 100, and the depth of the second groove 820 refers to the maximum distance between any two points in the second groove 820 in a direction perpendicular to the substrate 100.

[0132] It is understandable that the cross-sectional shape of the second groove 820 perpendicular to the substrate can be a regular shape such as an inverted trapezoid, a semicircle, a triangle, etc., or an irregular shape. As long as the requirements can be met, technicians in this field can flexibly choose according to actual conditions.

[0133] In one embodiment, the second groove 820 includes a sidewall portion and a groove bottom that are connected to each other, and the area of ​​the cross section of the second groove 820 parallel to the substrate 100 gradually increases in the direction from the substrate 100 to the organic layer 800. Thus, the cross-sectional shape of the second groove 820 is an inverted trapezoid, and the effect of relieving stress concentration in the area where the second groove is located is better.

[0134] In one embodiment, the angle between the side wall portion of the second groove 820 and the bottom of the groove is an obtuse angle; optionally, the angle between the side wall portion of the second groove 820 and the bottom of the groove is greater than or equal to 155° and less than or equal to 165°, for example, it can be 155°, 157°, 160°, 162° or 165°, etc.; thus, the slope of the inclined portion of the second groove 820 is smaller, which is more conducive to alleviating stress concentration.

[0135] For example, the display panel further includes a shielding portion 603, and the shielding portion 603 is connected to the first power line 604 through the second via 112. At least part of the shielding portion 603 may be located between the gate connection line 605 and the data line 300, and the shielding portion 603 may shield the signal interference between the gate connection line 605 and the data line 300. For example, the gate connection line 605 is connected to the gate of the driving transistor T1, for example, the gate connection line 605 is connected to the first initialization transistor T and the threshold compensation transistor T3, for example, the gate connection line 605 is connected to the gate of the driving transistor T1 through the third via 113. The orthographic projection of the shielding portion 603 on the substrate overlaps with the orthographic projection of the active portion of the threshold compensation transistor T3 (for example, the active portion between the third sub-transistor T3-1 and the fourth sub-transistor T3-2) on the substrate, and a coupling capacitor may be formed to stabilize the voltage of the intermediate node between the third sub-transistor T3-1 and the fourth sub-transistor T3-2, so as to reduce the leakage current of the threshold compensation transistor T3. For example, the film layer where the shielding portion 603 is located is located between the film layer where the first conductive trace 300 or the second conductive trace 400 is located and the film layer where the third conductive trace 500 is located. For example, the shielding portion 603 and the second initialization signal line 601 are arranged in the same layer.

[0136] In one embodiment, referring to Fig. 9 The cross-sectional structure diagram of the display panel shown in FIG. Fig.10 The schematic diagram of the positional relationship between the pixel opening and the first groove and the second groove is shown, and the display panel further includes: a pixel defining layer 900, the pixel defining layer 900 is provided with a pixel opening 910, and the orthographic projection of the pixel opening 910 on the substrate 100 is located outside the first overlapping area A and / or the orthographic projection of the first groove 810 on the substrate 100. Therefore, the setting of the first groove 810 will not affect the pixel opening 910, and further will not affect the flatness of the light-emitting device 50 located in the pixel opening 910, and will hardly affect the display effect of the display panel.

[0137] Exemplarily, the light emitting device 50 includes a first electrode layer 51 (or first electrode), a light emitting functional layer 52, and a second electrode layer 53 (or second electrode) which are stacked, and the first electrode layer 51 is located on a side of the light emitting functional layer 52 close to the substrate 100. The light emitting device 50 is a conventional light emitting device and will not be described in detail herein.

[0138] In one embodiment, an orthographic projection of the pixel opening 910 on the substrate 100 is located outside an orthographic projection of the second overlapping region B and / or the second groove 820 on the substrate 100 .

[0139] Optionally, refer to Fig.11, the pixel defining layer 900 is located on the side of the organic layer 800 away from the substrate 100, the pixel defining layer 900 covers the first groove 810, and the side of the pixel defining layer 900 away from the first groove 810 is recessed. It can be understood that the recess on the side of the pixel defining layer 900 away from the first groove 810 is arranged corresponding to the first groove 810, and the width of the recess can be the same as the width of the first groove 810, and / or the depth of the recess can be the same as the depth of the first groove 810.

[0140] Optionally, the pixel defining layer 900 covers the second groove 820, and the side of the pixel defining layer 900 away from the second groove 820 is recessed. It can be understood that the recess of the side of the pixel defining layer 900 away from the second groove 820 can refer to the recess of the side of the pixel defining layer 900 away from the first groove 810, and will not be described in detail here.

[0141] For example, refer to Figure 5 and Fig.10 , the display panel also includes a semiconductor layer 10 .

[0142] For example, the display panel further includes a first conductive layer 20, which is located on a side of the semiconductor layer 10 away from the substrate 100. A gate insulating layer (GI) 11 is provided between the first conductive layer 20 and the semiconductor layer 10. The gate insulating layer may be an inorganic insulating layer.

[0143] For example, the display panel further includes a second conductive layer 30, which is located on a side of the first conductive layer 20 away from the substrate 100, and a capacitance insulating layer (CI) 21 is provided between the first conductive layer 20 and the second conductive layer 30. The capacitance insulating layer may be an inorganic insulating layer.

[0144] For example, the display panel further includes a third conductive layer 40, which is located on a side of the second conductive layer 30 away from the substrate 100, and an interlayer dielectric layer (ILD) 31 is provided between the second conductive layer 30 and the third conductive layer 40. The interlayer dielectric layer may be an inorganic insulating layer.

[0145] For example, the semiconductor layer 10 includes the first semiconductor trace 200 and the second semiconductor trace 600 , the first conductive layer 20 includes the third conductive trace 500 , and the third conductive layer 40 includes the first conductive trace 300 and the second conductive trace 400 . The second conductive layer 30 may include a shielding portion 603 and a second initialization signal line 601 .

[0146] In one embodiment, referring to Fig.12The structural diagram of the display panel shown in the figure, the display panel also includes: an inorganic layer 1000, which is located between the substrate 100 and the first semiconductor wiring 200. For example, when the substrate is a flexible substrate, it is necessary to fix the substrate on a rigid substrate such as a glass surface before preparing the subsequent film layer. After the preparation is completed, the rigid substrate needs to be removed. At this time, laser removal is required. The inorganic layer 1000 can absorb or block the laser to protect the inorganic layer 1000 from the film layer on one side of the substrate 100.

[0147] In one embodiment, the inorganic layer 1000 includes a first inorganic layer 1100 and a second inorganic layer 1200 which are stacked, and the first inorganic layer 1100 is located on a side of the second inorganic layer 1200 close to the substrate 100; illustratively, the first inorganic layer 1100 includes silicon nitride, and the second inorganic layer 1200 includes silicon oxide.

[0148] Exemplarily, the substrate 100 is a flexible substrate 100 .

[0149] Optionally, the display panel includes at least one of a curved screen (eg, a fixed curved screen), a flexible folding screen, a flexible sliding screen, and a flexible rolling screen.

[0150] A second aspect of the present application provides a method for preparing a display panel, which comprises the following steps.

[0151] S100: preparing a semiconductor layer on a substrate.

[0152] It should be noted that the substrate is consistent with the previous description and will not be elaborated here.

[0153] It should be noted that the semiconductor layer includes the first semiconductor wiring and the second semiconductor wiring described above.

[0154] S200: preparing a first conductive layer on a side of the semiconductor layer away from the substrate.

[0155] It should be noted that the first conductive layer includes the third conductive trace described above, and the first conductive layer is consistent with the above description, which will not be described in detail here.

[0156] It should be noted that this embodiment can be combined with the previously described embodiments in part or in whole, and will not be described in detail here.

[0157] In one embodiment, the method for preparing a display panel further includes the following steps.

[0158] S300: preparing a second conductive layer on a side of the first conductive layer away from the substrate.

[0159] It should be noted that the display panel includes a pixel circuit, and the second conductive layer is an upper electrode layer of the capacitor; the second conductive layer is consistent with the above description and will not be described in detail here.

[0160] In one embodiment, the method for preparing a display panel further includes the following steps.

[0161] S400: preparing a third conductive layer on a side of the second conductive layer away from the substrate.

[0162] It should be noted that the third conductive layer includes the first conductive trace and the second conductive trace described above. The third conductive layer is consistent with the above description and will not be described in detail here.

[0163] In one embodiment, the method for preparing a display panel further includes the following steps.

[0164] S500: preparing an organic layer on a side of the third conductive layer away from the substrate.

[0165] It should be noted that the organic layer is consistent with the previous description and will not be elaborated here.

[0166] Illustratively, after the organic layer is prepared, a first groove and a second groove are opened on the surface of the organic layer away from the substrate. The first groove and the second groove are consistent with the above description and will not be described in detail herein.

[0167] The third aspect of the present application provides a display device, which includes the above-mentioned display panel. The display panel of the embodiment of the present application has high bending resistance and almost no display defects caused by broken wires.

[0168] It is understandable that, in addition to the above-mentioned display panel, the display device may also include structures that a conventional display device should have, such as a housing, a power supply, etc., which will not be elaborated herein.

[0169] Exemplarily, the display device is a flexible display device, which can be applied to application scenarios such as wearable devices, mobile phones, tablets, and computers.

[0170] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0171] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A display panel, characterized in that: include: substrate; A first semiconductor trace, located on the substrate, the first semiconductor trace comprising a first edge; A first conductive trace, wherein the first conductive trace and the first semiconductor trace are stacked along the thickness direction of the substrate, the first conductive trace comprises a second side portion, and an orthographic projection of the first conductive trace on the substrate and an orthographic projection of the first semiconductor trace on the substrate have a first overlapping region; an orthographic projection of the second side portion of the first conductive trace on the substrate overlaps with an orthographic projection of the first side portion of the first semiconductor trace on the substrate, and a first angle between the two is greater than or equal to 90°, and the first angle is outside the orthographic projections of the first semiconductor trace and the first conductive trace on the substrate.

2. The display panel according to claim 1, characterized in that: The first semiconductor routing line further includes a third side portion; the first side portion and the third side portion are located on two opposite sides of the first semiconductor routing line; The first conductive trace further includes a fourth side, the second side is connected to the fourth side, the second side and the fourth side are located on the same side of the first conductive trace, an orthographic projection of the fourth side of the first conductive trace on the substrate overlaps with an orthographic projection of the third side of the first semiconductor trace on the substrate, and a second angle between the two is greater than or equal to 90°, and the second angle is located outside the orthographic projections of the first semiconductor trace and the first conductive trace on the substrate; Preferably, the fourth side portion extends along the first direction; Preferably, the orthographic projection of the fourth side portion on the substrate coincides with an edge of the orthographic projection of the first overlapping region on the substrate.

3. The display panel according to claim 1, characterized in that: Also includes: A second conductive trace and a third conductive trace, wherein the second conductive trace and the third conductive trace are stacked along a thickness direction of the substrate; The second conductive trace includes a fifth side portion, and the third conductive trace includes a sixth side portion; There is a second overlapping area between the orthographic projection of the second conductive trace on the substrate and the orthographic projection of the third conductive trace on the substrate; at the second overlapping area, an angle between the orthographic projection of the fifth side of the second conductive trace on the substrate and the orthographic projection of the sixth side of the third conductive trace on the substrate is equal to 90°; Preferably, the second conductive trace comprises a seventh side, and the fifth side and the seventh side are located on two opposite sides of the second conductive trace; The third conductive trace comprises an eighth side; the sixth side and the eighth side are located on two opposite sides of the third conductive trace; At the second overlapping region, an angle between an orthographic projection of the seventh side of the second conductive trace on the substrate and an orthographic projection of the eighth side of the third conductive trace on the substrate is equal to 90°; At the second overlapping region, an angle between an orthographic projection of the seventh side of the second conductive trace on the substrate and an orthographic projection of the sixth side of the third conductive trace on the substrate is equal to 90°; At the second overlapping region, an angle between an orthographic projection of the fifth side of the second conductive trace on the substrate and an orthographic projection of the eighth side of the third conductive trace on the substrate is equal to 90°; Preferably, the second conductive trace is connected to a first initialization voltage; Preferably, the third conductive trace is a first scanning line.

4. The display panel according to claim 3, characterized in that: The display panel further includes a second semiconductor trace, an orthographic projection of the second semiconductor trace on the substrate overlaps with an orthographic projection of the third conductive trace on the substrate at the second overlapping region; Preferably, the display panel further comprises a pixel circuit, the pixel circuit comprises a driving transistor and a first initialization transistor, the first initialization transistor is connected to a gate of the driving transistor, and the second semiconductor trace and the third conductive trace form at least a part of the first initialization transistor at the second overlapping region; Preferably, the first initialization transistor comprises a first sub-transistor and a second sub-transistor connected in series, and the second semiconductor trace and the third conductive trace form the second sub-transistor at the second overlapping region; Preferably, the pixel circuit further comprises a second initialization transistor, In two adjacent rows of pixel circuits, the second initialization transistors in the pixel circuits in the previous row and the first initialization transistors in the pixel circuits in the current row share the same scanning line; The second sub-transistor is located between the first sub-transistor and the second initialization transistor; Preferably, the second conductive trace extends along a first direction, the third conductive trace extends along a second direction, and the first direction and the second direction intersect; Preferably, the second semiconductor trace extends along a first direction; The orthographic projection of the second semiconductor trace on the substrate overlaps with the orthographic projection of the second conductive trace on the substrate at the second overlapping region; Preferably, the second conductive trace is located on a side of the third conductive trace away from the substrate; Preferably, the second conductive trace is arranged on the same layer as the first conductive trace, and the first semiconductor trace is arranged on the same layer as the second semiconductor trace; Preferably, the fifth side portion and / or the seventh side portion extend along the first direction; the sixth side portion and / or the eighth side portion extend along the second direction; Preferably, a second insulating layer is provided between the second conductive trace and the third conductive trace.

5. The display panel according to claim 3 or 4, characterized in that: The display panel further includes: an organic layer located on a side of the first conductive trace and the first semiconductor trace away from the substrate; Preferably, at the second overlapping region, a second groove is provided on a surface of the organic layer away from the substrate; Preferably, in a direction parallel to the substrate, the width of the second groove is greater than or equal to 0.5 μm and less than or equal to 1 μm; in a direction perpendicular to the substrate, the depth of the second groove is greater than or equal to 0.2 μm and less than or equal to 0.5 μm; Preferably, the second groove comprises a side wall portion and a groove bottom connected to each other, and an area of ​​a cross section of the second groove parallel to the substrate gradually increases along a direction from the substrate to the organic layer; Preferably, the angle between the side wall portion of the second groove and the bottom of the groove is an obtuse angle; Preferably, the angle between the side wall portion of the second groove and the bottom of the groove is greater than or equal to 155° and less than or equal to 165°; Preferably, the display panel further comprises: a pixel defining layer, the pixel defining layer being provided with a pixel opening, the orthographic projection of the pixel opening on the substrate being located outside the orthographic projection of the second overlapping region and / or the second groove on the substrate; Preferably, the pixel defining layer is located on a side of the organic layer away from the substrate, the pixel defining layer covers the second groove, and a side of the pixel defining layer away from the second groove is recessed.

6. The display panel according to claim 1, characterized in that: The first conductive trace is a data line; Preferably, the display panel further comprises a pixel circuit, the pixel circuit comprises a driving transistor and a data writing transistor, the data writing transistor is connected between a data line and a first electrode of the driving transistor; Preferably, the first conductive trace extends along a first direction.

7. The display panel according to claim 1, characterized in that: The first conductive trace is located on a side of the first semiconductor trace away from the substrate; and / or, the first conductive trace is connected to the first semiconductor trace through a first via at the first overlapping region; And / or, a first insulating layer is provided between the first conductive wiring and the first semiconductor wiring.

8. The display panel according to claim 1, characterized in that: Also includes: an organic layer, located on a side of the first conductive trace and the first semiconductor trace away from the substrate; Preferably, at the first overlapping region, a first groove is provided on a surface of the organic layer away from the substrate; Preferably, in a direction parallel to the substrate, the width of the first groove is greater than or equal to 0.5 μm and less than or equal to 1 μm; in a direction perpendicular to the substrate, the depth of the first groove is greater than or equal to 0.2 μm and less than or equal to 0.5 μm; Preferably, the first groove comprises a side wall portion and a groove bottom connected to each other, and an area of ​​a cross section of the first groove parallel to the substrate gradually increases along a direction from the substrate to the organic layer; Preferably, the angle between the side wall portion of the first groove and the bottom of the groove is an obtuse angle; Preferably, the angle between the side wall portion of the first groove and the bottom of the groove is greater than or equal to 155° and less than or equal to 165°; Preferably, the display panel further comprises: a pixel defining layer, the pixel defining layer being provided with a pixel opening, the orthographic projection of the pixel opening on the substrate being located outside the orthographic projection of the first overlapping region and / or the first groove on the substrate; Preferably, the pixel defining layer is located on a side of the organic layer away from the substrate, the pixel defining layer covers the first groove, and a side of the pixel defining layer away from the first groove is recessed.

9. The display panel according to claim 1, characterized in that: Also includes: an inorganic layer, located between the substrate and the first semiconductor trace; Preferably, the inorganic layer comprises a first inorganic layer and a second inorganic layer which are stacked, and the first inorganic layer is located on a side of the second inorganic layer close to the substrate; Preferably, the first inorganic layer comprises silicon nitride, and the second inorganic layer comprises silicon oxide; Preferably, the substrate is a flexible substrate; Preferably, the display panel includes at least one of a curved screen, a flexible folding screen, a flexible sliding screen and a flexible curling screen.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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