Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a substrate, the substrate comprises a middle area and an edge area, and the edge area is located on the peripheral side of the middle area; the plurality of first data lines extend along the second direction, are arranged on the substrate at intervals along the first direction, and comprise a plurality of first data lines positioned in the edge area and a plurality of first data lines positioned in the middle area; the plurality of second data lines extend along the second direction and are arranged in the middle area of the substrate at intervals along the first direction; the plurality of connecting lines extend along a first direction and are used for connecting the plurality of first data lines and the plurality of second data lines in the edge area; the display panel further comprises a first conducting layer, a second conducting layer and a third conducting layer which are arranged on different layers, the first data line is arranged on the first conducting layer, at least part of the structure of the connecting line is located on the second conducting layer, and the second data line is arranged on the third conducting layer. Through the arrangement, the coupling capacitance can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of display panels, and in particular to a display panel and a display device. Background Art

[0002] In recent years, more and more terminal products (including mobile phones, tablets, and notebooks) have adopted OLED (Organic Light-Emitting Diode) display panels. While pursuing better display effects, customers have higher and higher requirements for the display form of the screen.

[0003] However, the borders of current mobile phones are relatively large, so there is an urgent need to develop new design solutions to reduce the borders. Summary of the invention

[0004] The purpose of the present application is to provide a display panel and a display device.

[0005] According to a first aspect of an embodiment of the present application, a display panel is provided, the display panel comprising:

[0006] A substrate, the substrate comprising a middle region and an edge region, wherein the edge region is located on a peripheral side of the middle region;

[0007] A plurality of first data lines, the plurality of first data lines extending along the second direction and spaced apart on the substrate along the first direction; the plurality of first data lines comprising a plurality of first data lines located in an edge region and a plurality of first data lines located in a middle region;

[0008] A plurality of second data lines extending along the second direction and spaced apart in a middle area of ​​the substrate along the first direction;

[0009] A plurality of connection lines are provided, and the plurality of connection lines extend along a first direction and are used to connect the plurality of first data lines and the plurality of second data lines located in an edge area.

[0010] Wherein, there is an angle greater than 0 between the first direction and the second direction;

[0011] The display panel further includes a first conductive layer, a second conductive layer, and a third conductive layer arranged in different layers. The first data line is arranged in the first conductive layer. At least part of the structure of the connecting line is located in the second conductive layer. The second data line is arranged in the third conductive layer.

[0012] In some embodiments, one second data line or multiple second data lines are disposed between two adjacent first data lines located in the middle area.

[0013] In some embodiments, a plurality of the connecting lines are spaced apart along the second direction.

[0014] In some embodiments, all of the plurality of connecting lines are located in the second conductive layer.

[0015] In some embodiments, the display panel is further provided with a plurality of first virtual data lines, and the plurality of first virtual data lines extend along the second direction;

[0016] Each of the second data lines is arranged in the same layer as a first virtual data line to form a first data line group, and the second data lines and the first virtual data lines in the first data line group are arranged on the same straight line extending along the second direction.

[0017] In some embodiments, the display panel is further provided with a plurality of second virtual data lines, and the plurality of second virtual data lines extend along the first direction;

[0018] Each of the connection lines is arranged in the same layer as a second virtual data line to form a second data line group, and the connection lines in the second data line group and the second virtual data lines are arranged on the same straight line extending along the first direction.

[0019] In some embodiments, the display panel is further provided with a plurality of third virtual data lines;

[0020] The third virtual data lines extend along the second direction and are located in the edge region, and have the same density as the plurality of second data lines located in the middle region.

[0021] In some embodiments, the display panel includes a driving circuit, and the driving circuit further includes a storage capacitor, a first gate line, a second gate line, a third gate line, a first electrical frequency line, a second electrical frequency line, and a light emitting control signal line;

[0022] The display panel comprises an active layer, a first gate layer, and a second gate layer;

[0023] The first gate line, the second gate line and the third gate line are arranged in the first gate layer, the storage capacitor is arranged in the second gate layer, the first electrical frequency line is arranged in the first conductive layer, and the second electrical frequency line is arranged in the active layer.

[0024] In some embodiments, the first gate line, the second gate line, and the third gate line are respectively connected to the second conductive layer through contact holes.

[0025] In some embodiments, the second electrical frequency lines include two lines, and the two second electrical frequency lines are both located in the active layer.

[0026] In some embodiments, the driving circuit further includes a reset line, and the reset line is disposed in the second gate layer.

[0027] According to a second aspect of the embodiments of the present application, a display device is provided, wherein the display device comprises the display panel described in the above embodiments.

[0028] The display panel of the present application achieves a narrow frame effect by setting a first data line, a second data line, and a connecting line, and introducing the first data line located in the edge area into the middle area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0030] Figure 1 Schematic diagram of the structure of a conventional large-size display panel according to the present application.

[0031] Figure 2 Schematic diagram of the structure of the display panel according to the present application.

[0032] Figure 3 Schematic diagram of data lines of a display panel according to the present application.

[0033] Figure 4 FIG. 4 is a schematic diagram of compensation for data lines of a display panel according to the present application.

[0034] Figure 5 A driving circuit for display panel pixels according to the present application.

[0035] Figure 6 It is a cross-sectional schematic diagram of a display panel according to the present application.

[0036] Figure 7 A top view of a display panel according to the present application.

[0037] Description of reference numerals:

[0038] Display panel 10

[0039] Substrate 100

[0040] Middle area 110

[0041] Edge area 120

[0042] First data line 210

[0043] Second data line 220

[0044] Connecting line 230

[0045] The first virtual data line 221

[0046] The second virtual data line 231

[0047] The third virtual data line 211

[0048] Reset line 290

[0049] Active layer 310

[0050] First conductive layer 320

[0051] The second conductive layer 330

[0052] The third conductive layer 340

[0053] The first gate layer 350

[0054] The second gate layer 360

[0055] Barrier layer 420

[0056] Buffer layer 430

[0057] Gate insulating layer 510

[0058] Capacitor insulation layer 520

[0059] Interlayer insulation layer 530

[0060] Passivation layer 540

[0061] First insulating layer 551

[0062] Second insulating layer 552

[0063] The third insulating layer 553

[0064] First contact hole 561

[0065] The second contact hole 562

[0066] The third contact hole 563

[0067] Anode 570

[0068] Pixel definition layer 580

[0069] Support column 590

[0070] Source Area 311

[0071] Drain area 312

[0072] First direction X

[0073] Second direction Y DETAILED DESCRIPTION

[0074] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0075] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and / or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0076] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0077] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0078] The use of "adapted to" or "configured to" in this specification is meant to be open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0079] The triangles, rectangles, trapezoids, pentagons or hexagons used in the specification and claims of this application are not in a strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0080] The term "about" as used in the specification and claims of this application refers to a numerical value that is not strictly limited and allows for process and measurement errors.

[0081] The transistors used in the present application can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0082] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0083] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0084] like Figure 1 As shown, the medium and large-sized OLED products in the related technology are mostly hard-screen COF designs. Since the horizontal screen design has a large number of data lines, in order to reduce the data line wiring (fanout) space, a mux circuit is generally used to reduce the number of fanout wiring. Therefore, its lower frame includes four parts: mux circuit, fanout circuit, COF and packaging. Therefore, the current size of the lower frame is relatively large, generally 3 to 5 mm.

[0085] Although the introduction of the mux circuit can effectively reduce the fanout space, the switching time of the mux circuit will shorten the scan time, resulting in insufficient pixel charging time, which limits the development of medium-sized products to higher resolutions. In addition, despite the introduction of the mux circuit, in order to avoid large differences in RC loading (resistance and capacitance load) between data lines, the fanout height is still relatively large, so a new solution is needed to reduce the bottom border.

[0086] In one embodiment, if Figure 2 and Figure 3As shown, the present application proposes a display panel 10, comprising: a substrate 100, a plurality of first data lines 210, a plurality of second data lines 220, and a plurality of connecting lines 230. The substrate 100 comprises a middle region 110 and an edge region 120, wherein the edge region 120 is located at the periphery of the middle region 110; the plurality of first data lines 210 extend along a second direction Y, and are arranged at intervals along a first direction X on the light-emitting side of the substrate 100, including a plurality of first data lines 210 located in the edge region 120 and a plurality of first data lines 210 located in the middle region 110; the plurality of second data lines 220 extend along a second direction Y, and are arranged at intervals along the first direction X on the light-emitting side of the substrate 100; the plurality of connecting lines 230 extend along a first direction X, and are used to connect the plurality of first data lines 210 located in the edge region 120 and the plurality of second data lines 220; wherein an angle greater than 0 is formed between the first direction X and the second direction Y.

[0087] With the above settings, Figure 2 As shown, the first data line 210 located in the edge area 120 is introduced into the middle area 110, so that the width of its fan-out area A becomes narrower, and thus the two sides of the fan-out area A become narrower, thereby achieving the requirement of a narrow frame of the display panel 10. The above technology is the Fanout in AA (FIAA for short) technology.

[0088] In the present application, the display panel 10 further includes a first conductive layer 320, a second conductive layer 330, and a third conductive layer 340 disposed in different layers, the first data line 210 is disposed in the first conductive layer 320, at least a portion of the structure of the connecting line 230 is located in the second conductive layer 330, and the second data line 220 is disposed in the third conductive layer 340. For example, the second conductive layer 330 is stacked between the first conductive layer 320 and the third conductive layer 340.

[0089] For example, the first conductive layer 320 is connected to the drain region 312 through the metal material filled in the first contact hole 561, the second conductive layer 330 is connected to the first conductive layer 320 through the metal material filled in the second contact hole 562, and the third conductive layer 340 is connected to the second conductive layer 330 through the metal material filled in the third contact hole 563. The first insulating layer 551, the second insulating layer 552 and the third insulating layer 553 protect the first conductive layer 320, the second conductive layer 330 and the third conductive layer 340 respectively.

[0090] During the manufacturing process, the first conductive layer 320 and the metal material filled in the first contact hole 561 are formed simultaneously. The second conductive layer 330 and the metal material filled in the second contact hole 562 are formed simultaneously. The third conductive layer 340 and the metal material filled in the third contact hole 563 are formed stepwise. It should be noted that since the metal material filled in the contact hole only plays a conductive role and its cross-sectional area is small, the first conductive layer 320, the second conductive layer 330 and the third conductive layer 340 described above do not include the metal material disposed in the contact hole.

[0091] Because the first conductive layer 320, the second conductive layer 330 and the third conductive layer 340 are protected by the first insulating layer 551, the second insulating layer 552 and the third insulating layer 553 respectively, and the first insulating layer 551, the second insulating layer 552 and the third insulating layer 553 have a certain thickness, the first data line 210, the second data line 220 and the connecting line 230 are arranged in different layers to prevent interference between the first data line 210, the second data line 220 and the connecting line 230, and at the same time, sufficient space can be reserved for the layout of other components.

[0092] Preferably, all of the plurality of connection lines 230 are located in the second conductive layer 330. All of the plurality of connection lines 230 are located in the second conductive layer 330, and the first data line 210 is located in the first conductive layer 320, and the second data line 220 is located in the third conductive layer 340, so that the connection lines 230 can be located in a single layer to completely avoid mutual influence between different layers.

[0093] In one embodiment, if Figure 3 As shown, one or more second data lines 220 are disposed between two adjacent first data lines 210 in the middle region 110. The second data lines 220 disposed between the first data lines 210 can prevent the second data lines 220 and the first data lines 210 from interfering with each other in the thickness direction.

[0094] Preferably, one or two second data lines 220 are arranged between two adjacent first data lines 210 to prevent too many second data lines 220 from making the circuit lines too densely arranged, thereby causing crosstalk. Crosstalk refers to the situation in a circuit where, when a signal is transmitted on one line, it affects the signal on another adjacent line, causing unnecessary interference and noise. Such interference and noise can be generated by electromagnetic induction, capacitive coupling, and resistive coupling.

[0095] Please refer to Figure 3As shown, the plurality of connection lines 230 are arranged at intervals along the second direction Y. By arranging the connection lines 230 at intervals along the second direction Y, the crosstalk problem caused by the overlapping of the plurality of connection lines 230 can be avoided.

[0096] In this embodiment, Figure 4 for Figure 1 Compensation diagram of the data line of the display panel. Figure 4 As shown, using dummy pattern technology, multiple first virtual data lines 221 are arranged on the display panel 10, and the multiple first virtual data lines 221 extend along the second direction Y; wherein, each second data line 220 is arranged on the same layer as a first virtual data line 221, and forms a first data line group, and the second data lines 220 and the first virtual data lines 221 in the first data line group are arranged on the same straight line extending along the second direction Y.

[0097] In the above arrangement, a plurality of first virtual data lines 221 are composed of some non-functional, repetitive graphics or shapes, which can be added to the design in a specific step of circuit manufacturing. Its functions include balanced layout, electromagnetic interference management, gap management and manufacturing process optimization. Although the above-mentioned first virtual data line 221 is arranged on the same straight line as the second data line 220, the first virtual data line 221 is isolated from the second data line 220 and is not connected. By setting the first virtual data line 221, the difference in metal density caused by setting the second data line 220 can be compensated, thereby causing the difference in reflectivity.

[0098] For example, Figure 4 As shown, the display panel 10 may further be provided with a plurality of second virtual data lines 231, and the plurality of second virtual data lines 231 extend along the first direction X; wherein each of the connecting lines 230 is arranged on the same layer as a second virtual data line 231, and forms a second data line group, and the connecting lines 230 and the second virtual data lines 231 in the second data line group are arranged on the same straight line extending along the first direction X.

[0099] Similarly, although the second virtual data line 231 and the connecting line 230 are arranged on the same straight line, they are isolated and not connected to each other. The second virtual data line 231 can compensate for the difference in metal density caused by the setting of the connecting line 230, thereby causing the difference in reflectivity.

[0100] For example, Figure 4As shown, the display panel 10 may further be provided with a plurality of third virtual data lines 211; the third virtual data lines 211 extend along the second direction Y, and are located in the edge region 120, and have the same density as the plurality of second data lines 220 located in the middle region 110. That is, in the middle region 110, the number of the second data lines 220 in the two adjacent first data lines 210 is the first number. In the edge region 120, the third virtual data lines 211 are the second number. The first number and the second number are the same. In addition, the third virtual data lines 211 are not connected to other lines.

[0101] The above configuration can make the density of the second data lines 220 in the middle area 110 and the density of the third dummy data lines 211 in the edge area 120 the same, thereby achieving similar or identical reflectivity in the middle area 110 and the edge area 120 .

[0102] Through the above arrangement, a first virtual data line 221, a second virtual data line 231, and a third virtual data line 211 are added to the circuit, thereby improving various aspects of circuit design and enhancing circuit performance, stability, and manufacturing efficiency.

[0103] like Figure 5 As shown, the conventional 7T1C circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor C, a first gate line S1, a second gate line S2, a third gate line S3, a first electrical frequency line VDD, a second electrical frequency line Vref, a light emitting control signal line EM, and a first data line Data (i.e., a first data line 210). Among them, the third transistor T3 includes a transistor T3_1 and a transistor T3_2 connected in series; and the fourth transistor T4 includes a transistor T4_1 and a transistor T4_2 connected in series.

[0104] The first electrode of the first transistor T1 is connected to the first connection point S, the second electrode of the first transistor T2 is connected to the second connection point D, and the gate of the first transistor T1 is connected to the third connection point G; the first electrode of the second transistor T2 is connected to the first data line Data (i.e., the first data line 210), the second electrode of the second transistor T2 is connected to the first connection point S, and the gate of the second transistor is connected to the second gate line S2; the first electrode of the third transistor T3 is connected to the second connection point D, the second electrode of the third transistor T3 is connected to the third connection point G, and the gate of the third transistor T3 is connected to the first gate line S1; the first electrode of the fourth transistor T4 is connected to the second frequency line Vref, the second electrode of the fourth transistor T4 is connected to the third connection point G, and the gate of the fourth transistor T3 is connected to the first gate line S1; The gate of the transistor T4 is connected to the second gate line S2; the first electrode of the fifth transistor T5 is connected to the first electrical frequency line VDD, the second electrode of the fifth transistor T5 is connected to the first connection point S, and the gate of the fifth transistor T5 is connected to the light-emitting control signal line EM; the first electrode of the sixth transistor T6 is connected to the second connection point D, the second electrode of the sixth transistor T6 is connected to the fourth connection point X, and the gate of the sixth transistor T6 is connected to the light-emitting control signal line EM; the first electrode of the seventh transistor T7 is connected to the second electrical frequency line Vref, the second electrode of the seventh transistor T7 is connected to the fourth connection point X, and the gate of the seventh transistor T7 is connected to the third gate line S3; the first electrode of the storage capacitor C is connected to the first electrical frequency line VDD, and the second electrode of the storage capacitor C is connected to the third connection point G.

[0105] Figure 6The cross-sectional schematic diagram of the display panel of the present application includes: a substrate 100 (Substrate), which is used to provide a material basis and support other layers and components; a barrier layer 420 (Barrier layer), which is used to prevent impurity diffusion or control interlayer reaction; a buffer layer 430 (Buffer layer), which is used to smooth the substrate surface or reduce the influence of lattice mismatch; a gate insulator layer 510 (Gate insulator layer, GIL), which is used to isolate the gate and channel layer and control the flow of current; a capacitor dielectric layer 520 (Capacitor dielectric layer, CDL), which is used to build a capacitor and isolate charges; an interlayer dielectric 530 (Interlayer dielectric, ILD), which is used to isolate different metal wire layers or circuits; a passivation layer 540 (Passivation layer), which is used to protect circuit components from environmental damage, such as corrosion or humidity; a first insulation layer 551 (First insulation layer, FIL) is the first insulating material layer located above other insulating layers, which is used to protect the first metal layer; a second insulation layer 552 (Second insulation layer, SIL)-a second insulating material layer located above the first insulation layer.The third insulating layer 553 (Third insulation layer, TIL) is a third insulating material layer located above the second insulating layer; the first contact hole 561 (First contact hole, FCH) is used to connect the upper layer or metal line with the lower layer or region; the second contact hole 562 (Second contact hole, SCH) is used to connect other layers or metal lines with the lower layer or region; the third contact hole 563 (Third contact hole, TCH) is used to connect other layers or metal lines with the lower layer or region; the anode 570 (Anode) is a positive electrode or an electron flow outlet; the pixel definition layer 580 (Pixel definition layer, PDL) is used to define the function and operation of each pixel; the support pillar 590 (Support pillar) is used to provide structural support or stability; the source region 311 (Source region) is used to inject electrons or holes and provide a current source; the drain region 312 (Drain region) is used to collect electrons or holes and receive current; the active layer 310 (Active layer) is used to inject electrons or holes and provide a current source ... The first conducting layer 320 (First conducting layer, CL1) is used to transmit current or connect circuit elements; the second conducting layer 330 (Second conducting layer, CL2) is used to transmit current or connect circuit elements; the third conducting layer 340 (Third conducting layer, CL3) is used to transmit current or connect circuit elements; the first gate electrode layer 350 (First gate electrode layer, GEL1) controls the on or off state of the transistor; the second gate electrode layer 360 (Second gate electrode layer, GEL2) is used in some device structures to enhance the performance or function of the transistor.

[0106] For example, Figure 6 and Figure 7 As shown, the first gate line S1, the second gate line S2 and the third gate line S3 are arranged in the first gate layer 350, the storage capacitor C is arranged in the second gate layer 360, the first electrical frequency line VDD is arranged in the first conductive layer 320, and the second electrical frequency line Vref is arranged in the active layer 310.

[0107] The above layout can not only meet the arrangement between the first data line 210, the second data line 220 and the connecting line 230, but also the layout between the first gate line S1, the second gate line S2, the third gate line S3, the first electrical frequency line VDD, the second electrical frequency line Vref, the light emitting control signal line EM and the first data line 210 is reasonable and not easy to affect each other.

[0108] In one embodiment, reference Figure 6 and Figure 7 As shown, the first gate line S1, the second gate line S2, and the third gate line S3 are respectively connected to the second conductive layer 330 through the contact holes. The first gate line S1, the second gate line S2, and the third gate line S3 are respectively connected to the second conductive layer 330, that is, the first gate line S1, the second gate line S2, and the third gate line S3 are connected to the second conductive layer 330 in parallel, which can effectively reduce the resistance thereof.

[0109] In one embodiment, reference Figure 6 and Figure 7 As shown, the second electrical frequency lines Vref include two, and the two second electrical frequency lines Vref are both located in the active layer 310 .

[0110] like Figure 7 As shown, the display panel includes a second electrical frequency line Vref1 and a second electrical frequency line Vref2. The two second electrical frequency lines Vref can provide sufficient electrical frequency and cooperate with the first electrical frequency line VDD to effectively improve the problem of uneven brightness of low grayscale.

[0111] refer to Figure 7 As shown, the driving circuit also includes a reset line 290, and the reset line 290 is arranged in the second gate layer 360. The reset line 290 can be used to reset the driving circuit. The reset line 290 is arranged in the second gate layer 360 without affecting the routing of other layers, and can also allow the circuit to be reset directly through the reset line, thereby improving the efficiency of the circuit.

[0112] The present application also provides a display device, which includes the display panel 10 described in the above embodiment. Since the display device includes the display panel 10 described in the above embodiment, the display device also has the functions and advantages of the display panel 10. The display device can be an electronic device with a display function, such as a mobile phone, a computer, or a tablet computer.

[0113] In the present application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0114] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. For example, those of ordinary skill in the art can use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the application. This should not be interpreted as a feature of an application that does not require protection being necessary for any claim. On the contrary, the subject matter of the present application may be less than all the features of the embodiments of a specific application. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present application should be determined with reference to the full scope of the equivalent forms of the attached claims and these claims.

[0115] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the present application, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0116] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0117] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The terms "plurality" and "several" refer to two or more than two, unless otherwise clearly defined.

[0118] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure of the present application. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0119] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display panel, characterized in that: include: A substrate, the substrate comprising a middle region and an edge region, wherein the edge region is located on a peripheral side of the middle region; A plurality of first data lines, the plurality of first data lines extending along the second direction and spaced apart on the substrate along the first direction; the plurality of first data lines comprising a plurality of first data lines located in an edge region and a plurality of first data lines located in a middle region; A plurality of second data lines extending along the second direction and spaced apart in a middle area of ​​the substrate along the first direction; A plurality of connection lines extending along a first direction and used to connect a plurality of the first data lines and a plurality of the second data lines located in an edge area; Wherein, there is an angle greater than 0 between the first direction and the second direction; The display panel also includes a first conductive layer, a second conductive layer, and a third conductive layer arranged in different layers. The first data line is arranged in the first conductive layer. At least part of the structure of the connecting line is located in the second conductive layer. The second data line is arranged in the third conductive layer.

2. The display panel according to claim 1, wherein: One second data line or a plurality of second data lines are arranged between two adjacent first data lines located in the middle area.

3. The display panel according to claim 1, wherein: A plurality of connecting lines are arranged at intervals along the second direction.

4. The display panel according to claim 1, wherein: The plurality of connection lines are all located in the second conductive layer.

5. The display panel according to claim 1, wherein: The display panel is further provided with a plurality of first virtual data lines, and the plurality of first virtual data lines extend along the second direction; Each of the second data lines is arranged in the same layer as a first virtual data line to form a first data line group, and the second data lines and the first virtual data lines in the first data line group are arranged on the same straight line extending along the second direction.

6. The display panel according to claim 5, wherein: The display panel is further provided with a plurality of second virtual data lines, and the plurality of second virtual data lines extend along the first direction; Each of the connection lines is arranged in the same layer as a second virtual data line to form a second data line group, and the connection lines in the second data line group and the second virtual data lines are arranged on the same straight line extending along the first direction.

7. The display panel according to claim 6, wherein: The display panel is further provided with a plurality of third virtual data lines; The third virtual data lines extend along the second direction and are located in the edge region, and have the same density as the plurality of second data lines located in the middle region.

8. The display panel according to claim 1, wherein: The display panel includes a driving circuit, and the driving circuit also includes a storage capacitor, a first gate line, a second gate line, a third gate line, a first electrical frequency line, a second electrical frequency line, and a light emitting control signal line; The display panel comprises an active layer, a first gate layer, and a second gate layer; The first gate line, the second gate line and the third gate line are arranged in the first gate layer, the storage capacitor is arranged in the second gate layer, the first electrical frequency line is arranged in the first conductive layer, and the second electrical frequency line is arranged in the active layer.

9. The display panel according to claim 8, wherein: The first gate line, the second gate line, and the third gate line are connected to the second conductive layer through contact holes, respectively.

10. The display panel according to claim 8, wherein: The second electrical frequency lines include a plurality of lines, and the plurality of second electrical frequency lines are all located in the active layer.

11. The display panel according to claim 8, wherein: The driving circuit further includes a reset line, and the reset line is arranged on the second gate layer.

12. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 11.

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