Shift register, gate drive circuit and display panel

Abstract

The invention discloses a shift register (SR), a gate drive circuit (GOA) and a display panel, and belongs to the technical field of display. A first input sub-circuit (M3) of a shift register (SR) causes a first supply voltage (V1) to be written to a first node (N1) in response to a first level of a first type clock signal (KA); the second input sub-circuit (M2) responds to a first level on the signal input end (In) so as to write a first type of clock signal (KA) into the first node (N1); the first output unit outputs a second power supply voltage (V2) in response to a first level on the first node (N1); the first control sub-circuit (M1) responds to a first level on the signal input end (In) and enables a second type clock signal (KB) to be written into the second node (N2); the second control sub-circuit (M4) responds to a first level on the first node (N1) to enable a second type clock signal (KB) to be written into the third node (N3); the third control sub-circuit (M5) responds to the first level of the first type clock signal (KA) to enable the third node (N3) and the second node (N2) to be conducted; the second output unit outputs a first power supply voltage (V1) in response to a first level of a second node (N2). This can ensure a stable output of the shift register (SR).

Description

Shift register, gate drive circuit and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display panel. Background Art

[0002] With the development of optical technology and semiconductor technology, flat panel displays represented by liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs) have the characteristics of light weight, low energy consumption, fast response speed, good color purity, and high contrast, and are widely used in various electronic display products.

[0003] GOA (Gate on Array) has the advantages of low cost, narrow bezels, and low power consumption, and has been widely used in LCD and OLED displays. The gate drive circuit consists of a series of cascaded shift registers. The output transistors of these shift registers are at risk of failure, which can cause display panel issues such as split-screen display.

[0004] The above information disclosed in this Background section is only configured to enhance understanding of the background of the present disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.

[0005] Summary of the Invention

[0006] The present disclosure aims to provide a shift register, a gate driving circuit and a display panel to improve the output stability of the shift register.

[0007] According to a first aspect of the present disclosure, there is provided a shift register, comprising:

[0008] A first input sub-circuit is configured to write a signal of the first power supply voltage terminal into the first node in response to a first level of the first-type clock signal terminal;

[0009] a second input sub-circuit configured to write the signal of the first-type clock signal terminal into the first node in response to a first level on the signal input terminal;

[0010] A first output sub-circuit includes a first output unit configured to write a signal at the second power supply voltage terminal into a signal output terminal in response to a first level on the first node;

[0011] a first control subcircuit configured to write a signal of the second-type clock signal terminal into the second node in response to a first level on the signal input terminal;

[0012] a second control subcircuit configured to write a signal of the second-type clock signal terminal into a third node in response to a first level on the first node;

[0013] a third control subcircuit configured to connect the third node to the second node in response to the first level of the first-type clock signal terminal; and

[0014] The second output sub-circuit includes a second output unit configured to write the signal at the first power supply voltage terminal into the signal output terminal in response to a first level on the second node.

[0015] According to one embodiment of the present disclosure, the first control subcircuit includes a first transistor, a first electrode of the first transistor is electrically connected to the second type clock signal terminal, a third electrode of the first transistor is electrically connected to the signal input terminal, and a second electrode of the first transistor is electrically connected to the second node.

[0016] According to one embodiment of the present disclosure, the second input sub-circuit includes a second transistor, a first electrode of the second transistor is electrically connected to the first type clock signal terminal, a third electrode of the second transistor is electrically connected to the signal input terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0017] According to one embodiment of the present disclosure, the second control subcircuit includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the second type clock signal terminal, a third electrode of the fourth transistor is electrically connected to the first node, and a second electrode of the fourth transistor is electrically connected to the third node.

[0018] According to one embodiment of the present disclosure, the first input sub-circuit includes a third transistor, a first electrode of the third transistor is electrically connected to the first power supply voltage terminal, a third electrode of the third transistor is electrically connected to the first type clock signal terminal, and a second electrode of the third transistor is electrically connected to the first node;

[0019] The third control subcircuit includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the third node, a third electrode of the fifth transistor is electrically connected to the first-type clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node;

[0020] The first output unit includes a seventh transistor, a first electrode of the seventh transistor is electrically connected to the second power supply voltage terminal, a third electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to the signal output terminal;

[0021] The second output unit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the first power supply voltage terminal, a third electrode of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the signal output terminal.

[0022] According to an embodiment of the present disclosure, the shift register further includes a voltage stabilizing subcircuit electrically connected to the second node and the fourth node respectively; the voltage stabilizing circuit is configured to write the voltage of the fourth node to the second node under the control of a signal at the first power supply voltage terminal;

[0023] The fourth node is electrically connected to the first control sub-circuit and the third control sub-circuit.

[0024] According to one embodiment of the present disclosure, the voltage stabilizing sub-circuit includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the fourth node, a third electrode of the sixth transistor is electrically connected to the first power supply voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

[0025] According to one embodiment of the present disclosure, the first output sub-circuit further includes a first capacitor, wherein a first electrode plate of the first capacitor is electrically connected to the first node; and a second electrode plate of the first capacitor is electrically connected to the second power supply voltage terminal;

[0026] The second output sub-circuit further includes a second capacitor, wherein a first electrode plate of the second capacitor is electrically connected to the second node; and a second electrode plate of the second capacitor is electrically connected to the signal output terminal.

[0027] According to an embodiment of the present disclosure, the duration of the first level of the first type of clock signal end is the same as the duration of the first level of the second type of clock signal end, and neither of them exceeds one third of the clock cycle.

[0028] According to an embodiment of the present disclosure, the first level of the first-type clock signal terminal is one-third of a clock cycle earlier than the first level of the second-type clock signal terminal.

[0029] According to an embodiment of the present disclosure, the amplitude of the second level of the first-type clock signal terminal and the amplitude of the second level of the second-type clock signal terminal are both greater than the amplitude of the signal of the second power supply voltage terminal.

[0030] According to a second aspect of the present disclosure, a gate drive circuit is provided, comprising a plurality of the above-mentioned shift registers cascaded in sequence; in two adjacent stages of the shift registers, the signal output terminal of the upper stage shift register is electrically connected to the signal input terminal of the lower stage shift register;

[0031] In the gate drive circuit, the signal input terminal of the first-stage shift register is electrically connected to the start signal terminal;

[0032] The gate driving circuit includes a plurality of shift register groups, each of which includes a first shift register, a second shift register, and a third shift register that are cascaded in sequence;

[0033] The first type of clock signal terminal of the first shift register is electrically connected to the third clock signal line, and the second type of clock signal terminal of the first shift register is electrically connected to the first clock signal line;

[0034] The first type of clock signal terminal of the second shift register is electrically connected to the first clock signal trace, and the second type of clock signal terminal of the second shift register is electrically connected to the second clock signal trace;

[0035] The first type of clock signal terminal of the third shift register is electrically connected to the second clock signal line, and the second type of clock signal terminal of the third shift register is electrically connected to the third clock signal line.

[0036] According to one embodiment of the present disclosure, the amplitude of the second level of the first clock signal routing, the amplitude of the second level of the second clock signal routing, and the amplitude of the second level of the third clock signal routing are the same, and are all 0.5 to 3 V higher than the amplitude of the signal at the second power supply voltage end.

[0037] According to an embodiment of the present disclosure, the duration of the first level of the first clock signal trace, the duration of the first level of the second clock signal trace, and the duration of the first level of the third clock signal trace are the same, and none of them exceeds one-third. According to an embodiment of the present disclosure, the starting time of the first level of the first clock signal trace differs from the starting time of the first level of the third clock signal trace by two-thirds of a clock cycle;

[0038] A start time of the first level of the second clock signal routing differs from a start time of the first level of the first clock signal routing by two-thirds of a clock cycle;

[0039] A start time of the first level of the third clock signal line differs from a start time of the first level of the second clock signal line by two-thirds of a clock cycle.

[0040] According to a third aspect of the present disclosure, a display panel is provided, comprising the above-mentioned gate driving circuit.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0043] FIG1 is an equivalent circuit diagram of a shift register in one embodiment of the present disclosure.

[0044] FIG2 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0045] FIG3 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0046] FIG4 is a schematic structural diagram of a gate driving circuit in one embodiment of the present disclosure.

[0047] FIG5 is a driving timing diagram of a gate driving circuit in one embodiment of the present disclosure.

[0048] FIG6 is a circuit state diagram of the first shift register circuit in the first time period.

[0049] FIG7 is a circuit state diagram of the first shift register circuit in the second time period.

[0050] FIG8 is a circuit state diagram of the first shift register circuit in the third time period.

[0051] FIG9 is a circuit state diagram of the first shift register circuit in the fourth time period.

[0052] FIG10 is a circuit state diagram of the first shift register circuit in the fifth time period.

[0053] FIG11 is a schematic diagram of a first shift register in one embodiment of the present disclosure.

[0054] FIG12 is a schematic diagram of a second shift register in one embodiment of the present disclosure.

[0055] FIG13 is a schematic diagram of a third shift register in one embodiment of the present disclosure.

[0056] The main components in the figure are denoted as follows: M1, first control sub-circuit; M2, second input sub-circuit; M3, first input sub-circuit; M4, second control subcircuit; M5, third control subcircuit; M6, voltage stabilization subcircuit; M7, first output subcircuit; M8, second output subcircuit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; C1, first capacitor; C2, second capacitor; N1, first node; N2, second node; N3, third node; N4, fourth node; V1, first power supply voltage; V2, second power supply voltage; VGH, high-level power supply voltage; VGL, low-level power supply voltage; GSTV, start signal; KA, first type clock signal; KB, second type clock signal; CK1, first clock signal; CK2, second clock signal; CK3, third clock signal; In, signal input terminal; OUT, signal output terminal; SRS, shift register group; SR1, first shift register; SR2, second shift register; SR3, third shift register. DETAILED DESCRIPTION

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and their detailed descriptions will be omitted. In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure.

[0058] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be employed. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0059] The terms "a" and "an" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusiveness and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first" and "second" are used merely as labels and do not limit the quantity of the objects thereof.

[0060] In the embodiment of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region through which current mainly flows. In the embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the third pole of the transistor.

[0061] In the prior art, with the use of automotive products and tandem devices, the voltage difference between the positive and negative poles of the OLED continues to increase (the tandem device causes Voled to increase from 4V to about 8V), thereby causing the voltage difference between the high-level power supply voltage and the low-level power supply voltage of the gate drive circuit (GOA) to continue to increase. In this high-voltage difference working environment, during the aging stage of the product manufacturing process and in the later high-temperature use environment, the threshold voltage Vth of the thin-film transistor is easily positively biased, causing the output transistor to fail, especially the output transistor with the highest W / L (width-to-length ratio), which causes the threshold voltage Vth to be closest to the high-level power supply voltage. In the related art, the control voltage on the output transistor comes from the high-level power supply voltage and the low-level power supply voltage. When the threshold voltage Vth of the output transistor is close to 0V due to the threshold offset of the output transistor, the gate-source voltage difference of the output transistor may not be able to turn off the output transistor, thereby causing the shift register output to fail and produce a poor split-screen effect.

[0062] The present disclosure provides a shift register, as shown in FIG1 , which may include: a first input subcircuit M3, a second input subcircuit M2, a first control subcircuit M1, a second control subcircuit M4, a third control subcircuit M5, a first output subcircuit M7, and a second output subcircuit M8, wherein:

[0063] The first input sub-circuit M3 is configured to respond to a first level of the first type clock signal terminal (for applying the first type clock signal KA) so as to write a signal of the first power voltage terminal (for applying the first power voltage V1) into the first node N1.

[0064] The second input sub-circuit M2 is configured to respond to the first level on the signal input terminal In so that the voltage of the first-type clock signal terminal (for loading the first-type clock signal KA) is written into the first node N1.

[0065] The first output sub-circuit M7 includes a first output unit configured to write a signal on the second power supply voltage terminal (used to load the second power supply voltage V2 ) into the signal output terminal OUT in response to a first level on the first node N1 .

[0066] The first control sub-circuit M1 is configured to write the voltage of the second-type clock signal terminal (for loading the second-type clock signal KB) into the second node N2 in response to the first level on the signal input terminal In.

[0067] The second control sub-circuit M4 is configured to respond to the first level on the first node N1 so that the voltage of the second-type clock signal terminal is written into the third node N3.

[0068] The third control sub-circuit M5 is configured to connect the third node N3 and the second node N2 in response to the first level of the first-type clock signal terminal.

[0069] The second output sub-circuit M8 includes a second output unit configured to respond to a first level on the second node N2 so as to write a signal at the first power supply voltage terminal into the signal output terminal OUT.

[0070] In one embodiment of the present disclosure, the first level is a low level, and the second level is a high level; the first power voltage V1 is a low-level power voltage VGL, and the second power voltage V2 is a high-level power voltage VGH.

[0071] In another embodiment of the present disclosure, the first level is a high level, and the second level is a low level; the first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL.

[0072] The shift register provided in an embodiment of the present disclosure includes a first output sub-circuit M7 and a second output sub-circuit M8. When the first output sub-circuit M7 outputs, the second power supply voltage V2 applied to the second power supply voltage terminal can be applied to the signal output terminal OUT, thereby causing the shift register to output the second power supply voltage V2. Whether the first output sub-circuit M7 outputs is controlled by the voltage on the first node N1. When the second level is applied to the first node N1, the first output sub-circuit M7 can be turned off. In this embodiment, the second level on the first node N1 is derived from the second level of the first-class clock signal KA, rather than from the second power supply voltage V2. Therefore, by adjusting the second level of the first-class clock signal KA, the voltage on the first node N1 is not limited to the second power supply voltage V2, eliminating the risk of the first output sub-circuit M7 failing to shut down due to the second level of the first node N1 being necessarily the second power supply voltage V2. For example, in one example, the amplitude of the second level of the first-class clock signal KA can be set higher than the second power supply voltage V2, thereby ensuring that the amplitude of the second level of the first node N1 is necessarily higher than the amplitude of the second power supply voltage V2, and ensuring that the first output sub-circuit M7 is necessarily turned off when the first node N1 is at the second level. For another example, when the second level on the first node N1 is insufficient to turn off the first output sub-circuit M7, the second level of the first-class clock signal KA can be increased without adjusting the second power supply voltage V2, thereby enabling the first output sub-circuit M7 to be turned off in response to the second level on the first node N1.

[0073] When the second output sub-circuit M8 is outputting, the first power supply voltage V1 can be applied to the signal output terminal OUT, thereby causing the shift register to output the first power supply voltage V1. Whether the second output sub-circuit M8 outputs is controlled by the voltage at the second node N2. When the second node N2 is loaded with a second level, the second output sub-circuit M8 is turned off. In this embodiment, the second level at the second node N2 is derived from the second level of the second-class clock signal KB, rather than from the second power supply voltage V2. Therefore, by adjusting the second level of the second-class clock signal KB, the voltage at the second node N2 is not limited to the second power supply voltage V2, eliminating the risk of the second output sub-circuit M8 failing to shut down due to the second level of the second node N2 being necessarily at the second power supply voltage V2. For example, in one example, the amplitude of the second level of the second-class clock signal KB can be set higher than the amplitude of the second power supply voltage V2, thereby ensuring that the amplitude of the second level of the second node N2 is always higher than the second power supply voltage V2, thereby ensuring that the second output sub-circuit M8 is always turned off when the second node N2 is at the second level. For another example, when the second level on the second node N2 is insufficient to turn off the second output sub-circuit M8, the amplitude of the second level of the second type clock signal KB can be increased without adjusting the second power supply voltage V2, thereby enabling the second output sub-circuit M8 to be turned off in response to the second level on the second node N2.

[0074] In summary, in the shift register provided in the embodiment of the present disclosure, the amplitude of the second level on the first node N1 and the second node N2 can be different from the amplitude of the second power supply voltage V2, and its voltage adjustment can be independent of the adjustment of the second power supply voltage V2. This allows the shift register to ensure that the first output sub-circuit M7 and the second output sub-circuit M8 are cut off in response to the second level of their control terminals by setting the second level of the first-type clock signal KA and the second level of the second-type clock signal KB, thereby ensuring the stable output of the shift register.

[0075] The shift register according to the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0076] In one embodiment of the present disclosure, referring to FIG1 , the first output sub-circuit M7 further includes a first capacitor C1, wherein a first electrode plate of the first capacitor C1 is electrically connected to the first node N1. Furthermore, a second electrode plate of the first capacitor C1 is electrically connected to the second power supply voltage terminal. It is understood that in other embodiments of the present disclosure, the second electrode plate of the first capacitor C1 may also be electrically connected to the first power supply voltage terminal.

[0077] In one embodiment of the present disclosure, referring to FIG1 , the second output sub-circuit M8 further includes a second capacitor C2, wherein a first electrode plate of the second capacitor C2 is electrically connected to the second node N2. Furthermore, a second electrode plate of the second capacitor C2 is electrically connected to the signal output terminal OUT. It is understood that in other embodiments of the present disclosure, the second electrode plate of the second capacitor C2 may also be electrically connected to the second power supply voltage terminal or the first power supply voltage terminal.

[0078] In one embodiment of the present disclosure, the shift register further includes a voltage stabilizing subcircuit M6, the first control subcircuit M1 and the third control subcircuit M5 are both connected to the second node N2 through the voltage stabilizing subcircuit M6, and the voltage stabilizing subcircuit M6 is configured to be electrically conductive in response to a signal on the first power supply voltage terminal.

[0079] For example, the first control subcircuit M1 is configured to write the voltage of the second-class clock signal terminal (for loading the second-class clock signal KB) to the fourth node N4 in response to the first level on the signal input terminal In. The third control subcircuit M5 is configured to write the signal on the third node N3 to the fourth node N4 in response to the first level on the first-class clock signal terminal. The voltage stabilization subcircuit M6 is electrically connected to the second node N2 and the fourth node N4, respectively; the voltage stabilization subcircuit M6 is configured to write the voltage of the fourth node N4 to the second node N2 under the control of the signal of the first power supply voltage terminal. In one embodiment of the present disclosure, the first control subcircuit M1 includes a first transistor T1, the first electrode of the first transistor T1 is electrically connected to the second-class clock signal terminal, the third electrode of the first transistor T1 is electrically connected to the signal input terminal In, and the second electrode of the first transistor T1 is electrically connected to the second node N2. It is understood that in some other embodiments of the present disclosure, the first control subcircuit M1 may include multiple first transistors T1 connected in series or in parallel.

[0080] In one embodiment of the present disclosure, the second input sub-circuit M2 includes a second transistor T2, a first electrode of the second transistor T2 is electrically connected to the first-type clock signal terminal, a third electrode of the second transistor T2 is electrically connected to the signal input terminal In, and a second electrode of the second transistor T2 is electrically connected to the first node N1. It will be understood that in other embodiments of the present disclosure, the second input sub-circuit M2 may include multiple second transistors T2 connected in series or in parallel.

[0081] In one embodiment of the present disclosure, the first input sub-circuit M3 includes a third transistor T3, wherein a first electrode of the third transistor T3 is electrically connected to the first power supply voltage terminal, a third electrode of the third transistor T3 is electrically connected to the first-type clock signal terminal, and a second electrode of the third transistor T3 is electrically connected to the first node N1. It will be appreciated that in other embodiments of the present disclosure, the first input sub-circuit M3 may include multiple third transistors T3 connected in series or in parallel.

[0082] In one embodiment of the present disclosure, the second control sub-circuit M4 includes a fourth transistor T4, a first electrode of the fourth transistor T4 being electrically connected to the second-type clock signal terminal, a third electrode of the fourth transistor T4 being electrically connected to the first node N1, and a second electrode of the fourth transistor T4 being electrically connected to the third node N3. It will be appreciated that in other embodiments of the present disclosure, the second control sub-circuit M4 may include multiple fourth transistors T4 connected in series or in parallel.

[0083] In one embodiment of the present disclosure, the third control sub-circuit M5 includes a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is electrically connected to the third node N3, a third electrode of the fifth transistor T5 is electrically connected to the first-type clock signal terminal, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2. It will be understood that in other embodiments of the present disclosure, the third control sub-circuit M5 may include multiple fifth transistors T5 connected in series or in parallel.

[0084] In one embodiment of the present disclosure, the voltage stabilizing sub-circuit M6 includes a sixth transistor T6, wherein a first electrode of the sixth transistor T6 is electrically connected to the second electrode of the first transistor T1 and the second electrode of the fifth transistor T5, respectively; a third electrode of the sixth transistor T6 is electrically connected to the first power supply voltage terminal; and a second electrode of the sixth transistor T6 is electrically connected to the second node N2. It will be appreciated that in other embodiments of the present disclosure, the voltage stabilizing sub-circuit M6 may include multiple sixth transistors T6 connected in series or in parallel.

[0085] In one embodiment of the present disclosure, the first output unit includes a seventh transistor T7, a first electrode of the seventh transistor T7 is electrically connected to the second power supply voltage terminal, a third electrode of the seventh transistor T7 is electrically connected to the first node N1, and a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT. It will be understood that in other embodiments of the present disclosure, the first output unit may include multiple seventh transistors T7 connected in series or in parallel.

[0086] In one embodiment of the present disclosure, the second output unit includes an eighth transistor T8, a first electrode of the eighth transistor T8 is electrically connected to the first power supply voltage terminal, a third electrode of the eighth transistor T8 is electrically connected to the second node N2, and a second electrode of the eighth transistor T8 is electrically connected to the signal output terminal OUT. It will be understood that in other embodiments of the present disclosure, the second output unit may include multiple eighth transistors T8 connected in series or in parallel.

[0087] In one example, referring to FIG1 , the first control subcircuit M1 includes a first transistor T1, wherein the first electrode of the first transistor T1 is used to load the second-type clock signal KB, the third electrode of the first transistor T1 is electrically connected to the signal input terminal In, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the second input subcircuit M2 includes a second transistor T2, wherein the first electrode of the second transistor T2 is used to load the first-type clock signal KA, the third electrode of the second transistor T2 is electrically connected to the signal input terminal In, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the first input subcircuit M3 includes a third transistor T3, wherein the first electrode of the third transistor T3 is used to load the first power supply voltage V1, the third electrode of the third transistor T3 is used to load the first-type clock signal KA, and the second electrode of the third transistor T3 is electrically connected to the first node N1; the second control subcircuit M4 includes a fourth transistor T4, wherein the first electrode of the fourth transistor T4 is used to load the second-type clock signal KB, the third electrode of the fourth transistor T4 is electrically connected to the first node N1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3. The third control sub-circuit M5 includes a fifth transistor T5, a first electrode of the fifth transistor T5 being electrically connected to the third node N3, a third electrode of the fifth transistor T5 being used to apply the first-class clock signal KA, and a second electrode of the fifth transistor T5 being electrically connected to the second node N2. The voltage stabilization sub-circuit M6 includes a sixth transistor T6, a first electrode of the sixth transistor T6 being electrically connected to the second electrode of the first transistor T1 and the second electrode of the fifth transistor T5, respectively, a third electrode of the sixth transistor T6 being used to apply the first power supply voltage V1, and a second electrode of the sixth transistor T6 being electrically connected to the second node N2. The first output unit includes a seventh transistor T7, a first electrode of the seventh transistor T7 being used to apply the second power supply voltage V2, a third electrode of the seventh transistor T7 being electrically connected to the first node N1, and a second electrode of the seventh transistor T7 being electrically connected to the signal output terminal OUT. The second output unit includes an eighth transistor T8, a first electrode of the eighth transistor T8 being used to apply the first power supply voltage V1, a third electrode of the eighth transistor T8 being electrically connected to the second node N2, and a second electrode of the eighth transistor T8 being electrically connected to the signal output terminal OUT.

[0088] In one example, the first transistor T1 to the eighth transistor T8 are all P-type thin film transistors. In this example, the first level is a low level, the second level is a high level, the first power supply voltage V1 is a low-level power supply voltage VGL, and the second power supply voltage V2 is a high-level power supply voltage VGH. Furthermore, the seventh transistor T7 and the eighth transistor T8 are thin film transistors with a large width-to-length ratio, so that the shift register has a large driving capability. The rest are ordinary thin film transistors, which are used as switches; the first capacitor C1 and the second capacitor C2 have the functions of energy storage and voltage stabilization, thereby improving the stability of the shift register. In addition, each transistor in this example embodiment can be an enhancement-mode transistor or a depletion-mode transistor.

[0089] In another example, the first to eighth transistors T1 to T8 are all N-type thin-film transistors. In this example, the first level is a high level, the second level is a low level, the first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. Furthermore, the seventh transistor T7 and the eighth transistor T8 are thin-film transistors with a large width-to-length ratio, so that the shift register has a large driving capability. The remaining transistors are ordinary thin-film transistors and serve as switches. The first capacitor C1 and the second capacitor C2 have the functions of energy storage and voltage regulation, thereby improving the stability of the shift register. In addition, each transistor in this exemplary embodiment can be an enhancement-mode transistor or a depletion-mode transistor. The shift register provided by the exemplary embodiment of the present disclosure may include eight thin-film transistors and two capacitors. The number of transistors is small, and the circuit structure is relatively simple. Therefore, the shift register circuit and the gate drive circuit composed of the shift register circuit can not only effectively reduce the occupied area of ​​the circuit layout, thereby facilitating the design of narrow-frame display panels, but also simplify the manufacturing process, thereby reducing costs.

[0090] In one embodiment of the present disclosure, the amplitude of the second level of the first-class clock signal KA (i.e., the amplitude of the second level of the first-class clock signal end) is higher than the amplitude of the second power supply voltage V2. In this way, even if the threshold value of the first output unit shifts, for example, the threshold value shifts to close to 0, the voltage of the second level of the first-class clock signal can keep the first output unit cut off. In one example, when the second level of the first-class clock signal KA is a high level, the amplitude of the second level of the first-class clock signal KA is its voltage value, which is greater than the voltage value of the high-level power supply voltage VGH. In another example, when the second level of the first-class clock signal KA is a low level, the voltage value of the second level of the first-class clock signal KA is a negative value, and its amplitude is the absolute value of the voltage value; the voltage value of the second level of the first-class clock signal KA is less than the voltage value of the low-level power supply voltage VGL. Taking the seventh transistor as a P-type transistor as an example, even if the threshold voltage of the seventh transistor is shifted to 0V, when the first node N1 is at the second level, the source-drain voltage difference Vgs of the seventh transistor T7 will be greater than 0, thereby ensuring that the seventh transistor T7 is turned off, avoiding output abnormality caused by the seventh transistor T7 not being able to be turned off.

[0091] In an example, the amplitude of the second level of the first-type clock signal KA is 0.5-3V higher than the amplitude of the second power supply voltage V2, for example, 0.5V, 1V, 1.5V, 2V, 2.5V or 3V higher.

[0092] In one example, the amplitude of the second level of the first-type clock signal KA is 10% to 20% higher than the amplitude of the second power supply voltage V2.

[0093] For example, the second power voltage V2 is 7V, and the second level voltage of the first-type clock signal KA is 8V.

[0094] In one embodiment of the present disclosure, the amplitude of the second level of the second-class clock signal KB (i.e., the amplitude of the second level of the second-class clock signal end) is higher than the second power supply voltage V2. In this way, even if the threshold value of the second output unit shifts, for example, the threshold value shifts to close to 0, the voltage of the second level of the second-class clock signal can keep the second output unit cut off. In one example, when the second level of the second-class clock signal KB is a high level, the amplitude of the second level of the second-class clock signal KB is its voltage value, which is greater than the voltage value of the high-level power supply voltage VGH. In another example, when the second level of the second-class clock signal KB is a low level, the voltage value of the second level of the second-class clock signal KB is a negative value, and its amplitude is the absolute value of the voltage value; the voltage value of the second level of the second-class clock signal KB is less than the voltage value of the low-level power supply voltage VGL.

[0095] Taking the eighth transistor as a P-type transistor as an example, even if the threshold voltage of the eighth transistor T8 is shifted to 0V, when the second node N2 is at the second level, the source-drain voltage difference Vgs of the eighth transistor T8 will be greater than 0, thereby ensuring that the eighth transistor T8 is turned off, avoiding output abnormality caused by the eighth transistor T8 not being able to be turned off.

[0096] In an example, the amplitude of the second level of the second-type clock signal KB is 0.5-3V higher than the amplitude of the second power supply voltage V2, for example, 0.5V, 1V, 1.5V, 2V, 2.5V or 3V higher.

[0097] In an example, the amplitude of the second level of the second-type clock signal KB is 10% to 20% higher than the amplitude of the second power supply voltage V2.

[0098] For example, the second power voltage V2 is 7V, and the second level voltage of the second-type clock signal KB is 8V.

[0099] In one embodiment of the present disclosure, the second level voltage of the first-class clock signal KA is equal to the first level voltage in absolute value, but has opposite electrical properties. For example, the second level voltage of the first-class clock signal KA is 8V, and the first level voltage of the first-class clock signal KA is -8V.

[0100] In one embodiment of the present disclosure, the second level voltage of the second-type clock signal KB is equal to the first level voltage in absolute value, but has opposite electrical properties. For example, the second level voltage of the second-type clock signal KB is 8V, and the first level voltage of the second-type clock signal KB is -8V.

[0101] In one embodiment of the present disclosure, the duration of the first level of the first-class clock signal KA (i.e., the first level of the first-class clock signal terminal) is the same as the duration of the first level of the second-class clock signal KB (i.e., the first level of the second-class clock signal terminal), and both do not exceed one-third of a clock cycle. In other words, the duty cycle of the first level of the first-class clock signal KA (i.e., the first level of the first-class clock signal terminal) and the duty cycle of the first level of the second-class clock signal KB (i.e., the first level of the second-class clock signal terminal) do not exceed 1 / 3.

[0102] In one embodiment of the present disclosure, the first level of the first-class clock signal KA is one-third of a clock cycle earlier than the first level of the second-class clock signal KB. This allows the shift register to output a first-level scanning signal with a length of two-thirds of a clock cycle. Furthermore, the first level of the first-class clock signal KA and the first level of the second-class clock signal KB have the same duration.

[0103] The embodiments of the present disclosure may also provide a display panel and a gate drive circuit applied to the display panel. Referring to FIG2 , the display panel includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel is provided with display units distributed in an array, and the display units include sub-pixels PIX and pixel drive circuits PDC that drive the sub-pixels PIX. The display panel does not set display units in the peripheral area BB, or the set display units are not used to display images. Referring to FIG2 , the display panel is provided with a plurality of gate lines GL extending along the row direction DH in the display area AA, and each gate line GL is provided in a one-to-one correspondence with each display unit row. The pixel drive circuit PDC of each display unit in the display unit row is electrically connected to the corresponding gate line GL. The display panel is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA, and each data line DL is provided in a one-to-one correspondence with each display unit column. The pixel drive circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to a gate line GL and a data line DL. When a gate signal is applied to the gate line GL, the driving voltage applied to the data line DL can be written into the pixel driving circuit PDC, thereby allowing the pixel driving circuit PDC to control the brightness of the sub-pixel PIX according to the written driving voltage.

[0104] Optionally, the display panel may be a display panel of a vehicle-mounted display device.

[0105] In one embodiment of the present disclosure, the display panel may be a liquid crystal display panel, and the pixel driving circuit PDC may be a switching transistor.

[0106] In some other embodiments of the present disclosure, the sub-pixel PIX can be a current-driven light-emitting element, for example, other types of light-emitting elements can be obtained for OLED, PLED, QLED, Micro LED, Mini LED. Optionally, the pixel driving circuit PDC includes at least a data write transistor, a driving transistor and a storage capacitor, and the gate of the driving transistor can be electrically connected to an electrode plate of the storage capacitor. The first electrode of the data write transistor can be electrically connected to the data line DL, and the gate of the data write transistor can be electrically connected to the selection line GL. The pixel driving circuit PDC is configured so that when a selection signal is loaded on the selection line GL, the data write transistor is turned on, thereby causing the driving voltage on the data line DL to be written into the gate of the driving transistor and the storage capacitor. When the data write transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It can be understood that the pixel driving circuit PDC of the embodiment of the present disclosure can also include other transistors or capacitors to enable the pixel driving circuit PDC to have better driving performance. For example, the pixel driving circuit PDC may be a 7T1C (seven thin film transistors and one storage capacitor), an 8T1C (eight thin film transistors and one storage capacitor) or a pixel driving circuit with other architectures.

[0107] It is understandable that other lines for driving the pixel driving circuit PDC may be provided on the display panel as needed, such as a light emitting control line for controlling whether the driving power supply voltage can be loaded onto the pixel driving circuit PDC, a gate reset line for resetting the gate of the driving transistor, an electrode reset line for resetting the pixel electrode of the light emitting element, etc. Among them, the light emitting control line may be loaded with a light emitting control signal, the gate reset line may be loaded with a gate reset control signal, and the electrode reset line may be loaded with an electrode reset control signal. When driving each sub-pixel row row by row to display an image, a scan signal may be loaded onto at least one of the selection line GL, the light emitting control line, the gate reset line, and the electrode reset line.

[0108] Referring to FIG3 , the gate drive circuit GOA is arranged on one side of the display area AA, and of course can also be arranged on both sides of the display area AA. The gate drive circuit may include a plurality of shift registers SR (e.g., a first shift register SR1, a second shift register SR2, and a third shift register SR3) cascaded in sequence, and each shift register SR is the shift register SR described in the above embodiment. Among them, in two adjacent stages of shift registers SR, the signal output end of the upper stage shift register SR is connected to the signal input end of the lower stage shift register SR. The scanning signal (the voltage is the first power supply voltage V1) output by the signal output end of the shift register SR can be used as one or more of the selection signal, light-emitting control line, gate reset control signal, and electrode reset control signal of the display panel.

[0109] For example, the output ends of the shift registers SR of the gate driving circuit are electrically connected to the gate lines GL in a one-to-one correspondence, so that the first level scanning signal output by the shift register SR is the gate signal on the connected gate line GL.

[0110] In one embodiment of the present disclosure, referring to FIG. 4 , the gate driving circuit includes a plurality of shift register sets SRSSRS. The shift register set SRSSRS includes a first shift register SR1 , a second shift register SR2 , and a third shift register SR3 cascaded in sequence.

[0111] In this exemplary embodiment, the display panel is provided with a first clock signal line, a second clock signal line, and a third clock signal line in the peripheral area BB for cooperating with the gate drive circuit. The first clock signal line is used to load the first clock signal CK1 to drive the first shift register SR1 and the second shift register SR2. The second clock signal line is used to load the second clock signal CK2 to drive the second shift register SR2 and the third shift register SR3. The third clock signal line is used to load the third clock signal CK3 to drive the first shift register SR1 and the third shift register SR3. As shown in Figures 4, 5, and 11 (taking the transistors as P-type transistors as an example), the first type of clock signal terminal of the first shift register SR1 (for loading the first type of clock signal KA) is electrically connected to the third clock signal line (for loading the third clock signal CK3), and the second type of clock signal terminal of the first shift register SR1 is electrically connected to the first clock signal line, and the corresponding signal output terminal is the signal output terminal OUT1;

[0112] As shown in FIG4 , FIG5 and FIG12 (taking the transistor as a P-type transistor as an example), the first type of clock signal terminal of the second shift register SR2 is electrically connected to the first clock signal trace, the second type of clock signal terminal of the second shift register SR2 is electrically connected to the second clock signal trace, and the corresponding signal output terminal OUT is the signal output terminal OUT2;

[0113] As shown in Figures 4, 5 and 13 (taking the transistor as a P-type transistor as an example), the first type of clock signal terminal of the third shift register SR3 is electrically connected to the second clock signal trace, the second type of clock signal terminal of the third shift register SR3 is electrically connected to the third clock signal trace, and the corresponding signal output terminal OUT is the signal output terminal OUT3.

[0114] In this embodiment, the display panel can provide three clock signals, namely, a first clock signal CK1, a second clock signal CK2, and a third clock signal CK3, to the gate drive circuit GOA. Each shift register SR can use two of the three clock signals to ensure its normal operation. In this way, the clock signals of the first shift register SR1, the second shift register SR2, and the third shift register SR3 can be multiplexed with each other, which can reduce the number of clock signals required by the gate drive circuit, thereby reducing the number of clock signal traces provided by the display panel.

[0115] Optionally, the amplitude of the second level of the first clock signal trace, the amplitude of the second level of the second clock signal trace, and the amplitude of the second level of the third clock signal trace are the same, and are all 0.5 to 3V higher than the amplitude of the signal at the second power supply voltage terminal.

[0116] For example, the high-level power supply voltage VGH is 7V, the low-level power supply voltage VGL is -7V, and the first and second levels of the first clock signal CK1, the first and second levels of the second clock signal CK2, and the first and second levels of the third clock signal CK3 all have an amplitude of 8V. This allows the third electrode and the source and drain of the seventh transistor T7 and the eighth transistor T8 to be written using different voltages. The design ensures that the gate-source voltage VGS is greater than 0 (for P-type MOS transistors, for example), preventing the threshold voltage Vth from being positively biased under high-load operating conditions (i.e., high temperature conditions or high-voltage aging conditions) and causing transistor failure and screen splitting, thereby improving product yield and reliability.

[0117] Optionally, the duration of the first level of the first clock signal routing, the duration of the first level of the second clock signal routing, and the duration of the first level of the third clock signal routing are the same and do not exceed one-third of a clock cycle, for example, 1 / 3 of a clock cycle, 1 / 4 of a clock cycle, 1 / 5 of a clock cycle, or 1 / 6 of a clock cycle.

[0118] Optionally, a start time of the first level of the first clock signal routing line differs from a start time of the first level of a subsequent third clock signal routing line by two-thirds of a clock cycle;

[0119] The difference between the start time of the first level of the second clock signal line and the start time of the first level of the subsequent first clock signal line is two-thirds of a clock cycle;

[0120] The difference between the start time of the first level of the third clock signal line and the start time of the first level of the subsequent second clock signal line is two-thirds of a clock cycle.

[0121] Of course, in other embodiments of the present disclosure, the clock signals of the first shift register SR1, the second shift register SR2 and the third shift register SR3 may not be multiplexed with each other. For example, the display panel may set six clock signal lines to provide the required clock signals for the three shift registers respectively.

[0122] The following describes the operating principle of the shift register in this exemplary embodiment in detail, taking each transistor as a P-type transistor as an example, in conjunction with the drive timing diagram in FIG5 . In the example in FIG5 , the first level of the clock signal is a low level, and the second level of the clock signal is a high level. The first power supply voltage is a low-level power supply voltage VGL, and the second power supply voltage is a low-level power supply voltage VGL.

[0123] In the example of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 in FIG5, the third clock signal CK3 and the first clock signal CK1 can be combined into a first clock signal group for driving the first shift register SR1. Specifically, the third clock signal CK3 is a first-type clock signal KA in the first clock signal group, and the first clock signal CK1 is a second-type clock signal KB in the first clock signal group. Driven by the first clock signal group, the first shift register SR1 can output the first-level scan signal of the current stage from the signal output terminal OUT1 according to the start signal GSTV at the signal input terminal (for example, an externally input start signal GSTV or a first-level scan signal output by the previous-stage shift register that can serve as the start signal GSTV).

[0124] For example, among the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 shown in FIG5 , the first clock signal CK1 and the second clock signal CK2 can be combined into a second clock signal group for driving the second shift register SR2. Specifically, the first clock signal CK1 is a first-type clock signal KA in the second clock signal group, and the second clock signal CK2 is a second-type clock signal KB in the second clock signal group. Driven by the second clock signal group, the second shift register SR2 can output the first-level scan signal of the current stage from the signal output terminal OUT2 according to the start signal GSTV at the signal input terminal (e.g., an externally input start signal GSTV or a first-level scan signal output by the previous-stage shift register that can serve as the start signal GSTV).

[0125] For example, among the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 shown in FIG5 , the second clock signal CK2 and the third clock signal CK3 can be combined into a third clock signal group. Specifically, the second clock signal CK2 is the first type of clock signal KA in the third clock signal group, and the third clock signal CK3 is the second type of clock signal KB in the third clock signal group. Driven by the third clock signal group, the third shift register SR3 can output the first level scan signal of this stage from the signal output terminal OUT3 according to the start signal GSTV at the signal input terminal (e.g., the start signal GSTV input externally or the first level scan signal output by the previous shift register, which can serve as the start signal GSTV).

[0126] Taking the working process of the first shift register SR1 (taking the transistor as a P-type transistor as an example) as an example, the principle of the shift register is exemplarily explained. In this example, the first clock signal CK1 is the second type of clock signal KB of the shift register, and the first clock signal CK1 is the second type of clock signal KB of the shift register.

[0127] First period H1: As shown in Figures 5 and 6, the first clock signal CK1 is at the second level, and the third clock signal CK3 is at the first level. The signal input terminal In of the first shift register SR1 is loaded with the start signal GSTV, which is at the first level. It will be understood that the first shift register SR1 in this example is the first-stage shift register in the gate drive circuit. During this first period H1, the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on. The low-level power supply voltage VGL is transmitted to the first node N1 via the third transistor T3, turning on the seventh transistor T7 and storing the first level in the first capacitor C1. The high-level power supply voltage VGH is transmitted to the signal output terminal OUT1 via the seventh transistor T7, which then outputs the second level. Since the low-level power supply voltage VGL is applied to the third electrode of the fourth transistor T4, the fourth transistor T4 is turned on, causing the second level of the first clock signal CK1 to be applied to the second node N2. This turns off the eighth transistor T8, and the second level of the first clock signal CK1 is stored in the second capacitor C2.

[0128] Second period H2: As shown in Figures 5 and 7, the first clock signal CK1 and the start signal GSTV are both at the first level, the signal input terminal In is at the first level, and the third clock signal CK3 is at the second level. The first transistor T1, the second transistor T2, and the sixth transistor T6 are turned on, and the third transistor T3 and the fifth transistor T5 are turned off. The second level of the third clock signal CK3 is transmitted to the first node N1 via the second transistor T2, causing the fourth transistor T4 and the seventh transistor T7 to turn off, and the second level is written into the first capacitor C1. The first level of the first clock signal CK1 is transmitted to the second node N2 via the first transistor T1 and the sixth transistor T6, causing the eighth transistor T8 to turn on. At the same time, the first level is written into the second capacitor C2, and the low-level power supply voltage VGL is transmitted to the signal output terminal OUT1 via the eighth transistor T8. At this time, the signal output terminal OUT1 outputs the low-level power supply voltage VGL.

[0129] During the third period H3, as shown in Figures 5 and 8, the first clock signal CK1, the third clock signal CK3, and the start signal GSTV are all at the second level. The signal input terminal In receives the second level of the start signal GSTV, the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned off, and the sixth transistor T6 is turned on. The second level of the first node N1 is maintained, and the fourth transistor T4 and the seventh transistor T7 remain off. The first level of the second node is maintained, and the eighth transistor T8 is turned on. The low-level power supply voltage VGL is transmitted to the signal output terminal OUT1 via the eighth transistor T8. At this time, the signal output terminal OUT1 outputs the low-level power supply voltage VGL.

[0130] Fourth period H4: As shown in Figures 5 and 9, the first clock signal CK1 and the start signal GSTV are both at the second level, the third clock signal CK3 is at the first level, and the signal input terminal In is connected to the second level of the start signal GSTV. The third transistor T3 and the fifth transistor T5 are both turned on, while the first transistor T1 and the second transistor T2 are both turned off. The low-level power supply voltage VGL is applied to the third electrode of the sixth transistor T6, turning on the sixth transistor T6. The low-level power supply voltage VGL is applied to the third electrode of the fourth transistor T4 and the first node N1 through the third transistor T3, turning on the fourth transistor T4 and the seventh transistor T7. At the same time, the first capacitor C1 maintains the low-level power supply voltage VGL, and the high-level power supply voltage VGH is transmitted to the signal output terminal OUT1 through the seventh transistor T7. At this time, the signal output terminal OUT1 outputs the second level. The second level of the first clock signal CK1 is transmitted to the second node N2 through the fourth transistor T4, the third node N3, the fifth transistor T5, and the sixth transistor T6. The eighth transistor T8 is turned off, and the second level of the first clock signal CK1 is stored in the second capacitor C2.

[0131] Fifth period H5: As shown in Figures 5 and 10, the third clock signal CK3 and the start signal GSTV are both at the second level, the first clock signal CK1 is at the first level, and the signal input terminal In is connected to the second level of the start signal GSTV. The first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned off. Since the sixth transistor T6 is loaded with the low-level power supply voltage VGL, the sixth transistor T6 is turned on. The second capacitor C2 maintains the second level at the second node N2, causing the eighth transistor T8 to remain off. The first capacitor C1 maintains the first level at the first node N1, causing the seventh transistor T7 to remain on. As a result, the high-level power supply voltage VGH is transmitted to the signal output terminal OUT1 through the seventh transistor T7. At this time, the signal output terminal OUT1 outputs the second level.

[0132] It should be noted that the first-type clock signal KA including the third clock signal CK3 and the second-type clock signal KB including the first clock signal CK1 are only used in the above exemplary embodiments.

[0133] Based on the above description, it can be seen that the shift register in this example embodiment completes the conversion from outputting the second-level signal to outputting the first-level signal in the first period H1 to the third period H3; in addition, in the Tf stage in the low-frequency LTPS gate drive circuit, it can stably output the square wave signal, avoid waveform jitter, reduce the possibility of mura in the product, and improve the image quality of the product.

[0134] Compared with the prior art, the gate driving circuit provided in this exemplary embodiment has a simple structure, which is conducive to the design of a narrow-frame display panel. At the same time, based on the stable output of the shift register, the output stability of the gate driving circuit is improved.

[0135] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known to be configured to implement the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A shift register, comprising: A first input subcircuit is configured to write a signal at a first power supply voltage terminal into a first node in response to a first level of a first-type clock signal terminal; A second input subcircuit is configured to write the signal of the first-type clock signal terminal into the first node in response to a first level on the signal input terminal; A first output subcircuit, comprising a first output unit, wherein the first output unit is configured to write a signal at a second power supply voltage terminal into a signal output terminal in response to a first level at the first node; A first control subcircuit is configured to write a signal of the second-type clock signal terminal into the second node in response to a first level on the signal input terminal; A second control subcircuit is configured to write the signal of the second-type clock signal terminal into a third node in response to the first level on the first node; A third control subcircuit is configured to connect the third node and the second node in response to the first level of the first-type clock signal terminal; as well as The second output sub-circuit includes a second output unit, wherein the second output unit is configured to write the signal at the first power supply voltage terminal into the signal output terminal in response to the first level at the second node.

2. The shift register according to claim 1, wherein: The first control subcircuit includes a first transistor, a first electrode of the first transistor is electrically connected to the second-type clock signal terminal, a third electrode of the first transistor is electrically connected to the signal input terminal, and a second electrode of the first transistor is electrically connected to the second node.

3. The shift register according to claim 1, wherein: The second input subcircuit includes a second transistor, a first electrode of the second transistor is electrically connected to the first type clock signal terminal, a third electrode of the second transistor is electrically connected to the signal input terminal, and a second electrode of the second transistor is electrically connected to the first node.

4. The shift register according to claim 1, wherein: The second control subcircuit includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the second type clock signal terminal, a third electrode of the fourth transistor is electrically connected to the first node, and a second electrode of the fourth transistor is electrically connected to the third node.

5. The shift register according to claim 1, wherein: The first input subcircuit comprises a third transistor, a first electrode of the third transistor is electrically connected to the first power supply voltage terminal, a third electrode of the third transistor is electrically connected to the first type clock signal terminal, and a second electrode of the third transistor is electrically connected to the first node; The third control subcircuit comprises a fifth transistor, a first electrode of the fifth transistor is electrically connected to the third node, a third electrode of the fifth transistor is electrically connected to the first type clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node; The first output unit includes a seventh transistor, a first electrode of the seventh transistor is electrically connected to the second power supply voltage terminal, a third electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to the signal output terminal; The second output unit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the first power supply voltage terminal, a third electrode of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the signal output terminal.

6. The shift register according to claim 1, wherein: The shift register further includes a voltage stabilizing subcircuit, which is electrically connected to the second node and the fourth node respectively; the voltage stabilizing circuit is configured to write the voltage of the fourth node into the second node under the control of the signal of the first power supply voltage terminal; The fourth node is electrically connected to the first control sub-circuit and the third control sub-circuit.

7. The shift register according to claim 6, wherein: The voltage stabilization subcircuit includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the fourth node, a third electrode of the sixth transistor is electrically connected to the first power supply voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

8. The shift register according to claim 1, wherein: The first output subcircuit further includes a first capacitor, a first electrode plate of the first capacitor is electrically connected to the first node; a second electrode plate of the first capacitor is electrically connected to the second power supply voltage terminal; The second output subcircuit further includes a second capacitor, wherein a first electrode plate of the second capacitor is electrically connected to the second node; and a second electrode plate of the second capacitor is electrically connected to the signal output terminal.

9. The shift register according to claim 1, wherein: The duration of the first level of the first-type clock signal end is the same as the duration of the first level of the second-type clock signal end, and neither of them exceeds one third of the clock cycle.

10. The shift register according to claim 9, wherein: The first level of the first-type clock signal terminal is one-third of a clock cycle earlier than the first level of the second-type clock signal terminal.

11. The shift register according to claim 9, wherein: The amplitude of the second level of the first-type clock signal terminal and the amplitude of the second level of the second-type clock signal terminal are both greater than the amplitude of the signal of the second power supply voltage terminal.

12. A gate drive circuit, comprising a plurality of shift registers according to any one of claims 1 to 11 connected in cascade order; in two adjacent stages of the shift registers, a signal output terminal of the upper stage shift register is electrically connected to a signal input terminal of the lower stage shift register; In the gate driving circuit, the signal input terminal of the first-stage shift register is electrically connected to the start signal terminal; The gate driving circuit includes a plurality of shift register groups, and the shift register group includes three sequentially cascaded first shift registers, second shift registers and third shift registers; in, The first type of clock signal terminal of the first shift register is electrically connected to a third clock signal wiring, and the second type of clock signal terminal of the first shift register is electrically connected to a first clock signal wiring; The first type of clock signal terminal of the second shift register is electrically connected to the first clock signal wiring, and the second type of clock signal terminal of the second shift register is electrically connected to the second clock signal wiring; The first type of clock signal terminal of the third shift register is electrically connected to the second clock signal wiring, and the second type of clock signal terminal of the third shift register is electrically connected to the third clock signal wiring.

13. The gate driving circuit according to claim 12, wherein: The amplitude of the second level of the first clock signal routing, the amplitude of the second level of the second clock signal routing and the amplitude of the second level of the third clock signal routing are the same, and are all 0.5 to 3V higher than the amplitude of the signal at the second power supply voltage terminal.

14. The gate driving circuit according to claim 12, wherein: The duration of the first level of the first clock signal routing, the duration of the first level of the second clock signal routing and the duration of the first level of the third clock signal routing are the same and do not exceed one third of a clock cycle.

15. The gate driving circuit according to claim 12, wherein: The starting time of the first level of the first clock signal routing line differs from the starting time of the first level of the third clock signal routing line by two-thirds of a clock cycle; The starting time of the first level of the second clock signal routing line differs from the starting time of the first level of the first clock signal routing line by two-thirds of a clock cycle; The start time of the first level of the third clock signal routing differs from the start time of the first level of the second clock signal routing thereafter by two-thirds of a clock cycle.

16. A display panel comprising the gate driving circuit according to any one of claims 12 to 15.

Images