Shift register unit, display driving circuit, display panel and control method

Abstract

A shift register unit (200), a display driving circuit (410), a display panel (400) and a control method wherein the shift register unit (200) comprises: an input circuit (210) for providing signals of an input signal terminal (IN) and a power signal terminal (VGH) to a first pull-up node (Q1) and a first pull-down node (QB1); the first control circuit (220) is used for controlling the potential of the first pull-down node (QB1) based on the potential of the first pull-up node (Q1) and controlling the potential of the first pull-up node (Q1) based on the potential of the first pull-down node (QB1); the second control circuit is used for controlling the potential of a second pull-up node (Q2) based on the signal of the first pull-up node (Q1) and controlling the potential of a second pull-down node (QB2) by using the signal of the first pull-down node (QB1); and the output circuit is used for providing a signal of one of a power supply signal end (VGH) and a reference signal end (VGL) to an output signal end (OUT) under the control of the second pull-up node (Q2) and the second pull-down node (QB2).

Description

Shift register unit, display driving circuit, display panel and control method Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit, a display driving circuit, a pixel driving circuit, a display panel, and a control method for a shift register unit. Background Art

[0002] In the display field, particularly OLED displays, oxides are widely used in medium and large-sized display devices due to their excellent uniformity. Internal compensation, a technique used to drive pixels for display, has attracted widespread attention due to its low cost and excellent performance. However, implementing pulse width modulation (PWM) waveforms in N-type TFTs is difficult.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides a shift register unit, comprising:

[0005] an input circuit connected to an input signal terminal, a power signal terminal, a first pull-up node, and a first pull-down node of the shift register unit, and configured to provide signals from the input signal terminal and the power signal terminal to the first pull-up node and the first pull-down node;

[0006] a first control circuit connected to the first pull-up node and the first pull-down node, configured to control the potential of the first pull-down node based on the potential of the first pull-up node and to control the potential of the first pull-up node based on the potential of the first pull-down node;

[0007] a second control circuit connected to the first pull-up node, the first pull-down node, the second pull-up node, and the second pull-down node of the shift register unit, configured to control the potential of the second pull-up node based on a signal of the first pull-up node, and to control the potential of the second pull-down node based on a signal of the first pull-down node; and

[0008] An output circuit is connected to the second pull-up node, the second pull-down node, the power signal terminal, the reference signal terminal and the output signal terminal of the shift register unit, and is used to provide a signal from one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node.

[0009] For example, the second control circuit includes: a first transmission control sub-circuit, connected to the first pull-up node, the third pull-up node of the shift register unit and the second clock signal terminal, for providing the signal at the second clock signal terminal to the third pull-up node under the control of the first pull-up node; a second transmission control sub-circuit, connected to the second pull-up node, the third pull-up node and the second clock signal terminal, for providing the signal at the third pull-up node to the second pull-up node under the control of the second clock signal terminal.

[0010] For example, the first transmission control sub-circuit includes a first transistor and a first capacitor, the gate of the first transistor is connected to the first pull-up node, the first electrode of the first transistor is connected to the second clock signal terminal, the second electrode of the first transistor is connected to the third pull-up node, the first electrode of the first capacitor is connected to the first pull-up node, and the second electrode of the first capacitor is connected to the third pull-up node; the second transmission control sub-circuit includes a second transistor, the gate of the second transistor is connected to the second clock signal terminal, the first electrode of the second transistor is connected to the third pull-up node, and the second electrode of the second transistor is connected to the second pull-up node.

[0011] For example, the second control circuit also includes: a third transmission control sub-circuit, connected to the first pull-down node, the reference signal terminal and the third pull-up node, for providing the signal at the reference signal terminal to the third pull-up node under the control of the first pull-down node.

[0012] For example, the third transmission control subcircuit includes a third transistor and a second capacitor, the gate of the third transistor is connected to the first pull-down node, the first electrode of the third transistor is connected to the reference signal end, the second electrode of the third transistor is connected to the third pull-up node, the first electrode of the second capacitor is connected to the first pull-down node, and the second electrode of the second capacitor is connected to the reference signal end.

[0013] For example, the second control circuit also includes: a fourth transmission control sub-circuit, connected to the first pull-down node, the second pull-down node and the second clock signal terminal, for providing the signal at the first pull-down node to the second pull-down node under the control of the second clock signal terminal.

[0014] For example, the fourth transmission control subcircuit includes a fourth transistor, the gate of the fourth transistor is connected to the second clock signal terminal, the first electrode of the fourth transistor is connected to the first pull-down node, and the second electrode of the fourth transistor is connected to the second pull-down node.

[0015] For example, the shift register unit also includes: a first voltage stabilizing circuit, connected between the first pull-up node and the first transmission control sub-circuit, wherein the first voltage stabilizing circuit and the first transmission control sub-circuit are connected to a fourth pull-up node, and the first voltage stabilizing circuit is used to stabilize the potential of the fourth pull-up node.

[0016] For example, the first voltage stabilizing circuit includes: a fifth transistor, a gate of the fifth transistor is connected to the power signal terminal, a first electrode of the fifth transistor is connected to the first pull-up node, and a second electrode of the fifth transistor is connected to the fourth pull-up node.

[0017] For example, the input circuit includes: a first input sub-circuit, connected to the input signal terminal, the first pull-up node and the first clock signal terminal of the shift register unit, for providing the signal at the input signal terminal to the first pull-up node under the control of the first clock signal terminal; a second input sub-circuit, connected to the power signal terminal, the first pull-down node and the first clock signal terminal, for providing the signal at the power signal terminal to the first pull-down node under the control of the first clock signal terminal.

[0018] For example, the first input sub-circuit includes a sixth transistor, the gate of the sixth transistor is connected to the first clock signal terminal, the first electrode of the sixth transistor is connected to the input signal terminal, and the second electrode of the sixth transistor is connected to the first pull-up node; the second input sub-circuit includes a seventh transistor, the gate of the seventh transistor is connected to the first clock signal terminal, the first electrode of the seventh transistor is connected to the power signal terminal, and the second electrode of the seventh transistor is connected to the first pull-down node.

[0019] For example, the first control circuit includes: a pull-up control subcircuit, connected to the first pull-up node, the first pull-down node and the first clock signal terminal, for providing the signal at the first clock signal terminal to the first pull-down node under the control of the first pull-up node; a pull-down control subcircuit, connected to the first pull-up node, the first pull-down node, the reference signal terminal and the second clock signal terminal of the shift register unit, for providing the signal at the reference signal terminal to the first pull-up node under the control of the second clock signal terminal and the first pull-down node.

[0020] For example, the pull-up control subcircuit includes an eighth transistor, the gate of the eighth transistor is connected to the first pull-up node, the first electrode of the eighth transistor is connected to the first clock signal end, and the second electrode of the eighth transistor is connected to the first pull-down node; the pull-down control subcircuit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor is connected to the second clock signal end, the first electrode of the ninth transistor is connected to the second electrode of the tenth transistor, the second electrode of the ninth transistor is connected to the first pull-up node or the fourth pull-up node, the gate of the tenth transistor is connected to the first pull-down node, and the first electrode of the tenth transistor is connected to the reference signal end.

[0021] For example, the output circuit includes: a first output sub-circuit, connected to one of the power supply signal terminal and the reference signal terminal, the second pull-up node and the output signal terminal, and used to provide the signal at one of the power supply signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node; a second output sub-circuit, connected to the other of the power supply signal terminal and the reference signal terminal, the second pull-down node and the output signal terminal, and used to provide the signal at the other of the power supply signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-down node.

[0022] For example, the first output sub-circuit includes an eleventh transistor and a third capacitor, wherein the gate of the eleventh transistor is connected to the second pull-up node, the first electrode of the eleventh transistor is connected to the power signal terminal, the second electrode of the eleventh transistor is connected to the output signal terminal, the first electrode of the third capacitor is connected to the second pull-up node, and the second electrode of the third capacitor is connected to the output signal terminal or the second clock signal terminal; the second output sub-circuit includes a twelfth transistor and a fourth capacitor, wherein the gate of the twelfth transistor is connected to the second pull-down node, the first electrode of the twelfth transistor is connected to the reference signal terminal, the second electrode of the twelfth transistor is connected to the output signal terminal, the first electrode of the fourth capacitor is connected to the second pull-down node, and the second electrode of the fourth capacitor is connected to the reference signal terminal.

[0023] For example, the second output sub-circuit also includes a thirteenth transistor and a fourteenth transistor, the first electrode of the twelfth transistor is connected to the reference signal terminal through the thirteenth transistor, wherein the gate of the thirteenth transistor is connected to the second pull-down node, the first electrode of the thirteenth transistor is connected to the reference signal terminal, and the second electrode of the thirteenth transistor is connected to the first electrode of the twelfth transistor; the gate of the fourteenth transistor is connected to the output signal terminal, the first electrode of the fourteenth transistor is connected to the power supply signal terminal, and the second electrode of the fourteenth transistor is connected to the first electrode of the twelfth transistor.

[0024] For example, the first output sub-circuit includes an eleventh transistor and a third capacitor, wherein the gate of the eleventh transistor is connected to the second pull-up node, the first electrode of the eleventh transistor is connected to the reference signal terminal, the second electrode of the eleventh transistor is connected to the output signal terminal, the first electrode of the third capacitor is connected to the second pull-up node, and the second electrode of the third capacitor is connected to the reference signal terminal; the second output sub-circuit includes a twelfth transistor and a fourth capacitor, wherein the gate of the twelfth transistor is connected to the second pull-down node, the first electrode of the twelfth transistor is connected to the power supply signal terminal, the second electrode of the twelfth transistor is connected to the output signal terminal, the first electrode of the fourth capacitor is connected to the second pull-down node, and the second electrode of the fourth capacitor is connected to the output signal terminal.

[0025] For example, the first output sub-circuit also includes a thirteenth transistor and a fourteenth transistor, the second electrode of the eleventh transistor is connected to the output signal end through the thirteenth transistor, wherein the gate of the thirteenth transistor is connected to the second pull-up node, the first electrode of the thirteenth transistor is connected to the second electrode of the eleventh transistor, and the second electrode of the thirteenth transistor is connected to the output signal end; the gate of the fourteenth transistor is connected to the output signal end, the first electrode of the fourteenth transistor is connected to the power signal end, and the second electrode of the fourteenth transistor is connected to the second electrode of the eleventh transistor.

[0026] For example, the shift register unit also includes: a second voltage stabilizing circuit, connected between the first pull-down node and the fourth transmission control sub-circuit, wherein the second voltage stabilizing circuit and the fourth transmission sub-circuit are connected to a third pull-down node, and the second voltage stabilizing circuit is used to stabilize the potential of the third pull-down node.

[0027] For example, the second voltage stabilizing circuit includes: a fifteenth transistor and a sixteenth transistor; the gate of the fifteenth transistor is connected to the first pull-down node, the first electrode of the fifteenth transistor is connected to the second clock signal terminal, the second electrode of the fifteenth transistor and the first electrode of the fourth transistor in the fourth transmission sub-circuit are connected to the third pull-down node; the gate of the sixteenth transistor is connected to the first pull-up node or the fourth pull-up node, the first electrode of the sixteenth transistor is connected to the reference signal terminal, and the second electrode of the sixteenth transistor is connected to the third pull-down node.

[0028] For example, the second voltage stabilizing circuit further includes: a seventeenth transistor, the gate of the seventeenth transistor is connected to the second clock signal end, the first electrode of the seventeenth transistor is connected to the second electrode of the sixteenth transistor, and the second electrode of the seventeenth transistor is connected to the second electrode of the fifteenth transistor.

[0029] For example, the third pull-up node is used as a control output terminal of the shift register unit for cascade connection with other shift register units.

[0030] For example, the input circuit includes: a first input sub-circuit, connected to the power signal terminal, the first pull-up node and the first clock signal terminal of the shift register unit, for providing the signal at the power signal terminal to the first pull-up node under the control of the first clock signal terminal; a second input sub-circuit, connected to the input signal terminal, the first pull-down node and the first clock signal terminal, for providing the signal at the input signal terminal to the first pull-down node under the control of the first clock signal terminal.

[0031] For example, the first input sub-circuit includes a sixth transistor, the gate of the sixth transistor is connected to the first clock signal terminal, the first electrode of the sixth transistor is connected to the power signal terminal, and the second electrode of the sixth transistor is connected to the first pull-up node; the second input sub-circuit includes a seventh transistor, the gate of the seventh transistor is connected to the first clock signal terminal, the first electrode of the seventh transistor is connected to the input signal terminal, and the second electrode of the seventh transistor is connected to the first pull-down node.

[0032] For example, the first control circuit includes: a pull-up control subcircuit, connected to the first pull-up node, the first pull-down node and the first clock signal terminal, for providing the signal at the first clock signal terminal to the first pull-up node under the control of the first pull-down node; a pull-down control subcircuit, connected to the first pull-up node, the first pull-down node, the reference signal terminal and the second clock signal terminal of the shift register unit, for providing the signal at the reference signal terminal to the first pull-down node under the control of the second clock signal terminal and the first pull-up node.

[0033] For example, the pull-up control subcircuit includes an eighth transistor, the gate of the eighth transistor being connected to the first pull-down node, the first electrode of the eighth transistor being connected to the first clock signal terminal, and the second electrode of the eighth transistor being connected to the first pull-up node; and the pull-down control subcircuit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor being connected to the first pull-up node, the first electrode of the ninth transistor being connected to the reference transistor, the second electrode of the ninth transistor being connected to the first electrode of the tenth transistor, the gate of the tenth transistor being connected to the second clock signal terminal, and the second electrode of the tenth transistor being connected to the first pull-down node.

[0034] For example, the output circuit includes: a first output sub-circuit, connected to the reference signal terminal, the second pull-up node and the output signal terminal, for providing the signal at the reference signal terminal to the output signal terminal under the control of the second pull-up node; a second output sub-circuit, connected to the power signal terminal, the second pull-down node and the output signal terminal, for providing the signal at the power signal terminal to the output signal terminal under the control of the second pull-down node.

[0035] For example, the first output sub-circuit includes an eleventh transistor and a third capacitor, wherein the gate of the eleventh transistor is connected to the second pull-up node, the first electrode of the eleventh transistor is connected to the reference signal terminal, the second electrode of the eleventh transistor is connected to the output signal terminal, the first electrode of the third capacitor is connected to the second pull-up node, and the second electrode of the third capacitor is connected to the reference signal terminal; the second output sub-circuit includes a twelfth transistor and a fourth capacitor, wherein the gate of the twelfth transistor is connected to the second pull-down node, the first electrode of the twelfth transistor is connected to the power supply signal terminal, the second electrode of the twelfth transistor is connected to the output signal terminal, the first electrode of the fourth capacitor is connected to the second pull-down node, and the second electrode of the fourth capacitor is connected to the output signal terminal.

[0036] For example, the first output sub-circuit also includes a thirteenth transistor and a fourteenth transistor, the first electrode of the eleventh transistor is connected to the reference signal terminal via the thirteenth transistor, wherein the gate of the thirteenth transistor is connected to the second pull-up node, the first electrode of the thirteenth transistor is connected to the reference signal terminal, and the second electrode of the thirteenth transistor is connected to the first electrode of the eleventh transistor; the gate of the fourteenth transistor is connected to the output signal terminal, the first electrode of the fourteenth transistor is connected to the power supply signal terminal, and the second electrode of the fourteenth transistor is connected to the first electrode of the eleventh transistor.

[0037] For example, the shift register unit further includes: a third voltage stabilizing circuit connected to the second pull-up node, the first pull-down node and the reference signal terminal, for providing the signal at the reference signal terminal to the second pull-up node under the control of the first pull-down node.

[0038] For example, the third voltage stabilization circuit includes an eighteenth transistor, the gate of the eighteenth transistor is connected to the first pull-down node, the first electrode of the eighteenth transistor is connected to the reference signal terminal, and the second electrode of the eighteenth transistor is connected to the second pull-up node.

[0039] For example, the shift register unit further includes: a fourth voltage stabilizing circuit connected between the first pull-down node and the second pull-down node, and configured to stabilize the potential of the second pull-down node.

[0040] For example, the fourth voltage stabilization circuit includes a nineteenth transistor, the gate of the nineteenth transistor is connected to the power signal terminal, the first electrode of the nineteenth transistor is connected to the first pull-down node, and the second electrode of the nineteenth transistor is connected to the second pull-down node.

[0041] For example, the shift register unit further includes a fifth voltage stabilizing circuit connected to the second pull-down node and configured to stabilize the potential at the second pull-down node.

[0042] For example, the fifth voltage stabilizing circuit includes a fifth capacitor, a first electrode of the fifth capacitor is connected to the first clock signal terminal, and a second electrode of the fifth capacitor is connected to the second pull-down node; or the fifth voltage stabilizing circuit includes a fifth capacitor and a twentieth transistor, a first electrode of the fifth capacitor is connected to the first clock signal terminal, a second electrode of the fifth capacitor is connected to the second pull-down node, a gate of the twentieth transistor is connected to the third clock signal terminal of the shift register unit, a first electrode of the twentieth transistor is connected to the first clock signal terminal, and a second electrode of the twentieth transistor is connected to the first electrode of the fifth capacitor; or the fifth voltage stabilizing circuit includes a fifth capacitor, a sixth capacitor and a twentieth transistor, a first electrode of the fifth capacitor is connected to the first clock signal terminal, a second electrode of the fifth capacitor is connected to the second pull-down node, a gate of the twentieth transistor is connected to the third clock signal terminal of the shift register unit, a first electrode of the twentieth transistor is connected to the first clock signal terminal, a second electrode of the twentieth transistor is connected to the first electrode of the fifth capacitor, a first electrode of the sixth capacitor is connected to the second electrode of the twentieth transistor, and a second electrode of the sixth capacitor is connected to the power signal terminal.

[0043] For example, the first control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor, the gate of the eighth transistor is connected to the first pull-down node, the first electrode of the eighth transistor is connected to the first clock signal terminal, the second electrode of the eighth transistor is connected to the first pull-up node, the gate of the ninth transistor is connected to the first pull-up node, the first electrode of the ninth transistor is connected to the reference signal terminal, the second electrode of the ninth transistor and the first electrode of the tenth transistor are connected to the second pull-down node, and the second electrode of the tenth transistor is connected to the second clock signal terminal; the output circuit includes an eleventh transistor, a twelfth transistor, and a fourth capacitor, the gate of the eleventh transistor is connected to the first pull-up node, the first electrode of the ninth transistor is connected to the reference signal terminal, the second electrode of the ninth transistor and the first electrode of the tenth transistor are connected to the second pull-down node, and the second electrode of the tenth transistor is connected to the second clock signal terminal; The second pull-up node, the first electrode of the eleventh transistor is connected to the reference signal terminal, the second electrode of the eleventh transistor is connected to the output signal terminal, the gate of the twelfth transistor is connected to the second pull-down node, the first electrode of the twelfth transistor is connected to the power signal terminal, the second electrode of the twelfth transistor is connected to the output signal terminal, the first electrode of the fourth capacitor is connected to the second pull-down node, and the second electrode of the fourth capacitor is connected to the gate of the tenth transistor; wherein the second control circuit includes a first transmission control sub-circuit and a second transmission control sub-circuit, or the second control circuit includes a first transmission control sub-circuit, a second transmission control sub-circuit and a third transmission control sub-circuit.

[0044] For example, at least one transistor in the input circuit, the first control circuit, the second control circuit, and the output circuit is an N-type transistor.

[0045] An embodiment of the present disclosure further provides a display driving circuit, comprising a plurality of shift register units connected in cascade, wherein the shift register units are the shift register units described above.

[0046] An embodiment of the present disclosure further provides a pixel driving circuit, comprising:

[0047] a driving circuit having a control terminal, a first terminal, and a second terminal, configured to generate a driving current from the first terminal to the second terminal under the control of a signal from the control terminal;

[0048] an input circuit connected to the data signal terminal and the control terminal of the driving circuit, and configured to provide the data signal at the data signal terminal to the control terminal of the driving circuit under the control of the first gate driving signal;

[0049] a compensation circuit connected to the first voltage terminal, the second voltage terminal, and the control terminal and the second terminal of the driving circuit, and configured to provide a reference voltage at the second voltage terminal to the second terminal of the driving circuit under the control of a second gate driving signal, and provide an initial voltage at the first voltage terminal to the control terminal of the driving circuit under the control of a third gate driving signal;

[0050] The light emitting control circuit is connected between the first end of the driving circuit and the power signal end, and is used to connect or disconnect the first end of the driving circuit and the power signal end under the control of the light emitting control signal.

[0051] For example, the compensation circuit includes a first transistor and a second transistor, the gate of the first transistor is configured to receive a second gate drive signal, the first electrode of the first transistor is connected to the second voltage end, and the second electrode of the first transistor is connected to the second end of the drive circuit; the gate of the second transistor is configured to receive a third gate drive signal, the first electrode of the second transistor is connected to the first voltage end, and the second electrode of the second transistor is connected to the control end of the drive circuit.

[0052] For example, the light emitting control circuit includes a third transistor, the gate of the third transistor is configured to receive the light emitting control signal, the first electrode of the third transistor is connected to the power signal terminal, and the second electrode of the third transistor is connected to the first terminal of the driving circuit.

[0053] For example, the input circuit includes a fourth transistor, the gate of the fourth transistor is configured to receive the first gate drive signal, the first electrode of the fourth transistor is connected to the data signal end, and the second electrode of the fourth transistor is connected to the control end of the drive circuit; the drive circuit includes a drive transistor and a capacitor, the gate, drain and source of the drive transistor serve as the control end, first end and second end of the drive circuit respectively, the first electrode of the capacitor is connected to the gate of the drive transistor, and the second electrode of the capacitor is connected to the second electrode of the drive transistor.

[0054] An embodiment of the present disclosure further provides a display panel, comprising at least one display driving circuit as described above and a plurality of sub-pixels arranged in an array, wherein the sub-pixels include a pixel driving circuit, and the pixel driving circuit includes:

[0055] A driving circuit having a control terminal, a first terminal, and a second terminal, configured to generate a driving current from the first terminal to the second terminal under the control of a signal from the control terminal;

[0056] an input circuit connected to the data signal terminal and the control terminal of the driving circuit, and configured to provide the data signal at the data signal terminal to the control terminal of the driving circuit under the control of the first gate driving signal;

[0057] a compensation circuit connected to the first voltage terminal, the second voltage terminal, and the control terminal and the second terminal of the driving circuit, and configured to provide a reference voltage at the second voltage terminal to the second terminal of the driving circuit under the control of a second gate driving signal, and provide an initial voltage at the first voltage terminal to the control terminal of the driving circuit under the control of a third gate driving signal;

[0058] a light emitting control circuit connected between the first terminal of the driving circuit and the power signal terminal, and configured to connect or disconnect the first terminal of the driving circuit and the power signal terminal under the control of a light emitting control signal;

[0059] The display driving circuit is configured to provide at least one of a first gate driving signal, a second gate driving signal, a third gate driving signal and a light emitting control signal to the plurality of sub-pixels.

[0060] An embodiment of the present disclosure further provides a method for controlling the shift register unit as described above, comprising:

[0061] In the input stage, the input circuit provides the signals of the input signal terminal and the power signal terminal to the first pull-up node and the first pull-down node respectively;

[0062] In the output phase, the first control circuit controls the potential of the first pull-down node based on the potential of the first pull-up node and controls the potential of the first pull-up node based on the potential of the first pull-down node, the second control circuit transmits the signal at the first pull-up node to the second pull-up node and transmits the signal at the first pull-down node to the second pull-down node, so that one of the second pull-up node and the first pull-up node is at a high level and the other of the second pull-up node and the first pull-up node is at a low level, and the output circuit provides the signal of one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node;

[0063] In the reset phase, the first control circuit controls the potential of the first pull-down node based on the potential of the first pull-up node and controls the potential of the first pull-up node based on the potential of the first pull-down node, the second control circuit transfers the signal at the first pull-up node to the second pull-up node and transfers the signal at the first pull-down node to the second pull-down node, so that one of the second pull-up node and the first pull-up node is at a high level and the other of the second pull-up node and the first pull-up node is at a low level, and the output circuit provides the signal of the other of the power supply signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] FIG1 shows a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0065] FIG. 2 shows a signal timing diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0066] FIG3 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0067] 4 to 21 respectively illustrate circuit diagrams of multiple examples of shift register units according to embodiments of the present disclosure.

[0068] FIG22 shows a schematic block diagram of a display driving circuit according to an embodiment of the present disclosure.

[0069] FIG23 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0070] FIG. 24 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure.

[0071] FIG. 25 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure.

[0072] FIG. 26 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] While the present disclosure will be fully described with reference to the accompanying drawings that contain preferred embodiments of the present disclosure, it should be understood before this description that one of ordinary skill in the art may modify the disclosure described herein while still achieving the technical benefits of the present disclosure. Therefore, it should be understood that the above description is intended to be a broad disclosure for one of ordinary skill in the art and is not intended to limit the exemplary embodiments described herein.

[0074] In addition, in the following detailed description, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments can be practiced without these specific details. In other cases, well-known structures and devices are shown in diagrammatic form to simplify the accompanying drawings.

[0075] FIG1 shows a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0076] As shown in FIG. 1 , the pixel driving circuit 100 includes a driving circuit 110 , an input circuit 120 , a compensation circuit 130 and a light emitting control circuit 140 .

[0077] The driving circuit 110 has a control terminal G, a first terminal D, and a second terminal S, and is configured to generate a driving current from the first terminal D to the second terminal S under the control of a signal from the control terminal G. The driving circuit 110 may include a driving transistor DTFT and a capacitor Cst. The gate, drain, and source of the driving transistor DTFT serve as the control terminal G, the first terminal D, and the second terminal S of the driving circuit, respectively. For ease of description, the gate, drain, and source of the driving transistor DTFT are also represented by G, D, and S, respectively, hereinafter. The first electrode of the capacitor Cst is connected to the gate of the driving transistor DTFT, and the second electrode of the capacitor Cst is connected to the second electrode of the driving transistor DTFT.

[0078] The input circuit 120 is connected to the data signal terminal DATA and the control terminal G of the driving circuit. Under the control of the first gate drive signal Gate1, the input circuit 120 can provide the data signal at the data signal terminal DATA to the control terminal G of the driving circuit. The input circuit 120 can include a fourth transistor M4, wherein the gate of the fourth transistor M4 is configured to receive the first gate drive signal Gate1, a first electrode of the fourth transistor M4 is connected to the data signal terminal DATA, and a second electrode of the fourth transistor M4 is connected to the control terminal G of the driving circuit.

[0079] The compensation circuit 130 is connected to the first voltage terminal Vini, the second voltage terminal Vref, and the control terminal G and the second terminal S of the driving circuit. Under the control of the second gate drive signal Gate2, the compensation circuit 130 can provide a reference voltage at the second voltage terminal Vref to the second terminal S of the driving circuit, and under the control of the third gate drive signal Gate3, provide an initial voltage at the first voltage terminal Vini to the control terminal G of the driving circuit. The compensation circuit 110 may include a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is configured to receive the second gate drive signal, a first electrode of the first transistor M1 is connected to the second voltage terminal Vref, and a second electrode of the first transistor M1 is connected to the second terminal S of the driving circuit. The gate of the second transistor M2 is configured to receive the third gate drive signal, a first electrode of the second transistor M2 is connected to the first voltage terminal Vini, and a second electrode of the second transistor M2 is connected to the control terminal G of the driving circuit.

[0080] The light-emission control circuit 140 is connected between the first terminal D of the driver circuit and the power supply signal terminal ELVDD. The light-emission control circuit 140 can connect or disconnect the first terminal D of the driver circuit from the power supply signal terminal ELVDD under the control of a light-emission control signal EM. The light-emission control circuit 140 may include a third transistor M3. The gate of the third transistor M3 is configured to receive the light-emission control signal EM. A first electrode of the third transistor M3 is connected to the power supply signal terminal ELVDD, and a second electrode of the third transistor M3 is connected to the first terminal D of the driver circuit.

[0081] According to an embodiment of the present disclosure, a pixel driving circuit 100 may be included in a sub-pixel to drive the light-emitting element in the sub-pixel to emit light. For example, in FIG1 , the second electrode S of the driving transistor DTFT of the pixel driving circuit 100 may be connected to the first electrode (e.g., anode) of the light-emitting element EL, and the second electrode (e.g., cathode) of the light-emitting element EL may be connected to the reference signal terminal ELVSS. The light-emitting element EL may be an organic light-emitting diode (OLED).

[0082] FIG. 2 shows a signal timing diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0083] During period t1, the first gate drive signal Gate1 is at a low level, the second gate drive signal Gate2 and the third gate drive signal Gate3 are at a high level, the fourth transistor M4 is off, and the first transistor M1 and the second transistor M2 are on, causing the gate G of the drive transistor DTFT to be reset to the first voltage of the first voltage terminal Vini, and the source S of the drive transistor DTFT to be reset to the second voltage of the second voltage terminal Vref. During this period, the high level of the second gate drive signal Gate2 may arrive later than the high level of the third gate drive signal Gate3, thereby causing the gate G and source S of the drive transistor DTFT to be reset successively. In addition, during this period, the emission control signal EM may be at a high level, causing the drain D of the drive transistor DTFT to be reset to the reference voltage of the reference signal terminal ELVDD. The drive transistor DTFT is reset during this period, and therefore, this period is also referred to as a reset period.

[0084] During period t2, the third gate drive signal Gate3 and the light emitting control signal EM remain at a high level, and the second gate drive signal Gate2 becomes a low level, so that the second transistor M2 and the third transistor M3 remain on, while the first transistor M1 is turned off. At this time, the gate-source voltage Vgs of the driving transistor DTFT is greater than the threshold voltage Vth of the driving transistor DTFT. The presence of the capacitor Cst charges the source electrode S of the driving transistor DTFT until Vgs = Vth, thereby achieving threshold voltage compensation. This period is also called a compensation period. During this period, the light emitting control signal EM can remain at a high level,

[0085] During period t3, the third gate drive signal Gate3 becomes low, and the second transistor M2 is turned off. Thereafter, the first gate drive signal Gate1 becomes high, and the light-emission control signal EM becomes low, turning on the third transistor M3 and the fourth transistor M4. As a result, when the data signal at the data signal terminal DATA arrives, the data signal is written into the gate G of the drive transistor DTFT. In FIG2 , the data signal at the data signal terminal DATA is shown as a high level. However, those skilled in the art should understand that this is merely to indicate the arrival of the data signal. The actual level of the data signal is determined by the image data and is not a fixed level. During this period, the data signal is written into the gate G of the drive transistor DTFT, and therefore this period is also referred to as the data write period.

[0086] During period t4, the emission control signal EM is at a high level, the first gate drive signal Gate1 becomes low, and the third transistor M3 is turned on. At this time, the first transistor M1, the second transistor M2, and the fourth transistor M4 are all turned off. The driving transistor DTFT generates a driving current from the drain D to the source S under the action of the voltage of the gate G. The generated driving current drives the light-emitting element EL to emit light. In some embodiments, a black insertion period tb can also be set in period t4. During this black insertion period, the emission control signal EM is at a low level, the third transistor M3 is turned off, and the driving transistor DTFT stops generating current, and the light-emitting element EL stops emitting light. After the black insertion period tb ends, the emission control signal EM returns to a high level, thereby continuing to drive the light-emitting element EL to emit light. In some embodiments, the emission control signal EM can be a multi-pulse signal to perform low grayscale dimming.

[0087] The pixel driving circuit proposed in the embodiment of the present disclosure can achieve internal compensation by setting up a compensation circuit and a light-emitting control circuit. Compared with using a source driving circuit with an external compensation function to perform compensation through complex calculations, it can reduce costs and calculation complexity.

[0088] According to an embodiment of the present disclosure, a shift register unit is also provided that can generate scanning signals required for display driving, such as gate drive signals or light-emitting control signals. This unit can be applied to pixel drive circuits with internal compensation functions or other circuits requiring scanning signals, such as the pixel drive circuits of the aforementioned embodiments. This will be described in detail below with reference to Figures 3 to 21.

[0089] FIG3 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0090] 3 , the shift register unit 200 includes an input circuit 210, a first control circuit 220, a second control circuit 230, and an output circuit 240. The shift register unit 200 may have an input signal terminal IN, an output signal terminal OUT, a power signal terminal VGH, a reference signal terminal VGL, a first pull-up node Q1, a second pull-up node Q2, a first pull-down node QB1, and a second pull-down node QB2.

[0091] The input circuit 210 is connected to the input signal terminal IN, the power signal terminal VGH, a first pull-up node Q1, and a first pull-down node QB1. The input circuit 210 can provide signals from the input signal terminal IN and the power signal terminal VGH to the first pull-up node Q1 and the first pull-down node QB1, respectively. In some embodiments, the input circuit 210 may include a first input sub-circuit and a second input sub-circuit. One of the first input sub-circuit and the second input sub-circuit is configured to provide a signal from one of the power signal terminal VGH and the input signal terminal IN to the first pull-up node Q1, and the other of the first input sub-circuit and the second input sub-circuit is configured to provide a signal from the other of the power signal VGH and the input signal terminal to the first pull-down node QB1.

[0092] The first control circuit 220 connects the first pull-up node Q1 and the first pull-down node QB1. The first control circuit 220 can control the potential of the first pull-down node QB1 based on the potential of the first pull-up node Q1, and can control the potential of the first pull-up node Q1 based on the potential of the first pull-down node QB1. In some embodiments, the first control circuit 220 may include a pull-up control subcircuit and a pull-down control subcircuit, one of which is configured to control the potential of the first pull-down node QB1 based on the potential of the first pull-up node Q1, and the other of which is configured to control the potential of the first pull-up node Q1 based on the potential of the first pull-down node QB1.

[0093] The second control circuit 230 is connected to the first pull-up node Q1, the first pull-down node QB1, the second pull-up node Q2, and the second pull-down node QB2. The second control circuit 230 can transmit the signal at the first pull-up node Q1 to the second pull-up node Q2, and transmit the signal at the first pull-down node QB1 to the second pull-down node QB2. In some embodiments, the second control circuit 230 may include one or more of a first transmission control subcircuit, a second transmission control subcircuit, a third transmission control subcircuit, and a fourth transmission control subcircuit. For example, the second control circuit 230 may include the first transmission control subcircuit and the second transmission control subcircuit, or include the first to third transmission subcircuits, or include the first to fourth transmission subcircuits, which will be described in detail below.

[0094] The output circuit 240 is connected to the second pull-up node Q2, the second pull-down node QB2, the power signal terminal VGH, the reference signal terminal VGL, and the output signal terminal OUT of the shift register unit. The output circuit 240 can provide a signal from either the power signal terminal VGH or the reference signal terminal VGL to the output signal terminal OUT under the control of the second pull-up node Q2 and the second pull-down node QB2. In some embodiments, the output circuit 240 can include a first output sub-circuit and a second output sub-circuit, one of the first output sub-circuit and the second output sub-circuit being configured to provide a potential from either the power signal terminal or the reference signal terminal to the output signal terminal under the control of the second pull-up node, and the other of the first output sub-circuit and the second output sub-circuit being configured to provide a potential from the other of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-down node.

[0095] According to an embodiment of the present disclosure, each of the input circuit 210 , the first control circuit 220 , the second control circuit 230 , and the output circuit 240 may include at least one N-type transistor.

[0096] In this way, the embodiment of the present disclosure implements a new shift register unit structure based on N-type transistors, and the input circuit, the first control circuit, the second control circuit and the output circuit cooperate with each other to generate the scanning signal required for display driving, such as a gate drive signal or a light-emitting control signal.

[0097] In some embodiments, a first voltage stabilizing circuit may be provided between the first pull-up node Q1 and the second control circuit 230. The first voltage stabilizing circuit may be connected to the fourth node of the second control circuit 230 (e.g., the control terminal of the first transmission control subcircuit in the second control circuit 230) to stabilize the potential of the fourth pull-up node. This will be described in detail below.

[0098] Several examples of the shift register unit according to the embodiment of the present disclosure will be described below with reference to FIG. 4 to FIG. 21 .

[0099] FIG4 shows a circuit diagram of a shift register unit 200A according to an embodiment of the present disclosure. The shift register unit 200A includes an input circuit, a first control circuit, a second control circuit, and an output circuit. The description of the input circuit, the first control circuit, the second control circuit, and the output circuit in the above embodiments also applies to the embodiment of FIG4 .

[0100] As shown in FIG4 , the input circuit includes a first input sub-circuit 2101A and a second input sub-circuit 2102A.

[0101] The first input sub-circuit 2101A is connected to the input signal terminal IN, the first pull-up node Q1, and the first clock signal terminal CKA of the shift register unit. The first input sub-circuit 2101A can provide the signal at the input signal terminal IN to the first pull-up node Q1 under the control of the first clock signal terminal CKA. For example, the first input sub-circuit 2101A includes a sixth transistor T6, the gate of which is connected to the first clock signal terminal CKA, the first electrode of which is connected to the input signal terminal IN, and the second electrode of which is connected to the first pull-up node Q1.

[0102] The second input sub-circuit 2102A is connected to the power supply signal terminal VGH, a first pull-down node QB1, and a first clock signal terminal CKA. Under the control of the first clock signal terminal CKA, the second input sub-circuit 2102A can provide a signal at the power supply signal terminal VGH to the first pull-down node QB1. The second input sub-circuit 2102A includes a seventh transistor T7, a gate of which is connected to the first clock signal terminal CKA, a first electrode of which is connected to the power supply signal terminal VGH, and a second electrode of which is connected to the first pull-down node QB1.

[0103] As shown in FIG4 , the first control circuit includes a pull-up control sub-circuit 2201A and a pull-down control sub-circuit 2202A.

[0104] The pull-up control subcircuit 2201A is connected to a first pull-up node Q1, a first pull-down node QB1, and a first clock signal terminal CKACKA. Under control of the first pull-up node Q1, the pull-up control subcircuit 2201A can provide a signal at the first clock signal terminal CKA to the first pull-down node QB1. For example, the pull-up control subcircuit 2201A includes an eighth transistor T8, a gate of which is connected to the first pull-up node Q1, a first electrode of which is connected to the first clock signal terminal CKA, and a second electrode of which is connected to the first pull-down node QB1.

[0105] The pull-down control subcircuit 2202A is connected to the first pull-up node Q1, the first pull-down node QB1, the reference signal terminal VGL, and the second clock signal terminal CKB of the shift register unit. The pull-down control subcircuit 2202A can provide a signal at the reference signal terminal VGL to the first pull-up node Q1 under the control of the second clock signal terminal CKB and the first pull-down node QB1. For example, the pull-down control subcircuit 2202A includes a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 is connected to the second clock signal terminal CKB, the first electrode of the ninth transistor T9 is connected to the second electrode of the tenth transistor T10, the second electrode of the ninth transistor T9 is connected to the first pull-up node Q1 or the fourth pull-up node, the gate of the tenth transistor T10 is connected to the first pull-down node QB1, and the first electrode of the tenth transistor T10 is connected to the reference signal terminal VGL.

[0106] As shown in FIG. 4 , the second control circuit includes a first transmission control sub-circuit 2301A, a second transmission control sub-circuit 2302A, a third transmission control sub-circuit 2303A, and a fourth transmission control sub-circuit 2304A.

[0107] The first transmission control subcircuit 2301A is connected to the first pull-up node Q1, the third pull-up node of the shift register unit, and the second clock signal terminal CKB. Under the control of the first pull-up node Q1, the first transmission control subcircuit 2301A can provide the signal at the second clock signal terminal CKB to the third pull-up node. For example, the first transmission control subcircuit 2301A includes a first transistor T1 and a first capacitor C1. The gate of the first transistor T1 is connected to the first pull-up node Q1, the first electrode of the first transistor T1 is connected to the second clock signal terminal CKB, and the second electrode of the first transistor T1 is connected to the third pull-up node. The first electrode of the first capacitor C1 is connected to the first pull-up node Q1, and the second electrode of the first capacitor C1 is connected to the third pull-up node.

[0108] The second transmission control sub-circuit 2302A is connected to the second pull-up node Q2, the third pull-up node Q3, and the second clock signal terminal CKB. Under the control of the second clock signal terminal CKB, the second transmission control sub-circuit 2302A can provide the signal at the third pull-up node to the second pull-up node Q2. For example, the second transmission control sub-circuit 2302A includes a second transistor T2. The gate of the second transistor T2 is connected to the second clock signal terminal CKB, the first electrode of the second transistor T2 is connected to the third pull-up node, and the second electrode of the second transistor T2 is connected to the second pull-up node Q2.

[0109] The third transmission control sub-circuit 2303A is connected to the first pull-down node QB1, the reference signal terminal VGL, and the third pull-up node Q3. Under the control of the first pull-down node QB1, the third transmission control sub-circuit 2303A can provide the signal at the reference signal terminal VGL to the third pull-up node Q3. For example, the third transmission control sub-circuit 2303A includes a third transistor T3 and a second capacitor C2. The gate of the third transistor T3 is connected to the first pull-down node QB1, the first electrode of the third transistor T3 is connected to the reference signal terminal VGL, the second electrode of the third transistor T3 is connected to the third pull-up node, the first electrode of the second capacitor C2 is connected to the first pull-down node QB1, and the second electrode of the second capacitor C2 is connected to the reference signal terminal VGL.

[0110] The fourth transmission control sub-circuit 2304A is connected to the first pull-down node QB1, the second pull-down node QB2, and the second clock signal terminal CKB. Under the control of the second clock signal terminal CKB, the fourth transmission control sub-circuit 2304A can provide the signal at the first pull-down node QB1 to the second pull-down node QB2. The fourth transmission control sub-circuit 2304A includes a fourth transistor T4. The gate of the fourth transistor T4 is connected to the second clock signal terminal CKB, the first electrode of the fourth transistor T4 is connected to the first pull-down node QB1, and the second electrode of the fourth transistor T4 is connected to the second pull-down node QB2.

[0111] As shown in FIG4 , the output circuit includes a first output sub-circuit 2401A and a second output sub-circuit 2402A.

[0112] The first output sub-circuit 2401A is connected to one of the power supply signal terminal VGH and the reference signal terminal VGL, a second pull-up node Q2, and the output signal terminal OUT. The first output sub-circuit 2401A can provide a signal at one of the power supply signal terminal VGH and the reference signal terminal VGL to the output signal terminal OUT under the control of the second pull-up node Q2. For example, the first output sub-circuit 2401A may include an eleventh transistor T11 and a third capacitor C3, wherein a gate of the eleventh transistor T11 is connected to the second pull-up node Q2, a first electrode of the eleventh transistor T11 is connected to the power supply signal terminal VGH, a second electrode of the eleventh transistor T11 is connected to the output signal terminal OUT, a first electrode of the third capacitor C3 is connected to the second pull-up node Q2, and a second electrode of the third capacitor C3 is connected to the output signal terminal OUT.

[0113] The second output sub-circuit 2402A is connected to the other of the power supply signal terminal VGH and the reference signal terminal VGL, a second pull-down node QB2, and the output signal terminal OUT. Under the control of the second pull-down node QB2, the second output sub-circuit 2402A can provide a signal at the other of the power supply signal terminal VGH and the reference signal terminal VGL to the output signal terminal OUT. For example, the second output sub-circuit 2402A includes a twelfth transistor T12 and a fourth capacitor C4. The gate of the twelfth transistor T12 is connected to the second pull-down node QB2, a first electrode of the twelfth transistor T12 is connected to the reference signal terminal VGL, a second electrode of the twelfth transistor T12 is connected to the output signal terminal OUT, and a first electrode of the fourth capacitor C4 is connected to the second pull-down node QB2, while a second electrode of the fourth capacitor C4 is connected to the reference signal terminal VGL.

[0114] Figure 5 shows a circuit diagram of a shift register unit 200B according to another embodiment of the present disclosure. The shift register unit 200B of Figure 5 is similar to the shift register unit 200A of Figure 4 , except that the connection method of the third capacitor C3 in the first output sub-circuit is different.

[0115] As shown in FIG5 , the first output sub-circuit 2301B includes an eleventh transistor T11 and a third capacitor C3. The gate of the eleventh transistor T11 is connected to the second pull-up node Q2, the first electrode of the eleventh transistor T11 is connected to the power supply signal terminal VGH, and the second electrode of the eleventh transistor T11 is connected to the output signal terminal OUT. Unlike FIG4 , the first electrode of the third capacitor C3 is connected to the second pull-up node Q2, and the second electrode of the third capacitor C3 is connected to the second clock signal terminal CKB.

[0116] The shift register unit according to the embodiment of the present disclosure may further include at least one of a first voltage stabilizing circuit and a second voltage stabilizing circuit, which will be described below with reference to FIG.

[0117] Fig. 6 shows a circuit diagram of a shift register unit 200C according to another embodiment of the present disclosure. The shift register unit 200C of Fig. 6 is similar to the shift register unit 200A of Fig. 4 , except that it further includes a first voltage stabilizing circuit.

[0118] As shown in FIG6 , the shift register unit 200C further includes a first voltage stabilizing circuit 250C. The first voltage stabilizing circuit 250C is connected between the first pull-up node Q1 and the first transmission control sub-circuit 2301C. The first voltage stabilizing circuit 250C and the first transmission control sub-circuit 2301C are connected to a fourth pull-up node Q4. For example, in FIG6 , the first voltage stabilizing circuit 250C and the gate of the first transistor T1 in the first transmission control sub-circuit 2301C are connected to the fourth pull-up node Q4. As shown in FIG6 , the first voltage stabilizing circuit 250C may include a fifth transistor T5, the gate of which is connected to the power supply signal terminal VGH, a first electrode of the fifth transistor T5 being connected to the first pull-up node Q1, and a second electrode of the fifth transistor T5 being connected to the fourth pull-up node Q4. The first voltage stabilizing circuit 250C can stabilize the potential of the fourth pull-up node Q4. For example, when the voltage of the first electrode or the second electrode of the fifth transistor T5 is higher than its gate voltage (i.e., the voltage of the power signal terminal VGH to which it is connected), the fifth transistor T5 is disconnected, thereby preventing the voltage of the fourth node Q4 from being too high, thereby stabilizing the potential of the fourth node Q4.

[0119] A first voltage stabilizing circuit may be provided in the shift register unit of any embodiment of the present disclosure. For example, a first voltage stabilizing circuit 250D may be added to the shift register unit 200B in FIG5 to obtain the circuit structure shown in FIG7 .

[0120] 8 shows a circuit diagram of a shift register unit 200E according to another embodiment of the present disclosure. The shift register unit 200E of FIG8 is similar to the shift register unit 200A of FIG4 , except that it further includes a first voltage stabilizing circuit and a second voltage stabilizing circuit.

[0121] 8 , the shift register unit 200E includes not only the first voltage stabilizing circuit 250E but also the second voltage stabilizing circuit 260E. In some embodiments, the shift register unit 200E may include the second voltage stabilizing circuit 260E instead of the first voltage stabilizing circuit 250E.

[0122] The description of the first voltage stabilizing circuit 250E may refer to any of the above embodiments and will not be repeated here.

[0123] The second voltage stabilizing circuit 260E is connected between the first pull-down node QB1 and the fourth transmission control sub-circuit 2304E. The second voltage stabilizing circuit 260E and the fourth transmission sub-circuit 2304E are connected to a third pull-down node QB3. For example, in FIG8 , the second voltage stabilizing circuit 260E and the first electrode of the fourth transistor T4 in the fourth transmission sub-circuit 2304E are connected to the third pull-down node QB3. The second voltage stabilizing circuit 2304E is configured to stabilize the potential of the third pull-down node QB3. For example, the second voltage stabilizing circuit 2304E may include a fifteenth transistor T15 and a sixteenth transistor T16. The gate of the fifteenth transistor T15 is connected to the first pull-down node QB1, the first electrode of the fifteenth transistor T15 is connected to the second clock signal terminal CKB, and the second electrode of the fifteenth transistor T15 and the first electrode of the fourth transistor T4 in the fourth transmission sub-circuit 2304E are connected to the third pull-down node QB3. The gate of the sixteenth transistor T16 is connected to the fourth pull-up node Q4 (connected to the first pull-up node Q1 in the absence of the first voltage stabilizing circuit 250E), the first electrode of the sixteenth transistor T16 is connected to the reference signal terminal VGL, and the second electrode of the sixteenth transistor T16 is connected to the third pull-down node QB3.

[0124] In the embodiments of the present disclosure, a second voltage-stabilizing circuit is provided to form another pull-down node, namely, a third pull-down node QB3, between the first pull-down node QB1 and the second pull-down node QB2. Both the third pull-down node QB3 and the third pull-up node Q3 are controlled by the potentials of Q4 and QB1. When Q4 is at a high level, the third pull-down node QB3 receives the signal from the reference signal terminal VGL, and when QB1 is at a high level, it receives the signal from the second clock signal terminal CKB. Conversely, when Q4 is at a high level, the third pull-up node Q3 receives the signal from the second clock signal terminal CKB, and when QB1 is at a high level, it receives the signal from the reference signal terminal VGL. Thus, the presence of the third pull-down node QB3 and the third pull-up node Q3 further stabilizes the potentials of the second pull-up node Q2 and the second pull-down node QB2, thereby further stabilizing the output signal of the shift register unit.

[0125] 9 shows a circuit diagram of a shift register unit 200F according to another embodiment of the present disclosure. The shift register unit 200F of FIG9 is similar to the shift register unit 200E of FIG8 , except for the structure of the second voltage stabilizing circuit.

[0126] As shown in FIG9 , the second voltage-stabilizing circuit 260F includes, in addition to the fifteenth transistor T15 and the sixteenth transistor T16, a seventeenth transistor T17. The gate of the seventeenth transistor T17 is connected to the second clock signal terminal CKB, the first electrode of the seventeenth transistor T17 is connected to the second electrode of the sixteenth transistor T16, and the second electrode of the seventeenth transistor T17 is connected to the second electrode of the fifteenth transistor T15. The seventeenth transistor T17 isolates the fifteenth transistor T15 from the sixteenth transistor T16. For example, when CKB is at a low level, transistor T17 is turned off, thereby isolating the third pull-down node QB3 from transistor T16.

[0127] Fig. 10 shows a circuit diagram of a shift register unit 200G according to another embodiment of the present disclosure. The shift register unit 200G of Fig. 10 is similar to the shift register unit 200E of Fig. 8 , except that the structure of the second output sub-circuit is different.

[0128] As shown in FIG10 , the second output sub-circuit 2402G includes, in addition to the twelfth transistor T12 and the fourth capacitor C4 , a thirteenth transistor T13 and a fourteenth transistor T14 .

[0129] A first electrode of the twelfth transistor T12 is connected to the reference signal terminal VGL through the thirteenth transistor T13. A gate of the thirteenth transistor T13 is connected to the second pull-down node QB2. A first electrode of the thirteenth transistor T13 is connected to the reference signal terminal VGL. A second electrode of the thirteenth transistor T13 is connected to the first electrode of the twelfth transistor T12.

[0130] A gate of the fourteenth transistor T14 is connected to the output signal terminal OUT, a first electrode of the fourteenth transistor T14 is connected to the power signal terminal VGH, and a second electrode of the fourteenth transistor T14 is connected to the first electrode of the twelfth transistor T12.

[0131] The thirteenth transistor T13 and the fourteenth transistor T14 can play a role in preventing leakage. For example, when the output signal terminal OUT is at a high level and the second pull-down node QB2 is at a low level, the twelfth transistor T12 is in an off state. If the thirteenth transistor T13 and the fourteenth transistor T14 are not provided, there is a large voltage difference between the first electrode and the second electrode of the twelfth transistor T12, which can easily cause leakage. By providing the thirteenth transistor T13 and the fourteenth transistor T14, when the output signal terminal OUT is at a high level and the second pull-down node QB2 is at a low level, the thirteenth transistor T13 is turned off and the fourteenth transistor T14 is turned on, so that the first electrode and the second electrode of the twelfth transistor T12 are both at a high level, thereby preventing the occurrence of the aforementioned leakage.

[0132] According to an embodiment of the present disclosure, a plurality of shift register units can be cascaded with each other. The so-called cascade refers to the signal generated by the output signal terminal OUT of the previous shift register unit being provided as an input signal to the input signal terminal of the subsequent shift register unit, so that the output signal generated by the subsequent shift register is shifted relative to the previous stage, thereby realizing shift registration. In some embodiments, the cascade connection is realized by connecting the output signal terminal OUT of the previous shift register unit to the input signal terminal of the subsequent shift register unit, that is, the output signal terminal OUT is connected to the pixels of the display area to provide output signals thereto, and is connected to other shift registers to realize cascade. In other embodiments, in order to avoid the influence of cascade with other shift registers on the output signal, a separate control output terminal can be set in the shift register unit, the control output terminal is connected to other shift registers to realize cascade, and the output signal terminal is connected to the pixels of the display area to provide output signals thereto. According to an embodiment of the present disclosure, the third pull-up node can be used as a control output terminal of a shift register unit for cascade connection with other shift register units. For example, as shown in the dotted box in Figure 11, the third pull-up node Q3 can be used as the control output terminal CR of the shift register unit 200H.

[0133] In the embodiments of the shift register unit described above with reference to FIG. 4 to FIG. 11 , the shift register unit can generate the gate drive signal required by the pixel drive circuit of the embodiment of the present disclosure, such as any one of the gate drive signals Gate1 , Gate2 and Gate3 shown in FIG. 2 .

[0134] Figure 12 shows a circuit diagram of a shift register unit 200I according to another embodiment of the present disclosure. The shift register unit 200I of Figure 12 is similar to the shift register unit 200H of Figure 11, except that the first output sub-circuit is connected to the reference signal terminal VGL, and the second output sub-circuit is connected to the power signal terminal VGH.

[0135] As shown in Figure 12, the first output sub-circuit 2401I includes an eleventh transistor T11 and a third capacitor C3, wherein the gate of the eleventh transistor T11 is connected to the second pull-up node Q2, the first electrode of the eleventh transistor T11 is connected to the reference signal terminal VGL, the second electrode of the eleventh transistor T11 is connected to the output signal terminal OUT, the first electrode of the third capacitor C3 is connected to the second pull-up node Q2, and the second electrode of the third capacitor C3 is connected to the reference signal terminal VGL.

[0136] The second output sub-circuit 2402I includes a twelfth transistor T12 and a fourth capacitor C4, wherein the gate of the twelfth transistor T12 is connected to the second pull-down node QB2, the first electrode of the twelfth transistor T12 is connected to the power supply signal terminal VGH, the second electrode of the twelfth transistor T12 is connected to the output signal terminal OUT, the first electrode of the fourth capacitor C4 is connected to the second pull-down node QB2, and the second electrode of the fourth capacitor C4 is connected to the output signal terminal OUT.

[0137] By connecting the first output sub-circuit 2401I to the reference signal terminal VGL and the second output sub-circuit 2402I to the power signal terminal VGH, the shift register unit can generate a low-level output based on a high-level input, thereby generating the light-emitting control signal required by the pixel driving circuit of the embodiment of the present disclosure, such as the light-emitting control signal EM shown in Figure 2.

[0138] Fig. 13 shows a circuit diagram of a shift register unit 200J according to another embodiment of the present disclosure. The shift register unit 200J of Fig. 13 is similar to the shift register unit 200I of Fig. 12, except for the structure of the first output sub-circuit.

[0139] As shown in FIG. 13 , the first output sub-circuit 2401J includes, in addition to the eleventh transistor T11 and the third capacitor C3 , a thirteenth transistor T13 and a fourteenth transistor T14 .

[0140] The second electrode of the eleventh transistor T11 is connected to the output signal terminal OUT through the thirteenth transistor T13, wherein the gate of the thirteenth transistor T13 is connected to the second pull-up node Q2, the first electrode of the thirteenth transistor T13 is connected to the second electrode of the eleventh transistor T11, and the second electrode of the thirteenth transistor T13 is connected to the output signal terminal OUT.

[0141] A gate of the fourteenth transistor T14 is connected to the output signal terminal OUT, a first electrode of the fourteenth transistor T14 is connected to the power signal terminal VGH, and a second electrode of the fourteenth transistor T14 is connected to the second electrode of the eleventh transistor T11.

[0142] The thirteenth transistor T13 and the fourteenth transistor T14 can prevent the eleventh transistor T11 from leaking electricity. The working principle of the thirteenth transistor T13 and the fourteenth transistor T14 is similar to that of the embodiment described above with reference to FIG10 , and will not be repeated here.

[0143] In the embodiments of the shift register unit described above with reference to Figures 4 to 13 , the input circuit is connected in a forward direction, i.e., the first input sub-circuit is connected to the input signal terminal IN, and the second input sub-circuit is connected to the power signal terminal VGH. Thus, when the output circuit is connected in a forward direction (i.e., as shown in Figures 4 to 111 , the first output sub-circuit is connected to the power signal terminal VGH and the second output sub-circuit is connected to the reference signal terminal VGL), the shift register unit can generate the gate drive signal required by the pixel drive circuit; and when the output circuit is connected in a reverse direction (i.e., as shown in Figures 12 and 13 , the first output sub-circuit is connected to the reference signal terminal VGL and the second output sub-circuit is connected to the power signal terminal VGH), the shift register unit can generate the light-emitting drive signal required by the pixel drive circuit.

[0144] The embodiment of the present disclosure further provides a shift register unit implemented when the input circuit is reversely connected, which can generate the light-emitting drive signal required by the pixel drive circuit. This will be described in detail with reference to Figures 14 to 21 below.

[0145] FIG14 shows a circuit diagram of a shift register unit 200K according to another embodiment of the present disclosure. The shift register unit 200K of FIG14 is similar to the shift register unit 200A of FIG4 , except that the input circuit, the first control circuit, and the output circuit are connected in reverse, the fourth transmission control subcircuit is omitted from the second control circuit, and a third voltage stabilization circuit is added.

[0146] As shown in FIG14 , the input circuit also includes a first input sub-circuit 2101K and a second input sub-circuit 2102K. The difference from FIG4 is that the first input sub-circuit 2101K is connected to the power signal terminal VGH, and the second input sub-circuit 2102K is connected to the input signal terminal IN.

[0147] The first input sub-circuit 2101K is connected to the power signal terminal VGH, the first pull-up node Q1, and the first clock signal terminal CKA. The first input sub-circuit 2101K can provide a signal at the power signal terminal VGH to the first pull-up node Q1 under the control of the first clock signal terminal CKA. For example, the first input sub-circuit 2101K includes a sixth transistor T6, wherein the gate of the sixth transistor T6 is connected to the first clock signal terminal CKA, the first electrode of the sixth transistor T6 is connected to the power signal terminal VGH, and the second electrode of the sixth transistor T6 is connected to the first pull-up node Q1.

[0148] The second input sub-circuit 2102K is connected to the input signal terminal IN, the first pull-down node QB1, and the first clock signal terminal CKA. The second input sub-circuit 2102K can provide the signal at the input signal terminal IN to the first pull-down node QB1 under the control of the first clock signal terminal CKA. For example, the second input sub-circuit 2102K includes a seventh transistor T7, the gate of which is connected to the first clock signal terminal CKA, the first electrode of which is connected to the input signal terminal IN, and the second electrode of which is connected to the first pull-down node QB1.

[0149] As shown in FIG14 , the first control circuit also includes a pull-up control subcircuit 2201K and a pull-down control subcircuit 2202K. Unlike FIG4 , the pull-up control subcircuit 2201K controls the first pull-up node Q1 based on the first pull-down node QB1, while the pull-down control subcircuit 2202K controls the first pull-down node based on the first pull-up node Q1.

[0150] The pull-up control subcircuit 2201K is connected to the first pull-up node, the first pull-down node QB1, and the first clock signal terminal CKA. Under the control of the first pull-down node QB1, the pull-up control subcircuit 2201K can provide the signal at the first clock signal terminal CKA to the first pull-up node Q1. For example, the pull-up control subcircuit 2201K includes an eighth transistor T8, the gate of which is connected to the first pull-down node QB1, the first electrode of which is connected to the first clock signal terminal CKA, and the second electrode of which is connected to the first pull-up node Q1.

[0151] The pull-down control subcircuit 2202K is connected to the first pull-up node Q1, the first pull-down node QB1, the reference signal terminal VGL, and the second clock signal terminal CKB of the shift register unit. Under the control of the second clock signal terminal CKB and the first pull-up node Q1, the pull-down control subcircuit 2202K can provide the signal at the reference signal terminal VGL to the first pull-down node QB1. For example, the pull-down control subcircuit 2202K includes a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 is connected to the first pull-up node Q1, the first electrode of the ninth transistor T9 is connected to the reference signal terminal VGL, the second electrode of the ninth transistor T9 is connected to the first electrode of the tenth transistor T10, the gate of the tenth transistor T10 is connected to the second clock signal terminal CKB, and the second electrode of the tenth transistor T10 is connected to the first pull-down node QB1.

[0152] As shown in Figure 14, the second control circuit also includes a first transmission control subcircuit 2301K, a second transmission control subcircuit 2302K, and a third transmission control subcircuit 2303K. The above description of the second control circuit with reference to Figure 4 is also applicable to this embodiment and will not be repeated here.

[0153] As shown in FIG14 , the output circuit also includes a first output sub-circuit 2401K and a second output sub-circuit 2402K. The difference from FIG4 is that the first output sub-circuit is connected to the reference signal terminal VGL, and the second output sub-circuit is connected to the power signal terminal VGH.

[0154] The first output sub-circuit 2401K is connected to a reference signal terminal VGL, a second pull-up node Q2, and an output signal terminal OUT. Under the control of the second pull-up node Q2, the first output sub-circuit 2401K can provide a signal at the reference signal terminal VGL to the output signal terminal OUT. For example, the first output sub-circuit 2401K includes an eleventh transistor T11 and a third capacitor C3. The gate of the eleventh transistor T11 is connected to the second pull-up node Q2, the first electrode of the eleventh transistor T11 is connected to the reference signal terminal VGL, and the second electrode of the eleventh transistor T11 is connected to the output signal terminal OUT. The first electrode of the third capacitor C3 is connected to the second pull-up node Q2, and the second electrode of the third capacitor C3 is connected to the reference signal terminal VGL.

[0155] The second output sub-circuit 2402K is connected to the power supply signal terminal VGH, the second pull-down node QB2, and the output signal terminal OUT. Under the control of the second pull-down node QB2, the second output sub-circuit 2402K can provide the signal at the power supply signal terminal VGH to the output signal terminal OUT. For example, the second output sub-circuit 2402K includes a twelfth transistor T12 and a fourth capacitor C4. The gate of the twelfth transistor T12 is connected to the second pull-down node QB2, the first electrode of the twelfth transistor T12 is connected to the power supply signal terminal VGH, and the second electrode of the twelfth transistor T12 is connected to the output signal terminal OUT. The first electrode of the fourth capacitor C4 is connected to the second pull-down node QB2, and the second electrode of the fourth capacitor C4 is connected to the output signal terminal OUT.

[0156] As shown in FIG14 , unlike FIG4 , the shift register unit 200K further includes a third voltage stabilizing circuit 270K. The third voltage stabilizing circuit 270K is connected to the second pull-up node Q2, the first pull-down node QB1, and the reference signal terminal VGL. Under the control of the first pull-down node QB1, the third voltage stabilizing circuit 270K can provide the signal at the reference signal terminal VGL to the second pull-up node Q2. For example, the third voltage stabilizing circuit 270K includes an eighteenth transistor T18, the gate of which is connected to the first pull-down node QB1, the first electrode of which is connected to the reference signal terminal VGL, and the second electrode of which is connected to the second pull-up node Q2. When the third pull-down node QB3 is at a high level, the eighteenth transistor T18 is turned on, thereby providing the low level of the reference signal terminal VGL to the second pull-up node Q2. This ensures that the second pull-up node Q2 and the second pull-down node QB2 have opposite levels, which is beneficial for stabilizing the output signal.

[0157] 15 shows a circuit diagram of a shift register unit 200L according to another embodiment of the present disclosure. The shift register unit 200L of FIG15 is similar to the shift register unit 200K of FIG14 , except that the shift register unit 200L further includes at least one of a first voltage stabilizing circuit and a fourth voltage stabilizing circuit.

[0158] As shown in FIG. 15 , the shift register unit 200L includes a first voltage stabilizing circuit 250L and a fourth voltage stabilizing circuit 280L.

[0159] The first voltage stabilizing circuit 250L is connected between the first pull-up node Q1 and the fourth pull-up node Q4 to stabilize the potential of the fourth pull-up node Q4. The description of the first voltage stabilizing circuit in the above embodiments is also applicable to this embodiment and will not be repeated here.

[0160] The fourth voltage stabilizing circuit 280L is connected between the first pull-down node QB1 and the second pull-down node QB2 and is configured to stabilize the potential of the second pull-down node QB2. For example, the fourth voltage stabilizing circuit 280L includes a nineteenth transistor T19, the gate of which is connected to the power supply signal terminal VGH, a first electrode of which is connected to the first pull-down node QB1, and a second electrode of which is connected to the second pull-down node QB2. The fourth voltage stabilizing circuit 280L stabilizes the potential of the second pull-down node QB2. Its operating principle is similar to that of the first voltage stabilizing circuit and will not be further described here. By providing both the first and fourth voltage stabilizing circuits, the voltages of both the pull-up node and the pull-down node can be simultaneously stabilized, thereby further stabilizing the output signal.

[0161] 16 shows a circuit diagram of a shift register unit 200M according to another embodiment of the present disclosure. The shift register unit 200M of FIG16 is similar to the shift register unit 200L of FIG15 , except for the structure of the first output sub-circuit.

[0162] As shown in FIG. 16 , the first output sub-circuit 2401M includes, in addition to the eleventh transistor T11 , a thirteenth transistor T13 and a fourteenth transistor T14 .

[0163] A first electrode of the eleventh transistor T11 is connected to the reference signal terminal VGL via the thirteenth transistor T13, wherein a gate of the thirteenth transistor T13 is connected to the second pull-up node Q2, a first electrode of the thirteenth transistor T13 is connected to the reference signal terminal VGL, and a second electrode of the thirteenth transistor T13 is connected to the first electrode of the eleventh transistor T11.

[0164] A gate of the fourteenth transistor T14 is connected to the output signal terminal OUT, a first electrode of the fourteenth transistor T14 is connected to the power signal terminal VGH, and a second electrode of the fourteenth transistor T14 is connected to the first electrode of the eleventh transistor T11.

[0165] The thirteenth transistor T13 and the fourteenth transistor T14 can prevent the eleventh transistor T11 from leaking electricity. The working principle of the thirteenth transistor T13 and the fourteenth transistor T14 is similar to that of the embodiment described above with reference to FIG10 , and will not be repeated here.

[0166] 17 to 19 illustrate circuit diagrams of shift register units according to various embodiments of the present disclosure. The shift register units in these embodiments are similar to the shift register unit 200M in FIG. 16 , except that they further include a fifth voltage stabilization circuit.

[0167] As shown in FIG17 , the shift register unit 200N includes a fifth voltage-stabilizing circuit 290N, which is connected to the second pull-down node QB2 and is configured to stabilize the potential at the second pull-down node QB2. In the example of FIG17 , the fifth voltage-stabilizing circuit 290N includes a fifth capacitor C5, a first electrode of the fifth capacitor C5 being connected to the first clock signal terminal CKA, and a second electrode of the fifth capacitor C5 being connected to the second pull-down node QB2.

[0168] When the first clock signal terminal CKA is at a high level and the input signal terminal IN is at a low level, transistors T7, T3, and FIG19 are turned on, and the second pull-down node QB2 is at a high level. At this time, one end of the fifth capacitor C5 is at a high level and the other end is at a low level. The bootstrap effect of the capacitor increases the potential of the second pull-down node QB2, thereby ensuring that the twelfth transistor T12 continuously outputs the high level of the power supply signal terminal VGH to the output signal terminal OUT.

[0169] According to the embodiments of the present disclosure, the fifth voltage stabilization circuit may be implemented in various other ways.

[0170] For example, in the example of FIG18 , the fifth voltage stabilization circuit 290Q may include, in addition to the fifth capacitor C5, a twentieth transistor T20. The first electrode of the fifth capacitor C5 is connected to the first clock signal terminal CKA, and the second electrode of the fifth capacitor C5 is connected to the second pull-down node QB2. The gate of the twentieth transistor T20 is connected to the third clock signal terminal CKC of the shift register unit, the first electrode of the twentieth transistor T20 is connected to the first clock signal terminal CKA, and the second electrode of the twentieth transistor T20 is connected to the first electrode of the fifth capacitor C5. By providing the twentieth transistor T20, floating of the fifth capacitor C5 is avoided. For example, the effective level of the clock signal at the third clock signal terminal CKC can be partially overlapped with the effective level of the clock signal at the first clock signal terminal CKA, so that the transistor T20 only captures the rising edge of the first clock signal at the first clock signal terminal CKA, thereby raising the potential of the second pull-down node QB2.

[0171] For example, in the example of FIG19 , the fifth voltage stabilization circuit 290P may include, in addition to the fifth capacitor C5 and the twentieth transistor T20, a sixth capacitor C6. A first electrode of the fifth capacitor C5 is connected to the first clock signal terminal CKA, a second electrode of the fifth capacitor C5 is connected to the second pull-down node QB2, a gate of the twentieth transistor T20 is connected to the third clock signal terminal CKC of the shift register unit, a first electrode of the twentieth transistor T20 is connected to the first clock signal terminal CKA, and a second electrode of the twentieth transistor T20 is connected to the first electrode of the fifth capacitor C5. A first electrode of the sixth capacitor C6 is connected to the second electrode of the twentieth transistor T20, and a second electrode of the sixth capacitor C6 is connected to the power supply signal terminal VGH. Providing the sixth capacitor C6 prevents the fifth capacitor C5 from being in a floating state when the twentieth transistor T20 is disconnected.

[0172] 20 shows a circuit diagram of a shift register unit 200Q according to another embodiment of the present disclosure. The shift register unit 200Q of FIG20 is similar to the shift register unit 200K of FIG14, except for the structures of the first control circuit and the output circuit.

[0173] As shown in FIG20 , similar to FIG14 , the first control circuit includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; the output circuit includes an eleventh transistor T11, a twelfth transistor T12, and a fourth capacitor T4; and the second control circuit includes a first transmission control sub-circuit 2301Q, a second transmission control sub-circuit 2302Q, and a third transmission control sub-circuit 2303Q. Unlike FIG14 , in the shift register unit 200Q, the second electrode of the ninth transistor T9 and the first electrode of the tenth transistor T10 are both connected to the second pull-down node QB2; the gate of the tenth transistor T10 is connected to the fourth capacitor C4 in the output circuit; and the second electrode of the tenth transistor T10 is connected to the second clock signal terminal CKB. In addition, unlike FIG14 , in shift register unit 200Q, fourth capacitor C4 is not connected between second pull-down node QB2 and output signal terminal OUT. Instead, the first electrode of fourth capacitor C4 is connected to second pull-down node QB2, the second electrode of ninth transistor T9, and the first electrode of tenth transistor T10, while the second electrode of fourth capacitor C4 is connected to the gate of tenth transistor T10. In this way, the first control circuit and the output circuit share fourth capacitor C4. Fourth capacitor C4 can store charge in the output circuit and control the potential of first pull-up node Q1 in the first control circuit. This greatly simplifies the circuit structure.

[0174] 21 shows a circuit diagram of a shift register unit 200R according to another embodiment of the present disclosure. The shift register unit 200R of FIG21 is similar to the shift register unit 200Q of FIG20 , except that the third transmission control sub-circuit is omitted.

[0175] As shown in FIG21 , the second control circuit of the shift register unit 200R includes a first transmission control sub-circuit 2031R and a second transmission control sub-circuit 2031R. Compared to FIG20 , the third transmission control sub-circuit 2303Q is omitted. The above description of the first and second transmission control sub-circuits also applies to this embodiment. It can be seen that omitting the third transmission control sub-circuit further simplifies the circuit structure.

[0176] FIG22 shows a schematic block diagram of a display driving circuit according to an embodiment of the present disclosure.

[0177] As shown in FIG. 22 , the display driving circuit 300 may include a plurality of shift register units GOA connected in cascade. <1> , GOA <2> , GOA <3> , GOA <4> , .... At least one of these shift register units can be implemented by the shift register unit of any of the above embodiments.

[0178] In FIG22 , the output signal terminal of each stage shift register unit is connected to the input signal terminal of the next stage shift register unit. For example, the first stage shift register unit GOA <1> The output signal terminal OUT is connected to the second stage shift register unit GOA <2> The input signal terminal IN, the second stage shift register unit GOA <2> The output signal terminal OUT is connected to the third-stage shift register unit GOA <3> The output signal terminal of the nth stage shift register unit can be connected to the input signal terminal of the n+ith stage shift register unit, where i can be set as needed, and the embodiment of the present disclosure does not limit this. The first stage shift register unit GOA <1> The input signal terminal IN receives the start signal STU. The waveform of the start signal determines the waveform of the output signal at the output signal terminal OUT. That is to say, by adjusting the pulse width of the start signal, the pulse width of the output signal can be adjusted, thereby realizing pulse width modulation output.

[0179] As shown in FIG22, odd-numbered shift register units (such as GOA <1> , GOA <3> , ...) is connected to receive the first clock signal Cka, and the second clock signal CKB is connected to receive the second clock signal Ckb. In contrast, the even-numbered shift register units (such as GOA <2> , GOA <3> , ...) is connected to receive the second clock signal Ckb, and the second clock signal terminal CKB is connected to receive the first clock signal Cka. However, the embodiments of the present disclosure are not limited thereto, and the clock connection methods of the odd-numbered stages and the even-numbered stages can be interchanged, which will not be repeated here.

[0180] In FIG22 , the output signal terminal OUT of each shift register unit is used to connect to other shift registers in cascade connection, and is also used to provide scanning signals to the sub-pixels in the display area. However, the embodiments of the present disclosure are not limited to this. In the case where a separate control output terminal CR is provided in the shift register unit, the control output terminal CR can be used for cascade connection, while the output signal terminal OUT is used to provide scanning signals to the sub-pixels in the display area.

[0181] The display driver circuit 300 can be used to provide gate drive signals or to provide light-emitting control signals, depending on the structure of the shift register unit included therein. For example, when the shift register unit in the display driver circuit 300 is implemented by the embodiments described above with reference to Figures 4 to 11, the display driver circuit 300 can function as a gate driver circuit to provide gate drive signals. When the shift register unit in the display driver circuit 300 is implemented by the embodiments described above with reference to Figures 12 to 21, the display driver circuit 300 can function as a light-emitting driver circuit to provide light-emitting control signals.

[0182] In any of the embodiments of the shift register unit described above, at least one transistor may be an N-type thin film transistor. In some embodiments, the transistors T1 to T20 described above may all be N-type transistors, such as N-type thin film transistors. Thus, the embodiments of the present disclosure implement a shift register unit based on N-type transistors.

[0183] The embodiments of the present disclosure further provide a display panel, which may include the display driving circuit described in any of the above embodiments and the pixel driving circuit described in any of the above embodiments. This will be described in detail below with reference to FIG23 .

[0184] FIG23 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0185] 23 , the display panel 400 includes a display driving circuit 410 and a plurality of sub-pixels P arranged in an array. The sub-pixels P include a pixel driving circuit, such as the pixel driving circuit 100 described above with reference to FIG1 .

[0186] The number of display driver circuits 410 can be one or more. For example, one of the display driver circuits can be used as a gate driver circuit to provide gate drive signals, and another can be used as a light-emitting driver circuit to provide light-emitting control signals. For the above-mentioned pixel driver circuit 100, three gate driver circuits and one light-emitting driver circuit can be provided to provide gate drive signals Gate1 to Gate3 and light-emitting control signal EM, respectively. At least one display driver circuit 410 can be implemented by the display driver circuit of the embodiment of the present disclosure.

[0187] As shown in FIG23 , a plurality of sub-pixels P are arranged in an N×M array, where N and M are both integers greater than 1. The display driver circuit can provide scan signals to N rows of sub-pixels respectively through a plurality of scan signal lines extending along a first direction (the x direction in FIG1 ). With a single display driver circuit, the display driver circuit 410 is connected to a plurality of sub-pixels P, and can be connected to N rows of sub-pixels respectively through a plurality of scan signal lines extending along a first direction (the x direction in FIG1 ), for example, connecting the first row of sub-pixels P through a first scan signal line to provide a first scan signal G1 to the first row of sub-pixels P, connecting the second row of sub-pixels P through a second scan signal line to provide a second scan signal G2 to the second row of sub-pixels P, and so on. In some embodiments, the gate driver circuit 10 can scan the N rows of sub-pixels P one by one or more rows, or scan the N rows of sub-pixels P every other row or more rows. The embodiments of the present disclosure are not limited to this. When the display driver circuit 410 is implemented as a gate driver circuit, the scan signal is a gate driver signal. When the display driver circuit 410 is implemented as a light-emitting driver circuit, the scan signal is a light-emitting control signal. A plurality of data lines D1 , D2 , . . . , DM extending along a second direction (the y direction in FIG. 1 ) can respectively provide data signals to M columns of sub-pixels P, thereby realizing picture display.

[0188] An embodiment of the present disclosure further provides a method for controlling a shift register unit, which is applicable to the shift register unit of any of the above embodiments.

[0189] In the input phase, the input circuit provides signals from the input signal terminal and the power signal terminal to the first pull-up node and the first pull-down node respectively.

[0190] In the output stage, the first control circuit controls the potential of the first pull-down node based on the potential of the first pull-up node and controls the potential of the first pull-up node based on the potential of the first pull-down node, the second control circuit transfers the signal at the first pull-up node to the second pull-up node and transfers the signal at the first pull-down node to the second pull-down node, so that one of the second pull-up node and the first pull-up node is at a high level and the other of the second pull-up node and the first pull-up node is at a low level, and the output circuit provides a signal from one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node.

[0191] In the reset phase, the first control circuit controls the potential of the first pull-down node based on the potential of the first pull-up node and controls the potential of the first pull-up node based on the potential of the first pull-down node, the second control circuit transfers the signal at the first pull-up node to the second pull-up node and transfers the signal at the first pull-down node to the second pull-down node, so that one of the second pull-up node and the first pull-up node is at a high level and the other of the second pull-up node and the first pull-up node is at a low level, and the output circuit provides the signal of the other of the power supply signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node.

[0192] The control method of the embodiment of the present disclosure will be described below with reference to the signal timings of FIG. 24 to FIG. 26 .

[0193] Figure 24 shows a signal timing diagram for a shift register unit according to an embodiment of the present disclosure. This timing diagram can be applied to the shift register unit according to an embodiment of the present disclosure to generate gate drive signals. For ease of explanation, the shift register unit of Figure 8 will be used as an example. The control method may include an input phase, an output phase, and a reset phase. In Figure 24, the input phase includes period P1, the output phase includes periods P2 to P6, and the reset phase includes period P7. During the input phase, the input circuit writes a high level input signal terminal IN to the first pull-up node Q1 and a high level power supply signal terminal VGH to the first pull-down node QB1. During the output phase, the first control circuit and the second control circuit control the second pull-up node Q2 to a high level and the second pull-down node QB2 to a low level. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB1 cause the output circuit to provide the high level power supply signal terminal VGH to the output signal terminal OUT, thereby outputting a high level. During the reset phase, the first control circuit and the second control circuit control the second pull-up node Q2 to a low level and the second pull-down node QB2 to a high level. The low level of the second pull-up node Q2 and the low level of the second pull-down node QB2 enable the output circuit to provide the low level of the reference signal terminal VGL to the output signal terminal, thereby outputting a low level. This will be described in detail below in conjunction with Figures 24 and 8.

[0194] During period P1, the input signal terminal IN and the first clock signal terminal CKA are at a high level. The sixth transistor T6, the fifth transistor T5, the first transistor T1, the sixteenth transistor T16, the seventh transistor T7, the third transistor T3, and the fifteenth transistor T15 are turned on, thereby providing the high level of the input signal terminal IN to the first pull-up node Q1 and the fourth pull-up node Q4, and providing the high level of the power supply signal terminal VGH to the first pull-down node QB1. Because the second clock signal terminal CKB is at a low level, the turned-on first transistor T1 and the third transistor write a low level to the third pull-up node Q3, and the turned-on fifteenth transistor T15 and the sixteenth transistor T16 write a low level to the second pull-down node QB3. The second transistor T2 and the fourth transistor T4 are turned off, causing the second pull-up node Q2 and the second pull-down node QB2 to maintain their original potentials. In FIG24 , the second pull-up node Q2 remains at a low level, and the second pull-down node QB2 remains at a high level. The low level of the second pull-up node Q2 turns off the eleventh transistor T11, and the high level of the second pull-down node QB2 turns on the twelfth transistor T12, thereby providing the low level of the reference signal terminal VGL to the output signal terminal OUT, and the output signal terminal OUT maintains a low level.

[0195] During period P2, the first clock signal terminal CKA reaches a low level, and the sixth and seventh transistors T6 and T7 are turned off. At this time, the high level of the first pull-up node Q1 turns on the eighth transistor T8, thereby providing the low level of the first clock signal terminal CKA to the first pull-down node QB1. The low level of the first pull-down node QB1 turns off the third and fifteen transistors T3 and T15, while the high level of the first pull-up node Q1 keeps the first transistor T1 and the sixteenth transistor T16 turned on. The second clock signal terminal CKB remains at a low level. The turned-on first transistor T1 and sixteenth transistor T16 keep the third pull-up node Q3 and the third pull-down node QB3 at a low level. The turned-off second transistor T2 and fourth transistor T4 keep the second pull-up node Q2 and the second pull-down node QB2 at their original levels, and the output signal terminal OUT continues to output a low level.

[0196] During period P3, the first clock signal terminal CKA remains low, the second clock signal terminal CKB becomes high, the first pull-up nodes Q1 and Q4 remain high, and the first pull-down node QB1 remains low. The first transistor T1 and the sixteenth transistor T16 remain on, thereby supplying the high level of the second clock signal terminal CKB to the third pull-up node Q3 and the low level of the reference signal terminal VGL to the third pull-down node QB3. The high level of the second clock signal terminal CKB turns on the second transistor T2 and the fourth transistor T4, thereby supplying the high level of the third pull-up node to the second pull-up node Q2 and the low level of the third pull-down node QB3 to the second pull-down node QB2. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB2 turn on the eleventh transistor T11 and turn off the twelfth transistor T12, thereby supplying the high level of the power supply signal terminal VGH to the output signal terminal OUT. In other words, the output signal terminal OUT outputs a high level.

[0197] In period P4, the second clock signal terminal CKB is at a low level, the second transistor T2 and the fourth transistor T4 always remain in a disconnected state, so no matter whether the first clock signal terminal CKA is at a high level or a low level, the second pull-up node Q2 still remains at a high level, and the second pull-down node QB2 still remains at a low level, so that the output signal terminal OUT continues to output a high level.

[0198] During period P5, the first clock signal terminal CKA remains at a low level, while the second clock signal terminal CKB is first high and then low. The fourth pull-up node Q4 remains at a high level, causing the first transistor T1 and the sixteenth transistor to remain on. Since the first transistor T1 remains on, the third pull-up node Q3 follows the potential of the second clock signal terminal CKB. That is, the third pull-up node Q3 is high when the second clock signal terminal CKB is high, and is low when the second clock signal terminal CKB is low. This ensures that the second transistor T2 maintains the second pull-up node Q2 at a high level regardless of whether the second clock signal terminal CKB is high or low. Since the sixteenth transistor T16 remains on, the third pull-down node QB3 maintains a low potential. Similarly, the fourth transistor T4 maintains the second pull-down node QB2 at a low level regardless of whether the second clock signal terminal CKB is high or low.

[0199] During period P6, the input signal terminal IN becomes low, and the first clock signal terminal CKA is high, turning on the sixth transistor T6 and the seventh transistor T7. This causes the low level of the input signal terminal IN to be supplied to the first pull-up node Q1 (and subsequently written to the fourth pull-up node Q4), and the high level of the power supply signal terminal VGH to be supplied to the first pull-down node QB1. The low level of the first pull-up node Q1 turns off the first transistor T1 and the sixteenth transistor T16, while the high level of the first pull-down node QB1 turns on the third transistor T3 and the fifteenth transistor T15. Since the second clock signal terminal CKB remains low throughout period P6, even if the first clock signal CKA subsequently becomes low, the second transistor T2 and the fourth transistor T4 remain off. This causes the second pull-up node Q2 to remain high, the second pull-down node QB2 to remain low, and the output signal terminal OUT still outputs a high level.

[0200] During period P7, the second clock signal terminal CKB becomes high, while the first clock signal terminal CKA remains low. Since the first pull-down node QB1 is high, the turned-on third transistor T3 causes the third pull-up node Q3 to remain low, and the turned-on fifteenth transistor T15 causes the third pull-down node QB3 to become high. The high level of the second clock signal terminal CKB turns on both the second transistor T2 and the fourth transistor T4, thereby transmitting the low level of the third pull-up node Q3 to the second pull-up node Q2 and the high level of the third pull-down node QB3 to the second pull-down node QB2. The low level of the second pull-up node Q2 turns off the eleventh transistor T11, while the high level of the second pull-down node QB2 turns on the twelfth transistor T12, thereby providing the low level of the reference signal terminal VGL to the output signal terminal OUT, which then outputs a low level. At this point, one output is completed. During this process, the high levels of the second clock signal terminal CKB and the first pull-down node QB1 turn on the ninth transistor T9 and the tenth transistor T10, thereby providing the low level of the reference signal terminal VGL to the fourth pull-up node Q4, which is conducive to stabilizing the fourth pull-up node Q4 at a low level.

[0201] Thereafter, regardless of whether the first clock signal terminal CKA is at a high level or a low level, the first pull-up node Q1 and the fourth pull-up node Q4 remain at a low level, and the first pull-down node QB1 remains at a high level. This causes the first transistor T1 and the sixteenth transistor T16 to remain in an off state, while the third transistor T3 and the fifteenth transistor T15 remain in an on state. Consequently, the third pull-up node Q3 remains at a low level, and the third pull-down node QB3 follows the potential of the second clock signal terminal CKB. Thus, when the second clock signal terminal CKB is at a high level, the second transistor T2 and the fourth transistor T4 are both turned on, causing the low level of the third pull-up node Q3 to be provided to the second pull-up node Q2, and the high level of the third pull-down node QB3 to be provided to the second pull-down node QB2. When the second clock signal terminal CKB is at a low level, the second transistor T2 and the fourth transistor T4 are both turned off, causing the second pull-up node Q2 to remain at a low level, while the second pull-down node QB2 remains at a high level. That is to say, no matter the second clock signal terminal CKB is at a high level or a low level, the second pull-up node Q2 is kept at a low level, and the second pull-down node QB2 is kept at a high level, so that the output signal terminal OUT is kept at a low level until the next high level of the input signal terminal IN arrives.

[0202] Figure 25 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure. This timing diagram can be applied to the shift register unit of the embodiment of the present disclosure, so that it generates a light-emitting control signal. For the sake of convenience, the shift register unit of Figure 12 will be used as an example for explanation below. The shift register unit of Figure 12 uses a third pull-up node Q3 as a control output terminal CR for cascading with other shift register units. The shift register unit of Figure 12 can receive signals from the control output terminals of other shift register units as input signals. Therefore, in the example of Figure 25, the signal waveform of the input signal terminal IN is the signal waveform at the third pull-up node of the other shift register units (including two short pulses with the same period as the clock signal), which is different from the signal waveform of the input signal terminal IN of Figure 24.

[0203] In Figure 25, similar to Figure 24, the input phase includes period P1, the output phase includes periods P2 to P6, and the reset phase includes period P7. During the input phase, the input circuit writes a high level of the input signal terminal IN to the first pull-up node Q1 and a high level of the power supply signal terminal VGH to the first pull-down node QB1. During the output phase, the first and second control circuits control the second pull-up node Q2 to a high level and the second pull-down node QB2 to a low level. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB1 cause the output circuit to provide the low level of the electrical reference signal terminal VGL to the output signal terminal OUT, thereby outputting a low level. During the reset phase, the first and second control circuits control the second pull-up node Q2 to a low level and the second pull-down node QB2 to a high level. The low level of the second pull-up node Q2 and the high level of the second pull-down node QB2 cause the output circuit to provide the low level of the power supply signal terminal VGH to the output signal terminal OUT, thereby outputting a high level. This will be explained in detail below in conjunction with Figures 25 and 12.

[0204] During period P1, the input signal terminal IN and the first clock signal terminal CKA are at a high level. The sixth transistor T6, the fifth transistor T5, the first transistor T1, the sixteenth transistor T16, the seventh transistor T7, the third transistor T3, and the fifteenth transistor T15 are turned on, thereby providing the high level of the input signal terminal IN to the first pull-up node Q1 and the fourth pull-up node Q4, and providing the high level of the power supply signal terminal VGH to the first pull-down node QB1. Because the second clock signal terminal CKB is at a low level, the turned-on first transistor T1 and the third transistor write a low level to the third pull-up node Q3, and the turned-on fifteenth transistor T15 and the sixteenth transistor T16 write a low level to the second pull-down node QB3. The second transistor T2 and the fourth transistor T4 are turned off, causing the second pull-up node Q2 and the second pull-down node QB2 to maintain their original potentials. In FIG25 , the second pull-up node Q2 remains at a low level, and the second pull-down node QB2 remains at a high level. The low level of the second pull-up node Q2 turns off the eleventh transistor T11, and the high level of the second pull-down node QB2 turns on the twelfth transistor T12, thereby providing the high level of the power signal terminal VGH to the output signal terminal OUT, and the output signal terminal OUT maintains a high level.

[0205] During period P2, the input signal terminal IN and the first clock signal terminal CKA go low, and the sixth transistor T6 and the seventh transistor T7 are turned off. At this time, the high level of the first pull-up node Q1 turns on the eighth transistor T8, thereby providing the low level of the first clock signal terminal CKA to the first pull-down node QB1. The low level of the first pull-down node QB1 turns off the third transistor T3 and the fifteenth transistor T15, while the high level of the first pull-up node Q1 keeps the first transistor T1 and the sixteenth transistor T16 turned on. The second clock signal terminal CKB remains low, and the turned-on first transistor T1 and the sixteenth transistor T16 keep the third pull-up node Q3 and the third pull-down node QB3 at a low level. The turned-off second transistor T2 and the fourth transistor T4 keep the second pull-up node Q2 and the second pull-down node QB2 at their original levels, and the output signal terminal OUT continues to output a high level.

[0206] During period P3, the first clock signal terminal CKA remains low, the second clock signal terminal CKB becomes high, the first pull-up nodes Q1 and Q4 remain high, and the first pull-down node QB1 remains low. The first transistor T1 and the sixteenth transistor T16 remain on, thereby supplying the high level of the second clock signal terminal CKB to the third pull-up node Q3 and the low level of the reference signal terminal VGL to the third pull-down node QB3. The high level of the second clock signal terminal CKB turns on the second transistor T2 and the fourth transistor T4, thereby supplying the high level of the third pull-up node Q3 to the second pull-up node Q2 and the low level of the third pull-down node QB3 to the second pull-down node QB2. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB2 turn on the eleventh transistor T11 and turn off the twelfth transistor T12, thereby supplying the low level of the reference signal terminal VGL to the output signal terminal OUT. In other words, the output signal terminal OUT outputs a low level.

[0207] In period P4, the second clock signal terminal CKB is at a low level, and the second transistor T2 and the fourth transistor T4 always remain in a disconnected state. Therefore, no matter whether the first clock signal terminal CKA and the input signal terminal IN are at a high level or a low level, the second pull-up node Q2 still remains at a high level, and the second pull-down node QB2 still remains at a low level, so that the output signal terminal OUT continues to output a low level.

[0208] During period P5, the first clock signal terminal CKA remains at a low level, while the second clock signal terminal CKB is first high and then low. The fourth pull-up node Q4 remains at a high level, causing the first transistor T1 and the sixteenth transistor to remain on. Since the first transistor T1 remains on, the third pull-up node Q3 follows the potential of the second clock signal terminal CKB. That is, the third pull-up node Q3 is high when the second clock signal terminal CKB is high, and is low when the second clock signal terminal CKB is low. This ensures that the second transistor T2 maintains the second pull-up node Q2 at a high level regardless of whether the second clock signal terminal CKB is high or low. Since the sixteenth transistor T16 remains on, the third pull-down node QB3 maintains a low potential. Similarly, the fourth transistor T4 maintains the second pull-down node QB2 at a low level regardless of whether the second clock signal terminal CKB is high or low.

[0209] During period P6, the input signal terminal IN is at a low level, and the first clock signal terminal CKA is at a high level, turning on the sixth transistor T6 and the seventh transistor T7. This causes the low level of the input signal terminal IN to be supplied to the first pull-up node Q1 (and subsequently written to the fourth pull-up node Q4), and the high level of the power supply signal terminal VGH to be supplied to the first pull-down node QB1. The low level of the first pull-up node Q1 turns off the first transistor T1 and the sixteenth transistor T16, while the high level of the first pull-down node QB1 turns on the third transistor T3 and the fifteenth transistor T15. Since the second clock signal terminal CKB remains low throughout period P6, even if the first clock signal CKA subsequently changes to a low level, the second transistor T2 and the fourth transistor T4 remain off. This causes the second pull-up node Q2 to remain high, the second pull-down node QB2 to remain low, and the output signal terminal OUT still outputs a low level.

[0210] During period P7, the second clock signal terminal CKB becomes high, while the first clock signal terminal CKA remains low. Since the first pull-down node QB1 is high, the turned-on third transistor T3 causes the third pull-up node Q3 to remain low, and the turned-on fifteenth transistor T15 causes the third pull-down node QB3 to become high. The high level of the second clock signal terminal CKB turns on both the second transistor T2 and the fourth transistor T4, thereby transmitting the low level of the third pull-up node Q3 to the second pull-up node Q2 and the high level of the third pull-down node QB3 to the second pull-down node QB2. The low level of the second pull-up node Q2 turns off the eleventh transistor T11, while the high level of the second pull-down node QB2 turns on the twelfth transistor T12, thereby providing the high level of the power supply signal terminal VGH to the output signal terminal OUT, which then outputs a high level. At this point, one output is completed. During this process, the high levels of the second clock signal terminal CKB and the first pull-down node QB1 turn on the ninth transistor T9 and the tenth transistor T10, thereby providing the low level of the reference signal terminal VGL to the fourth pull-up node Q4, which is conducive to stabilizing the fourth pull-up node Q4 at a low level.

[0211] Thereafter, regardless of whether the first clock signal terminal CKA is at a high level or a low level, the first pull-up node Q1 and the fourth pull-up node Q4 remain at a low level, and the first pull-down node QB1 remains at a high level. This causes the first transistor T1 and the sixteenth transistor T16 to remain in an off state, while the third transistor T3 and the fifteenth transistor T15 remain in an on state. Consequently, the third pull-up node Q3 remains at a low level, and the third pull-down node QB3 follows the potential of the second clock signal terminal CKB. Thus, when the second clock signal terminal CKB is at a high level, the second transistor T2 and the fourth transistor T4 are both turned on, causing the low level of the third pull-up node Q3 to be provided to the second pull-up node Q2, and the high level of the third pull-down node QB3 to be provided to the second pull-down node QB2. When the second clock signal terminal CKB is at a low level, the second transistor T2 and the fourth transistor T4 are both turned off, causing the second pull-up node Q2 to remain at a low level, while the second pull-down node QB2 remains at a high level. That is to say, no matter the second clock signal terminal CKB is at a high level or a low level, the second pull-up node Q2 is kept at a low level, and the second pull-down node QB2 is kept at a high level, so that the output signal terminal OUT is kept at a high level until the next high level of the input signal terminal IN arrives.

[0212] Figure 26 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure. This timing diagram can be applied to the shift register unit of the embodiment of the present disclosure, so that it generates a light-emitting control signal. For the sake of convenience, the shift register unit of Figure 15 will be used as an example for explanation. The shift register unit of Figure 15 is used to generate a low-level effective light-emitting control signal, which can receive the light-emitting control signal output from other shift register units as an input signal. Therefore, in the example of Figure 26, the signal waveform of the input signal terminal IN is the signal waveform at the output signal terminal of the other shift register unit (low-level effective light-emitting control signal).

[0213] In Figure 26, the method also includes an input phase, an output phase, and a reset phase. The input phase includes period P1, the output phase includes periods P2 to P5, and the reset phase includes periods P6 and P7. During the input phase, the input circuit writes a high level of the power supply signal terminal VGH to the first pull-up node Q1 and a low level of the input signal terminal IN to the first pull-down node QB1. During the output phase, the first control circuit and the second control circuit control the second pull-up node Q2 to a high level and the second pull-down node QB2 to a low level. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB1 cause the output circuit to provide the low level of the electrical reference signal terminal VGL to the output signal terminal OUT, thereby outputting a low level. During the reset phase, the first control circuit and the second control circuit control the second pull-up node Q2 to a low level and the second pull-down node QB2 to a high level. The low level of the second pull-up node Q2 and the high level of the second pull-down node QB2 cause the output circuit to provide the low level of the power supply signal terminal VGH to the output signal terminal OUT, thereby outputting a high level. This will be described in detail below with reference to FIG. 26 and FIG. 15 .

[0214] During period P1, the input signal terminal IN is at a low level, the first clock signal terminal CKA is at a high level, the sixth transistor T6, the fifth transistor T5, the first transistor T1, the seventh transistor T7, and the nineteenth transistor T19 are turned on, and the third transistor T3 is turned off. This causes the high level of the power supply signal terminal VGH to be supplied to the first pull-up node Q1 and the fourth pull-up node Q4, and the low level of the input signal terminal IN to be supplied to the first pull-down node QB1 and the second pull-down node QB2. Because the second clock signal terminal CKB is at a low level, the turned-on first transistor T1 writes the low level of the second clock signal terminal CKB to the third pull-up node Q3. The second transistor T2 is turned off, causing the second pull-up node Q2 to maintain its original potential. In FIG26 , the second pull-up node Q2 remains at a low level. The low level of the second pull-up node Q2 turns off the eleventh transistor T11, and the low level of the second pull-down node QB2 turns off the twelfth transistor T12, causing the output signal terminal OUT to maintain its original high level.

[0215] During period P2, the first clock signal terminal CKA goes low, and the sixth and seventh transistors T6 and T7 are turned off. The first and fourth pull-up nodes Q1 and Q4 remain high, causing the first transistor T1 to remain on. At this time, because the second clock signal terminal CKB remains low, the third pull-up node Q3 remains low. The second transistor T2, in its off state, causes the second pull-up node Q2 to continue to remain low. The first and second pull-down nodes QB2 and QB2 remain low. The low levels of the second pull-up and QB2 nodes cause the output signal terminal OUT to remain high. During this process, the low level of the first pull-down node QB1 turns off the eighth transistor T8, causing the first pull-up node Q1 to remain high. The high level of the first pull-up node Q1 and the low level of the second clock signal terminal CKB turn on the ninth transistor T9 and turn off the tenth transistor T10, causing the first pull-down node QB1 to remain low. In addition, the low level of the first pull-down node QB1 turns off the eighteenth transistor T18 , thereby maintaining the second pull-up node Q2 at a low level.

[0216] During period P3, the first clock signal terminal CKA remains at a low level, the second clock signal terminal CKB becomes high, the first pull-up nodes Q1 and Q4 remain high, and the first pull-down node QB1 and the second pull-down node QB2 remain low. The first transistor T1 remains on, thereby providing the high level of the second clock signal terminal CKB to the third pull-up node Q3. The high level of the second clock signal terminal CKB turns on the second transistor T2, thereby providing the high level of the third pull-up node Q3 to the second pull-up node Q2. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB2 turn on the eleventh transistor T11 and turn off the twelfth transistor T12, thereby providing the low level of the reference signal terminal VGL to the output signal terminal OUT. In other words, the output signal terminal OUT outputs a low level.

[0217] During period P4, the second clock signal terminal CKB is at a low level, the second transistor T2 remains in the off state, and the second pull-up node Q2 remains at a high level. Since the input signal terminal IN remains at a low level, the second pull-down node QB2 remains at a low level regardless of whether the seventh transistor T7 is in the on or off state. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB2 cause the output signal terminal OUT to continue to output a low level.

[0218] During period P5, the input signal terminal IN goes high, the first clock signal terminal CKA remains low, and the second clock signal terminal CKB is first high and then low. The first pull-up node Q1 and the fourth pull-up node Q4 remain high, causing the first transistor T1 to remain on. Because the first transistor T1 remains on, the third pull-up node Q3 follows the potential of the second clock signal terminal CKB. That is, the third pull-up node Q3 is high when the second clock signal terminal CKB is high, and is low when the second clock signal terminal CKB is low. This ensures that the second transistor T2 maintains the second pull-up node Q2 at a high level regardless of whether the second clock signal terminal CKB is high or low. Because the first clock signal terminal CKA remains low, the seventh transistor T7 is off, and the first pull-down node QB1 and the second pull-down node QB2 remain low. The high level of the second pull-up node Q2 and the low level of the second pull-down node QB2 cause the output signal terminal OUT to continue outputting a low level.

[0219] During the period P1 to P5, when the second clock signal terminal CKB and the first pull-up node Q1 are both at a high level, the ninth transistor T9 and the tenth transistor T10 are turned on, thereby providing the low level of the reference signal terminal VGL to the first pull-down node QB1, which is conducive to the first pull-down node QB1 being stable at a low level.

[0220] During period P6, the first clock signal terminal CKA becomes high, turning on the sixth transistor T6 and the seventh transistor T7. This provides the high level of the power supply signal terminal VGH to the first pull-up node Q1 (which is then written to the fourth pull-up node Q4), and the high level of the input signal terminal IN to the first pull-down node QB1 (which is then written to the second pull-down node QB2). The low level of the first pull-up node Q1 turns off the first transistor T1, and the high level of the first pull-down node QB1 turns on the third transistor T3, thereby writing the low level of the reference signal terminal VGL to the third pull-up node Q3. Since the second clock signal terminal CKB remains low, the second transistor T2 remains off, which causes the second pull-up node Q2 to remain high. The low level of the second pull-up node Q2 turns off the eleventh transistor T11, and the high level of the second pull-down node QB2 turns on the twelfth transistor T12, thereby providing the high level of the power supply signal terminal VGH to the output signal terminal OUT, which then outputs a high level. At this point, one output is completed.

[0221] During period P7, the first clock signal terminal CKA becomes low, the sixth transistor T6 and the seventh transistor T7 are turned off, and the first pull-down node QB1 and the second pull-down node QB2 remain high. The high level of the first pull-down node QB1 turns on the eighth transistor, thereby providing the low level of the first clock signal terminal CKA to the first pull-up node Q1. The high level of the first pull-down node QB1 also turns on the third transistor T3, thereby maintaining the third pull-up node Q3 at a low level. The low level of the second clock signal terminal CKB keeps the second transistor T2 turned off, and the second pull-up node Q2 remains low. The low level of the second pull-up node Q2 and the high level of the second pull-down node QB2 cause the output signal terminal OUT to continue to output a high level.

[0222] Thereafter, when the first clock signal terminal CKA is at a low level and the second clock signal terminal CKB is at a high level, the first pull-down node QB1 and the second pull-down node QB2 are at a high level, and the eighth transistor T8 is turned on, causing the first pull-up node Q1 to maintain a low level. The first transistor T1 is turned off and the third transistor T3 is turned on, causing the third pull-up node Q3 to maintain a low level. The second transistor T2 is turned on, causing the second pull-up node Q2 to be at a low level. The low levels of the second pull-up node Q2 and the second pull-down node Q2 cause the output signal terminal OUT to continue to output a low level.

[0223] Thereafter, when the first clock signal terminal CKA and the second clock signal terminal CKB are all at a low level, the sixth transistor T6, the seventh transistor and the second transistor T2 are all disconnected, the second pull-up node Q2 continues to maintain a low level, the second pull-down node QB2 continues to maintain a low level, and the output signal terminal OUT continues to output a low level.

[0224] Thereafter, when the first clock signal terminal CKA is at a high level and the second clock signal terminal CKB is at a low level, the second transistor T2 is turned off, so that the second pull-up node Q2 maintains a low level; the seventh transistor T7 is turned on, so that the first pull-down node QB1 and the second pull-down node QB2 maintain a high level, and the output signal terminal OUT continues to output a low level.

[0225] That is, after period P7, the second pull-up node Q2 remains at a low level, and the second pull-down node QB2 remains at a high level, so that the output signal terminal OUT remains at a high level until the next low level of the input signal terminal IN arrives.

[0226] The above-mentioned period P1 can correspond to the first phase. As shown in Figure 26, in the first phase, the input circuit writes the low level of the input signal terminal IN to the first pull-down node QB1 and writes the high level of the power signal terminal VGH to the first pull-up node Q1. Therefore, this phase is also called the input phase.

[0227] The aforementioned period P2 may correspond to the second phase. As shown in FIG26 , during the second phase, the first control circuit, under the control of the first clock signal terminal CKA and the second clock signal terminal CKB, maintains the first pull-up node Q1 at a high level and the first pull-down node QB1 at a low level. Therefore, this phase is also referred to as the control phase.

[0228] The above-mentioned periods P3 to P7 may correspond to the third phase. The third phase may include an output phase and a reset phase, wherein periods P3 to P5 may correspond to the output phase, and periods P6 to P7 may correspond to the reset phase. As shown in Figure 26, during the output phase, the second control circuit transmits the high level of the first pull-up node Q1 to the second pull-up node Q2, and transmits the low level of the first pull-down node QB1 to the second pull-down node QB2. The output circuit provides the low level of the reference signal terminal to the output signal terminal, thereby outputting a low level. During the reset phase, the first control circuit and the second control circuit, under the control of the first clock signal terminal CKA and the second clock signal terminal CKB, cause the second pull-up node Q2 to be low and the second pull-down node QB2 to be high. The output circuit provides the high level of the power supply signal terminal to the output signal terminal, thereby outputting a high level.

[0229] Those skilled in the art will appreciate that the embodiments described above are exemplary and that they may be improved upon. The structures described in the various embodiments may be freely combined without causing any conflict in structure or principle.

[0230] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art will clearly understand that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and that the present disclosure is not limited to the exemplary embodiments described in the specification.

Claims

1. A shift register unit, comprising: An input circuit connected to an input signal terminal, a power signal terminal, a first pull-up node, and a first pull-down node of the shift register unit, and configured to provide signals of the input signal terminal and the power signal terminal to the first pull-up node and the first pull-down node; a first control circuit connected to the first pull-up node and the first pull-down node, and configured to control the potential of the first pull-down node based on the potential of the first pull-up node and to control the potential of the first pull-up node based on the potential of the first pull-down node; a second control circuit connected to the first pull-up node, the first pull-down node, the second pull-up node and the second pull-down node of the shift register unit, and configured to control the potential of the second pull-up node based on a signal of the first pull-up node, and control the potential of the second pull-down node by using the signal of the first pull-down node; as well as An output circuit is connected to the second pull-up node, the second pull-down node, the power signal terminal, the reference signal terminal and the output signal terminal of the shift register unit, and is used to provide a signal from one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node.

2. The shift register unit according to claim 1, wherein: The second control circuit comprises: a first transmission control subcircuit, connected to the first pull-up node, the third pull-up node of the shift register unit and the second clock signal terminal, for providing a signal of the second clock signal terminal to the third pull-up node under the control of the first pull-up node; The second transmission control subcircuit is connected to the second pull-up node, the third pull-up node and the second clock signal terminal, and is used to provide the signal at the third pull-up node to the second pull-up node under the control of the second clock signal terminal.

3. The shift register unit according to claim 2, wherein: The first transmission control subcircuit includes a first transistor and a first capacitor, the gate of the first transistor is connected to the first pull-up node, the first electrode of the first transistor is connected to the second clock signal terminal, the second electrode of the first transistor is connected to the third pull-up node, the first electrode of the first capacitor is connected to the first pull-up node, and the second electrode of the first capacitor is connected to the third pull-up node; The second transmission control subcircuit includes a second transistor, a gate of the second transistor is connected to the second clock signal terminal, a first electrode of the second transistor is connected to the third pull-up node, and a second electrode of the second transistor is connected to the second pull-up node.

4. The shift register unit according to claim 2 or 3, wherein: The second control circuit also includes: a third transmission control subcircuit connected to the first pull-down node, the reference signal terminal and the third pull-up node, and configured to provide the signal at the reference signal terminal to the third pull-up node under the control of the first pull-down node.

5. The shift register unit according to claim 4, wherein: The third transmission control subcircuit includes a third transistor and a second capacitor, the gate of the third transistor is connected to the first pull-down node, the first electrode of the third transistor is connected to the reference signal terminal, the second electrode of the third transistor is connected to the third pull-up node, the first electrode of the second capacitor is connected to the first pull-down node, and the second electrode of the second capacitor is connected to the reference signal terminal.

6. The shift register unit according to claim 4 or 5, wherein: The second control circuit also includes: a fourth transmission control subcircuit, connected to the first pull-down node, the second pull-down node and the second clock signal terminal, for providing the signal at the first pull-down node to the second pull-down node under the control of the second clock signal terminal.

7. The shift register unit according to claim 6, wherein: The fourth transmission control subcircuit includes a fourth transistor, a gate of the fourth transistor is connected to the second clock signal terminal, a first electrode of the fourth transistor is connected to the first pull-down node, and a second electrode of the fourth transistor is connected to the second pull-down node.

8. The shift register unit according to any one of claims 1 to 7, further comprising: A first voltage stabilizing circuit is connected between the first pull-up node and the first transmission control subcircuit, wherein the first voltage stabilizing circuit and the first transmission control subcircuit are connected to a fourth pull-up node, and the first voltage stabilizing circuit is used to stabilize the potential of the fourth pull-up node.

9. The shift register unit according to claim 8, wherein: The first voltage stabilizing circuit includes: a fifth transistor, a gate of the fifth transistor is connected to the power signal terminal, a first electrode of the fifth transistor is connected to the first pull-up node, and a second electrode of the fifth transistor is connected to the fourth pull-up node.

10. The shift register unit according to any one of claims 1 to 9, wherein: The input circuit comprises: A first input subcircuit, connected to the input signal terminal, the first pull-up node and the first clock signal terminal of the shift register unit, for providing the signal at the input signal terminal to the first pull-up node under the control of the first clock signal terminal; A second input subcircuit is connected to the power signal terminal, the first pull-down node and the first clock signal terminal, and is used to provide the signal at the power signal terminal to the first clock signal terminal under the control of the first clock signal terminal. Pull down the node.

11. The shift register unit according to claim 10, wherein: The first input sub-circuit comprises a sixth transistor, a gate of the sixth transistor is connected to the first clock signal terminal, a first electrode of the sixth transistor is connected to the input signal terminal, and a second electrode of the sixth transistor is connected to the first pull-up node; The second input sub-circuit includes a seventh transistor, a gate of the seventh transistor is connected to the first clock signal terminal, a first electrode of the seventh transistor is connected to the power signal terminal, and a second electrode of the seventh transistor is connected to the first pull-down node.

12. The shift register unit according to claim 10 or 11, wherein: The first control circuit comprises: a pull-up control subcircuit, connected to the first pull-up node, the first pull-down node and the first clock signal terminal, for providing a signal at the first clock signal terminal to the first pull-down node under the control of the first pull-up node; A pull-down control subcircuit is connected to the first pull-up node, the first pull-down node, the reference signal terminal and the second clock signal terminal of the shift register unit, and is used to provide the signal at the reference signal terminal to the first pull-up node under the control of the second clock signal terminal and the first pull-down node.

13. The shift register unit according to claim 12, wherein: The pull-up control subcircuit comprises an eighth transistor, a gate of the eighth transistor is connected to the first pull-up node, a first electrode of the eighth transistor is connected to the first clock signal terminal, and a second electrode of the eighth transistor is connected to the first pull-down node; The pull-down control subcircuit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor is connected to the second clock signal terminal, the first electrode of the ninth transistor is connected to the second electrode of the tenth transistor, the second electrode of the ninth transistor is connected to the first pull-up node or the fourth pull-up node, the gate of the tenth transistor is connected to the first pull-down node, and the first electrode of the tenth transistor is connected to the reference signal terminal.

14. The shift register unit according to any one of claims 10 to 13, wherein: The output circuit comprises: a first output subcircuit connected to one of the power signal terminal and the reference signal terminal, the second pull-up node and the output signal terminal, and configured to provide a signal at one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node; A second output subcircuit is connected to the other of the power signal terminal and the reference signal terminal, the second pull-down node and the output signal terminal, and is used to output the power signal terminal under the control of the second pull-down node. The signal at the other of the reference signal terminals is provided to the output signal terminal.

15. The shift register unit according to claim 14, wherein: The first output sub-circuit comprises an eleventh transistor and a third capacitor, wherein a gate of the eleventh transistor is connected to the second pull-up node, a first electrode of the eleventh transistor is connected to the power signal terminal, a second electrode of the eleventh transistor is connected to the output signal terminal, a first electrode of the third capacitor is connected to the second pull-up node, and a second electrode of the third capacitor is connected to the output signal terminal or the second clock signal terminal; The second output sub-circuit includes a twelfth transistor and a fourth capacitor, wherein the gate of the twelfth transistor is connected to the second pull-down node, the first electrode of the twelfth transistor is connected to the reference signal terminal, the second electrode of the twelfth transistor is connected to the output signal terminal, the first electrode of the fourth capacitor is connected to the second pull-down node, and the second electrode of the fourth capacitor is connected to the reference signal terminal.

16. The shift register unit according to claim 15, wherein: The second output sub-circuit further includes a thirteenth transistor and a fourteenth transistor, The first electrode of the twelfth transistor is connected to the reference signal terminal through the thirteenth transistor, wherein the gate of the thirteenth transistor is connected to the second pull-down node, the first electrode of the thirteenth transistor is connected to the reference signal terminal, and the second electrode of the thirteenth transistor is connected to the first electrode of the twelfth transistor; A gate of the fourteenth transistor is connected to the output signal terminal, a first electrode of the fourteenth transistor is connected to the power signal terminal, and a second electrode of the fourteenth transistor is connected to the first electrode of the twelfth transistor.

17. The shift register unit according to claim 14, wherein: The first output sub-circuit comprises an eleventh transistor and a third capacitor, wherein a gate of the eleventh transistor is connected to the second pull-up node, a first electrode of the eleventh transistor is connected to the reference signal terminal, a second electrode of the eleventh transistor is connected to the output signal terminal, a first electrode of the third capacitor is connected to the second pull-up node, and a second electrode of the third capacitor is connected to the reference signal terminal; The second output sub-circuit includes a twelfth transistor and a fourth capacitor, wherein the gate of the twelfth transistor is connected to the second pull-down node, the first electrode of the twelfth transistor is connected to the power signal terminal, the second electrode of the twelfth transistor is connected to the output signal terminal, the first electrode of the fourth capacitor is connected to the second pull-down node, and the second electrode of the fourth capacitor is connected to the output signal terminal.

18. The shift register unit according to claim 17, wherein: The first output sub-circuit further includes a thirteenth transistor and a fourteenth transistor, The second electrode of the eleventh transistor is connected to the output signal terminal through the thirteenth transistor, wherein the gate of the thirteenth transistor is connected to the second pull-up node, and the first electrode of the thirteenth transistor is connected to the The second electrode of the eleventh transistor is connected to the output signal terminal; A gate of the fourteenth transistor is connected to the output signal terminal, a first electrode of the fourteenth transistor is connected to the power signal terminal, and a second electrode of the fourteenth transistor is connected to the second electrode of the eleventh transistor.

19. The shift register unit according to any one of claims 10 to 18, further comprising: The second voltage stabilizing circuit is connected between the first pull-down node and the fourth transmission control subcircuit, wherein the second voltage stabilizing circuit and the fourth transmission subcircuit are connected to a third pull-down node, and the second voltage stabilizing circuit is used to stabilize the potential of the third pull-down node.

20. The shift register unit according to claim 19, wherein: The second voltage stabilizing circuit comprises: a fifteenth transistor and a sixteenth transistor; The gate of the fifteenth transistor is connected to the first pull-down node, the first electrode of the fifteenth transistor is connected to the second clock signal terminal, and the second electrode of the fifteenth transistor and the first electrode of the fourth transistor in the fourth transmission sub-circuit are connected to the third pull-down node; A gate of the sixteenth transistor is connected to the first pull-up node or the fourth pull-up node, a first electrode of the sixteenth transistor is connected to the reference signal terminal, and a second electrode of the sixteenth transistor is connected to the third pull-down node.

21. The shift register unit according to claim 20, wherein: The second voltage stabilizing circuit also includes: a seventeenth transistor, a gate of the seventeenth transistor is connected to the second clock signal end, a first electrode of the seventeenth transistor is connected to the second electrode of the sixteenth transistor, and a second electrode of the seventeenth transistor is connected to the second electrode of the fifteenth transistor.

22. The shift register unit according to any one of claims 10 to 21, wherein: The third pull-up node is used as a control output terminal of the shift register unit for cascade connection with other shift register units.

23. The shift register unit according to any one of claims 1 to 22, wherein: At least one transistor in the input circuit, the first control circuit, the second control circuit, and the output circuit is an N-type transistor.

24. A display driving circuit, comprising a plurality of shift register units connected in cascade, wherein the shift register units are the shift register units according to any one of claims 1 to 23.

25. A pixel driving circuit, comprising: A driving circuit having a control end, a first end, and a second end, and configured to generate a driving current from the first end to the second end under the control of a signal at the control end; An input circuit is connected to the data signal terminal and the control terminal of the driving circuit, and is used for receiving a first gate drive signal providing a data signal at a data signal terminal to a control terminal of the driving circuit under the control of; a compensation circuit connected to the first voltage terminal, the second voltage terminal, and the control terminal and the second terminal of the driving circuit, and configured to provide a reference voltage at the second voltage terminal to the second terminal of the driving circuit under the control of a second gate driving signal, and provide an initial voltage at the first voltage terminal to the control terminal of the driving circuit under the control of a third gate driving signal; The light emitting control circuit is connected between the first end of the driving circuit and the power signal end, and is used to connect or disconnect the first end of the driving circuit and the power signal end under the control of the light emitting control signal.

26. The pixel driving circuit according to claim 25, wherein: The compensation circuit includes a first transistor and a second transistor, The gate of the first transistor is configured to receive a second gate driving signal, the first electrode of the first transistor is connected to the second voltage terminal, and the second electrode of the first transistor is connected to the second terminal of the driving circuit; The gate of the second transistor is configured to receive a third gate driving signal, the first electrode of the second transistor is connected to the first voltage terminal, and the second electrode of the second transistor is connected to the control terminal of the driving circuit.

27. The pixel driving circuit according to claim 25 or 26, wherein: The light emitting control circuit comprises a third transistor, a gate of the third transistor is configured to receive the light emitting control signal, a first electrode of the third transistor is connected to the power signal terminal, and a second electrode of the third transistor is connected to the first terminal of the driving circuit.

28. The pixel driving circuit according to any one of claims 25 to 27, wherein: The input circuit comprises a fourth transistor, a gate of the fourth transistor is configured to receive the first gate drive signal, a first electrode of the fourth transistor is connected to the data signal terminal, and a second electrode of the fourth transistor is connected to the control terminal of the drive circuit; The driving circuit includes a driving transistor and a capacitor, wherein the gate, drain and source of the driving transistor serve as a control terminal, a first terminal and a second terminal of the driving circuit respectively, the first terminal of the capacitor is connected to the gate of the driving transistor, and the second terminal of the capacitor is connected to the second terminal of the driving transistor.

29. A display panel comprising at least one display driving circuit as claimed in claim 24 and a plurality of sub-pixels arranged in an array, wherein the sub-pixels include a pixel driving circuit, and the pixel driving circuit includes: A driving circuit having a control end, a first end, and a second end, and configured to generate a driving current from the first end to the second end under the control of a signal at the control end; An input circuit, connected to the data signal terminal and the control terminal of the driving circuit, for providing the data signal at the data signal terminal to the control terminal of the driving circuit under the control of the first gate driving signal; a compensation circuit, connected to the first voltage terminal, the second voltage terminal, and the control terminal and the second terminal of the driving circuit, for providing the reference voltage at the second voltage terminal to the second terminal of the driving circuit under the control of a second gate driving signal, and providing the initial voltage at the first voltage terminal to the control terminal of the driving circuit under the control of a third gate driving signal; a light emitting control circuit connected between the first end of the driving circuit and the power signal end, and used to connect or disconnect the first end of the driving circuit and the power signal end under the control of the light emitting control signal, The display driving circuit is used to provide at least one of a first gate driving signal, a second gate driving signal, a third gate driving signal and a light emitting control signal to the plurality of sub-pixels.

30. A method for controlling a shift register unit according to any one of claims 1 to 23, comprising: In the input stage, the input circuit provides the signals of the input signal terminal and the power signal terminal to the first pull-up node and the first pull-down node respectively; In the output stage, the first control circuit controls the potential of the first pull-down node based on the potential of the first pull-up node and controls the potential of the first pull-up node based on the potential of the first pull-down node, the second control circuit transfers the signal at the first pull-up node to the second pull-up node and transfers the signal at the first pull-down node to the second pull-down node, so that one of the second pull-up node and the first pull-up node is at a high level and the other of the second pull-up node and the first pull-up node is at a low level, and the output circuit provides the signal of one of the power signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node; In the reset stage, the first control circuit controls the potential of the first pull-down node based on the potential of the first pull-up node and controls the potential of the first pull-up node based on the potential of the first pull-down node, the second control circuit transfers the signal at the first pull-up node to the second pull-up node and transfers the signal at the first pull-down node to the second pull-down node, so that one of the second pull-up node and the first pull-up node is at a high level and the other of the second pull-up node and the first pull-up node is at a low level, and the output circuit provides the signal of the other of the power supply signal terminal and the reference signal terminal to the output signal terminal under the control of the second pull-up node and the second pull-down node.

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