Cache data processing device, Cache data processing system and chip
By introducing a logical control unit into the pipeline processing unit of the Cache, the previous commands of the next pipeline level are judged and processed, the problem of pipeline pause during cache data read and write conflicts is solved, and the access efficiency of the Cache is improved.
Patent Information
- Application Number
- CN202510019832.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-05-09
AI Technical Summary
When existing Cache data read and write conflicts occur, the pipeline needs to be paused, resulting in a decrease in the access efficiency of the Cache.
When the logic control unit executes a read command at the current pipeline processing unit, it determines whether there is a prior command to write or read data at the next pipeline processing unit. If so, the next pipeline control level will control the execution of the prior command to avoid read and write conflicts, thereby improving the access efficiency of the cache.
This method can perform data reading or writing operations in advance when reading data miss, avoid read and write conflicts, and improve the access efficiency of the Cache.
Smart Images
Figure CN119960834A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a cache data processing device, a cache data processing system and a chip. Background Art
[0002] In modern computer architecture, cache (cache memory) plays a key role in reducing access latency and improving system performance as an important bridge between CPU and data storage unit. In the fields of multi-task concurrent execution, big data processing and real-time systems, with the surge in data processing volume, cache not only needs to quickly process massive read and write requests, but also needs to effectively manage potential data read and write conflicts to ensure data consistency and integrity.
[0003] At present, the existing cache data reading and writing methods generally adopt the pipeline processing method. In the pipeline, a command is decomposed into multiple operations, each operation is executed in a different pipeline stage, and the operation of a pipeline stage is executed within one clock cycle. When a data read or write conflict occurs, that is, when multiple instructions request to read or write at the same time, since the read or write operation cannot be performed simultaneously in the same pipeline stage, it is generally necessary to pause the pipeline, and the subsequent instructions must wait when encountering a read or write conflict to ensure the consistency and correctness of the data.
[0004] However, the entire pipeline is paused, and the execution of subsequent pipeline stages will be forced to be delayed, which greatly affects the access efficiency of the cache. Summary of the invention
[0005] In view of the deficiencies in the prior art, the present application provides a cache data processing device, a cache data processing system and a chip. A logic control unit is used to determine whether the next pipeline stage of the current pipeline stage has a prior command that requires writing data to a data storage unit or reading data from the data storage unit when the execution result of a read command executed at the current pipeline stage of a pipeline processing unit is a read data miss. If so, the next pipeline stage is controlled to execute a prior command. The data read or write operation of a prior command can be executed in advance by utilizing the characteristic that data does not need to be read from the data storage unit when the read data miss occurs, and no read-write conflict will occur at this time, thereby improving the access efficiency of the cache.
[0006] To solve the above problems, this application provides the following technical solutions:
[0007] In a first aspect, an embodiment of the present application provides a Cache data processing device, including a pipeline processing unit and a logic control unit.
[0008] The pipeline processing unit includes a plurality of pipeline stages;
[0009] The pipeline processing unit is used to receive a read command and execute the read command in a pipeline manner using the pipeline stage;
[0010] The logic control unit is used to determine whether the pipeline processing unit has a prior command to write data into or read data from a data storage unit within the execution time of a next pipeline level when the execution result of the read command executed by the current pipeline level of the pipeline processing unit is a read data miss; if so, control the execution of the prior command to write data into or read data from the data storage unit, wherein the current pipeline level and the next pipeline level are adjacent pipeline levels executed sequentially.
[0011] In some embodiments, when the current pipeline stage determines that the execution result of the read command is a hit, and the logic control unit determines that there is a read-write conflict when the next pipeline stage processes the read command, the logic control unit is further used to control another pipeline stage to read the read data corresponding to the read command from the data storage unit, and the next pipeline stage and the next pipeline stage are adjacent pipeline stages executed sequentially.
[0012] In some embodiments, when the current pipeline stage determines that the execution result of the read command is a hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage processes the read command, the logic control unit is also used to control the next pipeline stage to read the read data corresponding to the read command from the data storage unit.
[0013] In some embodiments, the pipeline processing unit is further used to receive a write command and execute the write command in the pipeline manner using the pipeline stage;
[0014] The logic processing unit is also used to control another pipeline stage of the current pipeline stage to write the write data corresponding to the write command into the data storage unit when the execution result of the write command executed by the current pipeline stage of the pipeline processing unit is hit, and the logic control unit determines that there is a read-write conflict when the next pipeline stage of the current pipeline stage processes the write command, wherein the current pipeline stage and the next pipeline stage are adjacent pipeline stages executed sequentially, and the next pipeline stage and the next pipeline stage are adjacent pipeline stages executed sequentially.
[0015] In some embodiments, when the current pipeline stage determines that the execution result of the write command is a hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage processes the write command, the logic control unit is also used to control the next pipeline stage to write the write data into the data storage unit.
[0016] In some embodiments, when the current pipeline stage determines that the execution result of the write command is not a hit and the cache is in a full state, the logic processing unit is also used to control the current pipeline stage to delay the write command for one clock cycle when it is determined that there is a read-write conflict when the next pipeline stage processes the write command, and then control the second next pipeline stage to read out the replacement data and control the next pipeline stage to write the write data into the data storage unit.
[0017] In some embodiments, when the current pipeline stage determines that the execution result of the write command is not a hit and the cache is in a full state, the logic processing unit is also used to control the next pipeline stage to read the data to be replaced from the data storage unit and control the next pipeline stage to write the write data into the data storage unit when it is determined that there is no read-write conflict when the next pipeline stage processes the write command.
[0018] In some embodiments, when the execution result of the write command executed by the current pipeline stage is not a hit and the cache is in a full state, the logic processing unit is also used to control the next pipeline stage to write the write data into the data storage unit when it is determined that there is no read-write conflict when the next pipeline stage processes the write command.
[0019] In some embodiments, when the execution result of the write command executed by the current pipeline stage of the pipeline processing unit is not a hit and the cache is in a full state, the logic processing unit is also used to control the next pipeline stage to write the write data into the data storage unit when it is determined that there is a read-write conflict when the next pipeline stage processes the write command.
[0020] In a second aspect, an embodiment of the present application provides a cache data processing system, including a data storage unit and a cache data processing device as described in the first aspect.
[0021] In a third aspect, an embodiment of the present application provides a chip, comprising the Cache data processing system as described in the second aspect.
[0022] The present application provides a cache data processing device, a cache data processing system and a chip. The present application uses a logic control unit to determine whether the next pipeline stage of the current pipeline stage has a previous command that requires writing data into a data storage unit or reading data from the data storage unit when the execution result of executing a read command at the current pipeline stage of the pipeline processing unit is a read data miss. If so, the next pipeline stage is controlled to execute a previous command. The data read or write operation of a previous command can be executed by utilizing the characteristic that data does not need to be read from the data storage unit when the read data miss occurs, and no read-write conflict will be generated at this time, thereby improving the access efficiency of the cache. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a structural diagram of a Cache data processing device provided in an embodiment of the present application.
[0024] Figure 2 It is a schematic diagram of the pipeline provided in the embodiment of the present application.
[0025] Figure 3 It is a structural diagram of the Cache data processing system provided in an embodiment of the present application. DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0028] See also Figure 1 , Figure 1 Schematic diagram of the structure of the Cache data processing device provided in the embodiment of the present application. Figure 1As shown, in some embodiments, the cache data processing device 100 includes a pipeline processing unit 110 and a logic control unit 120. The pipeline processing unit 110 includes a plurality of pipeline stages that are executed in sequence. The pipeline processing unit 110 is used to receive a read command and execute the read command in a pipeline manner using pipeline stages. The logic control unit 120 is used to determine whether the pipeline processing unit has a previous command to write data into or read data from a data storage unit within the execution time of the next pipeline stage of the current pipeline stage when the execution result of the read command executed by the current pipeline stage of the pipeline processing unit 110 is a read data miss, and if so, control the next pipeline stage to execute a previous command to write data into or read data from the data storage unit. Among them, the current pipeline stage and the next pipeline stage are adjacent pipeline stages that are executed in sequence for the same command. The execution time of the next pipeline stage is after the execution time of the current pipeline stage. In a specific embodiment, the execution time of a pipeline stage can be one clock cycle.
[0029] See also Figure 2 , Figure 2 Schematic diagram of the pipeline provided in the embodiment of the present application. Figure 2 As shown, in one embodiment, the pipeline processing unit 110 includes 8 pipeline stages, namely pipeline stage 10, pipeline stage 20, pipeline stage 30, pipeline stage 40, pipeline stage 50, pipeline stage 60, pipeline stage 70 and pipeline stage 80. All commands input into the pipeline processing unit share the pipeline processing unit. For a command, the pipeline processing unit executes the command in a pipeline manner.
[0030] like Figure 2 As shown, pipeline stage 10 of the pipeline processing unit receives write command 1 at execution time t0, and pipeline stage 20, pipeline stage 30, pipeline stage 40, pipeline stage 50, pipeline stage 60, pipeline stage 70 and pipeline stage 80 process the write command 1 at execution time t1, execution time t2, execution time t3, execution time t4, execution time t5, execution time t6 and execution time t7, respectively. Pipeline stage 10 of the pipeline processing unit receives write command 2 at execution time t1, and pipeline stage 20, pipeline stage 30, pipeline stage 40, pipeline stage 50, pipeline stage 60, pipeline stage 70 and pipeline stage 80 process the write command 2 at execution time t2, execution time t3, execution time t4, execution time t5, execution time t6, execution time t7 and execution time t8, respectively. And so on.
[0031] The pipeline stage 10 of the pipeline processing unit receives the read command 3 at the execution time t2, and the pipeline stages 20 and 30 process the read command 3 in sequence. When the execution result of the read command 3 executed by the current pipeline stage 40 is a read data miss, the logic control unit 120 determines whether the pipeline processing unit 110 has a previous command to write data into the data storage unit or read data from the data storage unit at the execution time t6 of the next pipeline stage 50. Figure 2 It can be seen that at the execution time t6, the write command 2 needs to be executed to write data into the data storage unit, so the logic control unit 120 controls the pipeline stage 60 to execute the write command 2 at the execution time t6 to write the data into the data storage unit.
[0032] The cache data processing device of the present application uses a logic control unit to determine whether there is a previous command at the execution time of the next pipeline stage of the current pipeline stage that needs to write data to the data storage unit or read data from the data storage unit when the execution result of the read command executed at the current pipeline stage of the pipeline processing unit is a read data miss. If so, the execution of a previous command is controlled. The data read or write operation of a previous command can be executed by utilizing the characteristic that data does not need to be read from the data storage unit when the read data miss occurs, and no read-write conflict will be generated at this time, thereby improving the access efficiency of the cache.
[0033] In some embodiments, when the current pipeline stage determines that the execution result of the read command is a hit, and the logic control unit determines that there is a read-write conflict in processing the read command at the execution time of the next pipeline stage, the logic control unit is further used to control reading the read data corresponding to the read command from the data storage unit at the execution time of the next pipeline stage. The next pipeline stage and the next pipeline stage are adjacent pipeline stages that are executed in sequence for the same command, and the execution time of the next pipeline stage is after the execution time of the next pipeline stage.
[0034] Continue reading Figure 2 When the current pipeline stage 40 determines that the execution result of the read command is a hit, if the logic control unit determines that there is a read-write conflict when the next pipeline stage 50 processes the read command at the execution time t6, the logic control unit controls another pipeline stage 60 to execute the read command at the execution time t7 and reads the corresponding data from the data storage unit.
[0035] In some embodiments, when the current pipeline stage determines that the execution result of the read command is a hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage processes the read command, the logic control unit is also used to control the next pipeline stage to read the read data corresponding to the read command from the data storage unit.
[0036] Continue reading Figure 2When the current pipeline stage 40 determines that the execution result of the read command is a hit, if the logic control unit determines that there is no read-write conflict when processing the read command at the execution time of the next pipeline stage 50, the logic control unit controls the next pipeline stage 50 to execute the read command at the execution time t6 and reads the corresponding data from the data storage unit.
[0037] In some embodiments, the pipeline processing unit is further used to receive a write command and execute the write command in a pipeline manner using a pipeline stage. The logic processing unit is also used to control the next pipeline stage of the current pipeline stage to write the write data corresponding to the write command into the data storage unit when the execution result of the write command executed by the current pipeline stage of the pipeline processing unit is hit and the logic control unit determines that there is a read-write conflict when the next pipeline stage of the current pipeline stage processes the write command. The current pipeline stage and the next pipeline stage are adjacent pipeline stages executed in sequence for the same command, and the next pipeline stage and the next pipeline stage are adjacent pipeline stages executed in sequence.
[0038] Continue reading Figure 2 , the pipeline processing unit is also used to receive write command 1, write command 2 and write command 4. Taking write command 2 as an example, for write command 2, if the execution result of the write command executed by the current pipeline stage 40 at the execution time t4 is hit, and the logic control unit determines that there is a read-write conflict when the next pipeline stage (i.e., pipeline stage 50) of the current pipeline stage processes the write command at the execution time t5, then the next pipeline stage (i.e., pipeline stage 60) of the current pipeline stage is controlled to write the write data corresponding to the write command into the data storage unit at the execution time t6.
[0039] In some embodiments, when the current pipeline stage determines that the execution result of the write command is a hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage processes the write command, the logic control unit is also used to control the next pipeline stage to write the write data into the data storage unit.
[0040] Continue reading Figure 2 , when the execution result of the write command executed by the current pipeline stage 40 is hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage (i.e., pipeline stage 50) processes the write command, the pipeline stage 50 is controlled to execute the write command at execution time t5 and write the write data into the data storage unit.
[0041] In some embodiments, when the current pipeline stage determines that the execution result of the write command is not a hit and the cache is in a full state, the logic processing unit is also used to control the current pipeline stage to delay the write command for one clock cycle when it is determined that there is a read-write conflict in the next pipeline stage processing the write command, and then control the second next pipeline stage to read out the replacement data and control the next pipeline stage to write the write data into the data storage unit.
[0042] Continue reading Figure 2 , when the execution result of the write command executed by the current pipeline stage 40 is hit, and the logic control unit determines that there is a read-write conflict when the next pipeline stage (i.e., pipeline stage 50) processes the write command, the pipeline stage 40 is controlled to delay the write command by one clock cycle (i.e., in this case, the execution time of the pipeline stage 40 is 2 clock cycles), and then the pipeline stage 60 is controlled to execute the write command at the execution time t6 to write the write data into the data storage unit.
[0043] In some embodiments, when the current pipeline stage determines that the execution result of the write command is not a hit and the cache is in a full state, the logic processing unit is also used to control the next pipeline stage to read the data to be replaced from the data storage unit and control another pipeline stage to write the write data into the data storage unit when it is determined that there is no read-write conflict when the next pipeline stage processes the write command.
[0044] Continue reading Figure 2 , when the execution result of the write command 1 executed by the current pipeline stage 40 is not a hit, and the cache is in a full state, and the logic control unit determines that there is no read-write conflict when the next pipeline stage (i.e., pipeline stage 50) processes the write command, then the pipeline stage 50 is controlled to execute the write command at execution time t4, read the data to be replaced from the data storage unit, and the pipeline stage 60 is controlled to write the write data into the data storage unit at execution time t5.
[0045] Continue reading Figure 2 , when the execution result of the write command executed by the current pipeline stage 40 is not a hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage (i.e., pipeline stage 50) processes the write command, the pipeline stage 50 is controlled to execute the write command at execution time t5 and write the write data into the data storage unit.
[0046] In some embodiments, when the execution result of the write command executed by the current pipeline stage is not a hit, and the cache is in a full state, and the cache is not full, the logic processing unit is also used to control the next pipeline stage to write the write data into the data storage unit when it is determined that there is no read-write conflict when the next pipeline stage processes the write command.
[0047] Please continue reading Figure 2 , when the execution result of the write command executed by the current pipeline stage 40 is not a hit, and the cache is not full, and the logic control unit determines that there is no read-write conflict when the next pipeline stage (i.e., pipeline stage 50) processes the write command, then the pipeline stage 50 is controlled to execute the write command at execution time t5 and write the write data into the data storage unit.
[0048] In some embodiments, when the execution result of the write command executed by the current pipeline stage of the pipeline processing unit is not a hit and the cache is not full, the logic processing unit is also used to control the next pipeline stage to write the write data into the data storage unit when it is determined that there is a read-write conflict in the next pipeline stage processing the write command.
[0049] See also Figure 3 , Figure 3 Schematic diagram of the structure of the Cache data processing system provided in the embodiment of the present application. Figure 3 As shown, the present application also provides a Cache data processing system 200, including a data storage unit 210 and the Cache data processing device 100 as described above.
[0050] The present application also provides a chip, comprising the Cache data processing system as described above.
[0051] In summary, the cache data reading and writing method provided in the embodiment of the present application has the following advantages:
[0052] 1. A logic control unit is used to determine whether the next pipeline stage of the current pipeline stage has a previous command to write data into or read data from a data storage unit when the execution result of a read command executed at the current pipeline stage of the pipeline processing unit is a read data miss. If yes, the next pipeline stage is controlled to execute a previous command. The data read or write operation of a previous command can be executed in advance by utilizing the characteristic that data does not need to be read from the data storage unit when the read data is missed, and no read-write conflict will be generated at this time, thereby improving the access efficiency of the Cache.
[0053] 2. By determining that there is a read-write conflict when processing a read command or a write command at the current pipeline stage, the pipeline stage executed after the current pipeline stage is controlled to perform data read or write operations when there is no read-write conflict, without pausing the entire pipeline, thereby improving the cache access efficiency.
[0054] In summary, the present application provides a cache data processing device, a cache data processing system and a chip, wherein the cache data processing device includes a pipeline processing unit and a logic control unit, wherein the pipeline processing unit includes a plurality of pipeline stages executed sequentially; the pipeline processing unit is used to receive a read command, and execute the read command in a pipeline manner using pipeline stages; the logic control unit is used to determine whether the next pipeline stage of the current pipeline stage has a prior command to write data to a data storage unit or read data from the data storage unit when the execution result of the read command executed by the current pipeline stage of the pipeline processing unit is a read data miss, and if so, control the next pipeline stage to execute a prior write command, wherein the current pipeline stage and the next pipeline stage are adjacent pipeline stages executed sequentially. The present application uses a logic control unit to determine whether the next pipeline stage of the current pipeline stage has a previous command that requires writing data to a data storage unit or reading data from the data storage unit when the execution result of a read command executed at the current pipeline stage of the pipeline processing unit is a read data miss. If so, the next pipeline stage is controlled to execute a previous command. The data read or write operation of a previous command can be executed in advance by utilizing the characteristic that data does not need to be read from the data storage unit when the read data is missed, and no read-write conflict will be generated at this time, thereby improving the access efficiency of the Cache.
[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A cache data processing device, characterized in that: Including pipeline processing unit and logic control unit, The pipeline processing unit includes a plurality of pipeline stages; The pipeline processing unit is used to receive a read command and execute the read command in a pipeline manner using the pipeline stage according to the control of the logic control unit; The logic control unit is used to determine whether the pipeline processing unit has a prior command to write data into or read data from a data storage unit within the execution time of a next pipeline level when the execution result of the read command executed by the current pipeline level of the pipeline processing unit is a read data miss; if so, control the pipeline processing unit to execute the prior command to write data into or read data from the data storage unit, wherein the current pipeline level and the next pipeline level are adjacent pipeline levels executed sequentially.
2. The device according to claim 1, characterized in that When the current pipeline stage determines that the execution result of the read command is a hit, and the logic control unit determines that there is a read-write conflict when the next pipeline stage processes the read command, the logic control unit is also used to control another pipeline stage to read the read data corresponding to the read command from the data storage unit, and the next pipeline stage and the next pipeline stage are adjacent pipeline stages executed sequentially.
3. The device according to claim 1, characterized in that When the current pipeline stage determines that the execution result of the read command is a hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage processes the read command, the logic control unit is also used to control the next pipeline stage to read the read data corresponding to the read command from the data storage unit.
4. The device according to any one of claims 1 to 3, characterized in that: The pipeline processing unit is further used to receive a write command and execute the write command in the pipeline manner according to the control of the logic control unit; The logic processing unit is also used to control the pipeline processing unit to write the write data corresponding to the write command into the data storage unit within the execution time of another pipeline stage, when the execution result of executing the write command in the current pipeline stage of the pipeline processing unit is hit, and the logic control unit determines that there is a read-write conflict when the pipeline processing unit processes the write command within the execution time of another pipeline stage, wherein the current pipeline stage and the next pipeline stage are adjacent pipeline stages executed sequentially, and the next pipeline stage and the next pipeline stage are adjacent pipeline stages executed sequentially.
5. The device according to claim 4, characterized in that When the current pipeline stage determines that the execution result of the write command is a hit, and the logic control unit determines that there is no read-write conflict when the next pipeline stage processes the write command, the logic control unit is also used to control the next pipeline stage to write the write data into the data storage unit.
6. The device according to claim 5, characterized in that When the current pipeline stage determines that the execution result of the write command is not a hit and the cache is in a full state, the logic processing unit is also used to control the current pipeline stage to delay the write command for one clock cycle when it is determined that there is a read-write conflict when the next pipeline stage processes the write command, and then control the second next pipeline stage to read out the replacement data and control the next pipeline stage to write the write data into the data storage unit.
7. The device according to claim 6, characterized in that When the current pipeline stage determines that the execution result of the write command is not a hit and the cache is in a full state, the logic processing unit is also used to control the next pipeline stage to read the data to be replaced from the data storage unit and control the next pipeline stage to write the write data into the data storage unit when it is determined that there is no read-write conflict when the next pipeline stage processes the write command.
8. The device according to claim 6, characterized in that When the execution result of the write command executed by the current pipeline stage is no hit and the cache is not full, the logic processing unit is also used to control the next pipeline stage to write the write data into the data storage unit when it is determined that there is no read-write conflict when the next pipeline stage processes the write command.
9. The device according to claim 8, characterized in that When the execution result of the write command executed by the current pipeline stage is no hit and the cache is not full, the logic processing unit is also used to control the next pipeline stage to write the write data into the data storage unit when it is determined that there is a read-write conflict when the next pipeline stage processes the write command.
10. A cache data processing system, characterized in that: It comprises a data storage unit and a Cache data processing device as described in any one of claims 1 to 9.
11. A chip, characterized in that: It comprises the Cache data processing system as claimed in claim 10.