Firmware loading system, firmware loading method, and endoscope processing device

Abstract

The invention discloses a firmware loading system, a firmware loading method and endoscope processing equipment, and is suitable for the technical field of endoscopes. The firmware loading system comprises a first type of processor, a second type of processor, an FPGA and a memory, wherein at least two pieces of firmware for being loaded by the FPGA are stored in the memory; the extraction information of each firmware stored in the memory is recorded in the database of the first type processor; the first type of processor is in communication connection with the second type of processor and is used for transmitting extraction information of target firmware to be loaded to the FPGA to the second type of processor; the output end of the second type of processor is connected with the input end of the storage, the output end of the storage is connected with the input end of the second type of processor and the input end of the FPGA, and the storage is used for outputting target firmware in response to extraction information input by the second type of processor so as to load the target firmware to the FPGA. Based on the scheme, dynamic loading of the firmware can be achieved, and the firmware loading efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of endoscopes, and in particular to a firmware loading system, a firmware loading method and an endoscope processing device. Background Art

[0002] In endoscopes, field-programmable gate arrays (FPGAs) are usually used to process image data collected by cameras. As the connected endoscope body changes, the logic program firmware of the FPGA also needs to change accordingly.

[0003] In the existing endoscope firmware loading, the processor and FPGA are usually independent of each other, and dynamic loading of firmware cannot be realized. For endoscope processing equipment, it is usually necessary to be compatible with multiple scope types. The logic program firmware of different scope types is different. If a conventional firmware loading system is used, mismatch may occur; some embedded processors are connected to FPGA and take on the firmware loading work to realize dynamic loading of firmware, but the firmware loading efficiency is low.

[0004] Therefore, how to improve the efficiency of dynamic firmware loading is an urgent problem that needs to be solved by those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a firmware loading system, a firmware loading method and an endoscope processing device to solve the technical problem that the existing firmware dynamic loading method has low efficiency.

[0006] In order to solve the above technical problems, the present invention provides a firmware loading system, comprising a first type processor, a second type processor, an FPGA and a memory, wherein the memory stores at least two firmwares for loading by the FPGA; the database of the first type processor records the extraction information of each firmware stored in the memory;

[0007] The first type of processor is communicatively connected with the second type of processor, and is used to transmit the extracted information of the target firmware to be loaded into the FPGA to the second type of processor;

[0008] An output terminal of the second type processor is connected to an input terminal of the memory;

[0009] The output end of the memory is connected to the input end of the second type processor and the input end of the FPGA respectively, and is used to output the target firmware in response to the extraction information input by the second type processor, so as to load the target firmware into the FPGA.

[0010] Exemplarily, the first type processor is also connected to the memory for burning the firmware into the memory.

[0011] Exemplarily, the first type of processor is also connected to the FPGA to monitor the loading status of the FPGA.

[0012] Exemplarily, the first type of processor, the second type of processor, the FPGA, and the memory share a clock signal.

[0013] Exemplarily, the number of the first type of processor and the number of the second type of processor are both one, and the first type of processor is a multi-tasking application processor, and the second type of processor is a real-time processor.

[0014] Exemplarily, the second type of processor, the FPGA and the memory are connected via an SPI bus, the second type of processor is a master device, and the FPGA and the memory are slave devices;

[0015] The output end of the second type processor is connected to the input end of the memory through the MOSI data line in the SPI bus, and the output end of the memory is connected to the input end of the second type processor and the input end of the FPGA respectively through the MISO data line in the SPI bus.

[0016] Exemplarily, a chip select signal pin of the first type of processor is connected to a chip select signal pin of the memory;

[0017] The first type of processor is connected to the input end of the memory via a MOSI data line in the SPI bus, and the first type of processor is a master device, and the memory is a slave device.

[0018] For example,

[0019] The GPIO port of the first type of processor is connected to the reset port of the FPGA.

[0020] To solve the above technical problems, the present invention also provides a firmware loading method, which is applied to a first type processor of a firmware loading system, and the firmware loading system also includes a second type processor, an FPGA and a memory, wherein the memory stores at least two firmwares for loading by the FPGA; the database of the first type processor records the extraction information of each firmware stored in the memory; the first type processor is communicatively connected with the second type processor, and the output end of the second type processor is connected to the input end of the memory; the output end of the memory is respectively connected to the input end of the second type processor and the input end of the FPGA, and the firmware loading method includes:

[0021] Determining target firmware to be loaded into the FPGA;

[0022] Based on the database, querying the extraction information of the target firmware in the memory;

[0023] The extraction information is transmitted to the second type of processor, so that the second type of processor controls the memory to output the target firmware based on the extraction information, so as to load the target firmware into the FPGA.

[0024] Exemplarily, the firmware loading system is applied to an endoscope processing device, and the determining of the target firmware to be loaded into the FPGA includes:

[0025] identifying scope information of an endoscope connected to the endoscope processing device;

[0026] The target firmware to be loaded into the FPGA is determined according to the scope information.

[0027] Exemplarily, the first type of processor is also connected to the memory, and when the extraction information of the target firmware in the memory cannot be queried in the database, the firmware loading method further includes:

[0028] Obtaining an installation package containing the target firmware;

[0029] Burning the target firmware in the installation package into the memory;

[0030] The mapping relationship between the target firmware and its extracted information in the memory is recorded in the database to facilitate reloading.

[0031] Exemplarily, the first type of processor is also connected to the memory, and before determining the target firmware to be loaded into the FPGA, the firmware loading method further includes:

[0032] Determine the user's access rights;

[0033] Obtaining a permission installation package corresponding to the usage permission;

[0034] Burning the firmware in the permission installation package into the memory;

[0035] The mapping relationship between each firmware and its extracted information in the memory is recorded in the database to facilitate firmware loading.

[0036] In order to solve the above technical problems, the present invention also provides a firmware loading method, which is applied to a second type processor of a firmware loading system, and the firmware loading system also includes a first type processor, an FPGA and a memory, wherein the memory stores at least two firmwares for loading by the FPGA; the database of the first type processor records the extraction information of each firmware stored in the memory; the first type processor is communicatively connected with the second type processor, and the output end of the second type processor is connected to the input end of the memory; the output end of the memory is respectively connected to the input end of the second type processor and the input end of the FPGA, and the firmware loading method includes:

[0037] receiving extraction information in the memory of target firmware to be loaded into the FPGA transmitted by the first type of processor;

[0038] The memory is controlled to output the target firmware according to the extracted information, so as to load the target firmware into the FPGA.

[0039] In order to solve the above technical problems, the present invention also provides an endoscope processing device, including the firmware loading system as described above.

[0040] Exemplarily, the first type of processor in the firmware loading system is also connected to the endoscope connected to the endoscope processing device for communication, so as to obtain the endoscope body information of the endoscope, and determine the target firmware to be loaded into the FPGA according to the endoscope body information.

[0041] The present invention provides a firmware loading system, comprising a first-class processor, a second-class processor, an FPGA and a memory; wherein the memory stores at least two firmwares for loading on the FPGA, and a database of the first-class processor records the extraction information of each firmware stored in the memory; thereby, the first-class processor can select one of the multiple firmwares stored in the memory (i.e., the target firmware) to load into the FPGA according to actual needs, so as to realize dynamic loading of the firmware; further, the first-class processor is communicatively connected with the second-class processor, and is used to transmit the extraction information of the target firmware to be loaded into the FPGA to the second-class processor, the output end of the second-class processor is connected to the input end of the memory, and the output end of the memory is respectively connected to the input end of the second-class processor and the input end of the FPGA; thereby, the second-class processor can read the target firmware from the memory according to the extraction information of the target firmware determined by the first-class processor, and complete the loading of the FPGA in the process of the memory outputting the target firmware related data. It can be seen that the firmware loading system provided by the present invention is composed of at least two types of processors to share the various subdivided steps of the firmware loading process (such as firmware query and firmware loading), and can assign corresponding subdivided steps to different types of processors according to their characteristics, making full use of the performance of different types of processors. Compared with a single processor performing all firmware loading tasks, the efficiency of firmware loading can be improved.

[0042] In addition, the present invention also provides an endoscope processing device and a firmware loading method for a first type processor and a second type processor respectively applied to a firmware loading system, which has the same beneficial effects as the above-mentioned firmware loading system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 It is a structural diagram of an existing firmware loading system;

[0045] Figure 2 It is a structural diagram of another existing firmware loading system;

[0046] Figure 3 It is a structural diagram of another existing firmware loading system;

[0047] Figure 4 A schematic diagram of the structure of a firmware loading system provided by an embodiment of the present invention;

[0048] Figure 5A schematic diagram of the structure of another firmware loading system provided by an embodiment of the present invention;

[0049] Figure 6 A flowchart of a firmware loading method for a first type of processor applied to a firmware loading system provided by an embodiment of the present invention;

[0050] Figure 7 A flowchart of a firmware loading method for a second type of processor applied to a firmware loading system provided by an embodiment of the present invention;

[0051] Figure 8 A flowchart of another firmware loading method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] The core of the present invention is to provide a firmware loading system, a firmware loading method and an endoscope processing device to solve the technical problem of low efficiency of the existing firmware dynamic loading method.

[0054] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0055] It should be noted that the existing firmware loading solutions are roughly divided into three types: one is a combination of an embedded processor, FPGA and dual flash memory (FLASH); Figure 1 It is a structural diagram of an existing firmware loading system, such as Figure 1 As shown, the programmable system-on-chip 1 (embedded processor subsystem) and the typical FPGA system 2 (FPGA subsystem) are independent subsystems, each with its own FLASH memory to store firmware or data. The FPGA's control pins PROGRAM_B, INIT_B, and DONE are directly pulled up and are not controlled by the embedded processor. In addition, the FPGA uses the Master mode and actively loads firmware data from the Flash after power-on. In this solution, the FPGA does not need to load firmware through the embedded processor and can complete it by itself. However, the target firmware that the embedded processor needs to call may not match the firmware loaded by the FPGA, resulting in the inability to change the FPGA firmware and dynamically load it. The second type is a combination of an embedded processor, FPGA, and a single FLASH. Figure 2A structural diagram of another existing firmware loading system is shown below. Figure 2 As shown in the figure, the programmable system on chip 1 (embedded processor subsystem) and the typical FPGA system 2 (FPGA subsystem) are closely connected, and the initialization signal of the FPGA is controlled by the embedded processor; the FPGA adopts the Slave mode and passively obtains the firmware data from the embedded processor, and this firmware data is obtained by the embedded processor from the Flash memory. In short, in the process of loading the FPGA firmware, the embedded processor is in the position of an intermediate agent. In this system, since the embedded processor is in the role of an intermediate agent, the FPGA loading process will pass through the embedded processor, and the loading efficiency is reduced. The third type is a combination of an embedded processor, an FPGA and a single FLASH multiplexing data and clock. Figure 3 It is a structural diagram of another existing firmware loading system, such as Figure 3 As shown, the master input slave output (MISO) signal line and clock signal line of the serial peripheral interface (SPI) bus are mainly reused. When the firmware is loaded, the embedded processor in the programmable chip system 1 (embedded processor subsystem) actively pulls the firmware data stream from the Flash memory (flash memory 1), but does not process it. The firmware data stream reaches the FPGA through a bypass. Figure 3 The firmware dynamic loading efficiency of the firmware loading system shown is Figure 2 The firmware loading system shown has been improved, but it is still difficult to meet the actual application requirements of endoscope processing equipment.

[0056] In view of this, an embodiment of the present invention provides a firmware loading system with a multi-processor architecture, a firmware loading method and an endoscope processing device, which can further improve the efficiency of dynamic firmware loading.

[0057] Figure 4 A schematic diagram of the structure of a firmware loading system provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the firmware loading system includes a first type processor 11, a second type processor 12, a memory 13 and an FPGA 14;

[0058] The memory 13 stores at least two firmwares for loading by the FPGA 14; the database of the first type of processor 11 records the extraction information of each firmware stored in the memory 13;

[0059] The first type processor 11 is communicatively connected with the second type processor 12, and is used to transmit the extracted information of the target firmware to be loaded into the FPGA 14 to the second type processor 12;

[0060] The output terminal of the second type processor 12 is connected to the input terminal of the memory 13;

[0061] The output end of the memory 13 is connected to the input end of the second type processor 12 and the input end of the FPGA 14 respectively, and is used to output the target firmware in response to the extraction information input by the second type processor 12 to load the target firmware into the FPGA 14 .

[0062] Specifically, the firmware loading system in this embodiment is a multiple processor architecture, with multiple (i.e., more than 1) processors or central processing units (CPU), which can process multiple tasks and data simultaneously. The multi-processor architecture can greatly improve the performance and throughput of the computer, and is particularly suitable for application scenarios that require processing large amounts of data and high concurrency. The first type of processor and the second type of processor in this embodiment refer to two types of processors with different properties. For example, one processor is used to process tasks with high real-time requirements, and the other processor is used to interact with users, run various software programs, etc. The embodiment of the present invention does not limit the number of the first type of processors and the second type of processors, and can be set according to actual conditions.

[0063] The memory may be any readable storage medium that can be used to store firmware, for example, a flash memory (FLASH), which stores at least two firmwares for FPGA to load. These firmwares may be firmwares pre-burned to the memory, and can be used to configure the FPGA, and the extraction information of these firmwares in the memory (for example, the firmware address information of the firmware in the memory and the byte length of the current firmware, etc.) is recorded in the database of the first type of processor. Therefore, the first type of processor can query the database for the extraction information of a certain firmware (for example, the target firmware to be loaded into the FPGA) in the memory according to the actual application requirements, so as to load the target firmware into the FPGA based on the extraction information in the subsequent steps, thereby realizing the process of dynamically loading firmware.

[0064] Exemplarily, when the firmware loading system provided by the present invention is applied to an endoscope processing device, at least two firmwares stored in the memory may have a mapping relationship with the scope information. Thus, the first type of processor may select a firmware matching the scope information from the at least two firmwares stored in the memory as the target firmware according to the scope information of the endoscope connected to the endoscope processing device, and query the extraction information of the target firmware, thereby providing a basis for subsequent firmware loading.

[0065] The first type of processor is communicatively connected to the second type of processor, whereby the first type of processor can transmit the determined extraction information of the target firmware to be loaded into the FPGA to the second type of processor.

[0066] Furthermore, the output end of the second type of processor is connected to the input end of the memory; the output end of the memory is respectively connected to the input end of the second type of processor and the input end of the FPGA, so that the second type of processor can transmit the extracted information of the target firmware to the memory, so that the memory outputs the target firmware related data. During this period, since the output end of the memory is also connected to the FPGA, the target firmware related data output by the memory will flow into the FPGA synchronously, thereby loading the target firmware into the FPGA. That is to say, in this embodiment, the first type of processor assigns the firmware loading task to the second type of processor, and the second type of processor pulls the target firmware related data, so that the FPGA completes the loading of the target firmware.

[0067] It should be noted that the present invention does not limit the connection between the various components. For example, the connection relationship between the first type of processor and the second type of processor can be a hard-wired connection or a wireless transmission connection. The connection pin relationship between other components is not limited here, and the type of bus connection used between them is also not limited.

[0068] A firmware loading system provided by an embodiment of the present invention comprises a first-class processor, a second-class processor, an FPGA and a memory; wherein the memory stores at least two firmwares for loading on the FPGA, and a database of the first-class processor records the extraction information of each firmware stored in the memory; thus, the first-class processor can select one of the multiple firmwares stored in the memory (i.e., the target firmware) to load into the FPGA according to actual needs, so as to realize dynamic loading of the firmware; further, the first-class processor is communicatively connected with the second-class processor, and is used to transmit the extraction information of the target firmware to be loaded into the FPGA to the second-class processor, the output end of the second-class processor is connected to the input end of the memory, and the output end of the memory is respectively connected to the input end of the second-class processor and the input end of the FPGA; thus, the second-class processor can read the target firmware from the memory according to the extraction information of the target firmware determined by the first-class processor, and complete the loading of the FPGA in the process of the memory outputting the target firmware related data. It can be seen that the firmware loading system provided by the present invention is composed of at least two types of processors to share the various subdivided steps of the firmware loading process (such as firmware query and firmware loading), and can assign corresponding subdivided steps to different types of processors according to their characteristics, making full use of the performance of different types of processors. Compared with a single processor performing all firmware loading tasks, the efficiency of firmware loading can be improved.

[0069] Based on the above embodiment, as an embodiment, the first type of processor is also connected to a memory for burning the firmware into the memory.

[0070] It is understandable that the burning here may include but is not limited to the following two situations: one is to pre-burn the relevant firmware to the memory before determining the target firmware, and the other is to re-burn the target firmware to the memory when the target firmware is not included in the firmware file library of the memory.

[0071] Based on this, the firmware burned into the memory can be managed more flexibly, so that the firmware loading system can be compatible with more firmware.

[0072] Based on the above embodiment, as an embodiment, the first type of processor is also connected to the FPGA to monitor the loading status of the FPGA.

[0073] In this way, the first type of processor can be used as a central control center to initialize and configure the FPGA and comprehensively monitor the loading status of the FPGA, which helps to improve the loading efficiency while maintaining the real-time and security of the loading.

[0074] Based on the above embodiments, as an embodiment, the first type of processor, the second type of processor, the FPGA and the memory share a clock signal.

[0075] Specifically, the firmware loading system in the present invention can be divided into the following three subsystems:

[0076] 1) A subsystem (1) is composed of a second-class processor, an FPGA, and a memory. In the subsystem, the second-class processor serves as a master device, the FPGA and the memory serve as slave devices, and the FPGA and the memory perform firmware reading and loading operations according to a clock signal provided by the second-class processor;

[0077] 2) A subsystem (2) is formed by a first-class processor and a memory, in which the first-class processor serves as a master device and the memory serves as a slave device, and the memory performs a firmware burning operation according to a clock signal provided by the first-class processor;

[0078] 3) A subsystem (3) is formed by the first type processor and the FPGA. In the subsystem, the first type processor serves as a master device and the FPGA serves as a slave device. The FPGA performs initialization configuration, feedback of firmware loading status, and other operations according to a clock signal provided by the first type processor.

[0079] The above three subsystems can achieve clock synchronization of each component through a common clock signal to ensure the correctness and reliability of the entire firmware loading system.

[0080] Likewise, the various components in the above embodiments may be communicatively connected to each other in any manner as long as the corresponding purpose can be achieved.

[0081] Further, in order to introduce the present invention in more detail, illustratively, Figure 5 A schematic diagram of the structure of another firmware loading system provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the present invention also provides another firmware loading system, which is particularly suitable for endoscope processing equipment. Therefore, the following is a detailed description mainly taking the application of the firmware loading system to endoscope processing equipment as an example.

[0082] Specifically, please refer to Figure 5 The firmware loading system includes a first-type processor 11, a second-type processor 12, a memory 13 and an FPGA 14. The first-type processor 11 is connected to the memory 13, the second-type processor 12 and the FPGA 14 respectively. The output end of the second-type processor 12 is connected to the input end of the memory 13, and the output end of the memory 13 is connected to the second-type processor 12 and the FPGA 14 respectively. In addition, the first-type processor 11, the second-type processor 12, the memory 13 and the FPGA 14 share a clock signal.

[0083] Exemplarily, the first type of processor 11 may be a multi-tasking application processor, and the second type of processor 12 may be a real-time processor. Among them, the multi-tasking application processor (Application Processor Unit, APU) is a processor that runs a multi-tasking system, such as a processor that runs a Linux system, which is designed to run various software applications, etc., to enhance interaction with users. The real-time processor (Realtime Processor Unit, RPU) is mainly used to process tasks with high real-time requirements, such as key or touch response, high-speed asynchronous communication, dimming, etc., and generally uses a microcontroller unit (Microcontroller Unit, MCU) with peripheral resources. The difference between the two processors is that the tasks they run focus on different aspects. The APU processor focuses on multi-tasking interaction with users; the RPU processor focuses on real-time execution of tasks.

[0084] In this embodiment, the first type of processor 11 mainly performs the functions of determining the target firmware, querying the firmware to extract information and burning the firmware. The processes of determining the target firmware and burning the firmware are usually accompanied by human-computer interaction (for example, in an endoscope device, the target firmware is determined based on the scope information, and the identified scope information usually needs to be presented to the user for the user to determine whether the correct endoscope has been connected; for example, in the process of firmware burning, there may also be human-computer interaction processes such as determining the user's authority and selecting the required firmware). Therefore, assigning these processes to an application processor used to execute multiple application tasks and human-computer interaction can make full use of the characteristics of the application processor.

[0085] Similarly, the firmware loading process has high real-time requirements, and assigning it to a real-time processor for execution can improve loading efficiency.

[0086] Specifically, the first type of processor 11 and the second type of processor 12 can be connected via serial communication to achieve command interaction and data transmission between the first type of processor 11 and the second type of processor 12. This embodiment does not limit the specific type of the serial port, for example, it can be a Universal Asynchronous Receiver / Transmitter (UART) serial port, or other serial ports. The UART serial port transmits data via serial communication. It performs parallel to serial data conversion at the transmitting end and serial to parallel data conversion at the receiving end. Among them, since the transmission speed, data speed and other parameters of the UART serial port are configurable and have strong versatility, it is simpler and less costly than other communication connections.

[0087] The second type processor 12, FPGA 14 and memory 13 are connected via an SPI bus, the second type processor 12 is a master device, and the FPGA 14 and memory 13 are slave devices. The output end of the second type processor 12 is connected to the input end of the memory 13 via the MOSI data line in the SPI bus, and the output end of the memory 13 is connected to the input end of the second type processor 12 and the input end of the FPGA 14 respectively via the MISO data line in the SPI bus.

[0088] like Figure 5 As shown, the output end (MOSI end) of the second type processor 12 is connected to the input end (MOSI end) of the memory 13 through the MOSI data line in the SPI bus, and the output end (MISO end) of the memory 13 is connected to the input end (MISO end) of the second type processor 12 and the input end (DIN end) of the FPGA 14 through the MISO data line in the SPI bus.

[0089] The firmware in the memory 13 is transmitted to the DIN end of the FPGA 14 via the MISO data line, so that it runs according to the firmware logic. Since both the FPGA 14 and the memory 13 are slave devices, it is impossible to actively transmit the target firmware from the memory 13 to the FPGA 14. Here, the master device (the second type of processor 12) needs to pull the extraction information from the memory 13 via the MISO signal line. At this time, the memory 13 will output the target firmware based on the extraction information, so that the target firmware can be loaded into the FPGA 14.

[0090] Furthermore, if Figure 5As shown, the first type processor 11 and the memory 13 can also be connected via an SPI bus, and the specific connection method is: the chip select signal pin SS of the first type processor 11 is connected to the chip select signal pin SS of the memory 13, which is used to select the memory for control; the first type processor 11 is connected to the input end of the memory 13 via the MOSI data line in the SPI bus, and the first type processor 11 is the master device, and the memory 13 is the slave device. Therefore, under the control of the first type processor 11, the relevant firmware can be burned into the memory 13 via the MOSI data line. Which firmware is burned is determined by the application software running on the first type processor 11 (the device will be burned when it leaves the factory), which burns the firmware data into the memory 13 through the MOSI signal line for storage, and saves the extracted information of the burned firmware in the database on the first type processor 11.

[0091] Furthermore, please continue to read Figure 5 As shown, the GPIO port of the first type processor 11 is connected to the reset port of the FPGA 14 .

[0092] Specifically, the three GPIO ports of the first type of processor 11 correspond to the PROGRAM_B port, INIT_B port and DONE port connected to FPGA14 respectively. The signal of the PROGRAM_B port is a low pulse, which is a continuous start state. The signal of the INIT_B port is the initial process of firmware loading. The signal of the DONE port is a completion mark. The first two signals are reset signals.

[0093] When firmware loading is required, the first type processor 11 sets the PROGRAM_B port of FPGA14 to a low pulse, clears the old configuration, and initializes the new configuration timing, waiting for loading the firmware configuration. FPGA14 is in the firmware configuration loading state, and when data flows into the DIN port, it will load the data according to the SCLK clock until the firmware end mark is detected.

[0094] The GPIO port of the first type processor 11 provided in the embodiment of the present invention is connected to the reset port of the FPGA 14 to monitor the firmware loading status, improve the loading efficiency, and maintain the real-time performance of the loading.

[0095] In summary, in this embodiment, the first type processor 11 and the second type processor 12 are both Master (master control device), and the memory 13 and the FPGA 14 are both Slave (slave device);

[0096] The clock SCLK is generated by the Master, and the Slave receives / responds to the clock. The Master and Slave perform full-duplex communication through MOSI and MISO according to the same clock SCLK.

[0097] In this embodiment, two types of multiplexing (clock multiplexing and data line multiplexing) are generated:

[0098] 1. Multiplexing of clock signals:

[0099] like Figure 5 As shown, the SCLK of the first type processor 11, the SCLK of the second type processor 12, the SCLK of the memory 13 and the CCLK clock signal of the FPGA 14 are all connected together (the clock can only be generated by the Master and received / responded by the Slave). The advantages of this are:

[0100] The memory 13 can receive or send data according to the clock signal given by different Masters. When the firmware is burned, the memory 13 receives firmware data according to the clock signal generated by the first type of processor 11; when the firmware is loaded, the memory 13 receives / sends data according to the clock signal generated by the second type of processor 12.

[0101] The second type of processor 12 is used to adapt to different business scenarios, taking into account the real-time performance and transmission efficiency of loading firmware, and using the clock signal generated by it; the business scenario of burning firmware focuses on multi-task logic processing, so the first type of processor 11 is used to be responsible for multi-task logic processing, such as business scenarios such as burning firmware, and the clock signal generated by it is used.

[0102] 2. Data line multiplexing:

[0103] like Figure 5 As shown, when the firmware burning service is performed, the first type processor 11 transmits the firmware data to the memory 13 through the MOSI data line for storage;

[0104] When performing the firmware loading service, the second type processor 12 transmits the extracted information such as the starting address and length of the firmware to be loaded to the memory 13 through the MOSI data line, allowing it to perform operations such as addressing and reading data.

[0105] In addition, there is another data multiplexing in the present invention, MISO data line multiplexing:

[0106] When the second-type processor 12 pulls the firmware data stream from the memory 13, the firmware data stream flows to the FPGA 14 through a bypass, which is equivalent to passively and indirectly loading the firmware to the FPGA 14. As for the address from which the data is pulled, the length of the data pulled, and the clock frequency at which the data is pulled, it is all determined by the second-type processor 12.

[0107] By using the firmware loading system provided in this embodiment, the first type of processor 11 (multi-task application processor) can pre-burn multiple firmwares into the memory 13 through the MOSI data line, and record the mapping relationship between each firmware and its extraction information in the memory in its database. When it is detected that the endoscope is connected to the endoscope device, the first type of processor 11 (multi-task application processor) identifies the body information of the endoscope and determines the corresponding target firmware, then queries the extraction information of the target firmware in the memory 13 through the database, and then transmits the extraction information of the target firmware to the second type of processor 12 (real-time processor) through the UART serial port, and sets the PROGRAM_B port of the FPGA to a low pulse through the GPIO port, clears the old configuration, and initializes the new configuration timing, so that the FPGA is in a state to be loaded. After receiving the extraction information, the second type of processor 12 (real-time processor) transmits the extraction information to the memory 13 through the MOSI data line, so that the memory 13 addresses and reads the target firmware according to the extraction information, and outputs the target firmware through the MISO data line. During this period, since the MISO data line of the memory 13 is also connected to the DIN port of the FPGA 14, the target firmware related data output from the memory 13 can be synchronously flowed into the FPGA 14, thereby loading the target firmware into the FPGA 14. After the loading of the target firmware is completed, the DONE port of the FPGA 14 sends a signal to the GPIO port of the first type processor 11 to inform the first type processor 11 that the loading of the target firmware has been completed.

[0108] Based on the above scheme, it can be seen that the firmware loading system provided by the embodiment of the present invention includes a multi-processor architecture, and divides the task of firmware loading into multiple single small tasks such as mirror type identification, firmware query, firmware burning, firmware loading, etc., and assigns tasks with high time performance requirements to the RPU real-time processor to complete, which can realize dynamic loading of firmware and improve firmware loading efficiency.

[0109] Figure 6 A flowchart of a firmware loading method for a first type of processor applied to a firmware loading system is provided in an embodiment of the present invention. Specifically, the firmware loading method can be executed by the first type of processor of the firmware loading system in any of the above embodiments. The basic composition and characteristics of the firmware loading system can be referred to the relevant description in the above embodiments, which will not be repeated here.

[0110] Specifically, the firmware loading method may include but is not limited to the following steps:

[0111] S11: Determine the target firmware to be loaded into the FPGA;

[0112] S12: Based on the database, query the extraction information of the target firmware in the memory;

[0113] S13: Transmitting the extracted information to the second type of processor, so that the second type of processor controls the memory to output the target firmware based on the extracted information, so as to load the target firmware into the FPGA.

[0114] Specifically, as an embodiment, the firmware loading system can be applied to an endoscope processing device, and in this application scenario, it is usually necessary to determine the target firmware to be loaded into the FPGA based on the connected endoscope. Therefore, in this embodiment, the specific implementation of step S11 (determining the target firmware to be loaded into the FPGA) may include:

[0115] Identifying scope information of an endoscope connected to an endoscope processing device;

[0116] The target firmware to be loaded into the FPGA is determined based on the mirror body information.

[0117] The scope information may be a specific model of the scope, etc. There is a mapping relationship between different scope information and different firmware. Therefore, the corresponding target firmware can be determined according to the identified scope information. In practical applications, the corresponding target firmware can be obtained by performing data analysis based on the model information of the scope, or the corresponding target firmware under the scope information can be determined according to the mapping relationship between the identified scope information, each scope information and each firmware.

[0118] Exemplarily, determining the corresponding target firmware according to the scope information includes:

[0119] Get the CID identification information corresponding to the scope information;

[0120] The corresponding target firmware is determined according to the CID identification information and the mapping relationship between the CID identification information and the firmware.

[0121] Specifically, the computer identification code (Coding Identification Number, CID) identification information corresponding to the scope information is obtained in order to enable the computer to correctly identify the information content and confirm the identity of each symbol therein, thereby achieving the confidentiality and security of the information. The corresponding target firmware is determined according to the CID identification information and the mapping relationship between the CID identification information and the firmware. Through the matching principle, the target firmware corresponding to the scope information can be determined based on the CID identification information and the corresponding mapping relationship.

[0122] The target firmware identification process provided by the embodiment of the present invention ensures the security of the scope information and improves the reliability of firmware loading through the mapping relationship between CID identification information and firmware. As mentioned above, the extraction information of each firmware stored in the memory is recorded in the database of the first type of processor. Through the database, the extraction information of the target firmware in the memory can be found. It should be noted here that the mapping relationship between the extraction information and the firmware can be pre-set to facilitate the search.

[0123] Furthermore, since there is a connection relationship between the first type of processor and the second type of processor, the first type of processor can transmit the extraction information of the target firmware to the second type of processor, so that after the second type of processor receives the extraction information, it can transmit it to the memory, and thus know the specific address of the target firmware in the memory. Subsequently, the target firmware corresponding to the extraction information can be pulled, and the target firmware can also be loaded into the FPGA.

[0124] A firmware loading method provided by an embodiment of the present invention is applied to a first-class processor of a firmware loading system, and the firmware loading system also includes a second-class processor, an FPGA and a memory, wherein at least two firmwares for loading on the FPGA are stored in the memory; the first-class processor may record the extraction information of each firmware stored in the memory in a database; thus, the first-class processor may select one of the multiple firmwares stored in the memory (i.e., the target firmware) to load into the FPGA according to actual needs, so as to realize dynamic loading of the firmware; further, the first-class processor is communicatively connected with the second-class processor, and is used to transmit the extraction information of the target firmware to be loaded into the FPGA to the second-class processor, the output end of the second-class processor is connected to the input end of the memory, and the output end of the memory is respectively connected to the input end of the second-class processor and the input end of the FPGA; thus, the second-class processor may read the target firmware from the memory according to the extraction information of the target firmware determined by the first-class processor, and complete the loading of the FPGA in the process of the memory outputting the target firmware related data. It can be seen that the firmware loading system provided by the present invention is composed of at least two types of processors to share the various subdivided steps of the firmware loading process (such as firmware query and firmware loading), and can assign corresponding subdivided steps to different types of processors according to their characteristics, making full use of the performance of different types of processors. Compared with a single processor performing all firmware loading tasks, the efficiency of firmware loading can be improved.

[0125] Based on the above embodiment, as an embodiment, the step S12 of querying the target firmware in the memory for extraction information based on the database includes:

[0126] Compare the target firmware with the firmware recorded in the database;

[0127] If the target firmware is identical to any firmware recorded in the database, the extraction information corresponding to the firmware identical to the target firmware is used as the extraction information of the target firmware.

[0128] Specifically, after the target firmware is identified, it is matched with the firmware recorded in the database, wherein the firmware recorded in the database is the firmware pre-stored in the memory. If the match is successful, the subsequent firmware loading operation can be entered. The matching process can be a simple comparison, or it can be matched according to multiple information of the target firmware corresponding to the matching list, which is not limited here.

[0129] In this embodiment, comparison is adopted. If the target firmware is identical to any firmware recorded in the database, it is determined that the target firmware is stored in the memory, and the extraction information of the target firmware in the memory can be further determined.

[0130] As an embodiment, the first type of processor is also connected to a memory, and when the extraction information of the target firmware in the memory cannot be queried in the database, the firmware loading method further includes:

[0131] Get the installation package containing the target firmware;

[0132] Burn the target firmware in the installation package into the storage;

[0133] The mapping relationship between the target firmware and its extracted information in the memory is recorded in the database to facilitate reloading.

[0134] Specifically, when the target firmware cannot be found in the database of the first type of processor, it means that the target firmware is not stored in the memory and needs to be re-burned into the memory. The first type of processor will obtain the installation package containing the target firmware and burn the target firmware in the installation package into the memory for reloading.

[0135] At the same time, the mapping relationship between the target firmware and its extracted information in the memory is also recorded in the database of the first type of processor. The recording process here can be to re-fill and update the database to ensure that when reloading, the database information is the information under the current latest corresponding mapping relationship.

[0136] Based on the above embodiment, as an embodiment, the first type of processor is further connected to the memory, and before determining the target firmware to be loaded into the FPGA, it also includes:

[0137] Determine the user's access rights;

[0138] Obtain the permission installation package corresponding to the usage permission;

[0139] Burn the firmware in the permission installation package into the storage;

[0140] The mapping relationship between each firmware and its extracted information in the memory is recorded in the database to facilitate firmware loading.

[0141] Specifically, the first type of processor can maintain the scope information and the firmware in the memory according to the user's usage rights, and write the scope firmware file that can be used by the user into the memory. First, obtain the user's usage rights, and the usage rights can be the software package purchased by the user. Obtain the permission installation package according to the usage rights; and pre-burn the firmware file in the permission installation package into the memory.

[0142] The burning in this embodiment includes two processes, one is the pre-burning before the first match, and the other is the re-burning when the match is unsuccessful, and the specific burning actions are the same. In the matching process between the target firmware and the extracted information in the memory, it is necessary to limit the number of burning times and the number of matching times so that the firmware loading process can run normally. If the preset number of matching times or the preset number of burning times is exceeded during the matching process, the scope information is temporarily retained and other scope information is obtained, so as not to delay the firmware loading of other scope information.

[0143] The burning and matching process in this embodiment improves the reliability and stability of firmware loading.

[0144] Based on the above embodiment, before or after the extraction information of the target firmware is transmitted to the second type processor, the firmware loading method further includes:

[0145] Control FPGA to reset the signal so that the target firmware can be loaded into FPGA.

[0146] Specifically, the loading status of the firmware is monitored in real time. Before loading the current target firmware, the data in the FPGA is reset by signal, the old configuration is cleared, and the new configuration timing is initialized, waiting for the firmware configuration to be loaded.

[0147] As an embodiment, controlling the FPGA to reset the signal includes:

[0148] Get the previous target firmware;

[0149] Monitor the loading progress of the firmware data stream of the previous target firmware until the firmware end flag of the previous target firmware is obtained, then start the reset mechanism to perform a signal reset on the FPGA.

[0150] Specifically, at the beginning of the continuous start flag PROGRAM_B signal, during this process, the file header and the check header are always checked by the first type of processor, and the reset mechanism is started through the DONE signal feedback, that is, through the firmware end flag feedback of the target firmware, to perform a signal reset on the FPGA.

[0151] The embodiment of the present invention monitors the firmware loading status through the first type of processor, which can improve the loading efficiency and maintain the real-time performance of the loading.

[0152] Figure 7 A flowchart of a firmware loading method for a second type processor of a firmware loading system provided in an embodiment of the present invention. The firmware loading method can be executed by the second type processor of the firmware loading system in any of the above embodiments. The basic composition and characteristics of the firmware loading system can be referred to the relevant description in the above embodiments, and will not be repeated here.

[0153] Specifically, if Figure 7 As shown, the firmware loading method may include but is not limited to the following steps:

[0154] S21: receiving the extraction information of the target firmware to be loaded into the FPGA in the memory transmitted by the first type processor;

[0155] S22: Control the memory to output the target firmware according to the extracted information, so as to load the target firmware into the FPGA.

[0156] For an introduction to a firmware loading method for a second type of processor applied to a firmware loading system provided by the present invention, please refer to the above method embodiment. The present invention will not be repeated here. It has the same beneficial effects as the above firmware loading method for a first type of processor applied to a firmware loading system.

[0157] Figure 8 A flowchart of another firmware loading method provided by an embodiment of the present invention, such as Figure 8 As shown, the specific process is as follows:

[0158] S31: Determine whether a scope is currently connected. If yes, proceed to step S32. If no, repeat step S31 until a scope is connected.

[0159] S32: onewire reads CID identification information to identify the mirror type;

[0160] S33: Determine the target firmware to be loaded into the FPGA according to the scope information of the identified scope type;

[0161] S34: Determine whether the target firmware matches the firmware recorded in the database, if not, proceed to step S35, if yes, proceed to step S36;

[0162] S35: The APU application processor writes the target firmware into the flash memory; return to step S34;

[0163] S36: The APU transmits the extraction information of the target firmware in the flash memory to the RPU real-time processor;

[0164] S37: The RPU real-time processor requests to read the firmware corresponding to the extracted information (ie, the target firmware) in the flash memory;

[0165] S38: The flash memory outputs the target firmware in response to the extraction information input by the RPU real-time processor, so as to flow the target firmware into the FPGA to realize firmware loading.

[0166] Among them, onewire is a wire, which is an encryption chip; flash memory refers to the memory in the present invention. APU application processor is a first type of processor, and RPU real-time processor is a second type of processor.

[0167] For an introduction to another firmware loading method provided by the present invention, please refer to the above method embodiment, and the present invention will not go into details here. It has the same beneficial effects as the above firmware loading method for the first type processor and / or the second type processor applied to the firmware loading device.

[0168] In addition, the present invention provides an endoscope processing device, including the above-mentioned firmware loading system. Please refer to the above-mentioned system embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above-mentioned firmware loading system.

[0169] Based on the above embodiment, the first type of processor is also connected to the endoscope connected to the endoscope processing device to communicate with the endoscope to obtain the endoscope body information, and determines the target firmware to be loaded into the FPGA according to the endoscope body information.

[0170] It can be understood that the first type of processor is connected to the endoscope connected to the endoscope processing device, mainly to obtain the endoscope body information through the encryption chip, and to identify the endoscope type information when a new endoscope is connected. The endoscope body information in the chip is read so that the target firmware to be loaded into the FPGA is determined in the first type of processor according to the endoscope body information.

[0171] The above describes in detail a firmware loading system, a firmware loading method for a first type of processor and a second type of processor applied to the firmware loading system, and an endoscope processing device provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0172] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A firmware loading system, characterized in that: The system comprises a first type processor, a second type processor, an FPGA and a memory, wherein the memory stores at least two firmwares for loading by the FPGA; the database of the first type processor records the extraction information of each firmware stored in the memory; The first type of processor is communicatively connected with the second type of processor, and is used to transmit the extracted information of the target firmware to be loaded into the FPGA to the second type of processor; An output terminal of the second type processor is connected to an input terminal of the memory; The output end of the memory is connected to the input end of the second type processor and the input end of the FPGA respectively, and is used to output the target firmware in response to the extraction information input by the second type processor, so as to load the target firmware into the FPGA.

2. The firmware loading system according to claim 1, characterized in that: The first type processor is also connected to the memory and is used to burn the firmware into the memory.

3. The firmware loading system according to claim 1, characterized in that: The first type of processor is also connected to the FPGA and is used to monitor the loading status of the FPGA.

4. The firmware loading system according to claim 1, characterized in that: The first type of processor, the second type of processor, the FPGA and the memory share a common clock signal.

5. The firmware loading system according to any one of claims 1 to 4, characterized in that: The number of the first type of processor and the number of the second type of processor are both one, and the first type of processor is a multi-tasking application processor, and the second type of processor is a real-time processor.

6. The firmware loading system according to claim 5, characterized in that: The second type of processor, the FPGA and the memory are connected via an SPI bus, the second type of processor is a master device, and the FPGA and the memory are slave devices; The output end of the second type processor is connected to the input end of the memory through the MOSI data line in the SPI bus, and the output end of the memory is connected to the input end of the second type processor and the input end of the FPGA respectively through the MISO data line in the SPI bus.

7. The firmware loading system according to claim 5, characterized in that: The chip select signal pin of the first type of processor is connected to the chip select signal pin of the memory; The first type of processor is connected to the input end of the memory via a MOSI data line in the SPI bus, and the first type of processor is a master device, and the memory is a slave device.

8. The firmware loading system according to claim 5, characterized in that: The GPIO port of the first type of processor is connected to the reset port of the FPGA.

9. A firmware loading method, characterized in that: The firmware loading method is applied to a first type processor of a firmware loading system, and the firmware loading system further includes a second type processor, an FPGA and a memory, wherein the memory stores at least two firmwares for loading by the FPGA; the database of the first type processor records the extraction information of each firmware stored in the memory; the first type processor is communicatively connected with the second type processor, and the output end of the second type processor is connected with the input end of the memory; the output end of the memory is respectively connected with the input end of the second type processor and the input end of the FPGA, and the firmware loading method includes: Determining target firmware to be loaded into the FPGA; Based on the database, querying the extraction information of the target firmware in the memory; The extraction information is transmitted to the second type of processor, so that the second type of processor controls the memory to output the target firmware based on the extraction information, so as to load the target firmware into the FPGA.

10. The firmware loading method according to claim 9, characterized in that: The firmware loading system is applied to an endoscope processing device, and the determining of the target firmware to be loaded into the FPGA includes: identifying scope information of an endoscope connected to the endoscope processing device; The target firmware to be loaded into the FPGA is determined according to the scope information.

11. The firmware loading method according to claim 9, characterized in that: The first type of processor is also connected to the memory, and when the extraction information of the target firmware in the memory cannot be queried in the database, the firmware loading method further includes: Obtaining an installation package containing the target firmware; Burning the target firmware in the installation package into the memory; The mapping relationship between the target firmware and its extracted information in the memory is recorded in the database to facilitate reloading.

12. The firmware loading method according to any one of claims 9 to 11, characterized in that: The first type of processor is also connected to the memory. Before determining the target firmware to be loaded into the FPGA, the firmware loading method further includes: Determine the user's access rights; Obtaining a permission installation package corresponding to the usage permission; Burning the firmware in the permission installation package into the memory; The mapping relationship between each firmware and its extracted information in the memory is recorded in the database to facilitate firmware loading.

13. A firmware loading method, characterized in that: The firmware loading method is applied to the second type processor of the firmware loading system, and the firmware loading system also includes the first type processor, FPGA and memory, wherein the memory stores at least two firmwares for the FPGA to load; the database of the first type processor records the extraction information of each firmware stored in the memory; the first type processor is communicatively connected with the second type processor, and the output end of the second type processor is connected with the input end of the memory; the output end of the memory is respectively connected with the input end of the second type processor and the input end of the FPGA, and the firmware loading method includes: receiving extraction information in the memory of target firmware to be loaded into the FPGA transmitted by the first type of processor; The memory is controlled to output the target firmware according to the extracted information, so as to load the target firmware into the FPGA.

14. An endoscope processing device, characterized in that: Comprising a firmware loading system as described in any one of claims 1 to 8.

15. The endoscope processing device according to claim 14, characterized in that: The first type of processor in the firmware loading system is also connected to the endoscope connected to the endoscope processing device for communication, so as to obtain the endoscope body information of the endoscope and determine the target firmware to be loaded into the FPGA according to the endoscope body information.

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