Memory compliance detection method, system and device based on terminal operation and medium

By implementing memory compliance detection methods in embedded terminal devices, generating memory node information registration tables and extracting thread handle tables, the problems of memory leakage, data pollution and program crashes are solved, fault location and memory management efficiency are improved, and the reliability and stability of the terminal are enhanced.

CN119961035APending Publication Date: 2025-05-09E SURFING IOT CO LTD
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Patent Information

Application Number
CN202411974329.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-30
Publication Date
2025-05-09

AI Technical Summary

Technical Problem

When writing complex programs, existing embedded terminal devices are prone to memory leakage, data pollution and program crashes, resulting in low fault location efficiency, low memory management efficiency and insufficient terminal reliability and stability.

Method used

A memory compliance detection method based on terminal runtime is provided. By generating memory node information registration table and extracting thread handle table, determining target node information and detecting based on preset node information, it improves fault location efficiency and memory management efficiency.

Benefits of technology

It improves the efficiency of fault location, improves memory management efficiency, and enhances the overall reliability and stability of the terminal.

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Abstract

The invention discloses a memory compliance detection method, system and device based on terminal runtime and a storage medium, and the method comprises the following steps: responding to a plurality of memory application operations of a first thread, and generating a memory node information registration form; the memory node information registration form comprises a plurality of memory nodes, and each memory node corresponds to one piece of memory address information; in response to a memory using operation and a memory releasing operation of the second thread, extracting a thread handle table of the second thread; determining target node information corresponding to the second thread based on the thread handle table and the memory address information; and determining a detection result based on the preset node information and the target node information. The method can be widely applied to the technical field of memory detection.
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Description

Technical Field

[0001] The present application relates to the field of memory detection technology, and in particular to a memory compliance detection method, system, device and storage medium based on terminal runtime. Background Art

[0002] When writing complex programs, existing embedded terminal devices generally use a dynamic memory allocation mechanism, which is generally used in conjunction with multithreading. Although dynamic memory is easy to use, developers are required to strictly implement the rules for applying, using, and releasing memory. If the memory that is no longer used is not released, memory leaks will occur. If a thread illegally uses the memory requested by other threads, data pollution will occur. If the memory that does not belong to itself is illegally released, the program will crash. Therefore, there are still technical problems that need to be solved in the relevant technology. Summary of the invention

[0003] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present application is to provide a memory compliance detection method, system, device and storage medium based on terminal runtime, which can improve the efficiency of fault location, improve memory management efficiency, and enhance the overall reliability and stability of the terminal.

[0005] In order to achieve the above-mentioned technical objectives, the technical solution adopted by the embodiment of the present application includes: a memory compliance detection method based on terminal runtime, comprising the following steps: in response to several memory application operations of a first thread, generating a memory node information registration table; the memory node information registration table includes several memory nodes, each of which corresponds to a memory address information; in response to the memory use operation and memory release operation of a second thread, extracting the thread handle table of the second thread; based on the thread handle table and the memory address information, determining the target node information corresponding to the second thread; based on the preset node information and the target node information, determining the detection result.

[0006] The present application can generate a memory node information registration table in response to several memory application operations of the first thread; the memory node information registration table includes several memory nodes, each of which corresponds to a memory address information; in response to the memory use operation and memory release operation of the second thread, the thread handle table of the second thread is extracted; based on the thread handle table and the memory address information, the target node information corresponding to the second thread is determined; based on the preset node information and the target node information, the detection result is determined. The present application can improve the efficiency of fault location, improve the efficiency of memory management, and enhance the overall reliability and stability of the terminal.

[0007] In addition, according to the above embodiment of the present invention, a memory compliance detection method based on terminal runtime may also have the following additional technical features:

[0008] Furthermore, in the embodiment of the present application, the first thread and the second thread are two different threads.

[0009] Further, in an embodiment of the present application, the target node information includes a target memory remaining time, the preset node information includes a first memory remaining time value and a second memory remaining time value, and the detection result is determined based on the preset node information and the target node information, including:

[0010] In the process of releasing memory, the target memory remaining time is the same as the first memory remaining time value, and the detection result is determined to be the first detection result; the first detection result is used to indicate that there is a memory leak in the process of releasing memory;

[0011] After releasing the memory, the target memory remaining time is the same as the second memory remaining time value, and the detection result is determined to be the second detection result; the first detection result is used to characterize that there is an erroneous release of the memory.

[0012] Further, in an embodiment of the present application, the preset node information includes a release node ID, the target node information includes a target node ID, and the determining of the detection result based on the preset node information and the target node information further includes:

[0013] During the memory release process, the target node ID is different from the releasing node ID, and the detection result is determined to be a third detection result; the third detection result is used to indicate that an abnormality exists in the memory release.

[0014] Further, in the embodiment of the present application, the determining of the detection result based on the preset node information and the target node information further includes:

[0015] The mirror generates a new memory node for the second thread, fills in the node information corresponding to the new memory node, and simultaneously releases the memory of the new memory node.

[0016] Further, in an embodiment of the present application, the first memory remaining time value is a binary number 0, and the second memory remaining time value is a binary number 0xFFFFFFF.

[0017] Further, in the embodiment of the present application, determining the target node information corresponding to the second thread based on the thread handle table and the memory address information includes:

[0018] Based on the thread handle table, determining memory releaser information of the second thread;

[0019] Determine target memory address information according to the memory releaser information of the second thread;

[0020] A node in the memory node information registration table whose memory address information is the same as the target memory address information is determined as a target node, and target node information corresponding to the target node is obtained.

[0021] On the other hand, an embodiment of the present application further provides a memory compliance detection system based on terminal runtime, including:

[0022] A first processing unit is used to generate a memory node information registration table in response to a plurality of memory application operations of the first thread; the memory node information registration table includes a plurality of memory nodes, each of which corresponds to a memory address information;

[0023] A second processing unit, configured to extract a thread handle table of the second thread in response to a memory use operation and a memory release operation of the second thread;

[0024] a third processing unit, configured to determine target node information corresponding to the second thread based on the thread handle table and the memory address information;

[0025] The fourth processing unit is used to determine the detection result based on the preset node information and the target node information.

[0026] On the other hand, the present application also provides a memory compliance detection device based on terminal runtime, including:

[0027] at least one processor;

[0028] at least one memory for storing at least one program;

[0029] When the at least one program is executed by the at least one processor, the at least one processor implements a memory compliance detection method based on terminal operation as described in any one of the inventive contents.

[0030] In addition, the present application also provides a computer-readable storage medium, which stores processor-executable instructions. When the processor-executable instructions are executed by the processor, they are used to execute a memory compliance detection method based on terminal runtime as described in any of the above items.

[0031] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0032] The present application can generate a memory node information registration table in response to several memory application operations of the first thread; the memory node information registration table includes several memory nodes, each of which corresponds to a memory address information; in response to the memory use operation and memory release operation of the second thread, the thread handle table of the second thread is extracted; based on the thread handle table and the memory address information, the target node information corresponding to the second thread is determined; based on the preset node information and the target node information, the detection result is determined. The present application can improve the efficiency of fault location, improve the efficiency of memory management, and enhance the overall reliability and stability of the terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the steps of a memory compliance detection method based on terminal runtime in a specific embodiment of the present invention;

[0034] Figure 2 A schematic diagram of the steps of a memory compliance detection method based on terminal runtime in another specific embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of information of a memory node in another specific embodiment of the present invention;

[0036] Figure 4 A schematic diagram of the steps of a memory compliance detection method based on terminal runtime in another specific embodiment of the present invention;

[0037] Figure 5 A schematic diagram of the steps of a memory compliance detection method based on terminal runtime in another specific embodiment of the present invention;

[0038] Figure 6 A schematic diagram of the steps of a memory compliance detection method based on terminal runtime in another specific embodiment of the present invention;

[0039] Figure 7 A schematic diagram of the steps of a memory compliance detection method based on terminal runtime in a specific embodiment of the present invention;

[0040] Figure 8 It is a structural schematic diagram of a memory compliance detection system based on terminal runtime in another specific embodiment of the present invention;

[0041] Fig. 9 It is a structural schematic diagram of a memory compliance detection device based on terminal runtime in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following describes in detail the embodiments of the present invention in conjunction with the accompanying drawings to illustrate the principles and processes of the terminal runtime-based memory compliance detection method, system, device and storage medium in the embodiments of the present invention.

[0043] When writing complex programs, existing embedded terminal devices generally use a dynamic memory allocation mechanism, which is generally used in conjunction with multithreading. Although dynamic memory is easy to use, developers are required to strictly implement the rules for applying, using, and releasing memory. If the memory that is no longer used is not released, memory leaks will occur. If a thread illegally uses the memory requested by other threads, data pollution will occur. If the memory that does not belong to itself is illegally released, the program will crash. Therefore, there are still technical problems that need to be solved in the relevant technology.

[0044] In view of the above-mentioned defects of the prior art, Figure 1 , this application provides a memory compliance detection method based on terminal runtime. Figure 1 In the method, the method may include the following steps S101-S104.

[0045] S101. In response to a plurality of memory application operations of a first thread, a memory node information registration table is generated; the memory node information registration table includes a plurality of memory nodes, and each memory node corresponds to a memory address information.

[0046] S102: In response to a memory use operation and a memory release operation of the second thread, extract a thread handle table of the second thread.

[0047] S103: Determine target node information corresponding to the second thread based on the thread handle table and the memory address information.

[0048] S104: Determine a detection result based on preset node information and target node information.

[0049] In some feasible embodiments of the present application, the first processing unit of the processor may establish a wired connection or a wireless connection with the second processing unit. The first processing unit may generate a memory node information registration table in response to several memory application operations of the first thread. Among them, each application may correspond to a memory node information, so that a registration table with multiple memory nodes can be formed in the end, and each memory node may correspond to a memory node information. Memory node information includes but is not limited to node address, node ID, memory application point information, time information, memory release point information, memory releaser information, etc. The memory node information registration table includes several memory nodes, and each memory node corresponds to a memory address information. In response to the memory use operation and memory release operation of the second thread, the processor can extract the thread handle table of the second thread. Based on the thread handle table and the memory address information, the processor can determine the target node information corresponding to the second thread.

[0050] It should be noted that the above-mentioned wired connection method may include a connection between a mobile device and a processing module, and may also include a connection between a processing module and a hardware device, as well as a wired connection between other devices currently known or to be developed in the future and the processing module; and the above-mentioned wireless connection method may include but is not limited to 3G / 4G / 5G connection, WiFi connection, Bluetooth connection, WiMAX connection, Zigbee connection, UWB (Ultra Wide Band) connection, and other wireless connection methods currently known or to be developed in the future.

[0051] The present application can generate a memory node information registration table in response to several memory application operations of the first thread; the memory node information registration table includes several memory nodes, each memory node corresponds to a memory address information; in response to the memory use operation and memory release operation of the second thread, the thread handle table of the second thread is extracted; based on the thread handle table and the memory address information, the target node information corresponding to the second thread is determined; based on the preset node information and the target node information, the detection result is determined. The present application can improve the efficiency of fault location, improve the efficiency of memory management, and enhance the overall reliability and stability of the terminal.

[0052] In some feasible embodiments of the present application, the target node information includes the target memory remaining time, and the preset node information includes the first memory remaining time value and the second memory remaining time value. Based on the preset node information and the target node information, the step of determining the detection result includes:

[0053] During the memory release process, the target memory remaining time is the same as the first memory remaining time value, and the detection result is determined to be the first detection result; the first detection result is used to characterize that there is a memory leak during the memory release process.

[0054] After the memory is released, the target memory remaining time is the same as the second memory remaining time value, and the detection result is determined to be the second detection result; the first detection result is used to characterize that there is an erroneous release of the memory.

[0055] In some feasible embodiments of the present application, the preset node information may include a releasing node ID, and the target node information may include a target node ID. Based on the preset node information and the target node information, the step of determining the detection result may also include:

[0056] During the memory release process, the target node ID is different from the releasing node ID, and the detection result is determined to be the third detection result; the third detection result is used to characterize that there is an abnormality in the memory release.

[0057] In some feasible embodiments of the present application, based on the preset node information and the target node information, the step of determining the detection result may also include:

[0058] The mirror generates a new memory node for the second thread, fills in the node information corresponding to the new memory node, and simultaneously releases the memory of the new memory node.

[0059] In some feasible embodiments of the present application, the first memory remaining time value is a binary number 0, and the second memory remaining time value is a binary number 0xFFFFFFF.

[0060] In some feasible embodiments of the present application, the step of determining the target node information corresponding to the second thread based on the thread handle table and the memory address information may include:

[0061] Determine memory releaser information of the second thread based on the thread handle table;

[0062] Determine target memory address information according to the memory releaser information of the second thread;

[0063] A node in the memory node information registration table whose memory address information is the same as the target memory address information is determined as a target node, and target node information corresponding to the target node is obtained.

[0064] The following is combined with Figure 2 To Attachment Figure 7 The principle of this application is explained.

[0065] The present invention proposes a memory compliance detection method and device based on the terminal runtime for the IoT terminal architecture solution. The method monitors the legitimacy of the memory usage of the code written by the developer in real time. Once the unreasonable memory usage behavior is detected, it will take effective means to notify the user, greatly improving the efficiency of fault location. The solution mainly includes the following contents: memory application registration, memory release registration, and memory leak detection.

[0066] First, the overall architecture of this embodiment is described. Figure 2 As shown, the present invention is a real-time monitoring of memory behavior based on runtime based on the heap memory management interface of the lower-level system and the upper-level thread interface. The system will use the basic information written by the user when applying for memory to analyze and evaluate the node information in real time during the memory usage and release phases. When applying for memory, the thread does not directly access the system heap memory, but obtains and releases memory through the middle layer (the solution proposed by the present invention), which is imperceptible to the user.

[0067] Memory application stage: It will automatically record the information of the application point (line number, function name, file name), time information (application time, release time, memory estimated time, etc.), thread whitelist information (specified threads can access or release), and the memory address information actually used by the user. The user only needs to configure the estimated memory usage time and thread whitelist.

[0068] Memory usage phase: It will detect the memory usage time in real time, whether the current thread can operate on the memory, etc. If it times out or triggers an illegal operation, a prompt warning message will be issued.

[0069] Memory release phase: whether the current thread has the power to release, if so, the current thread information will be registered in the memory node information, saved and written to the flash or file, and then the node information memory will be released and the node will be deleted.

[0070] Next, the memory node information of this embodiment is described. When applying for memory, a table will be used to record the information registered by the thread when applying for memory, mainly including thread information, memory application point information, time information, whitelist and release information, and memory allocation address. Figure 3 The following is an example of filling in the specific content of each node information:

[0071] Node address: stores the location information of the node in the linked list to facilitate quick access to previous and next memory nodes.

[0072] Node ID: Assign a unique identifier to the memory application node to facilitate tracking and identifying specific memory application records.

[0073] Memory application point information: application thread handle, application thread name, application line number, application function name, application file name and other information, used to record the code location and creator.

[0074] Time information: memory application time, remaining memory usage time, and memory release time, which are used to record memory access time information and assess the possibility of memory leakage or illegal use.

[0075] Memory release point information: release thread handle, release thread name, release line number, release function name, release file name and other information, used to record the code release location and releaser information.

[0076] Memory releaser information: stores thread index table information that has permission to release memory, and is used to check for illegal operations.

[0077] Warning information: Memory leaks, access warnings, and other information to inform users that the memory has memory compliance risks.

[0078] Requested memory address: contains the memory address of the actual memory allocation, so as to facilitate direct access during subsequent operations and memory release.

[0079] Then, the application information registration of the memory of this application is described. Figure 4 The figure shows the memory application process. The memory application stage requires registration of application point information (line number, function name, file name), time information (application time, remaining memory time, etc.), thread whitelist information (specified threads can access or release), and memory address information actually used by the user. The user only needs to configure the estimated memory usage time and thread whitelist when calling the interface.

[0080] The application point information mainly records the location where the memory application occurs, which is mainly line number, function name, file name and other information in the code. In addition to this information, the creator information is also recorded, which is mainly the basic information of the thread (handle and thread name). When the memory is illegally accessed, the user will be notified where the illegally used memory was created by which thread.

[0081] The application point time information mainly records the application start time and end time, as well as the remaining memory time. These two times will be used to constrain the compliance use of memory and to determine illegal operations.

[0082] The memory releaser information mainly records which threads can release memory and reclaim memory resources. For example, when a thread created by thread A is only configured to release memory by thread A, and thread B tries to use memory, a memory usage violation warning will be populated, indicating that the memory may be used illegally.

[0083] Next, the memory compliance detection-time point information of this embodiment is described.

[0084] The application point time information mainly records the application start time and end time, as well as the remaining memory time. The start time and remaining time are determined during the memory application phase. Next, let's talk about the memory release time. When the memory is released by the thread, the release point time will be recorded in the memory node. Based on the above three time information, you can warn of memory leaks or erroneous releases. The following is an analysis and warning of several scenarios. Figure 5 shown.

[0085] Memory leak detection: When the memory usage time is used up, it will be judged that the memory is not released within the specified time, and a memory leak warning will be issued. The warning information will be filled in the node information, and the node information will be saved in Flash or a file. When the memory is released within the specified time, it will be judged that the memory is released normally, and the node information will be released at the same time.

[0086] Memory violation release detection: When the remaining time is filled with 0xFFFFFFFF in the memory application phase, it is determined that the memory will not be released by any thread during its life cycle. If a thread attempts to release memory during the memory usage phase, it will be determined as illegal memory release, and a memory leak warning will be issued. The warning information will be filled in the node information, and the node information will be saved in Flash or a file.

[0087] The memory compliance detection of this embodiment - memory releaser management is described. The memory releaser information unit records which threads can release the memory and which threads cannot release it. First, the storage format of the releaser information is described. Its format uses a 128-bit storage space, which can store up to 128 threads, corresponding to bit0 to bit127. For example, if thread 0 has the release authority, bit0 is set to 1, otherwise it is 0. Threads 0 to 127 are thread index numbers, and the actual thread handle information is stored in the thread handle table. The thread index number is the index value of the thread handle table. In this way, the thread index value can be indirectly stored by storing the bit value, and finally the real thread handle information is obtained through the thread index value. Figure 6 shown.

[0088] The following example illustrates how memory releaser information is used for memory compliance detection: When thread A applies for memory, a memory node information is generated synchronously. This node information records a lot of information, including releaser information (thread index information), which specifies which threads can release the memory (for example: thread B, thread C, or other threads different from thread A). When the memory application is successful, when thread C tries to release the memory, it will check whether thread C is in the thread index table. If not, the exception handling process will be triggered. First, a memory node will be mirrored, and then the release point information (C thread information, release time, release line number, function name, file name, etc.), warning information, etc. will be filled in. The mirror node information is stored in flash or a file, and the mirror node is released synchronously. For example Figure 7 shown.

[0089] In summary, this application has the following advantages:

[0090] 1. This application implements memory compliance check based on the specified releaser and bitmap+index storage method. Based on the time monument mechanism and information registration, memory compliance check is implemented by restricting the usage time.

[0091] 2. This application can improve the standardized use of memory: constrain developers to use memory in a standardized manner and detect the standardization of memory usage in real time.

[0092] 3. This application can accelerate fault location: real-time operation detection, reduce troubleshooting time, and improve development efficiency.

[0093] 4. This application can enhance system reliability: accurate location of memory leaks improves system stability and reduces the risk of crashes.

[0094] In addition, refer to Figure 8 ,and Figure 1 Corresponding to the method, an embodiment of the present application also provides a memory compliance detection system based on terminal runtime. The system may include a first processing unit 1001, a second processing unit 1002, a third processing unit 1003 and a fourth processing unit 1004. Among them, the first processing unit 1001 can be used to generate a memory node information registration table in response to several memory application operations of the first thread; the memory node information registration table includes several memory nodes, and each memory node corresponds to a memory address information. The second processing unit 1002 can be used to extract the thread handle table of the second thread in response to the memory use operation and the memory release operation of the second thread. The third processing unit 1003 can be used to determine the target node information corresponding to the second thread based on the thread handle table and the memory address information. The fourth processing unit 1004 can be used to determine the detection result based on the preset node information and the target node information.

[0095] The present application can generate a memory node information registration table in response to several memory application operations of the first thread; the memory node information registration table includes several memory nodes, each of which corresponds to a memory address information; in response to the memory use operation and memory release operation of the second thread, the thread handle table of the second thread is extracted; based on the thread handle table and the memory address information, the target node information corresponding to the second thread is determined; based on the preset node information and the target node information, the detection result is determined. The present application can improve the efficiency of fault location, improve the efficiency of memory management, and enhance the overall reliability and stability of the terminal.

[0096] It should be noted that the first processing unit may be any integrated circuit unit or microprocessor unit obtained by integrating a chip having a processing function and its peripheral circuits through existing integration technology. The first processing unit and the second processing unit may also be any integrated circuit module or microprocessor module obtained by integrating a chip having a processing function and its peripheral circuits through existing integration technology. The first processing unit and the second processing unit may also include one or more memories.

[0097] This embodiment can generate memory node information in response to the memory application operation of the first thread, the memory node information includes thread index information and memory remaining time, the thread index information corresponds to a target thread table, the target thread table includes several target threads that can release memory; when the memory application is successful and the memory remaining time is configured as the first value, the second thread executes the memory release, and determines whether the second thread is in the target thread table; if so, directly releases the memory node information. This application can improve the efficiency of fault location, improve memory management efficiency, and enhance the overall reliability and stability of the terminal.

[0098] and Figure 1 Corresponding to the method, the embodiment of the present application also provides a memory compliance detection device based on terminal runtime, and its specific structure can be referred to Fig. 9 ,include:

[0099] at least one processor 1011;

[0100] At least one memory 1012, used to store at least one program;

[0101] When the at least one program is executed by the at least one processor, the at least one processor implements the memory compliance detection method based on terminal runtime.

[0102] The contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0103] and Figure 1 Corresponding to the method, an embodiment of the present application further provides a computer-readable storage medium, which stores processor-executable instructions, and the processor-executable instructions are used to execute the memory compliance detection method based on terminal runtime when executed by the processor.

[0104] The contents of the above-mentioned memory compliance detection method embodiment based on terminal runtime are all applicable to the present storage medium embodiment. The functions specifically implemented by the present storage medium embodiment are the same as those of the above-mentioned memory compliance detection method embodiment based on terminal runtime, and the beneficial effects achieved are also the same as those achieved by the above-mentioned memory compliance detection method embodiment based on terminal runtime.

[0105] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the application is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are expected, wherein the order of various operations is changed and the sub-operation described as a part of a larger operation is performed independently.

[0106] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present application. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional techniques of the engineer. Therefore, those skilled in the art can implement the present application set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the attached claims and their equivalents.

[0107] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several programs to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0108] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution systems, devices or apparatuses. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution systems, devices or apparatuses.

[0109] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0110] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0111] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0112] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0113] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A memory compliance detection method based on terminal runtime, characterized in that: The following steps are involved: In response to a plurality of memory application operations of the first thread, a memory node information registration table is generated; The memory node information registration table includes a plurality of memory nodes, each of which corresponds to a memory address information; In response to a memory use operation and a memory release operation of the second thread, extracting a thread handle table of the second thread; Determine the target node information corresponding to the second thread based on the thread handle table and the memory address information; Based on the preset node information and the target node information, a detection result is determined.

2. According to claim 1, a memory compliance detection method based on terminal runtime is characterized in that: The first thread and the second thread are two different threads.

3. According to claim 1, a memory compliance detection method based on terminal runtime is characterized in that: The target node information includes a target memory remaining time, the preset node information includes a first memory remaining time value and a second memory remaining time value, and determining the detection result based on the preset node information and the target node information includes: In the process of releasing memory, the target memory remaining time is the same as the first memory remaining time value, and the detection result is determined to be the first detection result; the first detection result is used to indicate that there is a memory leak in the process of releasing memory; After releasing the memory, the target memory remaining time is the same as the second memory remaining time value, and the detection result is determined to be the second detection result; the first detection result is used to characterize that there is an erroneous release of the memory.

4. According to claim 3, a memory compliance detection method based on terminal runtime is characterized in that: The preset node information includes a releasing node ID, the target node information includes a target node ID, and the determining of the detection result based on the preset node information and the target node information further includes: During the memory release process, the target node ID is different from the releasing node ID, and the detection result is determined to be a third detection result; the third detection result is used to indicate that an abnormality exists in the memory release.

5. According to claim 4, a memory compliance detection method based on terminal runtime is characterized in that: The determining of the detection result based on the preset node information and the target node information further includes: The mirror generates a new memory node for the second thread, fills in the node information corresponding to the new memory node, and simultaneously releases the memory of the new memory node.

6. According to claim 1, a memory compliance detection method based on terminal runtime is characterized in that: The first memory remaining time value is a binary number 0, and the second memory remaining time value is a binary number 0xFFFFFFF.

7. According to claim 1, a memory compliance detection method based on terminal runtime is characterized in that: The determining, based on the thread handle table and the memory address information, target node information corresponding to the second thread includes: Based on the thread handle table, determining memory releaser information of the second thread; Determine target memory address information according to the memory releaser information of the second thread; A node in the memory node information registration table whose memory address information is the same as the target memory address information is determined as a target node, and target node information corresponding to the target node is obtained.

8. A memory compliance detection system based on terminal runtime, characterized in that: include: A first processing unit, configured to generate a memory node information registration table in response to a plurality of memory application operations of a first thread; The memory node information registration table includes a plurality of memory nodes, each of which corresponds to a memory address information; A second processing unit, configured to extract a thread handle table of the second thread in response to a memory use operation and a memory release operation of the second thread; a third processing unit, configured to determine target node information corresponding to the second thread based on the thread handle table and the memory address information; The fourth processing unit is used to determine the detection result based on the preset node information and the target node information.

9. A memory compliance detection device based on terminal runtime, characterized in that include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the memory compliance detection method based on terminal operation as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing instructions executable by a processor, characterized in that: The processor-executable instructions are used to execute a memory compliance detection method based on terminal runtime as described in any one of claims 1-7 when executed by the processor.