Synchronous communication method and device of asynchronous clock and test method based on asynchronous clock communication

Abstract

The embodiment of the invention provides a synchronous communication method and device of an asynchronous clock and a test method based on asynchronous clock communication. The method comprises the following steps: acquiring a first clock and a second clock provided by a test machine; according to the receiving frequency obtained by the first clock, receiving communication data sent by the at least one chip to be detected according to the sending frequency corresponding to the own chip clock; wherein the receiving frequency is higher than the transmitting frequency; and writing the communication data into the cache queue units in one-to-one correspondence with the corresponding chips to be detected, outputting the communication data of the output positions in the cache queue units according to an output frequency which is obtained based on a second clock and is synchronized with the input frequency of the test machine, and forming a data signal sent to the test machine. Due to the existence of the cache queue unit, the receiving end is allowed to store data under the condition that the receiving end is not influenced by a sending end, namely a clock, and then the data are output according to the output frequency stably synchronized with the input frequency of the testing machine, so that long-term accumulative errors caused by clock skew are avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a synchronous communication method and device of an asynchronous clock, and a test method based on asynchronous clock communication. Background Art

[0002] In modern electronic systems, efficient data exchange is required between different components or devices, which usually relies on synchronous or asynchronous communication mechanisms. However, in a test environment, especially when multiple DUTs (Devices Under Test) are tested in parallel, each chip may have a different internal clock frequency, and these clock frequencies are inconsistent with the reference clock provided by the tester, which leads to synchronization problems that may occur during data transmission.

[0003] In asynchronous clock communication in the related art, the transmitter and receiver do not share the same clock source, but work independently at different clock frequencies. When the receiver tries to sample data from the transmitter, if its sampling window is not accurately aligned with the data transmission window of the transmitter, it may cause misreading of data bits. Especially in high-speed communication environments, even small time deviations may seriously affect the accuracy of data. In an asynchronous environment, if the transmission speed is faster than the output speed for a long time, the buffer will overflow; conversely, if the output speed is faster than the transmission speed, the buffer may be idle, that is, underflow. Both situations will affect the stability and reliability of the system. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present disclosure is to provide a synchronous communication method and device of an asynchronous clock and a test method based on asynchronous clock communication to solve the problems in the related art.

[0005] A first aspect of the present disclosure provides a synchronous communication method of an asynchronous clock, comprising:

[0006] Obtain a first clock and a second clock provided by the test machine;

[0007] According to the receiving frequency obtained by the first clock, receiving the communication data sent by at least one chip to be detected according to the sending frequency corresponding to the chip clock of itself; wherein the receiving frequency is higher than the sending frequency;

[0008] The communication data is written into the cache queue units corresponding to each chip to be tested, and the communication data at the output position in each cache queue unit is output according to the output frequency obtained based on the second clock and synchronized with the input frequency of the test machine, so as to respectively form each data signal sent to the test machine; wherein the output frequency is lower than the sending frequency.

[0009] In an embodiment of the first aspect, before receiving data sent by at least one chip to be detected at a sending frequency corresponding to its own chip clock according to the receiving frequency obtained by the first clock, the step further includes:

[0010] Receiving the communication data sent at the sending frequency through a first-stage trigger, and outputting the communication data after performing a first-stage processing on the communication data according to the edge of the first clock;

[0011] The communication data after the first-stage processing is subjected to second-stage processing by the second-stage trigger according to the next edge of the first clock, so as to obtain steady-state communication data and then output it to the cache queue unit.

[0012] In an embodiment of the first aspect, the cache queue unit includes a first cache queue and a second cache queue, and the step of writing the communication data to the cache queue unit corresponding to each chip to be detected includes:

[0013] According to the transmission frequency of the chip to be detected, the corresponding communication data is sequentially written into the first cache queue;

[0014] The communication data is sequentially taken out from the first cache queue to the second cache queue according to the receiving frequency, so as to be output to the test machine according to the output frequency.

[0015] In an embodiment of the first aspect, it also includes: synchronously combining each channel of communication data according to the output frequency to form a combined data signal, and sending it to the test machine; wherein each channel of communication data in a combined data signal is compared with a preset safety value or compared with each other to determine an abnormal chip.

[0016] A second aspect of the present disclosure provides a synchronous communication device of an asynchronous clock, comprising:

[0017] A clock unit, used for obtaining a first clock and a second clock provided by the test machine;

[0018] A receiving unit, configured to receive communication data sent by at least one chip to be detected at a sending frequency corresponding to its own chip clock at a receiving frequency obtained based on the first clock; wherein the receiving frequency is higher than the sending frequency;

[0019] A write unit is used to write the communication data to the cache queue units corresponding to each chip to be tested, and output the communication data at the output position in each cache queue unit according to the output frequency obtained based on the second clock and synchronized with the input frequency of the test machine, so as to respectively form each data signal sent to the test machine; wherein the output frequency is lower than the sending frequency.

[0020] In an embodiment of the second aspect, the asynchronous clock synchronous communication device is integrated in a probe card for contacting electrical contact points on the chip.

[0021] In an embodiment of the second aspect, the cache queue unit includes:

[0022] A first cache module, used for writing corresponding communication data into the first cache module in sequence according to the transmission frequency of the chip to be detected;

[0023] The second buffer module is used to sequentially fetch the communication data from the first buffer module to the second buffer module according to the receiving frequency, so as to output the communication data to the test machine according to the output frequency.

[0024] A third aspect of the present disclosure provides a method for testing asynchronous clock communication, which includes:

[0025] Synchronizing the communication data of the chip to be tested to the clock domain of the tester by the synchronous communication method as described in any one of claims 1 to 4;

[0026] The test machine generates detection data based on the received communication data

[0027] The detection data is compared with a preset safety value to obtain the status of the corresponding chip to be detected.

[0028] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein program instructions are stored, and the program instructions are executed to perform any of the above-mentioned synchronous communication methods.

[0029] A fifth aspect of the present disclosure provides a computer program product, which includes: program instructions for executing any of the synchronous communication methods described above.

[0030] The beneficial effects of the present disclosure are as follows: the existence of the cache queue unit allows the receiving end to store data without being affected by the sending end, i.e., the clock, and then output it at an output frequency that is stably synchronized with the input frequency of the test machine, thus avoiding long-term cumulative errors caused by clock offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic flow chart showing a synchronous communication method of an asynchronous clock in an embodiment of the present disclosure.

[0032] Figure 2 A schematic diagram of a process for reducing metastable state in a synchronous communication method of an asynchronous clock according to an embodiment of the present disclosure is shown.

[0033] Figure 3A schematic diagram of a process for reducing metastable state in a synchronous communication method of an asynchronous clock in yet another embodiment of the present disclosure is shown.

[0034] Figure 4 A schematic diagram showing the structure of a synchronous communication device in an embodiment of the present disclosure is shown.

[0035] Figure 5 A schematic diagram showing the structure of a cache queue unit in a synchronous communication device according to an embodiment of the present disclosure is shown.

[0036] Figure 6 A flowchart of a testing method based on asynchronous clock communication in an embodiment of the present disclosure is shown.

[0037] Figure 7 A schematic diagram of a top view of the structure in which a synchronous communication device is integrated into a probe card in one embodiment of the present disclosure is shown.

[0038] Figure 8 A schematic diagram of a side view of the structure in which a synchronous communication device is integrated into a probe card in one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0040] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0041] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.

[0043] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0044] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0045] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0046] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0047] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.

[0048] In the prior art, in an asynchronous environment, if the transmission speed is faster than the output speed for a long time, the buffer will overflow; conversely, if the output speed is faster than the transmission speed, the buffer may be idle, i.e., underflow. Both situations will affect the stability and reliability of the system. Since the transmitter and receiver use independent clock sources, even if the nominal frequencies of the two are the same, there may be slight frequency differences (i.e., offsets) and short-term frequency fluctuations (i.e., jitter) during actual operation. These factors will cause the data bit boundaries to drift at the receiver, which may cause data errors.

[0049] The present disclosure provides a synchronous communication method of an asynchronous clock, uses a high-frequency first clock for data reception, and ensures that each received data can enter the cache queue accurately without losing or misreading data bits due to misalignment between the receiving window and the sending window. By setting the output frequency to be lower than the sending frequency, it is ensured that there is enough time in the cache queue to process newly arrived data, and old data can be cleared in time to maintain the smooth operation of the system. In addition, an independent cache queue unit is set for each chip to be detected as a data buffer, so that even if there is clock offset and clock jitter, it will not directly affect the final data transmission quality.

[0050] exist Figure 1 In an embodiment, the synchronous communication method includes:

[0051] Step A1: Obtain a first clock and a second clock provided by a test machine.

[0052] Step A2: according to the receiving frequency obtained by the first clock, receiving the communication data sent by at least one chip to be detected according to the sending frequency corresponding to its own chip clock; wherein the receiving frequency is higher than the sending frequency.

[0053] Step A3: Write the communication data to the cache queue unit corresponding to each chip to be tested, and output the communication data at the output position in each cache queue unit according to the output frequency obtained based on the second clock and synchronized with the input frequency of the test machine, so as to respectively form each data signal sent to the test machine; wherein the output frequency is lower than the sending frequency.

[0054] Specifically, in some embodiments, in a multi-chip parallel test environment, the tester needs to test multiple chips to be tested at the same time, and each chip to be tested has its own chip clock frequency, but they are not consistent with the reference clock provided by the tester. The tester provides two sets of clock signals: one set is the first clock for receiving data, and its clock frequency is higher than the highest transmission frequency of all chips to be tested; when the clock frequency of the receiving end (i.e., the frequency of the first clock) is higher than the clock frequency of the transmitting end (i.e., the transmission frequency of the chip to be tested), this means that in each transmission cycle, the receiving end will have more sampling opportunities, i.e., a high sampling rate, thereby ensuring that the transmission data of the chip to be tested will not be lost.

[0055] In addition, this high sampling rate ensures that even if the data bit boundaries on the transmitter drift slightly due to clock jitter or offset, the receiver can still reliably detect the changes in these data bits. In other words, high-frequency reception helps to more accurately capture the data changes from the transmitter, thereby reducing the risk of data misreading due to sampling window mismatch. If the receiving frequency is lower than the transmitting frequency, even a small clock deviation may accumulate into a large error, ultimately resulting in data loss or error.

[0056] Another set of clock signals is used to provide a second clock for outputting data from the cache queue unit. Its frequency is lower than the lowest transmission frequency of all chips to be detected, which can ensure that the data in the cache queue has enough residence time, thereby avoiding the situation where the data is read away before being completely written due to the output speed being too fast. Considering that each chip to be detected may have a different transmission frequency, and even in extreme cases, the transmission frequency of some chips to be detected may be very low. By setting an output frequency lower than the lowest transmission frequency of all chips to be detected, it can be ensured that even the slowest transmitted data can be reliably output and processed, without causing data loss or misreading due to the output speed being too fast.

[0057] Optionally, in Figure 2 In an embodiment, before receiving data sent by at least one chip to be detected at a sending frequency corresponding to its own chip clock according to the receiving frequency obtained by the first clock, the method further includes:

[0058] Step A4: receiving the communication data sent at the sending frequency through the first-stage trigger, and performing the first-stage processing on the communication data according to the edge of the first clock and then outputting the processing.

[0059] Step A5: performing second-level processing on the communication data after the first-level processing according to the next edge of the first clock through the second-level trigger to obtain steady-state communication data and then output it to the cache queue unit.

[0060] Specifically, when data is transmitted between asynchronous clock domains, the frequency and phase between the two clock domains are not synchronized, which may cause the trigger at the receiving end to enter an uncertain state, the so-called "metastable state". In order to reduce or even eliminate this metastable phenomenon, a two-stage trigger (or a two-stage synchronizer) is a common solution. In some embodiments, the first-stage trigger receives the first clock and samples the clock signal from each chip to be detected at its edge to generate a preliminarily stable first primary clock signal, effectively reducing the risk of metastable states. The first primary clock signal is sampled twice at the next edge of the first clock (usually a different edge from that used by the first-stage trigger, for example, if the first stage uses a rising edge, the falling edge is used here), further eliminating the metastable state, and finally outputting a nearly stable clock signal to be detected, so that the second-stage trigger can reliably capture the correct logic level (0 or 1).

[0061] Optionally, in addition to eliminating the metastable state by means of a double-stage trigger in the above embodiment, the metastable state may also be eliminated by the following method. Figure 3 In an embodiment, the cache queue unit includes a first cache queue and a second cache queue, and the step of writing the communication data to the cache queue unit corresponding to each chip to be detected includes:

[0062] Step A31: According to the transmission frequency of the chip to be detected, the corresponding communication data is written into the first cache queue in sequence.

[0063] Step A32: taking the communication data out of the first buffer queue in sequence according to the receiving frequency and putting it into the second buffer queue, so as to be output to the test machine according to the output frequency.

[0064] Specifically, in some embodiments, two independent cache queues (a first cache queue and a second cache queue) are set to gradually transfer data from one clock domain to another clock domain, so as to reduce the risk of metastability caused by direct cross-clock domain transmission.

[0065] In some embodiments, metastable states can also be reduced by presetting a handshake protocol. By establishing a set of handshake protocols between the transmitter and the receiver, it is ensured that each data transmission is performed after both parties are ready, thereby avoiding metastable state problems caused by clock asynchrony.

[0066] Optionally, it also includes: synchronously combining the communication data of each channel according to the output frequency to form a combined data signal, and sending it to the tester; wherein each communication data in a combined data signal is compared with a preset safety value or compared with each other to determine the abnormal chip, so the tester will not miss the communication data sent by the chip to be tested. By operating at a lower clock rate, the tester can check whether there is new data arriving multiple times within the clock cycle of each chip to be tested. This increases the possibility of capturing all incoming data, especially for high-speed transmission data streams.

[0067] In some embodiments, each channel of communication data can be synchronously combined according to the output frequency to form a combined data signal, and sent to the test machine. Each channel of communication data in a combined data signal is compared with a preset safety value or compared with each other to determine the abnormal chip. For example, 10 identical chips (such as similar) are tested to obtain 10 channels of communication data. If a channel of communication data is abnormal compared to the preset safety value, the corresponding chip can be considered abnormal. What is more demanding is that if the 10 identical chips meet the preset safety value, but if the communication data of a certain chip deviates greatly from the communication data of other chips, the chip can also be considered as an abnormal chip. In this way, it can be more conducive to discovering potential abnormal chips.

[0068] In another embodiment of the present disclosure, a synchronous communication device of an asynchronous clock is provided, wherein Figure 4 In the embodiment, it includes:

[0069] The clock unit 100 is used to obtain a first clock and a second clock provided by the test machine.

[0070] The receiving unit 200 is used to receive data sent by at least one chip to be detected at a sending frequency corresponding to its own chip clock at a receiving frequency obtained based on the first clock; wherein the receiving frequency is higher than the sending frequency.

[0071] The write unit 300 is used to write the communication data to the cache queue unit corresponding to each chip to be tested, and output the communication data at the output position in each cache queue unit according to the output frequency obtained based on the second clock and synchronized with the input frequency of the test machine, so as to respectively form each data signal sent to the test machine; wherein the output frequency is lower than the sending frequency.

[0072] Specifically, in some embodiments, the two clocks, namely the first clock and the second clock, may have different frequencies to adapt to different operating requirements. The receiving unit 200 uses the first clock to determine the receiving frequency of its operation. This receiving frequency is set to be higher than the sending frequency of the chip to be detected. This is done to ensure that the receiving unit 200 can "oversample" - that is, to check whether new data has arrived multiple times within the data bit period sent by each chip to be detected, thereby greatly reducing the risk of data loss. The received data is written to a cache queue unit corresponding to each chip to be detected. The cache queue acts as a temporary storage for storing data received from each chip to be detected. The write unit 300 outputs the data in each cache queue based on the output frequency obtained by the second clock that is lower and synchronized with the input frequency of the tester. The output frequency here is lower than the sending frequency of the chip to be detected, which means that the tester has enough time to process the received data, avoiding data loss due to inability to process. After passing through the cache queue unit, the data is sorted into a data signal suitable for sending to the tester.

[0073] Optionally, in Figure 5 In an embodiment, the cache queue unit includes:

[0074] A first cache module 301, used to write corresponding communication data into the first cache module 301 in sequence according to the transmission frequency of the chip to be detected;

[0075] The second cache module 302 is communicatively connected to the first cache module 301 and is used to sequentially fetch the communication data from the first cache module to the second cache module according to the receiving frequency, so as to output the communication data to the test machine according to the output frequency.

[0076] Specifically, in some embodiments, the first cache module 301 is used to receive and store data from these chips. It writes the corresponding communication data in sequence according to the transmission frequency (i.e., high rate) of the chip to be tested. This means that whenever the chip to be tested sends new data, the first cache module 301 will immediately receive and temporarily store these data. The second cache module 302 operates according to a second clock with a lower frequency (i.e., a slow clock provided by the tester), and outputs communication data from the first cache module 301 in sequence at a slower speed. This helps to ensure that the tester has enough time to process the received data, while reducing the risk of data loss that may be caused by inability to process. At this time, the second cache module 302 takes out the communication data from the first cache module 301, which can be taken out according to the clock of the tester, thereby reducing metastable states.

[0077] In another embodiment of the present disclosure, a test method based on asynchronous clock communication is provided, wherein Figure 6In the embodiment, the testing method comprises:

[0078] Step B1: Synchronize the communication data of the chip to be tested to the clock domain of the tester through the synchronous communication method as described in any one of claims 1 to 4.

[0079] Step B2: The test machine generates detection data based on the received communication data.

[0080] Step B3: Compare the detection data with a preset safety value to obtain the status of the corresponding chip to be detected.

[0081] Specifically, in some embodiments, based on the synchronization of the clock signal, it is ensured that the communication data from the chip to be tested can be accurately transmitted to the tester. The tester receives the communication data after synchronization processing, which contains the status information, operation results, etc. of the chip to be tested. Based on the received communication data, the tester can start a series of predetermined test processes, such as analyzing specific data patterns, calculating performance indicators, monitoring abnormal behaviors, etc. The tester has a set of preset safety values ​​or thresholds built in, which are usually determined based on the design specifications of the chip, the requirements of the manufacturer, or historical test data. The test data is compared with these preset safety values ​​to determine whether it meets the expected standards. For example: in the test scenario of the image processing chip, on the basis of synchronization, the image data stream is transmitted from the image processing chip to the tester. After receiving the communication data, the tester parses it into each frame of the image and performs a detailed analysis of the results of each pixel. The tester first decodes the received image data stream to restore the original image frame. For each frame of the image, the tester checks its color value, brightness value, contrast, and other characteristics pixel by pixel, and records this information. Calculate the average brightness value, maximum and minimum brightness values, and other statistics, such as standard deviation, for each row and column. Compare the generated test data with the preset safety value or specification (spec) to evaluate the status of the image processing chip. Compare the color value, brightness value, etc. of each pixel with the preset specifications one by one, and mark the pixels that do not meet the specifications. Compare the brightness statistics of each row and column with the preset range to determine whether there are any abnormalities. Based on the above comparison results, comprehensively evaluate the quality of the entire image frame to determine whether the image processing chip meets the expected performance. If the brightness values ​​of most pixels and rows and columns are within the preset safety range, the image processing chip is considered to be working properly. If it is found that the brightness values ​​of a large number of pixels or rows and columns are beyond the safety range, or there are obvious image distortion, color deviation and other problems, it is considered that the image processing chip may be faulty and needs further diagnosis or replacement.

[0082] In yet another embodiment of the present disclosure, a computer-readable storage medium is provided, wherein program instructions are stored, and the program instructions are executed to execute the synchronous communication method described in any of the above embodiments.

[0083] In yet another embodiment of the present disclosure, a computer program product is provided, which includes: program instructions for executing the synchronous communication method described in any of the above embodiments.

[0084] like Figure 7 and Figure 8 , which is a schematic diagram showing an application scenario of an asynchronous clock synchronous communication device 100 in an embodiment of the present disclosure.

[0085] exist Figure 7 In the embodiment, the synchronous communication device 100 of the asynchronous clock is relatively small in size and can be directly integrated on a disc-shaped probe card 200 and form a communication connection with the probe card 200, and the synchronous communication device 100 is also communicatively connected with a test machine 300, wherein the probes on the probe card 200 directly contact the electrical contact points on a chip (or multiple chips sequentially or simultaneously) to form a communication connection between the synchronous communication device 100 and the chip, and the communication data of each chip is exported to the synchronous communication device 100, and then output to the test machine 300 for testing.

[0086] By integrating the synchronous communication device 100 into the probe card 200, the same test can be performed on each identical or similar chip with the probe card 200 while maintaining the communication connection (such as electrical contact or flying wire connection) with the probe card 200, and the work of synchronizing the asynchronous communication data sent based on the chip clock domain to the clock domain of the tester 300 can be completed efficiently and quickly.

[0087] In some embodiments, the synchronous communication device 100 can be fixed to the probe card 200 by means of snap-fitting or the like.

[0088] In some embodiments, the synchronous communication device 100 can also be disengaged from the restricted movement on the probe card 200. For example, a sliding limit mechanism is provided on the probe card 200 to form a sliding cavity, and the synchronous communication device 100 is placed therein, and the synchronous communication device 100 can slide in the sliding cavity but cannot be disengaged (for example, a stopper is provided to prevent the communication device from leaving).

[0089] In some embodiments, the synchronous communication device 100 can be electrically connected to the test machine 300 to obtain power supply and the first clock and the second clock.

[0090] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.

Claims

1. A synchronous communication method of an asynchronous clock, characterized in that: include: Obtain a first clock and a second clock provided by the test machine; According to the receiving frequency obtained by the first clock, receiving the communication data sent by at least one chip to be detected according to the sending frequency corresponding to the chip clock of itself; wherein the receiving frequency is higher than the sending frequency; The communication data is written into the cache queue units corresponding to each chip to be tested, and the communication data at the output position in each cache queue unit is output according to the output frequency obtained based on the second clock and synchronized with the input frequency of the test machine, so as to respectively form each data signal sent to the test machine; wherein the output frequency is lower than the sending frequency.

2. The synchronous communication method according to claim 1, characterized in that: Before receiving data sent by at least one chip to be detected according to the sending frequency corresponding to the chip clock thereof according to the receiving frequency obtained by the first clock, the method further includes: Receiving the communication data sent at the sending frequency through a first-stage trigger, and outputting the communication data after performing a first-stage processing on the communication data according to the edge of the first clock; The communication data after the first-stage processing is subjected to second-stage processing by the second-stage trigger according to the next edge of the first clock, so as to obtain steady-state communication data and then output it to the cache queue unit.

3. The synchronous communication method according to claim 1, characterized in that: The cache queue unit includes a first cache queue and a second cache queue, and the writing of the communication data to the cache queue unit corresponding to each chip to be detected includes: According to the transmission frequency of the chip to be detected, the corresponding communication data is sequentially written into the first cache queue; The communication data is sequentially taken out from the first cache queue to the second cache queue according to the receiving frequency, so as to be output to the test machine according to the output frequency.

4. The synchronous communication method according to claim 1, characterized in that: Also includes: The communication data of each channel are synchronously combined to form a combined data signal according to the output frequency, and sent to the test machine; wherein each communication data of a combined data signal is compared with a preset safety value or compared with each other to determine an abnormal chip.

5. A synchronous communication device of an asynchronous clock, characterized in that: include: A clock unit, used for obtaining a first clock and a second clock provided by the test machine; A receiving unit, configured to receive communication data sent by at least one chip to be detected at a sending frequency corresponding to its own chip clock at a receiving frequency obtained based on the first clock; wherein the receiving frequency is higher than the sending frequency; A write unit is used to write the communication data to the cache queue units corresponding to each chip to be tested, and output the communication data at the output position in each cache queue unit according to the output frequency obtained based on the second clock and synchronized with the input frequency of the test machine, so as to respectively form each data signal sent to the test machine; wherein the output frequency is lower than the sending frequency.

6. The asynchronous clock synchronous communication device according to claim 5, characterized in that: The asynchronous clock synchronous communication device is integrated in a probe card for contacting electrical contact points on a chip.

7. The asynchronous clock synchronous communication device according to claim 5, characterized in that: The cache queue unit includes: A first cache module, used for writing corresponding communication data into the first cache module in sequence according to the transmission frequency of the chip to be detected; The second buffer module is used to sequentially fetch the communication data from the first buffer module to the second buffer module according to the receiving frequency, so as to output the communication data to the test machine according to the output frequency.

8. A test method based on asynchronous clock communication, characterized in that: include: Synchronizing the communication data of the chip to be tested to the clock domain of the tester by the synchronous communication method as described in any one of claims 1 to 4; The test machine generates detection data based on the received communication data The detection data is compared with a preset safety value to obtain the status of the corresponding chip to be detected.

9. A computer-readable storage medium, characterized in that: Program instructions are stored, and the program instructions are executed to perform the synchronous communication method according to any one of claims 1 to 4.

10. A computer program product, characterized in that include: Program instructions for executing the synchronous communication method according to any one of claims 1 to 4.

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