Timing detection circuit, chip, electronic device, and timing detection method

Abstract

The application relates to a timing detection circuit, a chip, an electronic device and a timing detection method. The timing detection circuit comprises a signal generation module, a delay module and a signal detection module. The signal generation module is used for generating an excitation signal and a divided clock signal. The delay module is used for performing delay processing on the excitation signal to generate a delay signal. The signal detection module is used for periodically detecting the delay signal by taking the divided clock signal as a sampling reference, and generating a state signal used for representing a timing state of the delay signal according to a detection result, so that real-time monitoring of an internal timing margin of the chip can be realized, an alarm can be sent in time before a timing risk occurs, and the safety of the chip is ensured.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a timing detection circuit, chip, electronic device, and timing detection method. Background Technology

[0002] In electronic devices, the System-on-Chip (SOC) is a core component responsible for handling various complex tasks and ensuring the normal operation of the device. However, these chips can also become targets for malicious attackers. Attackers may manipulate the chip's clock path register to increase the operating frequency or adjust the power supply path register to decrease the operating voltage. These operations can cause the chip's internal logic circuitry to deviate from its normal operating characteristics, increasing timing risks and potentially triggering fault injection attacks, thus threatening the chip's security. Summary of the Invention

[0003] This application provides a timing detection circuit, a chip, an electronic device, and a timing detection method. The application generates an excitation signal and a frequency-divided clock signal through a signal generation module. A delay module processes the excitation signal to generate a delayed signal. A signal detection module uses the frequency-divided clock signal as a sampling reference to periodically detect the delayed signal. Based on the detection results, a status signal characterizing the timing state of the delayed signal is generated. This enables real-time monitoring of the chip's internal timing margin, allowing for timely alarms before timing risks occur, thus ensuring chip safety. The technical solution of this application is as follows:

[0004] The first aspect of this application provides a timing detection circuit, including:

[0005] The signal generation module is used to generate excitation signals and frequency-divided clock signals;

[0006] The delay module is used to perform delay processing on the excitation signal to generate a delayed signal;

[0007] The signal detection module is used to periodically detect the delayed signal using the frequency-divided clock signal as a sampling reference, and generate a status signal based on the detection result; wherein the status signal is used to characterize the timing state of the delayed signal.

[0008] A second aspect of this application provides a chip including: the timing detection circuit as described above.

[0009] A third aspect of this application provides an electronic device including a timing detection circuit as described above.

[0010] The fourth aspect of this application provides a timing detection method, including:

[0011] Generate excitation signals and frequency-divided clock signals;

[0012] The excitation signal is delayed to generate a delayed signal;

[0013] The frequency-divided clock signal is used as a sampling reference to periodically detect the delayed signal, and a status signal is generated based on the detection results; wherein, the status signal is used to characterize the timing state of the delayed signal.

[0014] The fifth aspect of this application provides a non-transitory computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the timing detection method described above.

[0015] A sixth aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the timing detection method described above.

[0016] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0017] The timing detection circuit in this embodiment includes a signal generation module, a delay module, and a signal detection module. The signal generation module generates an excitation signal and a frequency-divided clock signal. The delay module performs delay processing on the excitation signal to generate a delayed signal. The signal detection module uses the frequency-divided clock signal as a sampling reference to periodically detect the delayed signal and generates a status signal characterizing the timing state of the delayed signal based on the detection results. This enables real-time monitoring of the timing margin inside the chip, allowing for timely alarms before timing risks occur and ensuring chip safety.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0020] Figure 1 This is a schematic diagram of a timing detection circuit according to an embodiment of this application;

[0021] Figure 2 This is a circuit diagram of a timing detection circuit according to an embodiment of this application;

[0022] Figure 3 This is a timing diagram of a timing detection circuit according to an embodiment of the present application when the operating frequency changes;

[0023] Figure 4 This is a timing diagram of a timing detection circuit according to an embodiment of the present application when the operating voltage changes;

[0024] Figure 5 This is a flowchart of a timing detection method according to an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0026] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0027] The timing detection circuit, chip, electronic device, and timing detection method of this application are described below with reference to the accompanying drawings.

[0028] Critical timing paths within a chip are influenced by a variety of factors, including process variations, voltage changes, frequency adjustments, and aging effects. Identifying the most critical path during the design phase is extremely difficult because these factors can differ in real-world operating environments. Traditional direct measurement methods require precise modeling and verification of every possible critical path, which not only increases design complexity but can also extend the design cycle.

[0029] To address this, this application proposes an indirect measurement method that simulates the critical path in a real circuit by constructing an adjustable delay path. The delay of this path is close to one normal operating cycle and is used for safety timing detection, thus avoiding the need to select the critical path during the design phase.

[0030] Figure 1 This is a schematic diagram of a timing detection circuit according to an embodiment of this application.

[0031] like Figure 1 As shown, the timing detection circuit 100 of this application embodiment includes: a signal generation module 101, a delay module 103 and a signal detection module 104.

[0032] The signal generation module 101 generates an excitation signal *st* and a frequency-divided clock signal *clk_div*. The delay module 103 performs delay processing on the excitation signal *st* to generate a delay signal *delay*. The signal detection module 104 uses the frequency-divided clock signal *clk_div* as a sampling reference to periodically detect the delay signal *delay*, and generates a state signal *s0* based on the detection results; the state signal *s0* characterizes the timing state of the delay signal *delay*.

[0033] For example, the frequency division clock signal clk_div in this application includes a three-way frequency division clock signal.

[0034] For example, periodic detection of the delay signal can be performed by edge triggering.

[0035] In this embodiment, the clock signal input terminal of the signal generation module 101 is used to receive the reference clock signal clk, the first output terminal of the signal generation module 101 is connected to the input terminal of the delay module 103, the second output terminal of the signal generation module 101 is connected to the first input terminal of the signal detection module 104, the output terminal of the delay module 103 is connected to the second input terminal of the signal detection module 104, and the output terminal of the signal detection module 104 is used to output the status signal s0.

[0036] After receiving the reference clock signal clk, the signal generation module 101 generates an excitation signal st and a frequency-divided clock signal clk_div according to the received reference clock signal clk. The excitation signal st is output to the input terminal of the delay module 103, and the frequency-divided clock signal clk_div is output to the first input terminal of the signal detection module 104.

[0037] The delay module 103 performs a logical delay on the excitation signal st, generating a delay signal delay. The delay of this delay signal delay can cover the maximum logical delay of the detection area, ensuring the effectiveness of the detection. The delay signal delay is output to the second input terminal of the signal detection module 104.

[0038] The signal detection module 104 uses the frequency-divided clock signal clk_div as the sampling reference and periodically detects the delay signal delay using an edge-triggered method. Based on the detection results, it outputs a status signal s0. Specifically, if the delay duration of the delay signal delay meets the expected value (i.e., the preset setup time requirement), the signal detection module 104 outputs a low-level status signal S0, indicating that no timing risk has been detected; if the delay duration of the delay signal delay does not meet the expected value, the signal detection module 104 outputs a high-level status signal S0, indicating that a timing risk has been detected.

[0039] Therefore, this application significantly reduces chip area overhead by deploying a timing detection circuit 100 in the chip. This timing detection circuit 100, which works collaboratively by a signal generation module 101, a delay module 103, and a signal detection module 104, is designed to delay the excitation signal. By delaying the excitation signal, the timing detection circuit 100 can ensure that it covers all critical paths, thereby enabling real-time monitoring of the chip's internal timing margin. By periodically detecting the delay signal, alarms can be issued in time before timing risks occur, thus ensuring chip safety. Therefore, the timing detection circuit 100 of this application is suitable for various complex SOC designs.

[0040] To enable those skilled in the art to more clearly understand the timing detection circuit 100 of the embodiments of this application, the following is combined with... Figure 2 The circuit diagram of the timing detection circuit 100 shown is explained below.

[0041] like Figure 2 As shown, the signal generation module 101 of this application embodiment includes: a clock gating unit ICG and a frequency division unit 102.

[0042] The clock input terminal clk_in of the clock gating unit ICG serves as the clock signal input terminal of the signal generation module 101, used to receive the reference clock signal clk; the enable terminal en of the clock gating unit ICG is used to receive the control signal ctl; the clock gating unit ICG is used to perform gating processing on the reference clock signal clk according to the received control signal ctl, generating a gated reference clock signal; the output terminal clk_out of the clock gating unit ICG is used to output the gated reference clock signal.

[0043] The input terminal of the frequency divider unit 102 is connected to the output terminal of the clock gating unit ICG, and is used to receive the reference clock signal after gating processing; the frequency divider unit 102 is used to generate the excitation signal st and the frequency-divided clock signal clk_div according to the reference clock signal after gating processing; the first output terminal of the frequency divider unit 102 serves as the first output terminal of the signal generation module 101, and is used to output the excitation signal st; the second output terminal of the frequency divider unit 102 serves as the second output terminal of the signal generation module 101, and is used to output the frequency-divided clock signal clk_div.

[0044] In this embodiment, the frequency divider unit 102 includes a counter (not shown in the figure). The counter is used to count the gated reference clock signal, and to clear the count when the count value reaches a preset value, such as 2, and to synchronously generate an excitation signal st when the 0th bit of the count value flips; wherein the frequency divider clock signal clk_div is generated under the triggering of the excitation signal st.

[0045] like Figure 2As shown, the signal generation module 101 also includes an AND gate unit 107.

[0046] The first input terminal of AND gate unit 107 is used to receive the enable signal en; the second input terminal of AND gate unit 107 is used to receive the inverted state signal s0'; AND gate unit 107 is used to generate a control signal ctl based on the received enable signal en and the inverted state signal s0'; the output terminal of AND gate unit 107 is connected to the enable terminal en of clock gating unit ICG and is used to output the control signal ctl.

[0047] like Figure 2 As shown, the timing detection circuit 100 also includes a first inverter 108.

[0048] The input terminal of the first inverter 108 is connected to the output terminal of the signal detection module 104 to receive the status signal s0 output by the signal detection module 104; the first inverter 108 is used to invert the status signal s0 to generate the inverted status signal s0'; the output terminal of the first inverter 108 is connected to the second input terminal of the AND gate unit 107 to output the inverted status signal s0'.

[0049] like Figure 2 As shown, the delay module 103 in this embodiment includes a delay chain and a selector 106.

[0050] The delay chain includes multiple delay units 105 connected in series.

[0051] The input terminal of the first delay unit 105 is connected to the first output terminal of the frequency divider unit 102 and is used to receive the excitation signal st; the first delay unit 105 is used to perform a first delay processing on the excitation signal st to generate an excitation signal after the first delay processing; the output terminal of the first delay unit 105 is connected to the input terminal of the second delay unit 105 and the first input terminal of the selector 106 respectively and is used to output the excitation signal after the first delay processing.

[0052] The input terminal of the second delay unit 105 is connected to the output terminal of the first delay unit 105, and is used to receive the excitation signal after the first delay processing; the second delay unit 105 is used to perform a second delay processing on the excitation signal after the first delay processing, that is, to perform a second delay processing on the excitation signal to generate the excitation signal after the second delay processing; the output terminal of the second delay unit 105 is connected to the input terminal of the second delay unit 105 and the second input terminal of the selector 106 respectively, and is used to output the excitation signal after the second delay processing.

[0053] And so on, for the third delay unit 105, ..., the Nth delay unit 105.

[0054] The selection terminal of selector 106 is used to receive the selection signal sel; selector 106 is used to select the delayed excitation signal output by delay unit 105 from the delay chain according to the received selection signal sel, and use it as the delay signal delay; the output terminal of selector 106 outputs the delay signal delay.

[0055] like Figure 2 As shown, the signal detection module 104 includes a second inverter 109 and a trigger DFF.

[0056] The input terminal of the second inverter 109 is used to receive the delay signal delay; the second inverter 109 is used to invert the delay signal delay to generate the inverted delay signal; the output terminal of the second inverter 109 is used to output the inverted delay signal.

[0057] The D input of the flip-flop DFF is used to receive the inverted delayed signal; the clock input of the flip-flop DFF is used to receive the divided clock signal clk_div; the flip-flop DFF is used to capture the rising edge of the inverted delayed signal at each rising edge of the divided clock signal clk_div, and generate a status signal s0 based on the relative timing relationship between the captured rising edge of the inverted delayed signal and the rising edge of the divided clock signal; the Q output of the flip-flop DFF is used to output the status signal s0.

[0058] The logic for generating the state signal s0 is as follows:

[0059] If the rising edge of the captured, inverted, delayed signal occurs before the rising edge of the frequency divider clock signal clk_div, a low-level status signal is generated. In other words, if the delay duration of the delay signal delay meets the expected value, it indicates that the chip has not been subjected to DVFS (Dynamic Voltage and Frequency Scaling) attacks, and a low-level status signal s0 is output, indicating that no timing risk has been detected.

[0060] If the rising edge of the captured, inverted, delayed signal occurs after the rising edge of the frequency divider clock signal clk_div, a high-level status signal is generated. In other words, if the delay duration of the delay signal delay does not meet the expected value, it indicates that the chip may be under DVFS attack. In this case, the output status signal s0 is pulled high, indicating that a timing risk has been detected.

[0061] Therefore, the timing detection circuit 100 of this application embodiment, by using the frequency-divided clock signal clk_div as the sampling reference, can reserve sufficient margin for detection, avoiding false detections caused by the imbalance of the rising and falling edges of the delay chain. It also performs periodic detection on the inverted delay signal using an edge-triggered method to determine whether the delay duration of the delay signal meets the expected value, thereby detecting whether the chip is subjected to a DVFS attack. Therefore, the timing detection circuit 100 of this application embodiment can ensure that the detection results remain accurate and reliable even under different process conditions and operating environments.

[0062] Figure 3 This is a timing diagram of a timing detection circuit according to an embodiment of this application when the operating frequency changes. Figure 3 In the timing diagram of the timing detection circuit 100 shown, the reset signal reset_n is used to initialize the state of the timing detection circuit 100. When reset_n is high, the timing detection circuit 100 starts working and performs timing detection.

[0063] Figure 4 This is a timing diagram of a timing detection circuit according to an embodiment of this application when the operating voltage changes. Figure 4 In the timing diagram of the timing detection circuit 100 shown, the reset signal reset_n is used to initialize the state of the timing detection circuit 100. When reset_n is high, the timing detection circuit 100 starts working and performs timing detection.

[0064] like Figure 3 and Figure 4 As shown, the frequency-divided clock signal clk_div is illustrated using a three-way frequency-divided clock signal as an example. In this embodiment, the timing detection circuit 100 completes a safety check every three clock cycles to ensure a sufficiently high detection frequency, enabling the detection of potential problems before timing risks occur. Each high-level pulse used for timing detection has a width of one clock cycle, and a low-level pulse width of two clock cycles. The one-clock-cycle high-level pulse ensures the detection window meets the requirements of the timing detection circuit, preventing missed detections due to insufficient pulse width. The two-clock-cycle low-level pulse provides sufficient recovery time to ensure detection accuracy. A timing margin of one clock cycle between the high and low-level pulses ensures adequate delay compensation, avoiding false detections caused by rise and fall delay differences due to differences between PMOS (P-channel Metal-Oxide-Semiconductor) and NMOS (N-channel Metal-Oxide-Semiconductor) devices.

[0065] Continue to refer to Figure 3 When the operating frequency increases, the delay duration of the excitation signal st through the delay module 103 remains unchanged, but the period relative to the frequency divider clock signal clk_div becomes shorter. This causes the delay signal delay output by the delay module 103 to be delayed relative to the rising edge of the frequency divider clock signal clk_div. That is, the rising edge of the delay signal delay is later than the rising edge of the frequency divider clock signal clk_div. At this time, since the delay signal delay cannot be sampled as high at the rising edge of the frequency divider clock signal clk_div, the output status signal s0 is pulled high, indicating that a timing risk has been detected.

[0066] Continue to refer to Figure 4 When the operating voltage decreases, the delay time of the excitation signal st after passing through the delay module 103 increases, exceeding one normal operating clock cycle. That is, the delay of the delay signal delay is greater than one normal operating clock cycle. At this time, since the rising edge of the frequency divider clock signal clk_div cannot sample the delay signal delay as high, the output status signal s0 is pulled high, indicating that a timing risk has been detected.

[0067] Upon detecting a timing risk and issuing a status signal (i.e., used as an alarm signal), the Clock Gating Unit (ICG) gates the received reference clock signal clk, temporarily halting its transmission. This mechanism not only reduces power consumption but also minimizes unnecessary clock activity when potential timing issues are detected, ensuring system safety.

[0068] Therefore, the timing detection circuit in this embodiment is responsible for monitoring the timing margin of the timing path. When the timing margin is insufficient, it issues an alarm or takes corresponding measures (such as reducing the operating frequency, increasing the operating voltage, or disabling some functions). It can cope with the timing risks caused by frequency changes and voltage reductions and ensure chip safety.

[0069] In summary, the timing detection circuit of this application embodiment includes a signal generation module, a delay module, and a signal detection module. The signal generation module generates an excitation signal and a frequency-divided clock signal. The delay module performs delay processing on the excitation signal to generate a delayed signal. The signal detection module uses the frequency-divided clock signal as a sampling reference to periodically detect the delayed signal and generates a status signal to characterize the timing state of the delayed signal based on the detection results. This enables real-time monitoring of the timing margin inside the chip, allowing for timely alarms before timing risks occur and ensuring chip safety.

[0070] Based on the above embodiments, this application also proposes a chip that includes the timing detection circuit described above.

[0071] In the embodiments of this application, the chip may be an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), etc.

[0072] It should be noted that for details not disclosed in the chip of this application embodiment, please refer to the details disclosed in the timing detection circuit of this application embodiment, which will not be repeated here.

[0073] The chip in this embodiment of the application, by using the timing detection circuit described above, can realize real-time monitoring of the timing margin inside the chip and issue an alarm in time before timing risks occur, thereby ensuring chip safety.

[0074] Based on the above embodiments, this application also proposes an electronic device that includes the timing detection circuit described above.

[0075] In embodiments of this application, the electronic device may be a vehicle, mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0076] It should be noted that for details not disclosed in the electronic device of this application embodiment, please refer to the details disclosed in the timing detection circuit of this application embodiment, which will not be repeated here.

[0077] The electronic device of this application embodiment, by using the timing detection circuit described above, can realize real-time monitoring of the timing margin inside the chip and issue an alarm in time before timing risks occur, thereby ensuring chip safety.

[0078] Figure 5 This is a flowchart of a timing detection method according to an embodiment of this application.

[0079] like Figure 5 As shown, the timing detection method of this application embodiment includes:

[0080] S1 generates the excitation signal and the frequency-divided clock signal.

[0081] S2 performs a delay processing on the excitation signal to generate a delayed signal.

[0082] S3 uses the frequency-divided clock signal as a sampling reference to periodically detect the delayed signal and generates a status signal based on the detection results; the status signal is used to characterize the timing state of the delayed signal.

[0083] In one embodiment of this application, generating an excitation signal and a frequency-divided clock signal includes:

[0084] Based on the received control signal, the reference clock signal is gated to generate a gated reference clock signal;

[0085] Based on the gated reference clock signal, an excitation signal and a frequency-divided clock signal are generated.

[0086] In one embodiment of this application, the steps for generating the excitation signal are as follows:

[0087] The gating reference clock signal is counted, and when the count value reaches the preset value, it is cleared. When the 0th bit of the counter value flips, an excitation signal is generated synchronously.

[0088] The frequency division clock signal is generated under the triggering of the excitation signal.

[0089] In one embodiment of this application, the control signal generation step is as follows:

[0090] A control signal is generated based on the received enable signal and the inverted state signal.

[0091] In one embodiment of this application, the excitation signal is delayed to generate a delayed signal, including:

[0092] Based on the received selection signal, select the delayed excitation signal output by a delay unit from the delay chain as the delay signal.

[0093] In one embodiment of this application, a frequency-divided clock signal is used as a sampling reference to periodically detect a delayed signal, and a status signal is generated based on the detection results, including:

[0094] The delayed signal is inverted to generate an inverted delayed signal.

[0095] At each rising edge of the frequency-divided clock signal, the rising edge of the delayed signal after inversion is captured;

[0096] A status signal is generated based on the relative timing relationship between the rising edge of the captured, inverted, delayed signal and the rising edge of the frequency-divided clock signal.

[0097] In one embodiment of this application, a status signal is generated based on the relative timing relationship between the rising edge of the captured, inverted, delayed signal and the rising edge of the frequency-divided clock signal, including:

[0098] A low-level status signal is generated in response to the rising edge of the captured, inverted, delayed signal occurring before the rising edge of the frequency-divided clock signal.

[0099] A high-level status signal is generated in response to the rising edge of the captured, inverted, delayed signal occurring after the rising edge of the frequency-divided clock signal.

[0100] It should be noted that for details not disclosed in the timing detection method of this application embodiment, please refer to the details disclosed in the timing detection circuit of this application embodiment, which will not be repeated here.

[0101] The timing detection method in this application first generates an excitation signal and a frequency-divided clock signal, then delays the excitation signal to generate a delayed signal. Next, using the frequency-divided clock signal as a sampling reference, the delayed signal is periodically detected. Based on the detection results, a status signal characterizing the timing state of the delayed signal is generated. Therefore, this method enables real-time monitoring of the chip's internal timing margin and issues alarms before timing risks occur, ensuring chip safety.

[0102] Based on the above embodiments, this application proposes a non-transitory computer-readable storage medium.

[0103] The non-transitory computer-readable storage medium of this application embodiment stores computer program instructions, which, when executed by a processor, implement the steps of the timing detection method described above.

[0104] Based on the above embodiments, this application proposes a computer program product.

[0105] The computer program product of this application embodiment includes a computer program that, when executed by a processor, implements the steps of the timing detection method described above.

[0106] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0107] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0108] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0109] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and compact disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0110] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0111] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0112] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0113] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

[0114] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the appended claims.

[0115] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A timing detection circuit, characterized in that, include: The signal generation module is used to receive the reference clock signal and generate the excitation signal and the frequency-divided clock signal; The delay module is used to perform delay processing on the excitation signal to generate a delayed signal; The signal detection module is used to use the frequency-divided clock signal as a sampling reference, periodically detect the delayed signal through an edge-triggered method, and generate a status signal based on the detection result; wherein, the status signal is used to characterize the timing state of the delayed signal; The signal detection module includes: The second inverter is used to invert the delayed signal to generate an inverted delayed signal. A trigger is configured to capture the rising edge of the inverted delayed signal at each rising edge of the frequency-divided clock signal, and generate the state signal based on the relative timing relationship between the captured rising edge of the inverted delayed signal and the rising edge of the frequency-divided clock signal. The delay module includes: A delay chain, comprising multiple delay units connected in series, each delay unit being used to delay the excitation signal; The selector is used to select, based on the received selection signal, one of the delayed excitation signals output by the delay unit from the delay chain after delay processing, as the delay signal.

2. The timing detection circuit according to claim 1, characterized in that, The signal generation module includes: The clock gating unit is used to perform gating processing on the reference clock signal according to the received control signal, and generate the gating-processed reference clock signal; The frequency divider unit is used to generate the excitation signal and the frequency divider clock signal based on the gated reference clock signal.

3. The timing detection circuit according to claim 2, characterized in that, The frequency division unit includes: The counter is used to count the gated reference clock signal, clear the count value when it reaches a preset value, and synchronously generate the excitation signal when the 0th bit of the count value flips. The frequency division clock signal is generated under the triggering of the excitation signal.

4. The timing detection circuit according to claim 2 or 3, characterized in that, The signal generation module further includes: An AND gate unit is used to generate the control signal based on the received enable signal and the inverted state signal.

5. The timing detection circuit according to claim 4, characterized in that, The timing detection circuit further includes: The first inverter is used to invert the state signal to generate the inverted state signal.

6. The timing detection circuit according to claim 1, characterized in that, The trigger, when used based on the relative timing relationship between the rising edge of the captured inverted delayed signal and the rising edge of the frequency-divided clock signal, includes: In response to the rising edge of the captured inverted delayed signal occurring before the rising edge of the frequency division clock signal, a low-level status signal is generated. In response to the rising edge of the captured inverted delayed signal occurring after the rising edge of the frequency division clock signal, a high-level status signal is generated.

7. A chip, characterized in that, include: The timing detection circuit as described in any one of claims 1-6.

8. An electronic device, characterized in that, include: The timing detection circuit as described in any one of claims 1-6.

9. A timing detection method, said timing detection method being based on a timing detection circuit as described in any one of claims 1-6, characterized in that, include: Generate excitation signals and frequency-divided clock signals; The excitation signal is delayed to generate a delayed signal; Using the frequency-divided clock signal as a sampling reference, the delay signal is periodically detected by edge triggering, and a status signal is generated based on the detection result; wherein, the status signal is used to characterize the timing state of the delay signal, and further includes: inverting the delay signal to generate an inverted delay signal; At each rising edge of the frequency-divided clock signal, the rising edge of the inverted delayed signal is captured; based on the relative timing relationship between the captured rising edge of the inverted delayed signal and the rising edge of the frequency-divided clock signal, a status signal is generated.

10. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the steps of the timing detection method as described in claim 9.

11. A computer program product, characterized in that, It includes a computer program, which, when executed by a processor, implements the steps of the timing detection method as described in claim 9.

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