Wide voltage flexible regulation circuit based on two-stage timing monitoring and error correction
By using a wide-voltage elastic regulation circuit based on two-level timing monitoring and error correction, the timing error and performance reliability problems in adaptive voltage and frequency regulation technology are solved, achieving stable and low-cost circuit-level timing error correction and system performance improvement under wide voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOUTHEAST UNIV
- Filing Date
- 2023-10-17
- Publication Date
- 2026-06-26
Smart Images
Figure CN117590886B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to low-power integrated circuit design, and discloses a wide voltage elastic regulation circuit based on two-level timing monitoring and error correction, particularly relating to in-situ error correction triggers and path activation monitoring units, belonging to the technical field of basic electronic circuits. Background Technology
[0002] Digital chip design needs to address numerous deviations, primarily categorized as process, voltage, temperature, and aging (PVTA) deviations. To ensure the chip functions correctly even under the worst-case scenario with the greatest deviation, the design phase must be designed for worst-case conditions, leaving sufficient voltage margin beyond the minimum operating voltage. These deviations are particularly pronounced near the threshold region because as the voltage drops from the normal voltage range to near the threshold, circuit delay increases sharply. The impact of these deviations widens the gap between the worst-case and typical cases, necessitating a large margin in wide-voltage designs. However, in actual chip operation, the worst-case scenario where all deviations occur simultaneously is almost unheard of. Most of the time, the chip's operating voltage is higher than the required minimum operating voltage, leading to significant power consumption waste and severely limiting the power benefits of wide-voltage designs.
[0003] Adaptive Voltage Frequency Scaling (AVFS) technology can flexibly adjust voltage and frequency according to the actual operating conditions of each chip, compressing or even completely eliminating the timing margin reserved in traditional digital integrated circuit designs to achieve power consumption gains. However, there is still considerable room for exploration and optimization in AVFS technology, mainly in monitoring methods and timing error correction strategies. Traditional AVFS often only monitors for timing violations at the circuit level. If no timing error alarm signal is detected for several cycles, the voltage is reduced or the frequency is increased. The problem with this method is that the activation rate of the critical path is usually low. If an incorrect voltage and frequency adjustment command is issued when the critical path is not activated, it may cause timing errors in unmonitored secondary critical paths. At the same time, the traditional timing error correction strategy is to directly replace the flip-flops at the end of the critical path with latches, using the time borrowing characteristics of latches to correct timing errors. However, replacing latches introduces serious short-path problems, requiring a large cost to repair short paths. Furthermore, replacing latches is incompatible with traditional digital circuit design flows and may bring additional EDA tool problems during the design phase. Achieving real-time error correction at a low cost, and combining circuit-level and system-level monitoring to truly maximize chip performance while ensuring circuit reliability, is an important technology. Summary of the Invention
[0004] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing a wide voltage elastic adjustment circuit based on two-level timing monitoring and error correction. This circuit achieves circuit-level and system-level monitoring and real-time error correction of critical path timing, thus solving the technical problem that existing adaptive voltage and frequency adjustment technologies cannot guarantee circuit reliability or, although they can improve circuit reliability, limit chip performance.
[0005] To achieve the above-mentioned objectives, the present invention employs the following technical solution:
[0006] A wide-range voltage elastic regulation circuit based on two-level timing monitoring and error correction includes: a timing error and path activation monitoring unit inserted before the in-situ error correction trigger at the end of each critical path; an in-situ error correction trigger replacing the trigger at the end of each critical path; an adaptive stretching detection module; and a voltage and frequency regulation control module. The timing error and path activation monitoring unit monitors the timing information and activation status of the current critical path, generates a current critical path alarm signal when a timing error occurs, and generates a current critical path activation signal based on the input and output signals of the in-situ error correction trigger at the end of the current critical path. The in-situ error correction trigger performs real-time error correction on the current critical path output signal in the current cycle upon receiving the current critical path alarm signal. The adaptive stretching detection module quantizes and decodes the summarized critical path alarm signal into a timing stretching amount. The voltage and frequency regulation control module performs closed-loop regulation of voltage and frequency based on the critical path alarm signal summarized by the adaptive stretching detection module, the generated timing stretching amount, and the critical path activation signals generated by each timing error and path activation monitoring unit.
[0007] As a further optimization of the wide-voltage flexible regulation circuit based on two-level timing monitoring and error correction, the in-situ error correction trigger includes: a low-level transparent master latch, a multiplexer, and a high-level transparent slave latch. The enable terminal of the master latch is connected to a clock signal, and its input terminal is connected to the current critical path end output data. The 0 input terminal of the multiplexer is connected to the output terminal of the master latch, its 1 input terminal is connected to the input data of the master latch, and its control terminal is connected to the current critical path alarm signal. When no current critical path alarm signal is received, the output signal of the master latch is transmitted to the input terminal of the slave latch; when a current critical path alarm signal is received, the input data of the master latch is transmitted to the input terminal of the slave latch. The enable terminal of the slave latch is connected to a clock signal, and its input terminal is connected to the output terminal of the multiplexer. During the low-level clock period, the output signal remains unchanged; during the high-level clock period, the multiplexer output signal is output as the current critical path output signal after real-time error correction for the current cycle.
[0008] As a further optimization of the wide-voltage flexible regulation circuit based on two-level timing monitoring and error correction, the timing error and path activation monitoring unit includes: a first XOR gate, a second XOR gate, a charging / discharging path, and an inverter. The first input of the first XOR gate is connected to the input data of the in-situ error correction trigger at the end of the current critical path, and the second input is connected to the output signal of the main latch. The output of the first XOR gate transmits the XOR operation result to the inverter via the charging / discharging path. The first input of the second XOR gate is connected to the input data of the in-situ error correction trigger at the end of the current critical path, and the second input is connected to the output signal of the in-situ error correction trigger at the end of the current critical path. The second XOR gate outputs an activation signal indicating that the current critical path is in an active state. The first input of the charging / discharging path is connected to a clock signal, the second input is connected to the output of the first XOR gate, and the third input is connected to the clock signal. When the clock signal is high, the pre-charged stored charge is released; when the clock signal is low, pre-charging is performed. The input of the inverter is connected to the output of the charging / discharging path, outputting a current critical path alarm signal.
[0009] As a further optimization of the wide voltage elastic regulation circuit based on two-level timing monitoring and error correction, the charging and discharging path includes: a first transistor, a second transistor, and a third transistor. The first transistor is a PMOS transistor, and the second and third transistors are NMOS transistors. The gate of the first transistor serves as the first input terminal of the charging and discharging path and is connected to the clock signal. The gate of the second transistor serves as the second input terminal of the charging and discharging path and is connected to the output terminal of the first XOR gate. The gate of the third transistor serves as the third input terminal of the charging and discharging path and is connected to the clock signal. The source of the first transistor is connected to the power supply. The drain of the first transistor is connected to the drain of the second transistor as the output terminal of the charging and discharging path. The drain of the third transistor is connected to the source of the second transistor, and the source of the third transistor is grounded.
[0010] As a further optimization of the wide-voltage flexible regulation circuit based on two-level timing monitoring and error correction, the adaptive stretching detection module includes: an OR gate, m flip-flops, and m / 2 XOR gates. Each OR gate's input is connected to a critical path alarm signal, outputting a summarized critical path alarm signal. The m flip-flops detect the phase relationship between the summarized critical path alarm signal and clocks of different phases. The input of each flip-flop is connected to the output of the OR gate, which is the summarized critical path alarm signal. Each flip-flop's clock input is connected to a different phase clock signal. Each flip-flop outputs 1 when the rising edge of the current phase clock signal is delayed until after the rising edge of the summarized critical path alarm signal; otherwise, it outputs 0. The outputs of all flip-flops form a thermometer code, where m is an even number greater than or equal to 2. Each input of each XOR gate is connected to one bit of the thermometer code, and the outputs of all XOR gates represent the timing stretching amount.
[0011] As a further optimization of the wide voltage elastic regulation circuit based on two-level timing monitoring and error correction, the voltage and frequency regulation control module performs closed-loop regulation of voltage and frequency in the following specific way:
[0012] When the aggregated critical path alarm signal is low, if no critical path alarm signal is received for N consecutive cycles and at least one critical path is in an active state, a voltage reduction command is issued; otherwise, the critical path alarm signal aggregated by the adaptive tensile amount detection module and the critical path activation signal generated by each timing error and path activation monitoring unit continue to be collected, where N is a positive integer.
[0013] When the aggregated critical path alarm signal is low, if the critical path alarm signal collected within M cycles exceeds the threshold or if a critical path alarm signal is collected within consecutive cycles, an increase voltage command is issued, and adaptive clock stretching is performed according to the timing stretching amount generated by the adaptive stretching amount detection module. Otherwise, the critical path alarm signal aggregated by the adaptive stretching amount detection module and the critical path activation signal generated by each timing error and path activation monitoring unit continue to be collected, where M is a positive integer.
[0014] The present invention, by adopting the above technical solution, has the following beneficial effects:
[0015] (1) Based on the inventive concept of two-level monitoring and in-situ error correction, this application proposes a wide voltage elastic adjustment circuit. The timing error and path activation monitoring unit monitors the timing error information at the circuit level and the critical path activation at the system level. The in-situ error correction trigger performs real-time error correction on the chip output when there is a timing error in the critical path. Combined with the adaptive stretching detection module, the chip can fully obtain the timing status of the critical path in the current state. Under the premise of ensuring the correct timing, the adjustment strategy with the least impact on the system performance is selected to achieve the purpose of suppressing PVTA deviation in a wide voltage range. At the same time, the timing margin reserved in the traditional design is completely eliminated, and the power consumption is fully reduced.
[0016] (2) In the wide voltage elastic regulation circuit proposed in this invention, the timing error and path activation monitoring unit has the characteristics of low area, low power consumption and support for wide voltage operation. It is used to realize two-level timing monitoring including circuit-level monitoring and system-level monitoring. It not only monitors the timing error information at the circuit level, but also monitors the critical path activation at the system level, thereby avoiding incorrect timing margin compression and making timing compression more effective and accurate.
[0017] (3) In the wide voltage elastic adjustment circuit proposed in this invention, the in-situ error correction trigger circuit has low cost and avoids the impact of conventional timing error correction circuit on system throughput. It can achieve stable and low cost circuit-level timing error correction under wide voltage, and ensure system performance while improving system stability.
[0018] (4) In the wide voltage elastic adjustment circuit proposed in this invention, the adaptive stretching detection module combines timing monitoring with clock stretching, so that the chip can fully obtain the timing status of the critical path in the current state, and compress or even completely eliminate the reserved timing margin through linkage adjustment, so that the chip can adaptively maintain the lowest operating voltage. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the wide voltage elastic regulation circuit based on two-level timing monitoring and error correction of the present invention.
[0020] Figure 2 This is a schematic diagram of the in-situ error correction trigger of the present invention when the timing is correct.
[0021] Figure 3 This is a schematic diagram of the in-situ error correction trigger of the present invention in the event of a timing error.
[0022] Figure 4 This is a schematic diagram of timing error monitoring in the timing error and path activation monitoring unit of the present invention.
[0023] Figure 5 This is a schematic diagram of path activation monitoring in the timing error and path activation monitoring unit of the present invention.
[0024] Figure 6 This is a flowchart of the voltage and frequency closed-loop regulation of the voltage and frequency by the voltage and frequency regulation control module of the present invention.
[0025] Figure 7 This is a diagram illustrating the effect of the voltage frequency regulation control module of the present invention regulating the voltage.
[0026] The labels in the diagram are as follows: XOR1, first XOR gate; XOR2, second XOR gate; M1, first transistor; M2, second transistor; M3, third transistor; INV, inverter. Detailed Implementation
[0027] To better understand the purpose, structure, and function of this invention, the following detailed description of the wide voltage elastic regulation circuit based on two-stage timing monitoring and error correction proposed in this invention is provided in conjunction with the accompanying drawings.
[0028] like Figure 1As shown, the wide-voltage elastic regulation circuit based on two-level timing monitoring and error correction includes: an in-situ error correction trigger that replaces the trigger at the end of each critical path, a timing error and path activation monitoring unit inserted before the in-situ error correction trigger at the end of each critical path, an adaptive stretching detection module, and a voltage and frequency regulation control module. The in-situ error correction trigger can correct the error in real time during the current cycle and output the correct data when a timing error in the inserted current critical path causes an output error. The timing error and path activation monitoring unit not only monitors the timing information of the inserted current critical path and issues an alarm signal for the inserted current critical path when a timing error occurs, achieving circuit-level monitoring, but also monitors whether the critical path is in an active state and outputs an activation signal for the inserted current critical path, achieving system-level monitoring. The adaptive stretching detection module summarizes the alarm signals output by each timing error and path activation monitoring unit, quantizes them into a thermometer code, and outputs the stretching amount after decoding. The voltage and frequency regulation control module performs closed-loop regulation of voltage and frequency based on the stretching amount output by the adaptive stretching detection module, the summarized alarm signals of each critical path, and the activation signals of each critical path, to achieve stable and efficient chip operation.
[0029] like Figure 1As shown, the timing error and path activation monitoring unit consists of 15 transistors, including a charging / discharging path composed of a first XOR gate XOR1, a second XOR gate XOR2, a first transistor M1, a second transistor M2, and a third transistor M3, as well as an inverter INV. The first transistor M1 is a PMOS transistor, while the second transistors M2 and M3 are NMOS transistors. The first input of the first XOR gate XOR1 is connected to the input data D of the in-situ error correction trigger at the end of the critical path, and the second input is connected to the output signal mq of the main latch. The output of the first XOR gate XOR1 is connected to the gate of the second transistor M2. The first input of the second XOR gate XOR2 is connected to the input data D of the in-situ error correction trigger at the end of the critical path, and the second input is connected to the output signal Q of the slave latch. The second XOR gate XOR2 outputs the critical path activation signal Active. The source of the first transistor M1 is connected to the power supply. The gate of transistor M1 serves as the first input terminal of the charging / discharging path, connected to the clock signal CLK. Node N1, formed by connecting the drains of the first transistor M1 and the drains of the second transistor M2, serves as the output terminal of the charging / discharging path. The gate of the second transistor M2 serves as the second input terminal of the charging / discharging path. The drain of the third transistor M3 is connected to the source of the second transistor M2, and the gate of the third transistor M3 serves as the third input terminal of the charging / discharging path, connected to the clock signal CLK. The source of the third transistor M3 is grounded. The input terminal of inverter INV is connected to the output terminal of the charging / discharging path, and the output terminal of inverter INV outputs the alarm signal for the critical path. During the low-level clock phase, the first transistor M1 is turned on, and the third transistor M3 is turned off, causing node N1 to be charged to a high level. This, through the inverter, resets the alarm signal Error to a low level. At this time, node N1 is directly connected to the power supply through the first transistor M1, while the discharge path to ground is closed due to the turn-off of the third transistor M3. Therefore, regardless of how the input signal D flips during this phase, the alarm signal Error will remain in a reset low-level state.
[0030] The timing error detection phase occurs during the clock high level. At this time, the first transistor M1 is turned off, causing the charging channel to close, and the third transistor M3 is turned on. The level of the alarm signal Error for node N1 and the critical path is determined by the second transistor M2. The first XOR gate XOR1 operates on the output and input signals of the main latch in the in-place error correction trigger. If the input data flips during the clock high level, a high-level alarm signal is output after passing through the charging / discharging path and the inverter. Figure 4As shown, assuming the input data D flips from low to high during the high level of the clock signal CLK, the main latch does not conduct during the high level of the clock, and its output data mq will remain low. XORing this with D will cause the first XOR gate to output a high level, thus turning on the second transistor M2. Node N1 will release the charge stored during the pre-charge phase, generating a high-level alarm signal Error after passing through the inverter INV. The operation is similar when D flips from high to low during the high level of CLK.
[0031] like Figure 1 As shown, the second XOR gate, XOR2, operates on the input signal of the master latch and the output signal of the slave latch in the in-place error correction trigger. If the output is high, it indicates that the current path is active. Figure 5 As shown, the monitoring window for critical path activation is a low clock level. When D flips during this period, it indicates that the critical path is activated and the timing is loose. However, Q cannot follow the flip of D. At this time, the output signal Q of the in-place error correction trigger is XORed with D, causing the XOR gate to output a high-level signal Active, indicating that the timing is currently effectively monitored and the timing margin can be compressed.
[0032] like Figure 2 As shown, the in-place error correction trigger includes a master latch, a multiplexer, and a slave latch. The master latch is transparent at low levels, and the slave latch is transparent at high levels. During the low-level clock period, the master latch is turned on, and the input signal D is transmitted to mq. However, the slave latch is turned off at this time, so the output Q remains unchanged. When the clock reaches a high level, the slave latch is turned on, and the mq signal is output to the Q terminal at the instant of the rising edge of the clock. Afterward, because the master latch is turned off, changes in D during the high-level clock period will not be transmitted to Q, thus achieving rising-edge triggering.
[0033] A multiplexer consists of six transistors, including one inverter and two transmission gates. For example... Figure 2 As shown, when there is no timing alarm signal, the multiplexer selects the output mq of the master latch and passes it to the slave latch, similar to a standard master-slave flip-flop; as Figure 3 As shown, when a timing error occurs, the alarm signal Error goes high, and the multiplexer outputs D to the slave latch. This effectively converts the flip-flop into a latch, utilizing the time borrowing characteristic of the high-level transparent slave latch to correct the timing error. It's important to note that the timing alarm signal Error here is directly provided by the timing error and path activation monitoring unit inserted before the in-situ error correction trigger at the end of the critical path, not by the summarized and delayed Error_all. Therefore, it ensures rapid error correction after a timing error occurs, improving robustness.
[0034] like Figure 1As shown, the adaptive stretching detection module includes an OR gate, m flip-flops, and m / 2 XOR gates. It is used to detect the phase relationship between the timing alarm signal and the multi-phase clock, determining which phase clock's rising edge is delayed until after the rising edge of the timing alarm signal. This indicates that the phase clock precisely meets the timing requirements of the current system and no timing error will occur. m is an even number greater than or equal to 2.
[0035] The time-to-digital converter consists of m flip-flops. The input of each flip-flop is the timing alarm signal Error_all, which is aggregated by an OR gate. Multiple clocks with different phases serve as the clocks for each flip-flop. The timing alarm signal is quantized into a thermometer code, which is then decoded by an XOR gate to obtain the adaptive stretching amount.
[0036] like Figure 6 As shown, when the timing alarm signal is low, the voltage and frequency regulation control module starts counting the number of consecutive cycles without timing errors and with valid critical path activation signals, No_error_cnt. When No_error_cnt counts to N, the voltage and frequency regulation control module issues a voltage reduction command. When the timing alarm signal is high, it checks whether consecutive timing errors have occurred or whether the number of alarm signals within M cycles exceeds the threshold Error_threshold. If either of these occurs, it indicates a serious timing error has occurred, and relying solely on circuit-level correction by the error correction trigger is insufficient to maintain system robustness. In this case, the voltage and frequency regulation control module issues a voltage increase command and begins adaptive clock stretching to achieve adaptive voltage and frequency regulation. Note that M, N, and Error_threshold are all configurable parameters and can be flexibly adjusted according to actual needs.
[0037] like Figure 7As shown, voltage_up and voltage_down represent voltage rise and fall signals, respectively, and Vout is the current voltage. First, the continuous toggling of Active_all indicates that the current critical path is active, and the Error_all signal remains low, indicating loose timing and allowing for reduced voltage compression timing margin. After 10 cycles, the voltage_down signal generates a high-level pulse, correspondingly reducing the voltage by 10mV. The system continues to operate in a loose timing state, continuing to reduce the voltage. For a period afterward, Active_all does not toggle, indicating that none of the monitored critical paths are active, and the true timing situation of the system cannot be determined. Therefore, the voltage remains unchanged until Active_all toggles before continuing to reduce the voltage. When a minor, occasional timing error occurs, the voltage reduction stops, but due to circuit-level error correction, no instruction to increase the voltage is issued. The voltage continues to decrease until no further alarm signals appear, at which point continuous alarm signals occur, indicating a serious timing error. Voltage_up then generates a high-level pulse to increase the voltage, and finally, the system voltage stabilizes.
[0038] It is understood that the present invention has been described through some embodiments, and those skilled in the art can make various changes or equivalent substitutions to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.
Claims
1. A wide-range voltage elastic regulation circuit based on two-stage timing monitoring and error correction, characterized in that, include: A timing error and path activation monitoring unit, inserted before the in-situ error correction trigger at the end of each critical path, monitors the timing information and activation status of the current critical path. It generates an alarm signal for the current critical path when a timing error occurs, and generates an activation signal for the current critical path based on the input and output signals of the in-situ error correction trigger at the end of the current critical path. Replace the in-situ error correction trigger at the end of each critical path to perform real-time error correction on the output signal of the current critical path in the current cycle when an alarm signal for the current critical path is received. The adaptive stretching detection module is used to quantize and decode the summarized critical path alarm signals into time-series stretching amounts, and... The voltage and frequency regulation control module is used to perform closed-loop regulation of voltage and frequency based on the critical path alarm signals summarized by the adaptive stretching detection module, the generated timing stretching amounts, and the critical path activation signals generated by each timing error and path activation monitoring unit; wherein... The in-situ error correction trigger includes: A low-level transparent master latch, with its enable terminal connected to a clock signal and its input terminal connected to the output data at the end of the current critical path. A multiplexer has its input 0 connected to the output of the master latch, its input 1 connected to the input data of the master latch, and its control terminal connected to the current critical path alarm signal. When no current critical path alarm signal is received, it transmits the output signal of the master latch to the input of the slave latch; when a current critical path alarm signal is received, it transmits the input data of the master latch to the input of the slave latch. A high-level transparent slave latch has its enable terminal connected to a clock signal and its input terminal connected to the output terminal of the multiplexer. During the low level of the clock, the output signal remains unchanged, and during the high level of the clock, the output signal of the multiplexer is output as the current critical path output signal after real-time error correction in the current cycle. The timing error and path activation monitoring unit includes: The first XOR gate has its first input connected to the input data of the in-situ error correction trigger at the end of the current critical path, and its second input connected to the output signal of the main latch. The output of the first XOR gate transmits the XOR operation result to the inverter through the charging and discharging path. The second XOR gate has its first input connected to the input data of the in-situ error correction trigger at the end of the current critical path, and its second input connected to the output signal of the in-situ error correction trigger at the end of the current critical path. It outputs an activation signal indicating that the current critical path is in an active state. The charging / discharging path has a first input terminal connected to a clock signal, a second input terminal connected to the output terminal of the first XOR gate, and a third input terminal connected to a clock signal. When the clock signal is high, the pre-charged stored charge is released; when the clock signal is low, pre-charging is performed. An inverter, whose input is connected to the output of the charging / discharging path, outputs a current critical path alarm signal; The voltage frequency regulation control module. When the aggregated critical path alarm signal is low, and no critical path alarm signal is received for N consecutive cycles while at least one critical path is active, a voltage reduction command is issued. Otherwise, the system continues to collect critical path alarm signals aggregated by the adaptive tensile detection module and critical path activation signals generated by the timing error and path activation monitoring units, where N is a positive integer. When the aggregated critical path alarm signal is low, if the critical path alarm signal collected within M cycles exceeds the threshold or if a critical path alarm signal is collected within consecutive cycles, an increase voltage command is issued, and adaptive clock stretching is performed according to the timing stretching amount generated by the adaptive stretching amount detection module. Otherwise, the critical path alarm signal aggregated by the adaptive stretching amount detection module and the critical path activation signal generated by each timing error and path activation monitoring unit continue to be collected, where M is a positive integer.
2. The wide voltage elastic regulation circuit based on two-stage timing monitoring and error correction according to claim 1, characterized in that, The charging and discharging path includes a first transistor, a second transistor, and a third transistor. The first transistor is a PMOS transistor, and the second and third transistors are NMOS transistors. The gate of the first transistor serves as the first input terminal of the charging and discharging path and is connected to a clock signal. The gate of the second transistor serves as the second input terminal of the charging and discharging path and is connected to the output terminal of the first XOR gate. The gate of the third transistor serves as the third input terminal of the charging and discharging path and is connected to a clock signal. The source of the first transistor is connected to a power supply. The drain of the first transistor is connected to the drain of the second transistor as the output terminal of the charging and discharging path. The drain of the third transistor is connected to the source of the second transistor, and the source of the third transistor is grounded.
3. The wide voltage elastic regulation circuit based on two-stage timing monitoring and error correction according to claim 2, characterized in that, The adaptive tensile measurement detection module includes: An OR gate, whose inputs are each connected to a critical path alarm signal, and whose output is a summed critical path alarm signal; m flip-flops are used to detect the phase relationship between the aggregated critical path alarm signal and clocks of different phases. The input of each flip-flop is connected to the output of an OR gate, which is the aggregated critical path alarm signal. The clock input of each flip-flop is connected to a clock signal of a different phase. Each flip-flop outputs 1 when the rising edge of the current phase clock signal is delayed until after the rising edge of the aggregated critical path alarm signal; otherwise, it outputs 0. The outputs of all flip-flops form a thermometer code, where m is an even number greater than or equal to 2; and... m / 2 XOR gates, each input of which is connected to a single bit of a thermometer code, and the output of all XOR gates represents the timing stretch.