Regulator circuit testing method and apparatus

Abstract

This disclosure provides a method and apparatus for testing an adjustment circuit. The method is applied to a test platform, and the adjustment circuit includes a duty cycle adjustment circuit. The method includes: receiving write data at a specified storage address according to a first read / write clock signal; receiving read data from the specified storage address according to a second read / write clock signal; and generating a test result for the duty cycle adjustment circuit based on the written and read data. The duty cycle adjustment circuit is used to adjust the first initial read / write clock signal and / or the second initial read / write clock signal, correspondingly generating the first and second read / write clock signals. The duty cycle of the first and / or second initial read / write clock signals has a first deviation value. This disclosure can accurately detect whether the duty cycle adjustment circuit is in an effective state.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for testing regulating circuits. Background Technology

[0002] In the semiconductor industry, the read and write clock signals for memory chips such as Dynamic Random Access Memory (DRAM) are generally provided by an external control chip. Duty cycle deviations may occur during the generation, transmission, and processing of this read and write clock signal within the DRAM.

[0003] To correct the duty cycle deviation of the read / write clock signal, a duty cycle adjustment circuit has been proposed in related technologies. This duty cycle adjustment circuit can be used to correct the duty cycle deviation of the read / write clock signal.

[0004] However, since the correction amplitude of the duty cycle adjustment circuit is relatively small, generally only a few picoseconds, while the holding time of a data on the data bus is at least several hundred picoseconds, it is difficult to directly observe whether the duty cycle adjustment circuit is in an effective state in most cases. Summary of the Invention

[0005] This disclosure provides a method and apparatus for testing an adjustment circuit, which can accurately detect whether the duty cycle adjustment circuit is in an effective state.

[0006] In a first aspect, embodiments of this disclosure provide a method for testing an adjustment circuit, applied to a test platform, wherein the adjustment circuit includes a duty cycle adjustment circuit, and the test platform is electrically connected to the adjustment circuit. The method includes:

[0007] Data is received and written at the specified storage address according to the first read / write clock signal;

[0008] Data is received from the specified storage address according to the second read / write clock signal, and the test results of the duty cycle adjustment circuit are generated based on the written data and the read data.

[0009] The duty cycle adjustment circuit is used to adjust the first initial read / write clock signal and / or the second initial read / write clock signal to generate the first read / write clock signal and the second read / write clock signal, and the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal has a first deviation value.

[0010] In one feasible implementation, it further includes:

[0011] Based on the pre-set correspondence between the duty cycle deviation value and the correction value, and the first deviation value, the correction value of the duty cycle adjustment circuit is adjusted to the first correction value.

[0012] In one feasible implementation, the first deviation value is a deviation of N picoseconds in the first direction, where N is not 0;

[0013] The correction value of the duty cycle adjustment circuit is adjusted to a first correction value, including:

[0014] The correction value of the duty cycle adjustment circuit is adjusted to deviate by N picoseconds in the second direction, wherein the second direction is opposite to the first direction.

[0015] In one feasible implementation, generating the test results of the duty cycle adjustment circuit based on the written data and the read data includes:

[0016] Compare the written data with the read data;

[0017] When the written data is the same as the read data, it is determined that the duty cycle adjustment circuit is in an effective state;

[0018] When the written data is different from the read data, the duty cycle adjustment circuit is determined to be in an invalid state.

[0019] In one feasible implementation, it further includes:

[0020] Adjust the start time of the first read / write clock signal so that the time interval between the occurrence of the edge of the first read / write clock signal and the occurrence of the edge of the write command corresponding to the written data is equal to a preset time interval.

[0021] In one feasible implementation, before receiving the write data at the specified storage address according to the first read / write clock signal, the method further includes:

[0022] The written data is received at a specified storage address according to the third read / write clock signal;

[0023] The first read data is received from the specified storage address according to the fourth read / write clock signal;

[0024] The duty cycle of the third read / write clock signal and the fourth read / write clock signal is a standard duty cycle; the correction value of the duty cycle adjustment circuit is zero.

[0025] In one feasible implementation, before receiving the write data at the specified storage address according to the first read / write clock signal, the method further includes:

[0026] The written data is received at a designated storage address according to the fifth read / write clock signal;

[0027] The second read data is received from the specified storage address according to the sixth read / write clock signal;

[0028] The duty cycle of the fifth read / write clock signal and / or the sixth read / write clock signal has a first deviation value, and the correction value of the duty cycle adjustment circuit is zero.

[0029] In one feasible implementation, generating the test results of the duty cycle adjustment circuit based on the written data and the read data includes:

[0030] When the read data is the same as the first read data, it is determined that the duty cycle adjustment circuit is in an effective state;

[0031] When the read data is the same as the second read data, it is determined that the duty cycle adjustment circuit is in an invalid state.

[0032] In a second aspect, embodiments of this disclosure provide an adjustment circuit testing device applied to a test platform. The adjustment circuit includes a duty cycle adjustment circuit, and the test platform is electrically connected to the adjustment circuit. The device includes:

[0033] The write module is used to receive write data at a specified storage address according to the first read / write clock signal;

[0034] The read module is used to receive read data from the specified storage address according to the second read / write clock signal;

[0035] The processing module is used to generate test results for the duty cycle adjustment circuit based on the written data and the read data.

[0036] The duty cycle adjustment circuit is used to adjust the first initial read / write clock signal and / or the second initial read / write clock signal to generate the first read / write clock signal and the second read / write clock signal, and the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal has a first deviation value.

[0037] In one feasible implementation, it further includes:

[0038] The adjustment module is used to adjust the correction value of the duty cycle adjustment circuit to the first correction value according to the pre-set correspondence between the duty cycle deviation value and the correction value, and the first deviation value.

[0039] In one feasible implementation, the first deviation value is a deviation of N picoseconds in the first direction, where N is not 0;

[0040] The adjustment module is specifically used for:

[0041] The correction value of the duty cycle adjustment circuit is adjusted to deviate by N picoseconds in the second direction, wherein the second direction is opposite to the first direction.

[0042] In one feasible implementation, the processing module is used to:

[0043] Compare the written data with the read data;

[0044] When the written data is the same as the read data, it is determined that the duty cycle adjustment circuit is in an effective state;

[0045] When the written data is different from the read data, the duty cycle adjustment circuit is determined to be in an invalid state.

[0046] In one feasible implementation, the adjustment module is further configured to:

[0047] Adjust the start time of the first read / write clock signal so that the time interval between the occurrence of the edge of the first read / write clock signal and the occurrence of the edge of the write command corresponding to the written data is equal to a preset time interval.

[0048] In one feasible implementation, the writing module is further configured to: receive the written data at a specified storage address according to a third read / write clock signal;

[0049] The reading module is also configured to: receive first read data from the designated storage address according to the fourth read / write clock signal;

[0050] The duty cycle of the third read / write clock signal and the fourth read / write clock signal is a standard duty cycle; the correction value of the duty cycle adjustment circuit is zero.

[0051] In one feasible implementation, the writing module is further configured to: receive the written data at a specified storage address according to a fifth read / write clock signal;

[0052] The reading module is also configured to: receive second read data from the specified storage address according to the sixth read / write clock signal;

[0053] The duty cycle of the fifth read / write clock signal and / or the sixth read / write clock signal has a first deviation value, and the correction value of the duty cycle adjustment circuit is zero.

[0054] In one feasible implementation, the processing module is used to:

[0055] When the read data is the same as the first read data, it is determined that the duty cycle adjustment circuit is in an effective state;

[0056] When the read data is the same as the second read data, it is determined that the duty cycle adjustment circuit is in an invalid state.

[0057] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor and a memory;

[0058] The memory stores computer-executed instructions;

[0059] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the adjustment circuit test method as provided in the first aspect.

[0060] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the adjustment circuit testing method provided in the first aspect.

[0061] The adjustment circuit testing method and device provided in this embodiment of the invention provide an initial read / write clock signal with a duty cycle deviation. The duty cycle adjustment circuit adjusts the initial read / write clock signal and performs write and read operations at a specified storage address based on the adjusted read / write clock signal. Then, based on the written and read data, the effectiveness of the duty cycle adjustment circuit can be accurately determined. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of a clock signal adjustment process provided in an embodiment of the present disclosure;

[0063] Figure 2 This is a flowchart illustrating the steps of a method for testing an adjustment circuit provided in an embodiment of this disclosure;

[0064] Figure 3 This is a flowchart illustrating the steps of another adjustment circuit testing method provided in this embodiment of the present disclosure;

[0065] Figure 4 This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 1 ;

[0066] Figure 5 This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 2 ;

[0067] Figure 6 This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 3;

[0068] Figure 7 This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 4 ;

[0069] Figure 8 This is a flowchart illustrating the steps of another adjustment circuit testing method provided in this embodiment of the present disclosure.

[0070] Figure 9 This is a schematic diagram of the program modules of an adjustment circuit testing device provided in an embodiment of this disclosure;

[0071] Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0073] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0074] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0075] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0076] As used in this disclosure, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0077] This disclosure relates to semiconductor integrated circuits, and more particularly to memory chips, which can be used to detect whether the duty cycle adjustment circuit in the memory chip meets the ideal operating state.

[0078] Typically, a storage system includes a controller and a memory. In some embodiments of this disclosure, the memory may be dynamic random access memory (DRAM), such as low-power dual data rate (LPDDR) DRAM. The controller and memory communicate via several buses. For example, the memory receives commands and addresses on a command / address bus and provides data between the controller and the memory via a data bus.

[0079] Additionally, various clock signals can be provided between the controller and the memory via a clock bus. A clock signal is active when it periodically transitions between low and high clock levels. Conversely, a clock signal is inactive when it maintains a constant clock level and does not transition periodically.

[0080] The clock bus may include signal lines for providing system clock signals CK_t and CK_c received from the memory, data clock signals WCK_t and WCK_c received from the memory, and access data clock signals RDQS_t and RDQS_c provided by the memory to the controller.

[0081] For write commands: When the memory is ready to receive write data from the controller, the controller provides the WCK_t and WCK_c clock signals to the memory. The WCK_t and WCK_c clock signals can be used by the memory to generate an internal clock signal for timing the circuitry's reception of write data. The data is provided by the controller, and the memory receives the write data according to the WCK_t and WCK_c clock signals; this write data is then written to the memory address corresponding to that address.

[0082] For read commands: When the memory is ready to provide read data to the controller, the controller provides the WCK_t and WCK_c clock signals to the memory. The WCK_t and WCK_c clock signals can be used by the memory to generate the access data clock signals RDQS_t and RDQS_c. The RDQS_t and RDQS_c clock signals are provided by the memory performing the read operation to the controller to time the provision of read data to the controller. The controller can use the RDQS_t and RDQS_c clock signals to receive the read data.

[0083] A clock signal has a duty cycle, which is the fraction of a binary periodic signal that is valid within one cycle. For example, a clock signal may alternate between logic high levels (e.g., high voltage levels) and logic low levels (e.g., low voltage levels). Semiconductor devices can adjust the duty cycle of the clock signal to ensure that the clock signal matches a desired duty cycle (e.g., 50%).

[0084] The read / write clock signal WCK of DRAM is generally provided by an external controller. Duty cycle deviations may occur during the generation, transmission, and processing within the DRAM. To correct these deviations, a duty cycle adjuster (DCA) circuit has been proposed in the prior art. When a deviation occurs in the duty cycle of the read / write clock signal, the DCA circuit can adjust the duty cycle to maintain it at approximately 50%.

[0085] The duty cycle adjustment circuit's mode register can be set to different levels based on the degree of duty cycle offset, thus achieving internal correction. Furthermore, the mode register configuration must be set to different levels according to the degree of left or right offset of the clock duty cycle, thereby achieving internal correction.

[0086] In some embodiments, the duty cycle adjustment circuit can adjust the duty cycle of one or more read / write clock signals based on the value of the duty cycle code stored in the register of the mode register.

[0087] To better understand the embodiments of this disclosure, please refer to... Figure 1 , Figure 1 This is a schematic diagram of a clock signal adjustment process provided in an embodiment of this disclosure.

[0088] exist Figure 1 In this context, the reference signals include the initial WCK_c and WCK_t clock signals, the right-shift signal refers to the WCK_c and WCK_t clock signals after being shifted to the right by the duty cycle adjustment circuit, and the left-shift signal refers to the WCK_c and WCK_t clock signals after being shifted to the left by the duty cycle adjustment circuit.

[0089] The clock signals WCK_t and WCK_c are complementary, meaning that the rising edge of WCK_t occurs simultaneously with the falling edge of WCK_c, and the rising edge of WCK_c occurs simultaneously with the falling edge of WCK_t.

[0090] Because the correction amplitude of the duty cycle adjustment circuit is relatively small, the correction amplitude specified in the protocol is generally only a few picoseconds, while the minimum holding time of a data on the data bus is several hundred picoseconds, it is difficult to directly observe whether the duty cycle adjustment circuit is in an effective state in most cases.

[0091] To address the aforementioned technical problems, this disclosure provides a method for testing an adjustment circuit, applicable to a test platform. The adjustment circuit includes a duty cycle adjustment circuit. The test platform provides an initial read / write clock signal with a duty cycle deviation. After the duty cycle adjustment circuit adjusts this initial read / write clock signal, write and read operations are performed at a specified memory address based on the adjusted read / write clock signal. Then, based on the written and read data, the effectiveness of the duty cycle adjustment circuit can be accurately determined. Detailed embodiments are described below.

[0092] Reference Figure 2 , Figure 2 This is a schematic flowchart illustrating the steps of a testing method for an adjustment circuit provided in an embodiment of this disclosure. In one feasible implementation, the above-mentioned adjustment circuit testing method is applied to a test platform, the adjustment circuit includes a duty cycle adjustment circuit, the test platform is electrically connected to the adjustment circuit, and the adjustment circuit testing method includes:

[0093] S201. Receive the written data at the specified storage address according to the first read / write clock signal.

[0094] In some embodiments, during the testing process, the test platform is connected to the chip under test, and the tester can test the DCA circuit in the chip under test by starting the preset test program in the test platform or by inputting preset test commands into the test platform.

[0095] In some embodiments, the test platform can receive the written data at the storage address specified by the address signal after receiving the address signal and the write command signal.

[0096] Optionally, the data to be written can be binary data with a fixed format.

[0097] S202. Receive read data from the specified storage address according to the second read / write clock signal.

[0098] The duty cycle adjustment circuit is used to adjust the first initial read / write clock signal and / or the second initial read / write clock signal with a first deviation value of duty cycle, and generate the first read / write clock signal and the second read / write clock signal accordingly.

[0099] Optionally, in one feasible implementation, the test platform can directly provide a first initial read / write clock signal and / or a second initial read / write clock signal with a duty cycle having a first deviation value.

[0100] In another feasible implementation, the test platform can also provide a standard read / write clock signal with a duty cycle of 50%. By delaying the standard read / write clock signal, the test platform can output a first initial read / write clock signal and / or a second initial read / write clock signal with a first deviation value in the duty cycle.

[0101] It should be understood that the term "and / or" used in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0102] In some embodiments, the test platform can input the first initial read / write clock signal and / or the second initial read / write clock signal with the first deviation value into the duty cycle adjustment circuit, and the duty cycle adjustment circuit can adjust the first initial read / write clock signal and / or the second initial read / write clock signal to generate the first read / write clock signal and the second read / write clock signal respectively.

[0103] The duty cycle adjustment circuit corrects the first initial read / write clock signal and / or the second initial read / write clock signal based on the degree to which the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal shifts to the left or right, so that the duty cycle of the first initial read / write clock signal and the second initial read / write clock signal is 50%.

[0104] In some embodiments, the duty cycle adjustment circuit described above can be divided into multiple adjustment levels, with different adjustment levels corresponding to different adjustment ranges.

[0105] In some embodiments, the duty cycle adjustment circuit described above may include an adjustment range of 15 steps from +7 to -7. In this way, the duty cycle adjustment circuit can be set to any one of the 15 different step sizes within the duty cycle adjustment circuit range to adjust the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal. The difference between the actual values ​​of step size N and step size N+1 (or N-1) may not be linear. The duty cycle adjustment circuit shifts the read / write clock signal WCK to the right by increasing the (+) step size and shifts the read / write clock signal WCK to the left by decreasing the (-) step size.

[0106] For example, suppose the duty cycle adjustment circuit described above can be divided into seven adjustment levels: "-3", "-2", "-1", "0", "1", "2", and "3". "-3" corresponds to adjusting to the left by 'a' picoseconds, "-2" by 'b' picoseconds, "-1" by 'c' picoseconds, "0" maintains the sampling clock signal unchanged, "3" by 'a' picoseconds, "2" by 'b' picoseconds, and "1" by 'c' picoseconds. Here, a, b, and c are all positive numbers, and a > b > c.

[0107] In some embodiments, the duty cycle adjustment circuit can select an appropriate adjustment level to perform a correction adjustment operation on the first initial read / write clock signal and / or the second initial read / write clock signal based on the degree to which the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal is shifted to the left or right.

[0108] S203. Based on the written data and the read data, generate the test results of the duty cycle adjustment circuit.

[0109] It is understandable that if the duty cycle adjustment circuit is in an active state, the data written to the specified storage address by the test platform according to the adjusted first read / write clock signal will be consistent with the data that the test platform wants to write; at the same time, the data read from the specified storage address by the test platform according to the adjusted second read / write clock signal will also be consistent with the data written to the specified storage address.

[0110] If the duty cycle adjustment circuit is ineffective, the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal cannot be adjusted to 50%. In this case, due to the deviation in the duty cycle of the first read / write clock signal and / or the second read / write clock signal, the write data received by the test platform at the specified storage address based on the adjusted first read / write clock signal will be inconsistent with the data that the test platform wants to write; and / or, the read data received by the test platform from the specified storage address based on the adjusted second read / write clock signal will be inconsistent with the write data stored in the specified storage address.

[0111] Therefore, in some embodiments, the test platform can determine whether the duty cycle adjustment circuit is in an effective state by comparing the written data with the read data, and then generate the test result of the duty cycle adjustment circuit based on the determination result.

[0112] The adjustment circuit testing method provided in this embodiment involves a test platform that provides an initial read / write clock signal with a duty cycle deviation. After the duty cycle adjustment circuit adjusts the initial read / write clock signal, write and read operations are performed at a specified storage address based on the adjusted read / write clock signal. Then, based on the written and read data, the effectiveness of the duty cycle adjustment circuit can be accurately determined.

[0113] Based on the content described in the above embodiments, referring to Figure 3 , Figure 3 This is a flowchart illustrating the steps of another adjustment circuit testing method provided in this embodiment. In one feasible implementation, the above-mentioned adjustment circuit testing method is applied to a test platform, the adjustment circuit includes a duty cycle adjustment circuit, the test platform is electrically connected to the adjustment circuit, and the adjustment circuit testing method includes:

[0114] S301, Provide a first initial read / write clock signal and / or a second initial read / write clock signal, wherein the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal has a first deviation value.

[0115] Optionally, the test platform can directly provide a first initial read / write clock signal and / or a second initial read / write clock signal with a duty cycle having a first deviation value; or, the test platform can also provide a standard read / write clock signal with a duty cycle of 50%, and the test platform can output the first initial read / write clock signal and / or the second initial read / write clock signal with a duty cycle having a first deviation value by delaying the standard read / write clock signal.

[0116] In some embodiments, the initial read / write clock signal provided by the test platform includes the following four cases:

[0117] 1. The duty cycle of the first initial read / write clock signal has a first deviation value, and the duty cycle of the second initial read / write clock signal is 50%.

[0118] Second, the duty cycle of the second initial read / write clock signal has a first deviation value, and the duty cycle of the first initial read / write clock signal is 50%.

[0119] Third, the duty cycles of both the first initial read / write clock signal and the second initial read / write clock signal have a first deviation value.

[0120] Fourth, the duty cycle of both the first initial read / write clock signal and the second initial read / write clock signal is 50%.

[0121] In some embodiments, the above four situations can be selected by a control module. For example, when the state of the control module is 00, it belongs to the third situation; when the state of the control module is 01, it belongs to the first situation; when the state of the control module is 10, it belongs to the second situation; and when the state of the control module is 11, it belongs to the fourth situation.

[0122] S302. Based on the pre-set correspondence between the duty cycle deviation value and the correction value, and the first deviation value, adjust the correction value of the duty cycle adjustment circuit to the first correction value.

[0123] In some embodiments, the correspondence between the duty cycle deviation value and the correction value can be that the values ​​are the same but the directions are opposite. For example, when the first deviation value is N picoseconds to the left, the correction value should be N picoseconds to the right, where N is not 0.

[0124] In some embodiments, different duty cycle deviation values ​​can correspond to different correction gears. The correction gear of the duty cycle adjustment circuit can be adjusted according to the first deviation value.

[0125] For example, suppose the duty cycle adjustment circuit described above can be divided into seven adjustment levels: "-3", "-2", "-1", "0", "1", "2", and "3". Here, "-3" corresponds to adjusting to the left by 'a' picoseconds, "-2" by 'b' picoseconds, "-1" by 'c' picoseconds, "0" maintains the sampling clock signal unchanged, "3" by 'a' picoseconds, "2" by 'b' picoseconds, and "1" by 'c' picoseconds. Here, a, b, and c are all positive numbers, and a > b > c. Then, when the first deviation is a leftward deviation of N picoseconds, if N ≥ a, the correction level of the duty cycle adjustment circuit is determined to be "-3"; if a > N ≥ b, the correction level is determined to be "-2", and so on.

[0126] S303. The duty cycle adjustment circuit adjusts the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal according to the currently set correction value, thereby generating the first read / write clock signal and the second read / write clock signal accordingly.

[0127] In some embodiments, the duty cycle adjustment circuit can adjust the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal according to the currently set correction value or correction level, thereby generating the first read / write clock signal and the second read / write clock signal accordingly.

[0128] S304. Receive the written data at the specified storage address according to the first read / write clock signal.

[0129] S305. Receive read data from the specified storage address according to the second read / write clock signal.

[0130] S306. Based on the written data and the read data, generate the test results of the duty cycle adjustment circuit.

[0131] It is understandable that if the duty cycle adjustment circuit is in an active state, the duty cycle of the first read / write clock signal and the second read / write clock signal can be adjusted to 50%. The write data received by the test platform at the specified storage address according to the first read / write clock signal will be consistent with the read data received from the specified storage address according to the second read / write clock signal.

[0132] If the duty cycle adjustment circuit is in an invalid state, the duty cycle of the first read / write clock signal and / or the second read / write clock signal cannot be adjusted to 50%. At this time, since the duty cycle of the first read / write clock signal and / or the second read / write clock signal is deviated, the write data received by the test platform at the specified storage address according to the first read / write clock signal will be different from the read data received from the specified storage address according to the second read / write clock signal.

[0133] The aforementioned invalid states include several situations such as no correction operation performed, insufficient correction, excessive correction, and incorrect correction direction.

[0134] Therefore, in some embodiments, the test platform can determine whether the duty cycle adjustment circuit is in an effective state by comparing the written data with the read data, and then generate the test result of the duty cycle adjustment circuit based on the determination result.

[0135] In one feasible implementation, when the written data and the read data are the same, the duty cycle adjustment circuit is determined to be in an active state; when the written data and the read data are different, the duty cycle adjustment circuit is determined to be in an inactive state.

[0136] The adjustment circuit testing method provided in this embodiment involves a test platform that provides an initial read / write clock signal with a duty cycle deviation. The platform adjusts the correction value of the duty cycle adjustment circuit based on the duty cycle deviation of the initial read / write clock signal. After the duty cycle adjustment circuit adjusts the initial read / write clock signal, write and read operations are performed at a specified storage address based on the adjusted read / write clock signal. Then, based on the written and read data, the effectiveness of the duty cycle adjustment circuit can be accurately determined.

[0137] Based on the content described in the above embodiments, in some embodiments, when the test platform performs a write operation, it can adjust the start time of the first read / write clock signal so that the time interval between the time when the edge of the first read / write clock signal appears and the time when the edge of the write command corresponding to the written data appears is equal to a preset time interval. Thus, the actual sampling point can fall at the beginning position of the data.

[0138] Optionally, the above preset time interval is tWCK2DQI.

[0139] In some embodiments, the test platform may provide a third read / write clock signal and a fourth read / write clock signal, the duty cycle of which is a standard duty cycle (50%).

[0140] The test platform receives the written data at the specified storage address according to the third read / write clock signal, and receives the first read data from the specified storage address according to the fourth read / write clock signal; wherein, during the data writing and reading process, the correction value of the duty cycle adjustment circuit is set to zero, or the duty cycle adjustment circuit is not set.

[0141] For example, refer to Figure 4 , Figure 4 This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 1 .

[0142] exist Figure 4 In the above, the duty cycle of the fourth read / write clock signal WCK1 is the standard duty cycle (50%). The above-mentioned written data is preset to be D0D1D2D3D4D5D6D7. Then, according to the fourth read / write clock signal, the first read data received from the specified storage address should theoretically be D0D1D2D3D4D5D6D7.

[0143] The first read data mentioned above should theoretically be the data read based on the rising and falling edges of the fourth read / write clock signal WCK1.

[0144] In some embodiments, the test platform may provide a fifth read / write clock signal and a sixth read / write clock signal, the duty cycle of which has a first deviation value.

[0145] The test platform receives the written data at the specified storage address according to the fifth read / write clock signal, and receives the second read data from the specified storage address according to the sixth read / write clock signal; wherein, during the data writing and reading process, the correction value of the duty cycle adjustment circuit is set to zero, or the duty cycle adjustment circuit is not set.

[0146] For example, refer to Figure 5 , Figure 5This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 2 .

[0147] exist Figure 5 In the above, the duty cycle of the sixth read / write clock signal WCK2 deviates to the left by N picoseconds compared to the standard duty cycle (50%); if the above written data is preset to D0D1D2D3D4D5D6D7, then the second read data received from the specified storage address according to the sixth read / write clock signal should theoretically be D0D0D2D2D4D4D6D6.

[0148] Understandable, Figure 4 The data read / write process shown is the theoretical data read / write situation of the chip under test when the read / write clock signal adopts a standard duty cycle and no duty cycle adjustment circuit is set. Figure 5 The data read / write process shown represents the theoretical data read / write behavior of the chip under test when the read / write clock signal has a duty cycle deviation and no duty cycle adjustment circuit is set.

[0149] In this embodiment of the disclosure, under the premise of using the same write data (D0D1D2D3D4D5D6D7), the data read and write performance of the chip under test is tested when there is a duty cycle deviation in the read and write clock signal and a duty cycle adjustment circuit is set. Then, it is compared with the above-mentioned... Figure 4 and Figure 5 By comparing the data read and write statuses shown, it can be determined whether the duty cycle adjustment circuit mentioned above is effective.

[0150] Specifically, when the read data is the same as the first read data, the duty cycle adjustment circuit is determined to be in an active state; when the read data is the same as the second read data, the duty cycle adjustment circuit is determined to be in an inactive state.

[0151] The aforementioned invalid states include situations where no correction operation was performed, the correction was insufficient, and the correction direction was incorrect.

[0152] For example, refer to Figure 6 , Figure 6 This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 3 .

[0153] exist Figure 6In this test, the preset data to be written is D0D1D2D3D4D5D6D7. The duty cycle of the second initial read / write clock signal WCK3 deviates to the left by N picoseconds compared to the standard duty cycle (50%). After the duty cycle adjustment circuit adjusts the second initial read / write clock signal WCK3, an adjusted second read / write clock signal WCK3_DCA is generated. The test platform receives and reads data from a specified memory address based on the adjusted second read / write clock signal WCK3_DCA. If the read data is D0D1D2D3D4D5D6D7, the duty cycle adjustment circuit is determined to be in an active state; if the read memory data is D0D0D2D2D4D4D6D6, the duty cycle adjustment circuit is determined to be in an inactive state.

[0154] It is understandable that if no correction operation is performed, the correction is insufficient, or the correction direction is incorrect, the duty cycle of the second read / write clock signal WCK3_DCA will be biased to the left. Therefore, the read storage data will be D0D0D2D2D4D4D6D6.

[0155] In some embodiments, the aforementioned invalid state also includes the case of excessive correction.

[0156] Reference Figure 7 , Figure 7 This is a schematic diagram of a data read / write process provided in an embodiment of this disclosure. Figure 4 .

[0157] exist Figure 7 In this test, the preset data to be written is D0D1D2D3D4D5D6D7. The duty cycle of the second initial read / write clock signal WCK4 deviates to the right by N picoseconds compared to the standard duty cycle (50%). The correction value of the duty cycle adjustment circuit is N+2 picoseconds to the left. After the duty cycle adjustment circuit adjusts the second initial read / write clock signal WCK4, it generates the adjusted second read / write clock signal WCK4_DCA. The test platform receives and reads data from a specified storage address based on the adjusted second read / write clock signal WCK4_DCA. If the read data is D0D1D2D3D4D5D6D7, the duty cycle adjustment circuit is determined to be in an effective state. If the read storage data is D0D0D2D2D4D4D6D6, the duty cycle adjustment circuit is determined to be in an ineffective state, and this ineffective state is due to excessive correction by the duty cycle adjustment circuit.

[0158] To better understand the embodiments of this disclosure, please refer to... Figure 8 , Figure 8 This is a flowchart illustrating the steps of another adjustment circuit testing method provided in this embodiment.

[0159] In some embodiments, the above-described adjustment circuit testing method includes:

[0160] S801. The test platform generates an initial read / write clock signal with duty cycle deviation, and configures the correction setting of the duty cycle adjustment circuit to a setting that can compensate for the duty cycle deviation.

[0161] S802. The test platform receives the written data at the specified storage address according to the read / write clock signal adjusted by the duty cycle adjustment circuit, and records the written data content as expected data.

[0162] S803, the test platform receives and reads data from the specified storage address according to the read / write clock signal adjusted by the duty cycle adjustment circuit.

[0163] S804. Compare whether the read data and the written data are consistent. If yes, determine that the duty cycle adjustment circuit is in an active state; if no, determine that the duty cycle adjustment circuit is in an inactive state.

[0164] Understandably, simply configuring a duty cycle adjustment circuit is not conducive to verifying a single function. Therefore, based on the configuration of the duty cycle adjustment circuit, an input clock with a duty cycle deviation is generated, allowing the duty cycle adjustment circuit to perform duty cycle correction itself. Finally, the function of the duty cycle adjustment circuit is verified by comparing whether the read data meets expectations, which will result in higher accuracy.

[0165] The adjustment circuit testing method provided in this embodiment involves a test platform that provides a clock input signal with duty cycle deviation and configures the correction setting of the duty cycle adjustment circuit to compensate for the duty cycle deviation. The test platform can accurately determine whether the duty cycle adjustment circuit is effective by writing data to a specified address and reading data stored at a specified address and comparing the results.

[0166] This disclosure also provides an adjustment circuit testing device in its embodiments. (Refer to...) Figure 9 , Figure 9 This is a schematic diagram of a program module for an adjustment circuit testing device provided in an embodiment of the present disclosure. The adjustment circuit testing device is applied to a test platform. The adjustment circuit includes a duty cycle adjustment circuit. The test platform is electrically connected to the adjustment circuit. The adjustment circuit testing device 80 includes:

[0167] The write module 901 receives write data at a specified storage address according to the first read / write clock signal.

[0168] The read module 902 is used to receive read data from the specified storage address according to the second read / write clock signal.

[0169] The processing module 903 is used to generate the test results of the duty cycle adjustment circuit based on the written data and the read data.

[0170] The duty cycle adjustment circuit is used to adjust the first initial read / write clock signal and / or the second initial read / write clock signal to generate the first read / write clock signal and the second read / write clock signal, and the duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal has a first deviation value.

[0171] The adjustment circuit testing method provided in this embodiment involves a test platform that provides an initial read / write clock signal with a duty cycle deviation. After the duty cycle adjustment circuit adjusts the initial read / write clock signal, write and read operations are performed at a specified storage address based on the adjusted read / write clock signal. Then, based on the written and read data, the effectiveness of the duty cycle adjustment circuit can be accurately determined.

[0172] In some embodiments, an adjustment module is further included for:

[0173] Based on the pre-set correspondence between the duty cycle deviation value and the correction value, and the first deviation value, the correction value of the duty cycle adjustment circuit is adjusted to the first correction value.

[0174] In some embodiments, the processing module 903 is used for:

[0175] The written data is compared with the read data; when the written data and the read data are the same, the duty cycle adjustment circuit is determined to be in an active state; when the written data and the read data are different, the duty cycle adjustment circuit is determined to be in an inactive state.

[0176] In some embodiments, the adjustment module is further configured to:

[0177] Adjust the start time of the first read / write clock signal so that the time interval between the occurrence of the edge of the first read / write clock signal and the occurrence of the edge of the write command corresponding to the written data is equal to a preset time interval.

[0178] In some embodiments, the write module 901 is further configured to: receive the write data at a specified storage address according to a third read / write clock signal.

[0179] The read module 902 is also configured to: receive first read data from the specified storage address according to the fourth read / write clock signal.

[0180] The duty cycle of the third read / write clock signal and the fourth read / write clock signal is a standard duty cycle; the correction value of the duty cycle adjustment circuit is zero.

[0181] In some embodiments, the write module 901 is further configured to: receive the write data at a specified storage address according to a fifth read / write clock signal.

[0182] The read module 902 is also used to: receive second read data from the specified storage address according to the sixth read / write clock signal.

[0183] The duty cycle of the fifth read / write clock signal and / or the sixth read / write clock signal has a first deviation value, and the correction value of the duty cycle adjustment circuit is zero.

[0184] In some embodiments, the processing module 903 is configured to: determine that the duty cycle adjustment circuit is in an active state when the read data is the same as the first read data; and determine that the duty cycle adjustment circuit is in an inactive state when the read data is the same as the second read data.

[0185] It should be noted that the specific execution of the writing module 901, reading module 902, and processing module 903 in this embodiment can be found in the [reference needed]. Figures 1 to 8 The relevant content in the illustrated embodiments will not be repeated here.

[0186] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps of the adjustment circuit testing method described in the above embodiments, which will not be repeated here.

[0187] To better understand the embodiments of this disclosure, please refer to... Figure 10 , Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0188] like Figure 10 As shown, the electronic device 10 of this embodiment includes: a processor 1001 and a memory 1002; wherein:

[0189] Memory 1002 is used to store computer-executed instructions;

[0190] The processor 1001 is used to execute computer execution instructions stored in the memory to implement the various steps of the adjustment circuit testing method described in the above embodiments, and for details, please refer to the relevant descriptions in the foregoing method embodiments.

[0191] Alternatively, the memory 1002 can be either standalone or integrated with the processor 1001.

[0192] When the memory 1002 is set up independently, the device also includes a bus 1003 for connecting the memory 1002 and the processor 1001.

[0193] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the various steps of the adjustment circuit testing method described in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.

[0194] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0195] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0196] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0197] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this disclosure.

[0198] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this disclosure can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0199] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.

[0200] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0201] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0202] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0203] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0204] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of adjusting a circuit test, characterized by, The method is applied to a test platform, the adjustment circuit includes a duty cycle adjustment circuit, the test platform is electrically connected to the adjustment circuit, and the method includes: Data is received and written at the specified storage address according to the first read / write clock signal; Data is received from the specified storage address according to the second read / write clock signal, and the test results of the duty cycle adjustment circuit are generated based on the written data and the read data. The duty cycle adjustment circuit is used to adjust the first initial read / write clock signal and / or the second initial read / write clock signal, and correspondingly generate the first read / write clock signal and the second read / write clock signal. The duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal has a first deviation value. The method further includes: adjusting the correction value of the duty cycle adjustment circuit to a first correction value based on the pre-set correspondence between the duty cycle deviation value and the correction value, and the first deviation value.

2. The method of claim 1, wherein, The first deviation value is a deviation of N picoseconds in the first direction, where N is not 0; The correction value of the duty cycle adjustment circuit is adjusted to a first correction value, including: The correction value of the duty cycle adjustment circuit is adjusted to deviate by N picoseconds in the second direction, wherein the second direction is opposite to the first direction.

3. The method of claim 2, wherein, The step of generating the test results of the duty cycle adjustment circuit based on the written data and the read data includes: Compare the written data with the read data; When the written data is the same as the read data, it is determined that the duty cycle adjustment circuit is in an effective state; When the written data is different from the read data, the duty cycle adjustment circuit is determined to be in an invalid state.

4. The method of claim 1, wherein, Also includes: Adjust the start time of the first read / write clock signal so that the time interval between the occurrence of the edge of the first read / write clock signal and the occurrence of the edge of the write command corresponding to the written data is equal to a preset time interval.

5. The method of claim 1, wherein, Before receiving the write data at the specified storage address according to the first read / write clock signal, the method further includes: The written data is received at a specified storage address according to the third read / write clock signal; The first read data is received from the specified storage address according to the fourth read / write clock signal; The duty cycle of the third read / write clock signal and the fourth read / write clock signal is a standard duty cycle; the correction value of the duty cycle adjustment circuit is zero.

6. The method of claim 5, wherein, Before receiving the write data at the specified storage address according to the first read / write clock signal, the method further includes: The written data is received at a designated storage address according to the fifth read / write clock signal; The second read data is received from the specified storage address according to the sixth read / write clock signal; The duty cycle of the fifth read / write clock signal and / or the sixth read / write clock signal has a first deviation value, and the correction value of the duty cycle adjustment circuit is zero.

7. The method of claim 6, wherein, The step of generating the test results of the duty cycle adjustment circuit based on the written data and the read data includes: When the read data is the same as the first read data, it is determined that the duty cycle adjustment circuit is in an effective state; When the read data is the same as the second read data, it is determined that the duty cycle adjustment circuit is in an invalid state.

8. A test device for an adjustment circuit, characterized in that, The device is applied to a test platform, the adjustment circuit includes a duty cycle adjustment circuit, the test platform is electrically connected to the adjustment circuit, and the device includes: The write module is used to receive write data at a specified storage address according to the first read / write clock signal; The read module is used to receive read data from the specified storage address according to the second read / write clock signal; The processing module is used to generate test results for the duty cycle adjustment circuit based on the written data and the read data. The duty cycle adjustment circuit is used to adjust the first initial read / write clock signal and / or the second initial read / write clock signal, and generate the first read / write clock signal and the second read / write clock signal accordingly. The duty cycle of the first initial read / write clock signal and / or the second initial read / write clock signal has a first deviation value. The device further includes an adjustment module, used to adjust the correction value of the duty cycle adjustment circuit to a first correction value based on a pre-set correspondence between the duty cycle deviation value and the correction value, and the first deviation value.

9. The apparatus according to claim 8, characterized in that, The first deviation value is a deviation of N picoseconds in the first direction, where N is not 0; The adjustment module is specifically used for: The correction value of the duty cycle adjustment circuit is adjusted to deviate by N picoseconds in the second direction, wherein the second direction is opposite to the first direction.

10. The apparatus according to claim 9, characterized in that, The processing module is used for: Compare the written data with the read data; When the written data is the same as the read data, it is determined that the duty cycle adjustment circuit is in an effective state; When the written data is different from the read data, the duty cycle adjustment circuit is determined to be in an invalid state.

11. The apparatus according to claim 8, characterized in that, The adjustment module is also used for: Adjust the start time of the first read / write clock signal so that the time interval between the occurrence of the edge of the first read / write clock signal and the occurrence of the edge of the write command corresponding to the written data is equal to a preset time interval.

12. The apparatus according to claim 8, characterized in that, The writing module is also configured to: receive the written data at a specified storage address according to a third read / write clock signal; The reading module is also configured to: receive first read data from the designated storage address according to the fourth read / write clock signal; The duty cycle of the third read / write clock signal and the fourth read / write clock signal is a standard duty cycle; the correction value of the duty cycle adjustment circuit is zero.

13. The apparatus according to claim 12, characterized in that, The writing module is also configured to: receive the written data at a specified storage address according to the fifth read / write clock signal; The reading module is also configured to: receive second read data from the specified storage address according to the sixth read / write clock signal; The duty cycle of the fifth read / write clock signal and / or the sixth read / write clock signal has a first deviation value, and the correction value of the duty cycle adjustment circuit is zero.

14. The apparatus according to claim 13, characterized in that, The processing module is used for: When the read data is the same as the first read data, it is determined that the duty cycle adjustment circuit is in an effective state; When the read data is the same as the second read data, it is determined that the duty cycle adjustment circuit is in an invalid state.

15. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the adjustment circuit test method as described in any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by the processor, implement the adjustment circuit testing method as described in any one of claims 1 to 7.

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