Low-dropout voltage regulation circuit

Abstract

The application discloses a low-dropout voltage regulating circuit, comprising a unit gain buffer, a flip voltage follower and a floating source follower connected in sequence, and the floating source follower is also connected with the unit gain buffer; the floating source follower is used for providing a reference voltage for the flip voltage follower, the reference voltage is different from an output voltage by a preset threshold, so as to realize the isolation of a power supply voltage and the flip voltage follower; the unit gain buffer is used for obtaining an intermediate voltage through gain buffering based on a reference voltage; the flip voltage follower is used for adjusting the intermediate voltage based on the reference voltage to obtain the output voltage, and the output voltage is equal to the reference voltage. The application can achieve wide input range of the input power supply voltage by adaptively adding a floating source follower at the source end of the power adjusting tube, and the added floating source follower has no influence on the stability of the low-dropout voltage regulating circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-dropout voltage regulation circuit. Background Technology

[0002] Low dropout regulators (LDOs) have significant advantages such as simple structure, low noise, low power consumption, small package size, and fewer external components, making them widely used in portable electronic products. Compared to traditional LDO regulators, single-transistor controlled (STC) LDO regulator circuits based on the flipped voltage follower (FVF) structure have recently attracted increasing attention due to their simple structure and excellent transient response characteristics.

[0003] The stability of a single-transistor controlled LDO regulator (hereinafter referred to as STC-LDO) can be independent of the output capacitor, and the dominant pole can be located at the output terminal or at the gate of the power transistor. Therefore, many fully integrated LDO regulators based on the STC-LDO circuit principle that do not require external capacitors have been widely reported and implemented. The biggest limitation of STC-LDO is that the input voltage must be limited to a range approximately higher than the output rated value by a threshold voltage; otherwise, the output accuracy will rapidly degrade and the voltage regulation function will be lost. Therefore, it is necessary to improve the existing STC-LDO structure. Summary of the Invention

[0004] The purpose of this application is to provide a low dropout voltage regulation circuit to solve the problem that the input voltage of the existing STC-LDO can only be limited to a range that is about one threshold voltage higher than the output rated value, otherwise the output accuracy will degrade rapidly and thus lose the function of voltage regulation.

[0005] In a first aspect, this application provides a low dropout voltage regulation circuit, including a unity-gain buffer and a flip-flop voltage follower and a floating source follower respectively connected to the unity-gain buffer;

[0006] The floating source follower is used to provide a reference voltage for the flip voltage follower. The reference voltage differs from the output voltage by a preset threshold to achieve isolation between the power supply voltage and the flip voltage follower.

[0007] The unity-gain buffer is used to obtain an intermediate voltage based on a reference voltage through gain buffering.

[0008] The flip-flop voltage follower is used to adjust the intermediate voltage based on the reference voltage to obtain an output voltage, wherein the output voltage is equal to the reference voltage.

[0009] In one embodiment of this application, the floating source follower includes a first current source, a fourth NMOS transistor, and a fifth NMOS transistor;

[0010] The output terminal of the first current source is connected to the drain of the fourth NMOS transistor, the input terminal of the first current source is connected to the power supply voltage, the source of the fourth NMOS transistor is connected to the unity-gain buffer, and the drain of the fourth NMOS transistor is connected to the gate of the fourth NMOS transistor; the gate of the fifth NMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the fifth NMOS transistor is connected to the power supply voltage, and the source of the fifth NMOS transistor outputs the reference voltage.

[0011] In one embodiment of this application, the low dropout voltage regulation circuit further includes a current compensation unit, which includes a third current mirror structure and a sixth NMOS transistor. The sixth NMOS transistor is used to acquire the reference voltage and feed it back to the gate of the fourth NMOS transistor through the third current mirror structure.

[0012] In one embodiment of this application, the current compensation unit further includes a feedback capacitor, one end of which is connected to the drain of the sixth NMOS transistor, and the other end of which is connected to the output voltage.

[0013] In one embodiment of this application, the floating source follower includes a second current source, a diode, and an NPN transistor;

[0014] The output terminal of the second current source is connected to the positive terminal of the diode, the input terminal of the second current source is connected to the power supply voltage, the negative terminal of the diode is connected to the unity-gain buffer, the base of the NPN transistor is connected to the positive terminal of the diode, the collector of the NPN transistor is connected to the power supply voltage, and the emitter of the NPN transistor outputs the reference voltage.

[0015] In one embodiment of this application, the unity-gain buffer includes a first differential pair transistor, a first current mirror structure connected to the first differential pair transistor, and a third PMOS transistor. The source of the third PMOS transistor is connected to the output terminal of the first differential pair transistor, the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third PMOS transistor outputs the intermediate voltage.

[0016] The flip-over voltage follower includes a first power regulator and a fourth PMOS transistor. The first power regulator is a PMOS transistor. The reference voltage is input to the source of the first power regulator. The gate of the first power regulator is connected to the drain of the fourth PMOS transistor. The drain of the first power regulator is connected to the source of the fourth PMOS transistor. The intermediate voltage is input to the gate of the fourth PMOS transistor.

[0017] In one embodiment of this application, the gate-source voltages of the third PMOS transistor and the fourth PMOS transistor are equal, and the preset threshold is the gate-source voltage of the third PMOS transistor.

[0018] In one embodiment of this application, the floating source follower includes a third current source, an adjustment resistor, and a fifth PMOS transistor;

[0019] The input terminal of the third current source is connected to the unity-gain buffer through the regulating resistor. The output terminal of the third current source is grounded. The gate of the fifth PMOS transistor is connected to the input terminal of the third current source. The source of the fifth PMOS transistor provides a reference voltage. The drain of the fifth PMOS transistor is grounded.

[0020] In one embodiment of this application, the unity-gain buffer includes a second differential pair, a second current mirror structure connected to the second differential pair, and a third NMOS transistor. The source of the third NMOS transistor is connected to the output terminal of the second differential pair, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor outputs the intermediate voltage.

[0021] The flip-over voltage follower includes a second power regulator and a fourth NMOS transistor. The second power regulator is an NMOS transistor. The reference voltage is input to the source of the second power regulator. The gate of the second power regulator is connected to the drain of the fourth NMOS transistor. The drain of the second power regulator is connected to the source of the fourth NMOS transistor. The intermediate voltage is input to the gate of the fourth NMOS transistor.

[0022] In one embodiment of this application, the gate-source voltages of the third NMOS transistor and the fourth NMOS transistor are equal, and the preset threshold is the gate-source voltage of the third NMOS transistor.

[0023] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0024] The low-dropout voltage regulation circuit provided in this invention isolates the power supply and the power regulator by adaptively adding a floating source follower at the source terminal of the power regulator, enabling a wide input power supply voltage range. Furthermore, the added floating source follower has no impact on the stability of the low-dropout voltage regulation circuit. This invention features a simple circuit structure, does not increase power consumption, and effectively solves the problem that existing STC-LDOs can only limit the input voltage to a range approximately higher than the output rated value by a threshold voltage; otherwise, the output accuracy rapidly degrades, resulting in the loss of voltage regulation functionality.

[0025] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 A schematic diagram of the overall structure of the low dropout voltage regulation circuit described in an embodiment of this application is shown;

[0028] Figure 2 This paper shows a schematic diagram of a first specific structure of the low dropout voltage regulation circuit described in an embodiment of this application;

[0029] Figure 3 A schematic diagram of a second specific structure of the low dropout voltage regulation circuit described in an embodiment of this application is shown;

[0030] Figure 4 A schematic diagram of a third specific structure of the low dropout voltage regulation circuit described in an embodiment of this application is shown;

[0031] Figure 5 A schematic diagram of a fourth specific structure of the low dropout voltage regulation circuit described in the embodiments of this application is shown. Detailed Implementation

[0032] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0033] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] MOS transistor is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor. NMOS transistors are N-type metal-oxide-semiconductor transistors, and PMOS transistors are P-type metal-oxide-semiconductor transistors. An NPN transistor is a transistor composed of two N-type semiconductors sandwiching a P-type semiconductor; it is also called a bipolar junction transistor (BJT). gm is the transconductance of the MOS transistor.

[0035] The following embodiments of this application provide a low-dropout voltage regulation circuit, which solves the problem that the input voltage of the existing STC-LDO can only be limited to a range that is about one threshold voltage higher than the output rated value, otherwise the output accuracy will degrade rapidly and thus lose the function of voltage regulation.

[0036] The principle and implementation method of a low-dropout voltage regulation circuit according to this embodiment will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 A schematic diagram of the overall structure of the low dropout voltage regulation circuit described in an embodiment of this application is shown; Reference Figure 1 As shown, this embodiment provides a low dropout voltage regulation circuit, including a unity-gain buffer 1 and a flip-flop voltage follower 2 and a floating source follower 3 respectively connected to the unity-gain buffer 1. The flip-flop voltage follower 2 and the floating source follower 3 are connected.

[0038] The floating source follower 3 provides a reference voltage to the flip-flop voltage follower 2, thereby isolating the power supply voltage VDD from the flip-flop voltage follower 2. Specifically, the floating source follower 3 can be positioned between the power supply voltage VDD and the flip-flop voltage follower 2 to isolate the power supply voltage VDD from the power regulation transistor in the flip-flop voltage follower 2. Furthermore, the floating source follower 3 can also be positioned between the flip-flop voltage follower 2 and ground to further isolate the power supply voltage VDD from the power regulation transistor in the flip-flop voltage follower 2. Additionally, the reference voltage output by the floating source follower 3 must be set to have a preset threshold difference from its output voltage.

[0039] Unity-gain buffer 1 is primarily used to obtain the intermediate voltage VSET based on a reference voltage through gain buffering. Flip voltage follower 2 is used to adjust the intermediate voltage VSET based on a reference voltage to obtain the output voltage. Unity-gain buffer 1 and flip voltage follower 2 form an FVF STC-LDO, therefore the reference voltage input to unity-gain buffer 1 and the output voltage output from flip voltage follower 2 are equal.

[0040] Figure 2 A schematic diagram of a specific structure of a low-dropout voltage regulation circuit according to an embodiment of this application is shown; Reference Figure 2 As shown, the floating source follower 3 in this structure specifically includes a first current source Ia1, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5. The output terminal of the first current source Ia1 is connected to the drain of the fourth NMOS transistor MN4, and the input terminal of the first current source Ia1 is connected to the power supply voltage VDD. The source of the fourth NMOS transistor MN4 is connected to the unity-gain buffer 1, and the drain of the fourth NMOS transistor MN4 is connected to its gate. The gate of the fifth NMOS transistor MN5 is connected to the gate of the fourth NMOS transistor MN4, and the drain of the fifth NMOS transistor MN5 is connected to the power supply voltage VDD. The source of the fifth NMOS transistor MN5 outputs a reference voltage. The output current of the first current source Ia1 flows through the gate shared by the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5.

[0041] The above structure adds a floating source follower 3 between the bias branch of the unity-gain buffer 1 and the power regulation transistor MPas1 of the flip-flop voltage follower 2 and the power supply. The source output voltage of the fifth NMOS transistor MN5 is V. SOURCE( MN5 ) =VREF + VGSP(MP1) + VGSP(MN4) - VGSP(MN5), where VREF is the input reference voltage of unity-gain buffer 1, VGSP(MN4) is the gate-source voltage of the fourth NMOS transistor MN4, and VGSP(MN5) is the gate-source voltage of the fifth NMOS transistor MN5. Since VGSP(MN4) and VGSP(MN5) are approximately equal, V SOURCE( MN5 )=VREF + VGSP(MP1); Since the reference voltage and output voltage are equal, it can be further concluded that the floating source follower 3 of the above structure can ensure that the source potential of the fifth NMOS transistor MN5 is always higher than the output voltage by a voltage of VGSP. In this way, the source voltage of the fifth NMOS transistor MN5 can always maintain a voltage value that is approximately higher than the output voltage by a preset threshold (which is VGSP) under different power supply voltages VDD and output load currents. Therefore, the FVF STC-LDO can operate under a wider range of input voltages while maintaining the characteristics of simple structure, fast response, and naturally stable loop.

[0042] Figure 3 This illustration shows another specific structural diagram of the low dropout voltage regulation circuit described in an embodiment of this application; see reference. Figure 3 As shown, the floating source follower 3 in this structure specifically includes a second current source Ia2, a diode D0, and an NPN transistor. The output terminal of the second current source Ia2 is connected to the anode of diode D0, the input terminal of the second current source Ia2 is connected to the power supply voltage VDD, the cathode of diode D0 is connected to the unity-gain buffer 1, the base of the NPN transistor is connected to the input terminal of diode D0, the collector of the NPN transistor is connected to the power supply voltage VDD, and the emitter of the NPN transistor outputs a reference voltage.

[0043] The above structure also allows for the addition of a floating source follower 3 between the bias branch of the unity-gain buffer 1 and the power regulation transistor MPas1 of the flip-flop voltage follower 2 and the power supply. Where V Emitter( NPN ) =VREF+VGSP(MP1)+V D0 -V BE Because of V D0 and V BE They are approximately equal, therefore V Emitter( NPN ) =VREF + VGSP(MP1), and the reference voltage and output voltage are equal. Therefore, it can be seen that the adaptive dynamic floating voltage follower includes a second current source Ia2, diode D0, and transistor NPN. The adaptive dynamic floating voltage follower keeps the emitter potential of NPN approximately one VGSP higher than the output voltage VOUT. Since the gm of NPN is larger than that of MOS transistor, it can be known that... Figure 3 Compared to the floating source follower 3 shown Figure 2 The floating source follower 3 shown has better voltage stability.

[0044] In the above Figure 2 and Figure 3In the low-dropout voltage regulation circuit shown, the FVF STC-LDO has the same structure. Specifically, the unity-gain buffer 1 includes a first differential pair, a first current mirror structure, and a third PMOS transistor MP3. The first differential pair includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The gate of the first PMOS transistor MP1 serves as the input terminal (i.e., the reference voltage input terminal) of the unity-gain buffer 1. The source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, and the gate of the second PMOS transistor MP2 is connected to its drain. The drain of the second PMOS transistor MP2 is the output terminal of the first differential pair. The first current mirror structure includes a first NMOS transistor MN1 and a second NMOS transistor MN2. The gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2, and the gate of the first NMOS transistor MN1 is connected to its drain. The sources of both the first and second NMOS transistors are grounded. The source of the third PMOS transistor MP3 is connected to the gate of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3 is connected to the drain of the second NMOS transistor MN2, the gate of the third PMOS transistor MP3 is connected to the drain of the third PMOS transistor MP3, and the connection point of the drain of the third PMOS transistor MP3 serves as the output terminal of the unity-gain buffer 1 to output the intermediate voltage VSET.

[0045] The flip-flop voltage follower 2 includes a first power regulator transistor MPas1 and a fourth PMOS transistor MP4. MPas1 is a PMOS transistor with a reference voltage input at its source. Its gate is connected to the drain of MP4, and its drain is connected to the source of MP4. The gate of MP4 receives an intermediate voltage VSET. A seventh NMOS transistor MN7 is connected between the drain of MP4 and ground. The gate of MN7 is connected to the gate of the first NMOS transistor MN1 in the first current mirror structure, forming a current mirror structure with MN1 and MN2.

[0046] In the above structure, the gate of the third PMOS transistor MP3 in the unity-gain buffer 1 and the fourth PMOS transistor MP4 in the flip voltage follower 2 form a floating source follower structure with intermediate voltage VSET and output voltage VOUT. Where VSET = VREF - VGSP(MP3), VOUT = VSET + VGS(MP4), and since VGSP(MP3) and VGSP(MP4) are approximately equal, VOUT = VREF.

[0047] Since VGSP(MP1) and VGSP(MP3) are approximately equal, the preset threshold in the above circuit is actually the gate-source voltage VGSP of the third PMOS transistor MP3.

[0048] Based on the above structure, the following complementary symmetric instantiation structures can also be set up, such as... Figure 4 As shown, for reference Figure 4 As shown, the power adjustment transistor in the flip-flop voltage follower 2 is an NMOS transistor. The floating source follower 3 in this structure specifically includes a third current source Ia3, an adjustment resistor R1, and a fifth PMOS transistor MP5. The input terminal of the third current source Ia3 is connected to the unity-gain buffer 1 through the adjustment resistor R1, the output terminal of the third current source Ia3 is grounded, the gate of the fifth PMOS transistor MP5 is connected to the input terminal of the third current source Ia3, the source of the fifth PMOS transistor MP5 provides a reference voltage, and the drain of the fifth PMOS transistor MP5 is grounded.

[0049] The above structure adds a floating source follower 3 between the bias branch of the unity-gain buffer 1 and the power adjustment transistor MPas2 of the flip-flop voltage follower 2, and ground. The floating source follower 3 can adjust the resistance value of the adjustment resistor R1 so that the source potential of the fifth PMOS transistor MP5 is always approximately lower than the output voltage by a preset threshold.

[0050] The unity-gain buffer 1 in the above structure includes a second differential pair, a second current mirror structure, and a third NMOS transistor MN3. The second differential pair includes an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9. The gate of the eighth NMOS transistor MN8 serves as the input terminal (i.e., the reference voltage input terminal) of the unity-gain buffer 1. The source of the eighth NMOS transistor MN8 is connected to the source of the ninth NMOS transistor MN9, and the gate of the ninth NMOS transistor MN9 is connected to the drain of the ninth NMOS transistor MN9. The drain connection point of the ninth NMOS transistor MN9 is the output terminal of the second differential pair. The second current mirror structure includes a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7. The gate of the sixth PMOS transistor MP6 is connected to the gate of the seventh PMOS transistor MP7, and the gate of the sixth PMOS transistor MP6 is connected to the drain of the sixth PMOS transistor MP7. The sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are both connected to the power supply. The drain of the third NMOS transistor MN3 is connected to the drain of the seventh PMOS transistor MP7, the source of the third NMOS transistor MN3 is connected to the drain of the ninth NMOS transistor MN9, the gate of the third NMOS transistor MN3 is connected to the drain of the third NMOS transistor MN3, and the connection point of the drain of the third NMOS transistor MN3 serves as the output terminal of the unity-gain buffer 1 to output the intermediate voltage VSET.

[0051] The flip-flop voltage follower 2 includes a second power regulator MPas2 and a fourth NMOS transistor MN4. MPas2 is an NMOS transistor with a reference voltage input at its source. Its gate is connected to the drain of MN4, and its drain is connected to the source of MN4. The gate of MN4 receives an intermediate voltage VSET. An eighth PMOS transistor MP8 is also connected between the drain of MN4 and the power supply. The gate of MP8 is connected to the gate of the sixth PMOS transistor MP6 in the second current mirror structure, forming a current mirror structure with MP6 and MP7.

[0052] In the above structure, the gate of the third NMOS transistor MN3 in the unity-gain buffer 1 and the fourth NMOS transistor MN4 in the flip voltage follower 2 form a floating source follower structure with intermediate voltage VSET and output voltage VOUT. Where VSET = VREF - VGSP(MN3), VOUT = VSET + VGS(MN4), and since VGSP(MN3) and VGSP(MN4) are approximately equal, VOUT = VREF.

[0053] Figure 4 The preset threshold in the structure is set to the gate-source voltage VGSP of the third NMOS transistor MN3.

[0054] To improve circuit stability, the low-dropout voltage regulation circuit of this invention also includes a current compensation unit. The current compensation unit in this invention... Figure 2 The circuit shown is the basis for the setup. A specific low-dropout voltage regulation circuit with a current compensation unit is as follows: Figure 5 As shown.

[0055] The current compensation unit includes a third current mirror structure and a sixth NMOS transistor MN6. The third current mirror structure includes a ninth PMOS transistor MP9 and a tenth PMOS transistor MP10. The gate of the ninth PMOS transistor MP9 is connected to the gate of the tenth PMOS transistor MP10. The sources of both the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are connected to the power supply. The drain of the ninth PMOS transistor MP9 is connected to the gate of the fourth NMOS transistor MN4, and the gate and drain of the tenth PMOS transistor MP10 are connected. The drain of the sixth NMOS transistor MN6 is connected to the drain of the tenth PMOS transistor MP10, the gate of the sixth NMOS transistor MN6 is connected to the gate of the fourth NMOS transistor MN4, and the source of the sixth NMOS transistor MN6 is connected to the source of the fifth NMOS transistor. The sixth NMOS transistor MN6 is used to acquire the reference voltage and feed it back to the gate of the fourth NMOS transistor MN4 through the third current mirror structure. The current compensation unit dynamically adjusts the gate voltage of the fifth NMOS transistor MN5 according to the magnitude of the load current; the larger the load current, the higher the gate voltage of the fifth NMOS transistor MN5.

[0056] The current compensation unit also includes a feedback capacitor Cf. One end of the feedback capacitor is connected to the drain of the sixth NMOS transistor MN6, and the other end is connected to the output voltage. The feedback capacitor Cf is used to improve transient response speed. The feedback capacitor Cf uses a small capacitance value to detect rapid spikes in the output voltage. This is then converted into current by the tenth PMOS transistor MP10 and the ninth PMOS transistor MP9 and applied to the gate of the fifth NMOS transistor MN5. When the output voltage drops rapidly by ΔV per unit time, a coupling current (Cf*ΔV) is injected into the fourth NMOS transistor MN4, increasing the gate voltage of the fifth NMOS transistor MN5 by (Cf*ΔV / gm4). This increases the output current capability of the power regulation transistor MPas1 by (Cf*ΔV / gm4*gm5) to compensate for the output voltage change. Conversely, when the output voltage rapidly surges by ΔV within a unit of time, a coupling current (Cf*ΔV) is drawn away to the fourth NMOS transistor MN4, which lowers the gate voltage of the fifth NMOS transistor MN5 (Cf*ΔV / gm4), thereby reducing the output current capability of the regulating transistor MPas1 (Cf*ΔV / gm4*gm5) to compensate for the output voltage change. gm4 and gm5 are the transconductances of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5, respectively.

[0057] The aforementioned current compensation unit allows the bias current to dynamically change with the output, thereby better stabilizing the output voltage.

[0058] The low-dropout voltage regulation circuit provided in this invention isolates the power supply and the power regulator by adaptively adding a floating source follower at the source terminal of the power regulator, enabling a wide input power supply voltage VDD range. Furthermore, the added floating source follower has no impact on the stability of the low-dropout voltage regulation circuit. This invention features a simple circuit structure, does not increase power consumption, and effectively solves the problem that existing STC-LDOs can only limit the input voltage to a range approximately one threshold voltage higher than the output rated value; otherwise, the output accuracy rapidly degrades, leading to a loss of voltage regulation functionality.

[0059] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0060] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A low-dropout voltage regulation circuit, characterized in that, It includes a unity-gain buffer and a flip-flop voltage follower and a floating source follower connected to the unity-gain buffer, respectively, wherein the flip-flop voltage follower and the floating source follower are connected. The floating source follower is used to provide a reference voltage for the flip voltage follower. The reference voltage differs from the output voltage by a preset threshold to achieve isolation between the power supply voltage and the flip voltage follower. The floating source follower includes a first current source, a fourth NMOS transistor, and a fifth NMOS transistor. The output terminal of the first current source is connected to the drain of the fourth NMOS transistor, the input terminal of the first current source is connected to the power supply voltage, the source of the fourth NMOS transistor is connected to the unity-gain buffer, and the drain of the fourth NMOS transistor is connected to the gate of the fourth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the fifth NMOS transistor is connected to the power supply voltage, and the source of the fifth NMOS transistor outputs the reference voltage. The unity-gain buffer is used to obtain an intermediate voltage based on a reference voltage through gain buffering. The flip-flop voltage follower is used to adjust the intermediate voltage based on the reference voltage to obtain an output voltage, wherein the output voltage is equal to the reference voltage.

2. The voltage regulation circuit according to claim 1, characterized in that, It also includes a current compensation unit, which includes a third current mirror structure and a sixth NMOS transistor. The sixth NMOS transistor is used to acquire the reference voltage and feed it back to the gate of the fourth NMOS transistor through the third current mirror structure.

3. The voltage regulation circuit according to claim 2, characterized in that, The current compensation unit further includes a feedback capacitor, one end of which is connected to the drain of the sixth NMOS transistor, and the other end of which is connected to the output voltage. The gate of the sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, and the source of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor.

4. The voltage regulation circuit according to claim 2 or 3, characterized in that, The unity-gain buffer includes a first differential pair, a first current mirror structure connected to the first differential pair, and a third PMOS transistor; The first input terminal of the first differential pair is a reference voltage input terminal, the second input terminal of the first differential pair is connected to the floating source follower, the first output terminal of the first differential pair is connected to the input terminal of the first current mirror structure, and the second output terminal of the first differential pair is connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is connected to the drain of the third PMOS transistor and the flip voltage follower, the drain of the third PMOS transistor is connected to the output terminal of the first current mirror structure, the gate of the third PMOS transistor outputs the intermediate voltage, and the power supply terminal of the first current mirror structure is grounded. The flip-over voltage follower includes a first power regulator and a fourth PMOS transistor. The first power regulator is a PMOS transistor. The reference voltage is input to the source of the first power regulator. The gate of the first power regulator is connected to the drain of the fourth PMOS transistor. The drain of the first power regulator is connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor. The intermediate voltage is input to the gate of the fourth PMOS transistor.

5. The voltage regulation circuit according to claim 4, characterized in that, The gate-source voltages of the third PMOS transistor and the fourth PMOS transistor are equal, and the preset threshold is the gate-source voltage of the third PMOS transistor.

6. A low-dropout voltage regulation circuit, characterized in that, It includes a unity-gain buffer and a flip-flop voltage follower and a floating source follower connected to the unity-gain buffer, respectively, wherein the flip-flop voltage follower and the floating source follower are connected. The floating source follower is used to provide a reference voltage for the flip voltage follower. The reference voltage differs from the output voltage by a preset threshold to achieve isolation between the power supply voltage and the flip voltage follower. The floating source follower includes a second current source, a diode, and an NPN transistor. The output terminal of the second current source is connected to the anode of the diode, the input terminal of the second current source is connected to the power supply voltage, the cathode of the diode is connected to the unity-gain buffer, the base of the NPN transistor is connected to the anode of the diode, the collector of the NPN transistor is connected to the power supply voltage, and the emitter of the NPN transistor outputs the reference voltage. The unity-gain buffer is used to obtain an intermediate voltage based on a reference voltage through gain buffering. The flip-flop voltage follower is used to adjust the intermediate voltage based on the reference voltage to obtain an output voltage, wherein the output voltage is equal to the reference voltage.

7. The voltage regulation circuit according to claim 6, characterized in that, The unity-gain buffer includes a first differential pair, a first current mirror structure connected to the first differential pair, and a third PMOS transistor; The first input terminal of the first differential pair is a reference voltage input terminal, the second input terminal of the first differential pair is connected to the floating source follower, the first output terminal of the first differential pair is connected to the input terminal of the first current mirror structure, and the second output terminal of the first differential pair is connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is connected to the drain of the third PMOS transistor and the flip voltage follower, the drain of the third PMOS transistor is connected to the output terminal of the first current mirror structure, the gate of the third PMOS transistor outputs the intermediate voltage, and the power supply terminal of the first current mirror structure is grounded. The flip-over voltage follower includes a first power regulator and a fourth PMOS transistor. The first power regulator is a PMOS transistor. The reference voltage is input to the source of the first power regulator. The gate of the first power regulator is connected to the drain of the fourth PMOS transistor. The drain of the first power regulator is connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor. The intermediate voltage is input to the gate of the fourth PMOS transistor.

8. The voltage regulation circuit according to claim 7, characterized in that, The gate-source voltages of the third PMOS transistor and the fourth PMOS transistor are equal, and the preset threshold is the gate-source voltage of the third PMOS transistor.

9. A low-dropout voltage regulation circuit, characterized in that, It includes a unity-gain buffer and a flip-flop voltage follower and a floating source follower connected to the unity-gain buffer, respectively, wherein the flip-flop voltage follower and the floating source follower are connected. The floating source follower is used to provide a reference voltage for the flip voltage follower. The reference voltage differs from the output voltage by a preset threshold to achieve isolation between the power supply voltage and the flip voltage follower. The floating source follower includes a third current source, an adjusting resistor, and a fifth PMOS transistor. The input terminal of the third current source is connected to the unity-gain buffer through the adjusting resistor. The output terminal of the third current source is grounded. The gate of the fifth PMOS transistor is connected to the input terminal of the third current source. The source of the fifth PMOS transistor provides a reference voltage, and the drain of the fifth PMOS transistor is grounded. The unity-gain buffer is used to obtain an intermediate voltage based on a reference voltage through gain buffering. The flip-flop voltage follower is used to adjust the intermediate voltage based on the reference voltage to obtain an output voltage, wherein the output voltage is equal to the reference voltage.

10. The voltage regulation circuit according to claim 9, characterized in that, The unity-gain buffer includes a second differential pair, a second current mirror structure connected to the second differential pair, and a third NMOS transistor; The first input terminal of the second differential pair is the reference voltage input terminal, the second input terminal of the second differential pair is connected to the floating source follower, the first output terminal of the second differential pair is connected to the input terminal of the second current mirror structure, and the second output terminal of the second differential pair is connected to the source of the third NMOS transistor. The gate of the third NMOS transistor is connected to the drain of the third NMOS transistor and the flip voltage follower, the drain of the third NMOS transistor is connected to the output terminal of the second current mirror structure, the gate of the third NMOS transistor outputs the intermediate voltage, and the power supply terminal of the second current mirror structure is connected to the power supply voltage. The flip-flop voltage follower includes a second power regulator and a fourth NMOS transistor. The second power regulator is an NMOS transistor. The reference voltage is input to the source of the second power regulator. The gate of the second power regulator is connected to the drain of the fourth NMOS transistor. The drain of the second power regulator is connected to the source of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of a third NMOS transistor. The intermediate voltage is input to the gate of the fourth NMOS transistor.

11. The voltage regulation circuit according to claim 10, characterized in that, The gate-source voltages of the third NMOS transistor and the fourth NMOS transistor are equal, and the preset threshold is the gate-source voltage of the third NMOS transistor.

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