Display device

Abstract

The invention relates to a display device. The display device includes a substrate including a display area and a non-display area; a plurality of data drivers disposed in the display area on the substrate, each of the first and second latches includes a first latch disposed adjacent to a side of the display area facing the non-display area, a shift register spaced apart from the first latch in a first direction and sequentially outputting an output signal, and a second latch spaced apart from the shift register in the first direction; a plurality of pixels disposed between elements of the data driver adjacent to each other, in which the elements include a first latch, a shift register, and a second latch; and a plurality of first data lines disposed in the non-display area on the substrate, adjacent to the first latch, connected to the data driver, and to which a data signal in digital form is applied.

Description

Technical Field

[0001] Embodiments relate to a display device and more particularly to a display including a data driver. Background Art

[0002] A display device is a device that displays images and is used to provide visual information to a user. Display devices include liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), and the like. Recently, display devices including micro light emitting diodes (micro LEDs), micro organic light emitting diodes (micro OLEDs), organic light emitting diodes on silicon wafer substrates (OLEDoS), and light emitting diodes on silicon wafer substrates (LEDoS) have attracted much attention.

[0003] Meanwhile, the display device includes a display panel including a plurality of pixels. In addition, the display device includes a gate driver and a data driver for driving the display panel. The plurality of pixels are arranged in a display area of ​​the display device, and components of the data driver are arranged in a non-display area of ​​the display device. Since the components of the data driver are arranged in the non-display area, the area of ​​the display area of ​​the display device may be reduced. Summary of the invention

[0004] Embodiments provide a display device having an expanded display area.

[0005] According to an embodiment, a display device includes: a substrate including a display area and a non-display area adjacent to the display area; a plurality of data drivers arranged on the substrate in the display area, and each including a first latch arranged adjacent to a side of the display area facing the non-display area, a shift register spaced apart from the first latch in a first direction and outputting output signals in sequence, and a second latch spaced apart from the shift register in the first direction; a plurality of pixels arranged on the substrate in the display area and between elements of the data drivers adjacent to each other, wherein the elements include the first latch, the shift register, and the second latch; and a plurality of first data lines arranged on the substrate in the non-display area, adjacent to the first latch, connected to the data driver, and applied with data signals in digital form.

[0006] In an embodiment, the display device may further include a gamma driver overlapping at least a portion of the non-display area and spaced apart from the data driver and each of the pixels in a second direction intersecting the first direction.

[0007] In an embodiment, the gamma driver may include: a gamma voltage generator overlapping the display area; and a gamma amplifier overlapping at least a portion of the non-display area and adjacent to the gamma voltage generator.

[0008] In an embodiment, the gamma voltage generator may be spaced apart from the data driver and each of the pixels in the second direction, and the gamma voltage generator and the gamma amplifier may be spaced apart from each other in the second direction.

[0009] In an embodiment, the display area may include: a first display area, a second display area, a third display area, and a fourth display area, which are located at the outermost edge of the display area and are spaced apart from each other; and a fifth display area, which is located between the first display area, the second display area, the third display area, and the fourth display area.

[0010] In an embodiment, the pixel may overlap with the first display area, the second display area, the third display area, the fourth display area, and the fifth display area, and the first latch, the second latch, and the shift register may overlap with the first display area, the second display area, the third display area, and the fourth display area without overlapping with the fifth display area.

[0011] In an embodiment, a gap between pixels adjacent in the first direction among pixels located in the first display area, the second display area, the third display area, and the fourth display area may be relatively longer than a gap between pixels adjacent in the first direction among pixels located in the fifth display area.

[0012] In an embodiment, an element of the data driver may be disposed between pixels, and the element may further include a plurality of digital-to-analog converters and a demultiplexing circuit overlapping the first display area, the second display area, the third display area, and the fourth display area.

[0013] In an embodiment, the demultiplexing circuit may be disposed adjacent to the fifth display area.

[0014] In an embodiment, the pixels may be arranged in a second direction intersecting the first direction, and the digital-to-analog converters may be arranged alternately with the pixels in the first direction.

[0015] In an implementation, the data driver may further include a level shifter, and the level shifter may be disposed between the second latch and a digital-to-analog converter adjacent to the second latch among the plurality of digital-to-analog converters.

[0016] In an embodiment, the display device may further include: an encapsulation layer disposed on the pixel and the data driver and overlapping the display area and the non-display area, and the non-display area may include a first non-display area overlapping the encapsulation layer and a second non-display area not overlapping the encapsulation layer.

[0017] In an implementation, the first data line may overlap the first non-display area.

[0018] In an implementation, the display device may further include a plurality of second data lines electrically connected to the data driver and the pixels and applied with the data voltage in an analog form, and the first data lines and the second data lines may be spaced apart from each other.

[0019] A display device according to an embodiment includes: a substrate including a display area and a non-display area adjacent to the display area, and including a silicon wafer; a plurality of data drivers arranged on the substrate in the display area, and each including a first latch arranged adjacent to a side of the display area facing the non-display area, a shift register spaced apart from the first latch in a first direction and outputting output signals in sequence, and a second latch spaced apart from the shift register in the first direction; a plurality of pixels arranged on the substrate in the display area and between elements of the data driver adjacent to each other, wherein the elements include the first latch, the shift register, and the second latch; a plurality of first data lines arranged on the substrate in the non-display area, adjacent to the first latch, and applied with data signals in digital form; and a plurality of second data lines electrically connected to the data driver and the pixels, and applied with data voltages in analog form.

[0020] In an embodiment, the display device may further include a gamma driver overlapping at least a portion of the non-display area and spaced apart from the data driver and each of the pixels in a second direction intersecting the first direction.

[0021] In an embodiment, the gamma driver may include: a gamma voltage generator overlapping the display area; and a gamma amplifier overlapping at least a portion of the non-display area and adjacent to the gamma voltage generator.

[0022] In an implementation, elements of the data driver may be disposed between pixels and may also include a plurality of digital-to-analog converters and demultiplexing circuits overlapping the display area.

[0023] In an embodiment, the display device may further include: an encapsulation layer disposed on the pixel and the data driver and overlapping the display area and the non-display area, and the non-display area may include a first non-display area overlapping the encapsulation layer and a second non-display area not overlapping the encapsulation layer.

[0024] In an embodiment, the first data line overlaps the first non-display area.

[0025] In a display device according to an embodiment of the present disclosure, the display device may include a display area and a first non-display area, and a data driver may be disposed in the display area. Therefore, there is no need to arrange a separate area for the data driver, effectively improving the integration density of the semiconductor chip included in the display device, and increasing the area of ​​the display area.

[0026] In addition, the first data line can be disposed in the first non-display area, and the first latch can be disposed adjacent to the first data line in the outermost portion of the display area. Therefore, the first latch can quickly store the digital form of the data signal received from the first data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating driving of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a diagram showing a display panel included in a display device Figure 1 A plan view of the display device in FIG.

[0030] Figure 3 is a diagram showing a data driver included in a display device Figure 1 A plan view of the display device in FIG.

[0031] Figure 4 It is shown Figure 1 A plan view of the gamma drive in Figure 1.

[0032] Figure 5 It is shown Figure 1 Circuit diagram of the gamma driver in .

[0033] Figure 6 It is shown Figure 3 Block diagram of the data driver in .

[0034] Figure 7 It is shown Figure 6 Circuit diagram of the shift register in .

[0035] Figure 8 It is shown Figure 6 Block diagram of the level shifter and digital-to-analog converter in Figure 1.

[0036] Fig. 9 It is shown Figure 6 Circuit diagram of the digital-to-analog converter in.

[0037] Fig.10 It is shown Figure 2 A plan view of an enlarged example of the first display area.

[0038] Fig.11 It is shown Figure 2 A plan view of an enlarged example of area A in FIG.

[0039] Fig.12 It is shown Figure 2 A plan view of the fifth display area in FIG.

[0040] Fig.13 It is shown Figure 2 A plan view of another enlarged example of the first display area in FIG.

[0041] Fig.14 It is shown Figure 2 A plan view of another enlarged example of area A in FIG.

[0042] Fig.15 It is shown Figure 2 A plan view of yet another enlarged example of the first display area in FIG. DETAILED DESCRIPTION

[0043] The terms used herein are only used for the purpose of describing a particular embodiment, and are not intended to be limited. Unless the context clearly indicates otherwise, as used herein, "a", "an", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one" should not be interpreted as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the statement "at least one of a, b and c" means only a, only b, only c, a and b, a and c, b and c, all or variations thereof in a, b and c. It will also be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including” when used in this specification specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0044] It will be understood that although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0045] It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or directly connected to the other element, or intervening elements may exist between them. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0046] Hereinafter, a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0047] Figure 1 is a block diagram illustrating driving of a display device according to an embodiment of the present disclosure.

[0048] refer to Figure 1 The display device 10 may include a display panel PN and a display panel driver. The display panel driver may include a driving controller CON, a gamma driver 100, a data driver 200, and a gate driver 300.

[0049] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2. For example, the second direction DR2 may be perpendicular to the first direction DR1.

[0050] The display device 10 may further include a plurality of first data lines (eg, Figure 2 The invention also includes a first data line 280 in the embodiment of the present invention, a plurality of gate lines GL, a plurality of second data lines DL, and a plurality of pixels PX electrically connected to each of the gate lines GL and the second data lines DL. Each of the second data lines DL may extend along the first direction DR1, and each of the gate lines GL may extend along the second direction DR2.

[0051] In an embodiment, the first data line (eg, Figure 2 The first data line 280 in FIG. 1 and the second data line DL may be spaced apart from each other.

[0052] In an embodiment, a component of the gamma driver 100 may be disposed in a display area (eg, Figure 2 In addition, other components of the gamma driver 100 except the one component may be disposed in a non-display area (eg, Figure 2 In the non-display area PA).

[0053] In an embodiment, one component of the data driver 200 may be disposed in the display region. In addition, other components of the data driver 200 except the one component may be disposed in the non-display region. The gate driver 300 may be disposed in the display region.

[0054] The driving controller CON may receive input image data IMG and input control signals CONT from an external device (not shown). For example, the input image data IMG may include red (R) image data, green (G) image data, and blue (B) image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signals CONT may include a master clock signal and a data enable signal. The input control signals CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0055] The driving controller CON may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA in a digital form based on the input image data IMG and the input control signal CONT.

[0056] The driving controller CON may generate a first control signal CONT1 for controlling driving of the gate driver 300 based on the input control signal CONT, and may output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0057] The driving controller CON may generate a second control signal CONT2 for controlling driving of the data driver 200 based on the input control signal CONT, and may output the second control signal CONT2 to the data driver 200. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0058] The driving controller CON may generate a data signal DATA in a digital form based on the input image data IMG. The driving controller CON may output the data signal DATA to the data driver 200. For example, the driving controller CON may output the data signal DATA to the data driver 200 through the first data line (eg, Figure 2 The first data line 280 in the data driver 200 outputs the data signal DATA.

[0059] The driving controller CON may generate a third control signal CONT3 for controlling the driving of the gamma driver 100 based on the input control signal CONT, and may output the third control signal CONT3 to the gamma driver 100 .

[0060] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller CON. The gate driver 300 may output the gate signal to the gate line GL. For example, the gate driver 300 may output the gate signal to the gate line GL in sequence.

[0061] The gamma driver 100 may generate a gamma reference voltage VG in response to a third control signal CONT3 received from the driving controller CON. The gamma driver 100 may supply the gamma reference voltage VG generated from the gamma driver 100 to the data driver 200. The gamma reference voltage VG may have a value corresponding to each of the data signals DATA. The gamma reference voltage VG may have 256 potentials from a first gamma reference voltage VG0, a second gamma reference voltage VG1, ..., and a twenty-hundred and fifty-sixth gamma reference voltage VG255. However, the present disclosure may not be limited thereto.

[0062] The data driver 200 may receive the second control signal CONT2 and the data signal DATA from the driving controller CON and the gamma reference voltage VG from the gamma driver 100. The data driver 200 may convert the data signal DATA into an analog data voltage VD using the gamma reference voltage VG. The data driver 200 may output the data voltage VD to the second data line DL.

[0063] Figure 2 is a diagram showing a display panel included in a display device Figure 1 A plan view of the display device in FIG. Figure 3 is a diagram showing a data driver included in a display device Figure 1 As used herein, a “plan view” is a view in the thickness direction (ie, third direction DR3) of the substrate SUB.

[0064] refer to Figure 2 and Figure 3 , the display device 10 may include a substrate SUB, a display panel PN and an encapsulation layer EN.

[0065] The substrate SUB may include a silicon wafer. However, the present disclosure may not be limited thereto, and the substrate SUB may include glass, plastic, or the like.

[0066] The display panel PN may be disposed on the substrate SUB. The display panel PN may be a display panel for an organic light emitting diode on a silicon wafer substrate (OLEDoS) and a light emitting diode on a silicon wafer substrate (LEDoS). However, the present disclosure may not be limited thereto, and the display panel PN may be an organic light emitting display panel including an organic light emitting diode (OLED) or a micro light emitting display panel including a micro light emitting diode (micro LED) or a quantum dot light emitting display panel including a quantum dot light emitting diode.

[0067] The encapsulation layer EN may be disposed on the display panel PN. The encapsulation layer EN may protect the display panel PN. The encapsulation layer EN may include an inorganic insulating material. For example, the inorganic insulating material may include silicon nitride, silicon oxide, etc. However, the present disclosure may not be limited thereto, and the encapsulation layer EN may include glass.

[0068] The display panel PN of the display device 10 may include a display area DA and a non-display area PA. Therefore, the substrate SUB disposed under the display panel PN may include the display area DA and the non-display area PA. The non-display area PA may be located adjacent to the display area DA. For example, the non-display area PA may completely surround the display area DA.

[0069] The display area DA may be defined as an area where an image is generated. A plurality of pixels PX may be disposed in the display area DA. Each of the pixels PX may emit light. An image may be generated in the display area DA by light emitted by each of the pixels PX. The pixels PX may be arranged along a first direction DR1 and a second direction DR2.

[0070] The display area DA may include a first display area DA1, a second display area DA2, a third display area DA3, a fourth display area DA4, and a fifth display area DA5. Each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4 may be disposed in an outermost portion of the display area DA. For example, each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4 may be disposed adjacent to four edge areas included in the display area DA.

[0071] In an embodiment, the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4 may be spaced apart from each other. For example, the second display area DA2 may be spaced apart from the first display area DA1 in the first direction DR1. The third display area DA3 may be spaced apart from the first display area DA1 in the second direction DR2. The fourth display area DA4 may be spaced apart from the second display area DA2 in the second direction DR2. The fourth display area DA4 may be spaced apart from the third display area DA3 in the first direction DR1.

[0072] The fifth display area DA5 may be located in an area other than the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4 in the display area DA. For example, the first display area DA1 and the third display area DA3 may be symmetrical with respect to an imaginary line passing through the center of the fifth display area DA5 and parallel to the first direction DR1. In addition, the second display area DA2 and the fourth display area DA4 may be symmetrical with respect to an imaginary line passing through the center of the fifth display area DA5 and parallel to the first direction DR1.

[0073] The first display area DA1 and the second display area DA2 may be symmetrical with respect to an imaginary line passing through the center of the fifth display area DA5 and parallel to the second direction DR2. In addition, the third display area DA3 and the fourth display area DA4 may be symmetrical with respect to an imaginary line passing through the center of the fifth display area DA5 and parallel to the second direction DR2.

[0074] The non-display area PA may include a first non-display area PA1 and a second non-display area PA2. The first non-display area PA1 may be disposed adjacent to the display area DA. For example, the first non-display area PA1 may surround the display area DA. The second non-display area PA2 may be disposed adjacent to the first non-display area PA1. For example, the second non-display area PA2 may surround the first non-display area PA1. In addition, a boundary of the first non-display area PA1 adjacent to the second non-display area PA2 may be a boundary of an encapsulation layer EN included in the display device 10. That is, the encapsulation layer EN may overlap with the display area DA and the first display area PA1. In addition, the encapsulation layer EN may not overlap with the second non-display area PA2.

[0075] The second non-display area PA2 may include a pad area PE. The pad area PE may be located from one side of the first non-display area PA1 in a direction opposite to the second direction DR2. The pad area PE may include a flexible printed circuit and a driving chip involved in electrical signal transmission.

[0076] The data drivers 200 may be respectively disposed in the first display area DA1, the second display area DA2, the third display area DA3 and the fourth display area DA4. Each of the data drivers 200 may include a first latch 210, a shift register 220, a second latch 230, a digital-to-analog converter 240 and a first data line 280. Figure 3 Each of the data drivers 200 may correspond to Figure 1 The data driver 200 in FIG.

[0077] At least one of the first latches 210 may be disposed in each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. For example, the first latch 210 may be disposed in all of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. However, the present disclosure may not be limited thereto.

[0078] The first latch 210 may be adjacent to the non-display area PA in the display area DA. That is, the first latch 210 may be disposed in the outermost portion of each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. For example, in the first display area DA1, the first latch 210 may be disposed adjacent to a side of the first display area DA1 facing a direction opposite to the first direction DR1. In the second display area DA2, the first latch 210 may be disposed adjacent to a side of the second display area DA2 facing the first direction DR1. In the third display area DA3, the first latch 210 may be disposed adjacent to a side of the third display area DA3 facing a direction opposite to the first direction DR1. In the fourth display area DA4, the first latch 210 may be disposed adjacent to a side of the fourth display area DA4 facing the first direction DR1.

[0079] The first latch 210 in the first display area DA1 and the first latch 210 in the second display area DA2 may be symmetrical with respect to an imaginary line passing through the center of the fifth display area DA5 and parallel to the second direction DR2. In addition, the first latch 210 in the third display area DA3 and the first latch 210 in the fourth display area DA4 may be symmetrical with respect to an imaginary line passing through the center of the fifth display area DA5 and parallel to the second direction DR2.

[0080] Circuit components included in the first latch 210 may be arranged in the first, second, third, and fourth display areas DA1, DA2, DA3, and DA4 along the second direction DR2. However, the first latch 210 may not be provided in the fifth display area DA5.

[0081] At least one of the shift registers 220 may be provided in each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. For example, the shift register 220 may be provided in all of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. However, the present disclosure may not be limited thereto.

[0082] The shift register 220 may be spaced apart from the first latch 210 in the first direction DR1 or in a direction opposite to the first direction DR1. For example, in the first display area DA1 and the third display area DA3, the shift register 220 may be spaced apart from the first latch 210 in the first direction DR1. In addition, in the second display area DA2 and the fourth display area DA4, the shift register 220 may be spaced apart from the first latch 210 in a direction opposite to the first direction DR1.

[0083] Circuit components included in the shift register 220 may be arranged in the first, second, third, and fourth display areas DA1, DA2, DA3, and DA4 along the second direction DR2. However, the shift register 220 may not be provided in the fifth display area DA5.

[0084] A plurality of pixels PX may be disposed between the shift register 220 and the first latch 210. The pixels PX may be arranged along the second direction DR2 in the display area DA between the shift register 220 and the first latch 210. Each of the pixels PX may be spaced apart from each of the shift register 220 and the first latch 210 in the first direction DR1 or in a direction opposite to the first direction DR1.

[0085] At least one of the second latches 230 may be provided in each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. For example, the second latch 230 may be provided in all of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. However, the present disclosure may not be limited thereto.

[0086] The second latch 230 may be disposed to be spaced apart from the shift register 220 in a direction opposite to the direction from the shift register 220 to the first latch 210. The second latch 230 may be spaced apart from the shift register 220 in the first direction DR1 or in a direction opposite to the first direction DR1. For example, in the first display area DA1 and the third display area DA3, the second latch 230 may be spaced apart from the shift register 220 in the first direction DR1. In addition, in the second display area DA2 and the fourth display area DA4, the second latch 230 may be spaced apart from the shift register 220 in a direction opposite to the first direction DR1.

[0087] In the first, second, third, and fourth display areas DA1, DA2, DA3, and DA4, circuit components included in the second latch 230 may be arranged along the second direction DR2. However, the second latch 230 may not be provided in the fifth display area DA5.

[0088] The pixels PX may be disposed between the second latch 230 and the shift register 220. The pixels PX may be arranged along the second direction DR2 in the display area DA between the second latch 230 and the shift register 220. Each of the pixels PX may be spaced apart from each of the second latch 230 and the shift register 220 in the first direction DR1 or in a direction opposite to the first direction DR1.

[0089] At least one of the digital-to-analog converters 240 may be disposed in each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. For example, the digital-to-analog converter 240 may be disposed in all of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. However, the present disclosure may not be limited thereto.

[0090] The digital-to-analog converter 240 may be disposed to be spaced apart from the second latch 230 in a direction opposite to the direction from the second latch 230 to the shift register 220. The digital-to-analog converter 240 may be spaced apart from the second latch 230 in the first direction DR1 or in a direction opposite to the first direction DR1. For example, in the first display area DA1 and the third display area DA3, the digital-to-analog converter 240 may be spaced apart from the second latch 230 in the first direction DR1. In addition, in the second display area DA2 and the fourth display area DA4, the digital-to-analog converter 240 may be spaced apart from the second latch 230 in a direction opposite to the first direction DR1.

[0091] The first data line 280 may be a line that transmits a digital data signal (eg, Figure 1In addition, the first data line 280 may be disposed in the non-display area PA. Specifically, the first data line 280 may be disposed in the first non-display area PA1. That is, the first data line 280 may not be disposed in the second non-display area PA2. The first data line 280 may be disposed under the encapsulation layer EN. In addition, the first data line 280 may be disposed to overlap the encapsulation layer EN in a plan view. Therefore, the first data line 280 may be protected by the encapsulation layer EN.

[0092] The first data line 280 may be disposed adjacent to the outermost edge of the display area DA. The first data line 280 may be disposed adjacent to the first latch 210. For example, the first data line 280 may be disposed to be spaced apart from the first latch 210 disposed in the first display area DA1 and the third display area DA3 in a direction opposite to the first direction DR1. In addition, the first data line 280 may be disposed to be spaced apart from the first latch 210 disposed in the second display area DA2 and the fourth display area DA4 in the first direction DR1. Since the first data line 280 may be adjacent to the first latch 210, the first latch 210 may quickly receive the data signal DATA in digital form.

[0093] According to components of the data driver 200 (eg, the first latch 210 , the shift register 220 , the second latch 230 , and the digital-to-analog converter 240 ) that may be disposed in the display area DA, the first data line 280 may be adjacent to the display area DA.

[0094] However, when the first data line 280 is disposed in the display area DA, an electromagnetic coupling phenomenon may occur. In order to prevent the electromagnetic coupling phenomenon, the first data line 280 may be disposed in the non-display area PA.

[0095] For example, the first data line 280 may transmit a data signal in an 8-bit digital form. For example, the first data line 280 may transmit a signal to a pixel PX that emits red (R) light, green (G) light, and blue (B) light. The first data line 280 may include 24 lines that transmit a signal to each of the pixels PX that emit red (R) light, green (G) light, and blue (B) light. However, the present disclosure may not be limited to a number of data line bits and a number of data lines.

[0096] The first data line 280 may extend from the pad area PE located in the non-display area PA, and may surround at least a portion of the display area DA. The first data line 280 may be disposed adjacent to the first display area DA1 and the second display area DA2, and may be arranged parallel to the second direction DR2. In addition, the first data line 280 may be disposed adjacent to the third display area DA3 and the fourth display area DA4, and may be arranged parallel to the second direction DR2. However, the first data line 280 may not extend to the area where the gate driver 300 is positioned in the second direction DR2. Specifically, the first data line 280 may not overlap the gate driver 300 in the first direction DR1.

[0097] The gamma driver 100 may be disposed in the non-display area PA and the display area DA. For example, the gamma driver 100 may overlap at least a portion of the first non-display area PA1. In addition, the gamma driver 100 may be disposed in each of the first display area DA1, the second display area DA2, the third display area DA3, and the fourth display area DA4. The gamma driver 100 may be disposed adjacent to one side of the display area DA perpendicular to the other side of the positioning first latch 210. However, the gamma driver 100 may not be disposed in the fifth display area DA5.

[0098] The gamma driver 100 may be spaced apart from each of the data driver 200 and the pixel PX in the second direction DR2 or in a direction opposite to the second direction DR2. For example, the gamma driver 100 may be spaced apart from each of the data driver 200 and the pixel PX in the first display area DA1 and the second display area DA2 in a direction opposite to the second direction DR2. The gamma driver 100 may be spaced apart from each of the data driver 200 and the pixel PX in the third display area DA3 and the fourth display area DA4 in the second direction DR2.

[0099] The gamma driver 100 may be adjacent to the first data line 280. The gamma driver 100 may be spaced apart from the first data line 280 in the second direction DR2. Thus, the gamma driver 100 may transmit or receive an electrical signal to or from the first data line 280.

[0100] Figure 4 It is shown Figure 1 A plan view of the gamma drive in Figure 1. Figure 5 It is shown Figure 1 Circuit diagram of the gamma driver in .

[0101] refer to Figure 4 and Figure 5, the gamma driver 100 may include a gamma voltage generator 120, a gamma amplifier 140, and a gamma output circuit 160. The gamma voltage generator 120 may include a gamma voltage setter 122 and a gamma tap generator 124.

[0102] The gamma voltage setter 122 may receive a first reference voltage VREF1 and a second reference voltage VREF2. The gamma voltage setter 122 may select a high gamma reference voltage VGH and a low gamma reference voltage VGL based on a third control signal CONT3. The high gamma reference voltage VGH may be defined as a gamma reference voltage corresponding to a highest grayscale gamma tap voltage among voltages between the first reference voltage VREF1 and the second reference voltage VREF2. In addition, the low gamma reference voltage VGL may be defined as a gamma reference voltage generated based on a maximum grayscale level of input image data IMG in one frame and a set brightness.

[0103] The gamma voltage setter 122 may include a resistor string Rstring, a first reference selector MUX1, and a second reference selector MUX2. The resistor string Rstring may allocate a first reference voltage VREF1 and a second reference voltage VREF2. The resistor string Rstring may include a plurality of resistors connected in series with each other. The first reference voltage VREF1 and the second reference voltage VREF2 may be applied to both ends of the resistor string Rstring. A plurality of voltages may be allocated and output at contact points of the resistors included in the resistor string Rstring.

[0104] The first reference selector MUX1 may select one of the voltages distributed by the resistor string Rstring as the high gamma reference voltage VGH based on the third control signal CONT3. The first reference selector MUX1 may select the gamma reference voltage VG corresponding to grayscale 0 of the input image data IMG as the high gamma reference voltage VGH. The gamma reference voltage VG corresponding to grayscale 0 may be referred to as a voltage level corresponding to grayscale 0.

[0105] The second reference selector MUX2 may receive a plurality of voltages relatively close to the second reference voltage VREF2 from the resistor string Rstring. The second reference selector MUX2 may select and output a low gamma reference voltage VGL based on the received plurality of voltages and the set brightness. The low gamma reference voltage VGL may correspond to a voltage level of the set brightness. For example, each of the first reference selector MUX1 and the second reference selector MUX2 may be a multiplexer that selects and outputs one of the plurality of input voltages. However, although in Figure 5 Two reference selectors are shown in FIG. 1 , but the present disclosure may not be limited thereto.

[0106] The gamma tap generator 124 may receive the high gamma reference voltage VGH output from the first reference selector MUX1 and the low gamma reference voltage VGL output from the second reference selector MUX2. The gamma tap generator 124 may divide the high gamma reference voltage VGH and the low gamma reference voltage VGL, select an intermediate gamma reference voltage from the divided voltages, and generate and output a gamma tap voltage. That is, the gamma tap generator 124 may generate a gamma tap voltage based on the high gamma reference voltage VGH and the low gamma reference voltage VGL.

[0107] The gamma tap generator 124 may include a plurality of resistor strings Rstring and a plurality of reference selectors MUX. The plurality of resistor strings Rstring may distribute the high gamma reference voltage VGH and the low gamma reference voltage VGL into a plurality of voltage sections. Therefore, the plurality of resistor strings Rstring may be connected to each other in a subordinate manner to distribute the voltage into a plurality of voltage sections.

[0108] The multiple reference selectors MUX may select one of the voltages assigned to each of the multiple resistor strings Rstring based on the multiple gamma tap selection signals. For example, the multiple reference selectors MUX may be a multiplexer that selects one of the multiple input voltages. In this case, the gamma tap selection signal may be selected according to user input or external input, or may be stored during the manufacturing process.

[0109] The gamma amplifier 140 may include a plurality of amplifiers. The gamma amplifier 140 may output a voltage selected from a plurality of reference selectors MUX included in the gamma tap generator 124 as a gamma tap voltage.

[0110] The gamma tap generator 124 and the gamma amplifier 140 may include a plurality of stages. For example, the gamma tap generator 124 and the gamma amplifier 140 may include a stage that outputs a gamma tap voltage. Specifically, when the gamma tap voltage includes a first gamma tap voltage to a tenth gamma tap voltage, the stage may include a first stage to a tenth stage that outputs a gamma tap voltage. The first stage may output a high gamma reference voltage VGH as a first gamma tap voltage. The first gamma tap voltage may correspond to a first gamma reference voltage VG0 having a 0th grayscale level.

[0111] Each of the Kth stages outputting a Kth gamma tap voltage (for example, K is a natural number between 2 and 9) may include a resistor string Rstring, a plurality of reference selectors MUX, and a gamma amplifier included in the gamma amplifier 140. The Kth stage may distribute the first gamma tap voltage and the (K+1)th gamma tap voltage using the resistor string Rstring, select one of the distributed voltages through the reference selector MUX, and output the selected voltage as the Kth gamma tap voltage through the gamma amplifier 140.

[0112] The tenth stage may output the low gamma reference voltage VGL as the tenth gamma tap voltage. For example, the tenth gamma tap voltage may correspond to a 256th gamma reference voltage VG255 having a 255th grayscale.

[0113] The gamma amplifier 140 may amplify and send the amplification to the pixel (eg, Figure 1 and Figure 2 The gamma amplifier 140 may amplify or charge the electrical signal to the pixel PX using the gamma reference voltage VG.

[0114] The gamma output circuit 160 may divide the gamma tap voltage and output the first gamma reference voltage VG0 to the second hundred and fifty-sixth gamma reference voltage VG255. The gamma output circuit 160 may generate the first gamma reference voltage VG0 to the second hundred and fifty-sixth gamma reference voltage VG255 by dividing the gamma tap voltage using a plurality of resistor strings. However, the present disclosure may not be limited to the number of gamma reference voltages generated by the gamma output circuit 160. For example, the gamma output circuit 160 may generate 2048 gamma reference voltages.

[0115] Figure 6 It is shown Figure 3 Block diagram of the data driver in . Figure 7 It is shown Figure 6 Circuit diagram of the shift register in . Figure 8 It is shown Figure 6 Block diagram of the level shifter and digital-to-analog converter in Figure 1. Fig. 9 It is shown Figure 6 Circuit diagram of the digital-to-analog converter in.

[0116] refer to Figure 6 , Figure 7 , Figure 8 and Fig. 9 , the data driver 200 can receive the first data line (eg, Figure 2 The first data line 280 in the embodiment receives a data signal in digital form (eg, Figure 2For example, the data signal in digital form may sequentially pass through the shift register 220, the first latch 210, the second latch 230, the level shifter 260, and the digital-to-analog converter 240, and be output as an analog signal.

[0117] A plurality of shift registers 220 may be connected in series. The shift register 220 may input a horizontal synchronization signal STH and a data clock signal CLK. When the horizontal synchronization signal STH is applied to the shift register 220, the shift register 220 may sequentially shift a sampling signal input according to the data clock signal CLK. For example, since the shift register 220 may shift the horizontal synchronization signal STH within one horizontal period based on the data clock signal CLK, the shift register 220 may sequentially generate a sampling signal.

[0118] The first latch 210 may sequentially sample pixel data for the second control signal CONT2 transmitted from the driving controller CON in response to the sampling signal transmitted from the shift register 220. The first latch 210 may include a sampling latch that stores the pixel data in response to the sampling signal.

[0119] The first latch 210 may be closer to the first data line (eg, Figure 2 Thus, the first latch 210 may receive the first data line (eg, Figure 2 The signal transmitted by the first data line 280).

[0120] The load signal may be applied to the second latch 230. The second latch 230 may store pixel data sampled by the first latch 210 in response to the load signal. The second latch 230 may include a plurality of holding latches corresponding to each of the sampling latches included in the first latch 210.

[0121] The level shifter 260 may change the voltage level of the pixel data output from the second latch 230. For example, the level shifter 260 may shift the voltage level to a level suitable for the digital-to-analog converter 240. The level shifter 260 may include a first level shifter 262, a second level shifter 264, and a third level shifter 266 to increase the voltage level of the pixel data.

[0122] The digital-to-analog converter 240 may perform digital-to-analog conversion on the shifter output signal output from the level shifter 260. Thus, the shifter output signal in a digital form input to the digital-to-analog converter 240 may be converted into an analog signal.

[0123] The gamma driver 100 may output a first gamma reference voltage VGR corresponding to a first color, a second gamma reference voltage VGG corresponding to a second color, and a third gamma reference voltage VGB corresponding to a third color. For example, the first color may be red, the second color may be green, and the third color may be blue.

[0124] The digital-to-analog converter 240 may include a first digital-to-analog converter 242 corresponding to the first color, a second digital-to-analog converter 244 corresponding to the second color, and a third digital-to-analog converter 246 corresponding to the third color.

[0125] The first level shifter 262 may increase the level of the data signal corresponding to the first color. The data signal and the first gamma reference voltage VGR may be matched to generate a first data voltage VD1.

[0126] The second level shifter 264 may increase the level of the data signal corresponding to the second color. The data signal and the second gamma reference voltage VGG may be matched to generate a second data voltage VD2.

[0127] The third level shifter 266 may increase the level of the data signal corresponding to the third color. The data signal and the third gamma reference voltage VGB may be matched to generate a third data voltage VD3. The first data voltage VD1 to the third data voltage VD3 may be output to the first data line (eg, Figure 2 The first data line 280 in FIG.

[0128] The first digital-to-analog converter 242 may include nine transistors. The first digital-to-analog converter 242 may include 128 switches. In addition, the first digital-to-analog converter 242 may include a first grayscale 1GY, a second grayscale 2GY, a third grayscale 3GY, a fourth grayscale 4GY, a fifth grayscale 5GY, a sixth grayscale 6GY, ..., a second hundred and fifty-fifth grayscale 255GY and a second hundred and fifty-sixth grayscale 256GY. However, the present disclosure may not be limited to Fig. 9 The number of transistors, switches, and gray levels shown in .

[0129] The output signal output from the first level shifter 262 may be input to the first digital-to-analog converter 242. In this case, the first digital-to-analog converter 242 may select one of the first grayscale 1GY to the second hundred and fifty-sixth grayscale 256GY. The selected grayscale may generate the first data voltage VD1. However, the present disclosure may not be limited to the first digital-to-analog converter 242, and the second digital-to-analog converter 244 and the third digital-to-analog converter 246 may be substantially the same as the first digital-to-analog converter 242.

[0130] Analog data voltage (e.g. Figure 1The data voltage VD in the first data line (eg, the first data line VD1, the second data line VD2, and the third data line VD3) may be generated. The data voltage VD may be applied to the second data line (eg, Figure 1 The second data line DL in the image is transmitted to the pixel PX through the second data line.

[0131] Fig.10 It is shown Figure 2 A plan view of an enlarged example of the first display area. Fig.11 It is shown Figure 2 A plan view of an enlarged example of area A in FIG. Fig.12 It is shown Figure 2 A plan view of the fifth display area in FIG.

[0132] In the following, the references will be omitted or simplified. Figure 2 and Figure 3 Descriptions of descriptions overlap descriptions.

[0133] refer to Fig.10 and Fig.11 , a demux circuit 250 may be disposed in the first display area DA1. The demux circuit 250 may be disposed adjacent to one side of the first display area DA1 facing the first direction DR1.

[0134] In an implementation, the first latch 210, the pixel PX, the shift register 220, the pixel PX, the second latch 230, the pixel PX, the digital-to-analog converter 240, the pixel PX, and the demultiplexing circuit 250 may be sequentially arranged in this order in the first direction DR1.

[0135] The demultiplexing circuit 250 may include a plurality of demultiplexing switches. The demultiplexing circuit 250 may receive a data voltage (eg, Figure 1 The demultiplexing circuit 250 may time-divide the data voltage and apply the data voltage to the second data line (eg, Figure 1 For example, the demultiplexing circuit 250 may time-divide the data voltage through a switching operation of the demultiplexing switch and apply the data voltage to the second data line.

[0136] The plurality of D / A converters 240 may be arranged in a direction opposite to the direction from the second latch 230 to the shift register 220. As described above, the D / A converters 240 may include first to third D / A converters (eg, Figure 8244 and the third digital-to-analog converter 246 in the first display area DA1). For example, the first digital-to-analog converter, the second digital-to-analog converter and the third digital-to-analog converter may be alternately arranged in the first direction DR1. Specifically, a plurality of units consisting of the first digital-to-analog converter, the second digital-to-analog converter and the third digital-to-analog converter in sequence may be arranged from the second latch 230 in the first display area DA1 in the first direction DR1. However, the present disclosure may not be limited to the arrangement order of the first digital-to-analog converter to the third digital-to-analog converter.

[0137] The gamma voltage generator 120 may be disposed in the first display area DA1 and may be spaced apart from each of the pixel PX, the first latch 210, the shift register 220, the second latch 230, and the digital-to-analog converter 240 in the second direction DR2.

[0138] The gamma amplifier 140 may be disposed in the first non-display area PA1. The gamma amplifier 140 may be disposed in the first non-display area PA1 adjacent to one side of the first display area DA1 facing in a direction opposite to the second direction DR2. That is, the gamma amplifier 140 may be disposed adjacent to the first display area DA1. Therefore, the gamma amplifier 140 may also be used as an amplifier that amplifies a signal transmitted from the digital-to-analog converter 240 to the pixel PX.

[0139] The first data line 280 may be disposed on one side of the first display area DA1 and adjacent to the gamma amplifier 140. The first data line 280 may be disposed adjacent to the first latch 210 and the gamma amplifier 140. Since the first data line 280 is disposed adjacent to the first latch 210, the digital data signal transmitted through the first data line 280 may be transmitted to the first latch 210 faster than to the shift register 220.

[0140] Despite Fig.10 and Fig.11 Only the first display area DA1 is shown in FIG. 1 , but the second to fourth display areas (eg, Figure 2 The second display area DA2, the third display area DA3 and the fourth display area DA4) may be substantially the same as the first display area DA1.

[0141] refer to Fig.12, the fifth display area DA5 may be an area in which a data driver (e.g., the data driver 200) may not be disposed. The pixels PX disposed in the first to fourth display areas DA1 to DA4 may be disposed between elements (e.g., the shift register 220, the second latch 230, and the digital-to-analog converter 240) of the data driver 200 in the first direction DR1. In an embodiment, a gap between pixels PX disposed in the first, second, third, and fourth display areas DA1, DA2, DA3, and DA4 in the first direction DR1 may be relatively longer than a gap between pixels PX disposed in the fifth display area DA5 in the first direction DR1 because no elements (e.g., the shift register 220, the second latch 230, and the digital-to-analog converter 240) of the data driver 200 are located between the pixels PX disposed in the fifth display area DA5 in the first direction DR1.

[0142] In the display device 10 according to an embodiment of the present disclosure, the data driver 200 may be disposed in the display area DA of the display device 10. Therefore, a separate area in which the data driver 200 is disposed may not be required, the integration density of semiconductor chips included in the display device 10 may be increased, and the area of ​​the display area DA may be increased.

[0143] Furthermore, the first data line 280 may be disposed in the first non-display area PA1, and the first latch 210 may be disposed adjacent to the first data line 280 at the outermost portion of the display area DA. Therefore, the first latch 210 may quickly store a digital data signal received from the first data line 280.

[0144] Fig.13 It is shown Figure 2 A plan view of another enlarged example of the first display area in FIG. Fig.14 It is shown Figure 2 A plan view of another enlarged example of area A in FIG.

[0145] In addition to the arrangement of the gamma voltage generator 120 ′, refer to Fig.13 and Fig.14 The display device described and the reference Fig.11 and Fig.12 The display devices described are essentially the same.

[0146] In the following, the references will be omitted or simplified. Fig.11 and Fig.12 Describes the components of a display device that overlay content.

[0147] refer to Fig.13 and Fig.14, the gamma voltage generator 120' may be disposed in the first non-display area PA1. The gamma voltage generator 120' may be disposed adjacent to one side of the first display area DA1 facing in a direction opposite to the second direction DR2. That is, the gamma voltage generator 120' may not be disposed in the first display area DA1. However, the present disclosure may not be limited thereto.

[0148] Fig.15 It is shown Figure 2 A plan view of yet another enlarged example of the first display area in FIG.

[0149] In addition to the arrangement of the level shifter 260, reference Fig.15 The display device described and the reference Fig.11 and Fig.12 The display devices described are essentially the same.

[0150] In the following, the references will be omitted or simplified. Fig.11 and Fig.12 Describes the components of a display device that overlay content.

[0151] refer to Fig.15 , the level shifter 260 may be disposed in the first display area DA1. The level shifter 260 may be disposed between the second latch 230 and the digital-to-analog converter 240. The level shifter 260 may be disposed between the pixel PX adjacent to the second latch 230 in the first direction DR1 and the pixel PX adjacent to the digital-to-analog converter 240 in the direction opposite to the first direction DR1.

[0152] In the first display area DA1, the first latch 210, the pixel PX, the shift register 220, the pixel PX, the second latch 230, the pixel PX and the level shifter 260, the pixel PX, the digital-to-analog converter 240, the pixel PX and the demultiplexing circuit 250 may be sequentially arranged in the first direction DR1.

[0153] Despite Fig.15 The first display area DA1 is shown in the figure, but the second to fourth display areas (for example, the second display area DA2, the third display area DA3, and the fourth display area DA4) may also be substantially the same as the first display area DA1.

[0154] The display device according to the embodiment may be applied to devices included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, and the like.

[0155] Although the display device according to the embodiment has been described with reference to the accompanying drawings, the illustrated embodiment is an example and may be modified and changed by a person of ordinary skill in the relevant technical field without departing from the technical spirit described in the appended claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area adjacent to the display area; A plurality of data drivers are disposed in the display area on the substrate and each includes: A first latch is disposed adjacent to a side of the display area facing the non-display area; a shift register spaced apart from the first latch in a first direction and outputting output signals in sequence; and a second latch spaced apart from the shift register in the first direction; a plurality of pixels disposed in the display region on the substrate and disposed between mutually adjacent elements of the data driver, wherein the elements include the first latch, the shift register, and the second latch; and A plurality of first data lines are disposed in the non-display area on the substrate, are adjacent to the first latch, are connected to the data driver, and are applied with data signals in a digital form.

2. The display device according to claim 1, further comprising: a gamma driver overlapping at least a portion of the non-display area and spaced apart from the data driver and each of the pixels in a second direction intersecting the first direction; Wherein, the gamma driver comprises: a gamma voltage generator overlapping the display area; and A gamma amplifier overlaps at least a portion of the non-display area and is adjacent to the gamma voltage generator.

3. The display device according to claim 2, wherein: The gamma voltage generator is spaced apart from the data driver and each of the pixels in the second direction, and The gamma voltage generator and the gamma amplifier are spaced apart from each other in the second direction.

4. The display device according to claim 1, wherein: The display area includes: a first display area, a second display area, a third display area, and a fourth display area, which are located at the outermost edge of the display area and are spaced apart from each other; and a fifth display area, located between the first display area, the second display area, the third display area and the fourth display area, wherein the pixel overlaps with the first display area, the second display area, the third display area, the fourth display area and the fifth display area, and The first latch, the second latch, and the shift register overlap with the first display area, the second display area, the third display area, and the fourth display area, but do not overlap with the fifth display area.

5. The display device according to claim 1, wherein: The display area includes: a first display area, a second display area, a third display area, and a fourth display area, which are located at the outermost edge of the display area and are spaced apart from each other; and a fifth display area, located between the first display area, the second display area, the third display area and the fourth display area, The element of the data driver is disposed between the pixels, and further comprises a plurality of digital-to-analog converters and a multiplexing circuit overlapping the first display area, the second display area, the third display area and the fourth display area.

6. The display device according to claim 5, wherein: The multiplexing circuit is disposed adjacent to the fifth display area.

7. The display device according to claim 5, wherein: The pixels are arranged in a second direction intersecting the first direction, and The digital-to-analog converters and the pixels are arranged alternately in the first direction.

8. The display device according to claim 1, further comprising: an encapsulation layer disposed on the pixel and the data driver and overlapping the display area and the non-display area, and Wherein, the non-display area includes: a first non-display area overlapping the encapsulation layer; and The second non-display area does not overlap with the encapsulation layer. Wherein, the first data line overlaps with the first non-display area.

9. A display device, comprising: A substrate including a display area and a non-display area adjacent to the display area, and comprising a silicon wafer; A plurality of data drivers are disposed in the display area on the substrate and each includes: A first latch is disposed adjacent to a side of the display area facing the non-display area; a shift register spaced apart from the first latch in a first direction and outputting output signals in sequence; and a second latch spaced apart from the shift register in the first direction; a plurality of pixels disposed in the display area on the substrate and disposed between mutually adjacent elements of the data driver, wherein the elements include the first latch, the shift register, and the second latch; a plurality of first data lines disposed in the non-display area on the substrate, adjacent to the first latch, and applied with data signals in digital form; and A plurality of second data lines are electrically connected to the data driver and the pixels and are applied with data voltages in an analog form.

10. The display device according to claim 9, further comprising: a gamma driver overlapping at least a portion of the non-display area and spaced apart from the data driver and each of the pixels in a second direction intersecting the first direction; Wherein, the gamma driver comprises: a gamma voltage generator overlapping the display area; and A gamma amplifier overlaps at least a portion of the non-display area and is adjacent to the gamma voltage generator.

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