Display apparatus and operating method for a display apparatus

Abstract

A display device and an operating method for the display device are provided. The display device includes a pixel array, a multiplexer circuit, and a holding circuit. The pixel array includes a first pixel column and a second pixel column. The multiplexer circuit provides a first data signal to the first pixel column in a first period and provides a second data signal to the second pixel column in a second period. The holding circuit provides a reference signal to the second pixel column in the first period to hold the second pixel column at a display result in a previous period, and provides the reference signal to the first pixel column in the second period to hold the first pixel column at a display result in the first period.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an electronic device and an operating method for the electronic device, and more particularly, to a display device and an operating method for the display device. BACKGROUND

[0002] The display device includes a plurality of pixel columns and a multiplexer. The multiplexer is coupled to a first pixel column and a second pixel column among the plurality of pixel columns. The multiplexer provides a data signal to the first pixel column and causes the second pixel column not to receive the data signal in a frame period. Thus, when the first pixel column among the plurality of pixel columns is driven in response to the data signal, the second pixel column adjacent to the first pixel column maintains a display result according to a data signal of a previous frame period.

[0003] However, in the above-described display architecture, the data signal of the previous frame period can be changed due to a leakage or interference of other data signals. Thus, the display result maintained by the second pixel column is changed. As such, how to ensure that a pixel column can maintain a display result in a previous frame period is one of the focuses of the person skilled in the art based on the above-described display architecture. SUMMARY

[0004] The present disclosure provides a display device and an operating method for the display device, which can ensure that a pixel column of the display device maintains a display result in a previous period.

[0005] The display device of the present disclosure includes a pixel array, a multiplexer circuit, and a holding circuit. The pixel array includes a first pixel column and a second pixel column. The multiplexer circuit is coupled to the first pixel column and the second pixel column. The multiplexer circuit provides a first data signal to the first pixel column in a first period and provides a second data signal to the second pixel column in a second period. The holding circuit is coupled to the first pixel column and the second pixel column. The holding circuit provides a reference signal to the second pixel column in the first period to cause the second pixel column to maintain a display result in a previous period, and provides the reference signal to the first pixel column in the second period to cause the first pixel column to maintain a display result in the first period.

[0006] The operating method of the present disclosure is for a display device. The display device includes a pixel array. The pixel array includes a first pixel column and a second pixel column. The operating method includes: providing a first data signal to the first pixel column in a first period and providing a reference signal to the second pixel column in the first period to cause the second pixel column to maintain a display result in a previous period; and providing a second data signal to the second pixel column in a second period and providing the reference signal to the first pixel column in the second period to cause the first pixel column to maintain a display result in the first period.

[0007] Based on the above, in the first period, the display result of the second pixel column in the previous period can be maintained based on the reference signal. In the second period, the display result of the first pixel column in the first period can be maintained based on the reference signal. In this way, the display device of the present application can ensure that the pixel column maintains the display result in the previous period. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic diagram of a display device according to an embodiment of the present application;

[0009] Figure 2 is a circuit schematic diagram of a display device according to a first embodiment of the present application;

[0010] Figure 3 is a signal timing diagram according to an embodiment of the present application;

[0011] Figure 4 is a circuit schematic diagram of a display device according to a second embodiment of the present application;

[0012] Figure 5 is a flowchart of an operation method according to an embodiment of the present application.

[0013] REFERENCE SIGNS

[0014] 100, 200, 200’: display device

[0015] 110, 210: pixel array

[0016] 120, 220: multiplexer circuit

[0017] 130, 230: holding circuit

[0018] DU1_1, DU1_2, DU2_1, DU2_2: display unit

[0019] E1: first side

[0020] E2: second side

[0021] F1: first frame period

[0022] F2: second frame period

[0023] P1_1-P1_n, P2_1-P2_n: pixel circuit

[0024] PC1, PC2: pixel column

[0025] S100: operation method

[0026] S110, S120: step

[0027] SC1-SC4: switch control signal

[0028] SD1, SD1_1-SD1_n, SD2, SD2_1-SD2_n: data signal

[0029] SG1-SGn: scan signal

[0030] SS1_1, SS1_2, SS2_1, SS2_2: selection circuit

[0031] ST1-STn: display period

[0032] SW1, SW2: selection switch

[0033] SW3, SW4: holding switch

[0034] VREF: reference signal DETAILED DESCRIPTION

[0035] Some embodiments of the present application will be described in detail with reference to the drawings, wherein like reference numerals refer to like elements throughout. The embodiments are merely exemplary and do not represent all embodiments of the present application. Indeed, the present application is intended to encompass a variety of alternatives, modifications and equivalents. For example, it is intended that the listing of features describing the application is inclusive of replacement of some equivalents of some features by other

[0036] Reference will now be made to Figure 1 , Figure 1 is a schematic diagram of a display device according to an embodiment of the present application. In this embodiment, the display device 100 includes a pixel array 110, a multiplexer circuit 120, and a holding circuit 130. The pixel array 110 includes at least pixel columns PC1, PC2. In this embodiment, the pixel column PC1 includes a plurality of pixel circuits arranged in a column direction. The pixel column PC2 includes a plurality of pixel circuits arranged in a column direction.

[0037] In this embodiment, the multiplexer circuit 120 is coupled to the pixel columns PC1, PC2. In a first frame period, the multiplexer circuit 120 provides a data signal SD1 to the pixel column PC1. In a second frame period, the multiplexer circuit 120 provides a data signal SD2 to the pixel column PC2.

[0038] In the embodiment, the holding circuit 130 is coupled to the pixel columns PC1, PC2. In the first frame period, the holding circuit 130 provides the reference signal VREF to the pixel column PC2 to hold the display result of the pixel column PC2 in the previous frame period. In the second frame period, the holding circuit 130 provides the reference signal VREF to the pixel column PC1 to hold the display result of the pixel column PC1 in the first frame period. The frame period can also be a specific period (time interval). The period described in the present application is not limited to the frame period.

[0039] It is worth mentioning here that the holding circuit 130 uses the reference signal VREF to hold the display result of the pixel column PC2 in the previous frame period in the first frame period. In the second frame period, the holding circuit 130 uses the reference signal VREF to hold the display result of the pixel column PC1 in the previous frame period. The holding circuit 130 can ensure that the pixel columns PC1, PC2 maintain the display result in the previous frame period. In this way, the pixel columns PC1, PC2 will not be changed due to long-time power leakage or interference by other data signals.

[0040] In the embodiment, the pixel columns PC1, PC2 can be a pair of adjacent pixel columns. The data signals SD1, SD2 can be the same as each other or different from each other.

[0041] For example, the display device 100 can be a bistable display (but the present application is not limited thereto). The display device 100 can be an electro-phoretic display (EPD). The pixel columns PC1, PC2 are adjacent to each other. The pixel column PC1 receives the data signal SD1 in the first frame period. The pixel column PC2 receives the reference signal VREF in the first frame period. Therefore, in the first frame period, the display result of the pixel column PC2 can be maintained without being interfered by the data signal SD1. The reference signal VREF can be a reference low-voltage signal (for example, a ground or a voltage signal with 0 volts).

[0042] The pixel column PC2 receives the data signal SD2 in the second frame period. The pixel column PC1 receives the reference signal VREF in the second frame period. Therefore, in the second frame period, the display result of the pixel column PC1 can be maintained without being interfered by the data signal SD2.

[0043] Please refer to Figure 2 , Figure 2is a circuit schematic diagram of a display device according to the first embodiment of the present application. In the present embodiment, the display device 200 includes a pixel array 210, a multiplexer circuit 220, and a holding circuit 230. The pixel array 210 includes at least pixel columns PC1, PC2. In the present embodiment, the pixel column PC1 includes pixel circuits P1_1 ~ P1_n. The pixel column PC2 includes pixel circuits P2_1 ~ P2_n.

[0044] In the present embodiment, the multiplexer circuit 220 is coupled to the pixel columns PC1, PC2. The multiplexer circuit 220 includes at least selection switches SW1, SW2. A first terminal of the selection switch SW1 receives one of data signals SD1_1 ~ SD1_n in a first frame period. A second terminal of the selection switch SW1 is coupled to the pixel column PC1. A control terminal of the selection switch SW1 receives a switch control signal SC1. A first terminal of the selection switch SW2 receives one of data signals SD2_1 ~ SD2_n in a second frame period. A second terminal of the selection switch SW2 is coupled to the pixel column PC2. A control terminal of the selection switch SW2 receives a switch control signal SC2. In the present embodiment, the data signals SD1_1 ~ SD1_n, SD2_1 ~ SD2_n are provided by a data driving circuit (although the present application is not limited thereto).

[0045] In the present embodiment, the holding circuit 230 is coupled to the pixel columns PC1, PC2. The holding circuit 230 includes at least holding switches SW3, SW4. A first terminal of the holding switch SW3 receives a reference signal VREF. A second terminal of the holding switch SW3 is coupled to the pixel column PC1. A control terminal of the holding switch SW3 receives a switch control signal SC3. A first terminal of the holding switch SW4 receives the reference signal VREF. A second terminal of the holding switch SW4 is coupled to the pixel column PC2. A control terminal of the holding switch SW4 receives a switch control signal SC4.

[0046] In the present embodiment, the multiplexer circuit 220 is located at a first side E1 of the pixel array 210. The holding circuit 230 is located at a second side E2 of the pixel array 210. The first side E1 is different from the second side E2. For example, the first side E1 and the second side E2 are opposite to each other (although the present application is not limited thereto).

[0047] In the present embodiment, the selection switches SW1, SW2 and the holding switches SW3, SW4 are implemented by N-type field effect transistors or N-type thin film transistors. In some embodiments, the selection switches SW1, SW2 and the holding switches SW3, SW4 are implemented by P-type field effect transistors or P-type thin film transistors.

[0048] In this embodiment, the pixel circuits P1_1, P2_1 are located in the same row. The pixel circuit P1_1 includes a selection circuit SS1_1 and a display unit DU1_1. The first terminal of the selection circuit SS1_1 is coupled to the second terminal of the selection switch SW1 and the second terminal of the holding switch SW3. The second terminal of the selection circuit SS1_1 is coupled to the display unit DU1_1. The control terminal of the selection circuit SS1_1 receives the scan signal SG1. The pixel circuit P2_1 includes a selection circuit SS2_1 and a display unit DU2_1. The first terminal of the pixel circuit P2_1 is coupled to the second terminal of the selection switch SW2 and the second terminal of the holding switch SW4. The second terminal of the selection circuit SS2_1 is coupled to the display unit DU2_1. The control terminal of the selection circuit SS2_1 receives the scan signal SG1. In some embodiments, the pixel circuits P1_1, P2_1 can be regarded as a pixel pair.

[0049] The pixel circuits P1_2, P2_2 are located in the same row. The pixel circuit P1_2 includes a selection circuit SS1_2 and a display unit DU1_2. The first terminal of the selection circuit SS1_2 is coupled to the second terminal of the selection switch SW1 and the second terminal of the holding switch SW3. The second terminal of the selection circuit SS1_2 is coupled to the display unit DU1_2. The control terminal of the selection circuit SS1_2 receives the scan signal SG2. The pixel circuit P2_2 includes a selection circuit SS2_2 and a display unit DU2_2. The first terminal of the pixel circuit P2_2 is coupled to the second terminal of the selection switch SW2 and the second terminal of the holding switch SW4. The second terminal of the selection circuit SS2_2 is coupled to the display unit DU2_2. The control terminal of the selection circuit SS2_2 receives the scan signal SG2. In some embodiments, the pixel circuits P1_2, P2_2 can be regarded as a pixel pair.

[0050] In this embodiment, the pixel circuits P1_n, P2_n are located in the same row. In some embodiments, the pixel circuits P1_n, P2_n can be regarded as a pixel pair.

[0051] In this embodiment, the selection circuits SS1_1, SS1_2, SS2_1, SS2_2 are respectively implemented by N-type field effect transistors or N-type thin film transistors. In some embodiments, the selection circuits SS1_1, SS1_2, SS2_1, SS2_2 are respectively implemented by P-type field effect transistors or P-type thin film transistors.

[0052] For example, the display device 200 can be an electrophoretic display (the present application is not limited thereto). The display units DU1_1, DU1_2, DU2_1, DU2_2 can be display components having a plurality of electrophoretic microcapsules, respectively. The electrophoretic microcapsules can be electrophoretic particles having a specific color. The "specific color" can be black, white, or other colors. The display units DU1_1, DU1_2, DU2_1, DU2_2 generate electrophoretic polarities according to voltage values of the received data signals, respectively, and move the plurality of electrophoretic microcapsules using the electrophoretic polarities to provide display results corresponding to the data signals. In addition, voltage values of the reference signals VREF do not change the electrophoretic polarities. Therefore, the display units DU1_1, DU1_2, DU2_1, DU2_2 maintain the display results in the previous frame period according to the reference signals VREF, respectively.

[0053] Please refer to Figure 2 and Figure 3 , Figure 3 is a signal timing diagram according to an embodiment of the present application. In the first frame period F1, the switch control signals SC1, SC4 have high voltage levels. The switch control signals SC2, SC3 have low voltage levels. Therefore, the selection switch SW1 and the sustain switch SW4 are turned on. The selection switch SW2 and the sustain switch SW3 are turned off.

[0054] During the display period ST1 of the first frame period F1, the scan signal SG1 has a high voltage level. Therefore, the pixel circuits P1_1, P2_1 located in the same row are selected by the selection switch based on the scan signal SG1. The selection circuits SS1_1, SS2_1 are turned on. During the display period ST1 of the first frame period F1, the pixel circuit P1_1 operates in response to the data signal SD1_1 to change the first cell picture of the display unit DU1_1. The display unit DU1_1 provides a display result according to the data signal SD1_1. In addition, the pixel circuit P2_1 maintains the cell picture in the previous frame period in response to the reference signal VREF. The voltage value of the reference signal VREF is not enough to change the display result. Therefore, the display unit DU2_1 maintains the display result in the previous frame period according to the reference signal VREF.

[0055] During the display period ST2 of the first frame period Fl, the scan signal SG2 has a high voltage level. Therefore, the pixel circuits P1_2, P2_2 in the same row are selected by the scan signal SG2. The selection circuits SS1_2, SS2_2 are turned on. During the display period ST2 of the first frame period Fl, the pixel circuit P1_2 operates in response to the data signal SD1_2. The display unit DU1_2 provides a display result according to the data signal SD1_2. In addition, the pixel circuit P2_2 maintains the display result in the previous frame period in response to the reference signal VREF. The display unit DU2_2 maintains the display result in the previous frame period according to the reference signal VREF.

[0056] During the display period STn of the first frame period Fl, the scan signal SGn has a high voltage level. Therefore, the pixel circuits P1_n, P2_n in the same row are selected by the scan signal SGn. The pixel circuit P1_n operates in response to the data signal SD1_n. The pixel circuit P2_n maintains the display result in the previous frame period in response to the reference signal VREF.

[0057] During the second frame period F2, the switch control signals SCI, SC4 have low voltage levels. The switch control signals SC2, SC3 have high voltage levels. Therefore, the selection switch SW1 and the holding switch SW4 are turned off. The selection switch SW2 and the holding switch SW3 are turned on.

[0058] During the display period ST1 of the second frame period F2, the scan signal SG1 has a high voltage level. Therefore, the pixel circuits P1_1, P2_1 in the same row are selected by the scan signal SG1. The selection circuits SS1_1, SS2_1 are turned on. During the display period ST1 of the second frame period F2, the pixel circuit P2_1 operates in response to the data signal SD2_1 to change the second sub-picture of the display unit DU2_1. The display unit DU2_1 provides a display result according to the data signal SD2_1. In addition, the pixel circuit P1_1 maintains the first sub-picture in the first frame period Fl in response to the reference signal VREF. The display unit DU2_1 maintains the display result in the first frame period Fl according to the reference signal VREF.

[0059] During the display period ST2 of the second frame time period F2, the scan signal SG2 has a high voltage level. Therefore, the pixel circuits P1_2 and P2_2 located in the same row are selected based on the scan signal SG2. The selection circuits SS1_2 and SS2_2 are turned on. During the display period ST2 of the second frame time period F2, the pixel circuit P2_2 operates in response to the data signal SD2_2. The display unit DU2_2 provides the display result according to the data signal SD2_2. In addition, the pixel circuit P1_2 maintains the display result in the first frame time period F1 in response to the reference signal VREF. The display unit DU2_2 maintains the display result in the first frame time period F1 according to the reference signal VREF.

[0060] During the display period STn of the second frame time period F2, the scan signal SGn has a high voltage level. Therefore, the pixel circuits P1_n and P2_n located in the same row are selected based on the scan signal SGn. During the display period STn of the second frame time period F2, the pixel circuit P2_n operates in response to the data signal SD2_n. In addition, the pixel circuit P1_n responds to the reference signal VREF to maintain the display result in the first frame time period F1.

[0061] In this embodiment, the scan signals SG1 to SGn are provided by the gate driving circuit (however, the present invention is not limited thereto).

[0062] Please refer to Figure 4 , Figure 4 This is a circuit diagram of a display device according to a second embodiment of the present invention. In this embodiment, the display device 200' includes a pixel array 210, a multiplexer circuit 220, and a holding circuit 230. The circuit implementations of the pixel array 210, the multiplexer circuit 220, and the holding circuit 230 have already been described. Figure 2 as well as Figure 3 The embodiments are clearly illustrated and will not be repeated here. Figure 2 The difference is that the multiplexer circuit 220 and the holding circuit 230 of the display device 200' are located on the same side of the pixel array 210. For example, the multiplexer circuit 220 and the holding circuit 230 are located on the first side E1 of the pixel array 210 (however, the invention is not limited thereto). Therefore, other sides of the display device 200' other than the first side E1 are allowed to have narrow bezels.

[0063] In this embodiment, the holding circuit 230 is disposed between the pixel array 210 and the multiplexer circuit 220. In some embodiments, the multiplexer circuit 220 is disposed between the pixel array 210 and the holding circuit 230.

[0064] Please also refer to Figure 1 as well asFigure 5 , Figure 5 is a flowchart of an operation method according to an embodiment of the present application. In this embodiment, the operation method S100 is used for the display device 100. The operation method S100 includes steps S110, S120. In step S110, in a first frame period, the multiplexer circuit 120 provides the data signal SD1 to the pixel column PC1. In addition, in the first frame period, the holding circuit 130 provides the reference signal VREF to the pixel column PC2 to hold the pixel column PC2 at the display result in a previous frame period.

[0065] In step S120, in a second frame period, the multiplexer circuit 120 provides the data signal SD2 to the pixel column PC2. In addition, in the second frame period, the holding circuit 130 provides the reference signal VREF to the pixel column PC1 to hold the pixel column PC1 at the display result in the first frame period.

[0066] The operation method S100 can also be applied to the display device 200 as shown in Figure 2 and the display device 200' as shown in Figure 4 .

[0067] The implementation details of steps S110, S120 can be sufficiently taught in the embodiments of Figures 1 to 3 and thus are not repeated here.

[0068] In summary, the display device uses the reference signal VREF to hold the pixel column in the pixel array at the display result in the previous frame period. In this way, the pixel column will not be changed in the display result due to long-time leakage or interference from other data signals.

[0069] Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, and thus the scope of protection of the present application shall be subject to the appended claims.

Claims

1.A display apparatus, comprising: a pixel array including a first pixel column and a second pixel column; a multiplexer circuit coupled to the first pixel column and the second pixel column, and configured to provide a first data signal to the first pixel column in a first time period and to provide a second data signal to the second pixel column in a second time period; and a holding circuit coupled to the first pixel column and the second pixel column, and configured to provide a reference signal to the second pixel column in the first time period to hold a display result of the second pixel column in a previous time period, and to provide the reference signal to the first pixel column in the second time period to hold a display result of the first pixel column in the first time period, wherein the holding circuit includes a first holding switch and a second holding switch, wherein in the first time period, the second holding switch is turned on to provide the reference signal to the second pixel column, and the first holding switch is turned off, wherein in the second time period, the first holding switch is turned on to provide the reference signal to the first pixel column, and the second holding switch is turned off, and wherein the reference signal is a voltage signal having a fixed low voltage level. 2.The display apparatus of claim 1, wherein the multiplexer circuit includes: a first selection switch having a first end receiving the first data signal in the first time period, a second end coupled to the first pixel column, and a control end receiving a first switch control signal; and a second selection switch having a first end receiving the second data signal in the second time period, a second end coupled to the second pixel column, and a control end receiving a second switch control signal. 3.The display apparatus of claim 2, wherein: the first holding switch has a first end receiving the reference signal, a second end coupled to the first pixel column, and a control end receiving a third switch control signal; and the second holding switch has a first end receiving the reference signal, a second end coupled to the second pixel column, and a control end receiving a fourth switch control signal. 4.The display apparatus of claim 3, wherein in the first time period, the first selection switch is turned on, and the second selection switch is turned off. 5.The display apparatus of claim 3, wherein in the second time period, the first selection switch is turned off, and the second selection switch is turned on. 6.The display apparatus of claim 1, wherein: the first pixel column includes a first pixel circuit, and the first pixel circuit is selected by a selection switch based on a scan signal, and changes a first cell picture of a corresponding display cell in the first time period in response to the first data signal, and holds the first cell picture in the first time period in response to the reference signal in the second time period. ​ ​ ​ 7.The display apparatus of claim 6, wherein: the second pixel column comprises a second pixel circuit, the second pixel circuit and the first pixel circuit are located in a same row, and the second pixel circuit is selected by the second pixel circuit based on the scan signal to change a second cell picture of a corresponding display cell in the second time period in response to the second data signal, and to maintain another cell picture in a previous time period in the first time period in response to the reference signal. 8.The display apparatus of claim 1, wherein the multiplexer circuit and the holding circuit are located at a same side of the pixel array. 9.The display apparatus of claim 1, wherein: the multiplexer circuit is located at a first side of the pixel array, the holding circuit is located at a second side of the pixel array, and the first side is different from the second side. 10.An operation method for a display apparatus, wherein the display apparatus comprises a pixel array, wherein the pixel array comprises a first pixel column and a second pixel column, wherein the operation method comprises: providing a first data signal to the first pixel column in a first time period, and providing a reference signal to the second pixel column in the first time period to maintain a display result in a previous time period; and providing a second data signal to the second pixel column in a second time period, and providing the reference signal to the first pixel column in the second time period to maintain a display result in the first time period, wherein the display apparatus further comprises a holding circuit, wherein the holding circuit comprises a first holding switch and a second holding switch, wherein the operation method comprises: in the first time period, turning on the second holding switch to provide the reference signal to the second pixel column, and turning off the first holding switch; and in the second time period, turning on the first holding switch to provide the reference signal to the first pixel column, and turning off the second holding switch, wherein the reference signal is a voltage signal with a fixed low voltage level. ​

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