Digital lock-in amplifier, signal processing system, and signal processing method

Abstract

The present invention provides a digital lock-in amplifier, a signal processing system and a signal processing method, which can be applied to the field of signal measurement technology. The digital lock-in amplifier includes: a sampling circuit configured to sample a plurality of cycles of a signal to be measured from a signal input end to obtain a plurality of cycles of digital signals; each cycle of digital signals includes a plurality of signal pulses; a signal processing circuit configured to: under the control of a control signal received via a control end, down-convert the plurality of cycles of digital signals to obtain a down-converted signal; slice the down-converted signal to obtain a sliced signal, and determine the pulse slicing time information of the sliced signal; each sliced signal includes a single signal pulse; based on a reference signal and the sliced signal, determine the amplitude signal of the sliced signal; and send the amplitude signal and the pulse slicing time information to a terminal device, so that the terminal device generates a signal waveform diagram of the signal to be measured according to the pulse slicing time information and the amplitude signal.

Description

Technical Field

[0001] The present invention relates to the technical field of signal measurement, and particularly to a digital lock-in amplifier, a signal processing system, and a signal processing method. Background Art

[0002] The lock-in amplifier has characteristics such as a narrow passband, a stable center frequency, a high quality factor, and a high signal-to-noise ratio. For different types of signals to be detected, the lock-in amplifier is widely used in different scenarios. A digital lock-in amplifier refers to a lock-in amplifier that implements functional components in a digital manner. However, after a multi-period multi-pulse signal is input into the digital lock-in amplifier, the output signal of the digital lock-in amplifier is difficult to be used to display the overall morphology of the signal. Summary of the Invention

[0003] In view of the above problems, the present invention provides a digital lock-in amplifier, a signal processing system, and a signal processing method.

[0004] According to a first aspect of the present invention, there is provided a digital lock-in amplifier, including: a sampling circuit, including a signal input end, configured to sample a plurality of periods of a signal to be measured from the signal input end to obtain a plurality of periods of digital signals; each period of digital signal includes a plurality of signal pulses; a signal processing circuit, connected to the sampling circuit and a terminal device, configured to: under the control of a control signal received via a control end, down-convert the plurality of periods of digital signals to obtain a down-converted signal; slice the down-converted signal to obtain a sliced signal, and determine the pulse slicing time information of the sliced signal; each sliced signal includes a single signal pulse; based on a reference signal and the sliced signal, determine the amplitude signal of the sliced signal; send the amplitude signal and the pulse slicing time information to the terminal device, so that the terminal device generates a signal waveform diagram of the signal to be measured according to the pulse slicing time information and the amplitude signal.

[0005] According to an embodiment of the present invention, the signal processing circuit is further configured to: under the control of the control signal, down-convert the plurality of periods of digital signals by caching the plurality of periods of digital signals; the period of the control signal is the same as the period of the plurality of periods of the signal to be measured.

[0006] According to an embodiment of the present invention, the sampling circuit includes a plurality of signal channels, and the sampling circuit is further configured to output a plurality of periods of digital signals in parallel via the plurality of signal channels; the signal processing circuit includes: a serial-parallel conversion unit, connected to the sampling circuit via the plurality of signal channels, configured to cache the plurality of periods of parallel digital signals under the control of the control signal to obtain an intermediate down-converted signal, and output the intermediate down-converted signal in a serial manner; a caching unit, connected to the serial-parallel conversion unit, configured to cache the intermediate down-converted signal to obtain a down-converted signal.

[0007] According to an embodiment of the present invention, the signal processing circuit further includes: a reference signal generating unit configured to generate a reference signal, the frequency of the reference signal being the same as the frequency of the down-converted signal; a processing unit connected to the reference signal generating unit and configured to extract the amplitude signal of the sliced signal according to the frequency of the reference signal.

[0008] According to an embodiment of the present invention, the processing unit includes: a quadrature phase discrimination sub-unit configured to extract the initial amplitude signal of the sliced signal according to the frequency of the reference signal; and a low-pass filtering sub-unit connected to the quadrature phase discrimination sub-unit and configured to filter the initial amplitude signal at a predetermined frequency to obtain the amplitude signal.

[0009] According to an embodiment of the present invention, the above digital lock-in amplifier further includes: a crystal oscillation circuit configured to generate an initial clock signal; the signal processing circuit further includes a phase-locked loop unit connected to the crystal oscillation circuit and configured to perform frequency division processing on the initial clock signal to obtain an intermediate clock signal and perform frequency multiplication on the intermediate clock signal to obtain a first clock signal; the reference signal generating unit is further connected to the phase-locked loop unit and is further configured to generate a reference signal according to the first clock signal.

[0010] According to an embodiment of the present invention, the above digital lock-in amplifier further includes a sampling clock circuit connected to the phase-locked loop unit via a clock transmission interface and configured to generate a second clock signal having a different frequency from the first clock signal under the control of the first clock signal; the signal to be measured is a current signal; the sampling circuit includes: a resistor sampling unit connected to the signal input terminal and configured to sample the signal to be measured for a plurality of cycles to obtain voltage signals for a plurality of cycles; an amplifying unit connected to the resistor sampling unit and configured to amplify the voltage signals for a plurality of cycles to obtain amplified signals for a plurality of cycles; an analog-to-digital conversion unit connected to the amplifying unit and the sampling clock circuit and configured to receive the second clock signal from the sampling clock circuit and perform analog-to-digital conversion on the amplified signals for a plurality of cycles under the control of the second clock signal to obtain digital signals for a plurality of cycles.

[0011] According to an embodiment of the present invention, the signal processing circuit further includes: a slicing unit configured to slice the down-converted signal according to the signal rising edge and the signal falling edge to obtain a sliced signal.

[0012] A second aspect of the present invention provides a signal processing system, including: a digital lock-in amplifier according to any one of the above; and a terminal device; wherein, the signal processing circuit of the digital lock-in amplifier is implemented based on a programmable logic circuit.

[0013] A third aspect of the present invention provides a signal processing method, including: sampling multiple cycles of a signal to be measured from a signal input end to obtain digital signals of multiple cycles; the digital signals of multiple cycles include multiple signal pulses; under the control of a control signal received via a control end, down-converting the digital signals of multiple cycles to obtain a down-converted signal; slicing the down-converted signal to obtain a sliced signal, and determining pulse slicing time information of the sliced signal; each sliced signal includes a single signal pulse; based on a reference signal and the sliced signal, determining an amplitude signal of the sliced signal; sending the amplitude signal and the pulse slicing time information to a terminal device so that the terminal device generates a signal waveform diagram of the signal to be measured according to the pulse slicing time information and the amplitude signal.

[0014] According to an embodiment of the present invention, a sampling circuit samples multiple cycles of a signal to be measured to obtain digital signals of multiple cycles, and then a signal processing circuit down-converts and slices the digital signals of multiple cycles to obtain sliced signals of each pulse of the digital signals of each cycle and pulse slicing time information of each sliced signal. Then, a signal waveform diagram that can reflect the accurate waveform of a high-speed signal to be measured with multiple cycles and multiple pulses can be plotted for each pulse according to the amplitude signal of the sliced signal and the pulse slicing time information.

[0015] According to an embodiment of the present invention, the digital lock-in amplifier of the present invention has beneficial detection performance for periodic multi-pulse signals with a pulse width of more than 16 ns, and can detect multi-cycle multi-pulse signals with a pulse width of more than 5 ns. The digital lock-in amplifier of the present invention can also be extended to detect the signal morphology of periodic arbitrary waveforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Through the following description of the embodiments of the present invention with reference to the drawings, the above content and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0017] Figure 1A A schematic diagram of a digital lock-in amplifier according to a first embodiment of the present invention is shown.

[0018] Figure 1B A schematic diagram of a signal to be measured and a control signal according to an embodiment of the present invention is shown.

[0019] Figure 1C A schematic diagram of signal slicing according to an embodiment of the present invention is shown.

[0020] Figure 1D A waveform diagram of a single-cycle multi-pulse signal to be measured according to an embodiment of the present invention is shown.

[0021] Figure 2A A schematic diagram of a digital lock-in amplifier according to a second embodiment of the present invention is shown.

[0022] Figure 2B Shows a schematic diagram of a serial - parallel conversion unit according to an embodiment of the present invention.

[0023] Figure 3A Shows a schematic diagram of a digital lock - in amplifier according to the third embodiment of the present invention.

[0024] Figure 3B Shows a signal timing diagram according to an embodiment of the present invention.

[0025] Figure 4 Shows a schematic diagram of a digital lock - in amplifier according to the fourth embodiment of the present invention.

[0026] Figure 5 Shows a schematic diagram of a digital lock - in amplifier according to the fifth embodiment of the present invention.

[0027] Figure 6 Shows a schematic diagram of a signal processing system according to an embodiment of the present invention.

[0028] Figure 7 Shows a schematic diagram of a signal processing method according to an embodiment of the present invention. Detailed implementation manners

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well - known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention.

[0030] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0032] In the case of using expressions such as "at least one of A, B, and C", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0033] In addition, in the description of the embodiments of the present invention, the term "electrically connected" may mean that two components are directly connected, or may mean that the two components are connected via one or more other components. In addition, the two components may be connected or coupled by wired or wireless means.

[0034] Figure 1A A schematic diagram of a digital phase-locked amplifier according to a first embodiment of the present invention is shown.

[0035] In Figure 1A In the signal processing system 100 shown, the digital phase-locked amplifier PSR1 includes a sampling circuit SC1 and a signal processing circuit SP1.

[0036] The sampling circuit SC1 can be used to sample the signal to be measured. For example, when multiple cycles of the signal to be measured are received at the signal input terminal INPUT of the sampling circuit SC1, the sampling circuit SC1 can sample multiple cycles of the signal to be measured, thereby obtaining multiple cycles of digital signals. In the embodiments of the present invention, the signal to be measured may be a weak signal. Each cycle of the signal to be measured includes multiple signal pulses, and thus each cycle of the digital signal obtained by sampling also correspondingly includes multiple signal pulses.

[0037] Figure 1B A schematic diagram of the signal to be measured and the control signal according to an embodiment of the present invention is shown. As Figure 1B shown, the signal to be measured may be a multi-cycle multi-pulse external signal with a frequency of 10 Hz and both rising and falling edges (i.e., the leading edge and the trailing edge) having a length of 8 ns. In Figure 1B , the signal to be measured is masked in external noise and lags behind the control signal, and its morphology is a pulse signal with six 16 ns time widths at equal intervals. The input end of the signal processing circuit SP1 is connected to the sampling circuit SC1, so that it can receive multiple cycles of digital signals output by the sampling circuit SC1. And, when the sampling circuit SC1 receives each cycle of the signal to be measured, the signal processing circuit SP1 will correspondingly receive the control signal. Under the control of the control signal received via the control terminal CTRL, the signal processing circuit SP1 can down-convert the high-speed digital signal of multi-cycle multi-pulse to obtain a down-converted signal.

[0038] Figure 1CShows a schematic diagram of signal slicing according to an embodiment of the present invention.

[0039] As Figure 1C shown, the signal processing circuit SP1 slices the down-converted signal to obtain the sliced signals of each signal pulse in the down-converted signal, and determines the pulse slicing time information of each sliced signal according to the slicing window for slicing the signal to be measured. After slicing the signal to be measured, zeros can be filled in the time window outside the slicing window. Then, based on the quadrature phase discrimination technique, the amplitude signal of each sliced signal can be determined using the reference signal.

[0040] The output end of the signal processing circuit SP1 is connected to the terminal device TE, and can send the amplitude signal and the pulse slicing time information to the terminal device TE. Figure 1D Shows a waveform diagram of the signal to be measured with single-cycle multi-pulses according to an embodiment of the present invention. After receiving the amplitude signal and the pulse slicing time information, the terminal device TE can perform point plotting based on the pulse slicing time information and the amplitude signal to obtain the signal waveform diagram of the signal to be measured for each signal cycle as Figure 1D shown. In Figure 1D it, the signal to be measured is restored from external noise, the intervals of multiple pulses are equal, and the pulse width is about 16 ns.

[0041] According to an embodiment of the present invention, the sampling circuit SC1 samples the signal to be measured for multiple cycles to obtain digital signals for multiple cycles. Then, the signal processing circuit SP1 down-converts and slices the digital signals for multiple cycles to obtain the sliced signals of each pulse of the digital signals for each cycle and the pulse slicing time information of each sliced signal. Then, the signal waveform diagram that can reflect the accurate waveform of the high-speed signal to be measured with multi-cycle multi-pulses can be obtained by plotting for each pulse according to the amplitude signal and the pulse slicing time information of the sliced signals.

[0042] According to an embodiment of the present invention, the digital lock-in amplifier PSR1 of the present invention has beneficial detection performance for periodic multi-pulse signals with a pulse width of more than 16 ns, and can detect periodic multi-pulse signals with a pulse width of more than 5 ns. The digital lock-in amplifier PSR of the present invention can also be extended to the detection of the signal morphology of multi-cycle arbitrary waveforms.

[0043] Optionally, under the control of a control signal, the signal processing circuit SP1 can down-convert digital signals of multiple periods by caching digital signals of multiple periods to obtain a down-converted signal. The period of the control signal is the same as the period of the digital signals of multiple periods to be measured. For example, in the case of receiving the digital signal of each period to be measured, the control signal can be received, and under the control of the control signal, the processing operation of the digital signal of each period can be triggered, so as to obtain a down-converted signal. The frequency of the high-speed digital signal with multiple periods and multiple pulses after down-conversion is consistent with the frequency of the reference signal, so as to use the reference signal to determine the amplitude signal of the slice signal based on the quadrature phase discrimination method.

[0044] Optionally, the signal processing circuit SP1 can detect the rising edge and falling edge of each signal pulse in the down-converted signal, and accurately slice the down-converted signal according to the detected signal rising edge and signal falling edge to obtain a slice signal. Moreover, accurate pulse slicing time information can be generated based on the time when the rising edge is detected and the time when the falling edge is detected.

[0045] Figure 2A The schematic diagram of the digital lock-in amplifier according to the second embodiment of the present invention is shown. Figure 2B The schematic diagram of the serial-parallel conversion unit according to the embodiment of the present invention is shown.

[0046] In Figure 2A In the signal processing system 200 shown, the signal processing circuit SP2 can include a serial-parallel conversion unit SPC2, a caching unit CU2, a slicing unit SU2, and a processing unit OL2.

[0047] As Figure 2B shown, multiple output terminals of the sampling circuit are electrically connected to multiple input terminals of the serial-parallel conversion unit SPC2 via multiple signal channels, and multiple periods of digital signals can be output to the serial-parallel conversion unit SPC2 in parallel via the multiple signal channels.

[0048] Under the control of a control signal, the serial-parallel conversion unit SPC2 caches digital signals of multiple cycles in parallel under the control of the control signal at the control terminal CTRL, obtains an intermediate down-converted signal, and outputs the intermediate down-converted signal in a serial manner. For example, the serial-parallel conversion unit SPC2 can convert a 12-bit (bit) parallel signal output by the sampling circuit SC2 into a serial signal according to two adjacent signal cycles. However, this is only an example, and serial-parallel conversion can also be performed with other numbers of signal cycles, which will not be elaborated here. Moreover, when receiving a parallel signal, the serial-parallel conversion unit SPC2 can cache the parallel signal at half the sampling clock frequency of the sampling circuit SC2 to achieve a slowdown in data transmission. Among them, the control signal is used to control the operation of the serial-parallel conversion unit SPC2. The working duration of the serial-parallel conversion unit SPC2 is determined by the effective pulse width in the control signal.

[0049] The input end of the cache unit CU2 is electrically connected to the output end of the serial-parallel conversion unit SPC2, and can receive the intermediate down-converted signal from the serial-parallel conversion unit SPC2. The cache unit CU2 can cache the intermediate down-converted signal to further down-convert the intermediate down-converted signal, thereby obtaining a down-converted signal.

[0050] The input end of the slicing unit SU2 is electrically connected to the output end of the cache unit CU2, and can receive the down-converted signal. The slicing unit SU2 can detect the rising edge and falling edge of each signal pulse in the down-converted signal, and accurately slice the down-converted signal according to the detected signal rising edge and signal falling edge, thereby obtaining a sliced signal and determining the pulse slicing time information of the sliced signal.

[0051] The first input end of the processing unit OL2 is electrically connected to the output end of the slicing unit SU2, and can receive the sliced signal and the pulse slicing time information. The second input end of the processing unit OL2 is electrically connected to the output end of the reference signal generation unit RSG2, and can receive the reference signal generated by the reference signal generation unit RSG2. The processing unit OL2 can extract the component with the same frequency as the reference signal from the received signal according to the frequency of the reference signal, thereby obtaining the amplitude signal of the sliced signal.

[0052] The output end of the processing unit OL2 can be electrically connected to the terminal device TE, so as to send the amplitude signal and the pulse slicing time information to the terminal device TE, so that the terminal device TE can generate a signal waveform diagram of the signal to be measured according to the amplitude signal and the pulse slicing time information.

[0053] Optionally, the processing unit may include a quadrature phase discrimination sub-unit and a low-pass filtering sub-unit. The following will be described in conjunction with Figure 3A and Figure 3B for illustration. Figure 3A shows a schematic diagram of a digital lock-in amplifier according to the third embodiment of the present invention.Figure 3B shows a signal timing diagram according to an embodiment of the present invention. In Figure 3A the signal processing system 300 shown, the signal processing circuit SP3 may include a serial-to-parallel conversion unit SPC3, a buffer unit CU3, a slicing unit SU3, a quadrature phase discrimination sub-unit OP3, a low-pass filtering sub-unit LPF3, a reference signal generation unit RSG3, and a communication unit CN3.

[0054] Multiple output terminals of the sampling circuit SC3 are electrically connected to multiple input terminals of the serial-to-parallel conversion unit SPC3 via multiple signal channels, and may output digital signals of multiple periods in parallel to the serial-to-parallel conversion unit SPC3 via the multiple signal channels. Under the control of a control signal, the serial-to-parallel conversion unit SPC3 caches digital signals of multiple periods in parallel, obtains an intermediate down-converted signal, and outputs the intermediate down-converted signal in a serial manner.

[0055] The input terminal of the buffer unit CU3 is electrically connected to the output terminal of the serial-to-parallel conversion unit SPC3, and may receive the intermediate down-converted signal from the serial-to-parallel conversion unit SPC3. The buffer unit CU3 may cache the intermediate down-converted signal to perform further down-conversion on the intermediate down-converted signal, thereby obtaining a down-converted signal.

[0056] The input terminal of the slicing unit SU3 is electrically connected to the output terminal of the buffer unit CU3, and may receive the down-converted signal. The slicing unit SU3 may detect the rising edge and falling edge of each signal pulse in the down-converted signal, and accurately slice the down-converted signal according to the detected signal rising edge and signal falling edge, thereby obtaining a sliced signal and determining the pulse slicing time information of the sliced signal.

[0057] The first input terminal of the quadrature phase discrimination sub-unit OP3 is electrically connected to the output terminal of the slicing unit SU3, and receives the sliced signal and the pulse slicing time information. The second input terminal of the quadrature phase discrimination sub-unit OP3 is electrically connected to the output terminal of the reference signal generation unit RSG3, and receives the reference signal. And, as Figure 3B shown, the reference signal includes a sine wave reference signal and a cosine wave reference signal with the same frequency. Thus, the quadrature phase discrimination sub-unit OP3 may extract the initial amplitude signal of the sliced signal based on the quadrature phase discrimination principle using the sine wave reference signal and the cosine wave reference signal according to the frequency of the reference signal.

[0058] The input terminal of the low-pass filtering sub-unit LPF3 is electrically connected to the output terminal of the quadrature phase discrimination sub-unit OP3, and receives the initial amplitude signal and the pulse slicing time information. The low-pass filtering sub-unit LPF3 may filter the initial amplitude signal according to a predetermined frequency to obtain an amplitude signal.

[0059] The output terminal of the low-pass filter subunit LPF3 can be electrically connected to the terminal device TE, and directly send the amplitude signal and the pulse slicing time information to the terminal device TE, so that the terminal device TE can generate the signal waveform diagram of the signal to be measured according to the amplitude signal and the pulse slicing time information. And the embodiment of the present invention is not limited thereto. The output terminal of the low-pass filter subunit LPF3 can also be electrically connected to the input terminal of the communication unit CN3. The communication unit CN3 is communicatively connected to the terminal device TE. In this way, the amplitude signal and the pulse slicing time information can be sent to the terminal device TE via the communication unit CN3. For example, the communication unit CN3 can be implemented based on the UART (Universal Asynchronous Receiver / Transmitter) interface.

[0060] According to an embodiment of the present invention, the digital lock-in amplifier may further include a power supply circuit configured to supply power to circuits such as the sampling circuit and the signal processing circuit. For example, the power supply circuit may include a DC power supply, a DC voltage converter electrically connected to the output terminal of the DC power supply, and a low dropout regulator (LDO) electrically connected to the output terminal of the DC voltage converter. The power supply circuit uses two groups of parallel DC voltage converters and low dropout regulators to supply power to the sampling circuit SC and the signal processing circuit SP respectively. A power supply control switch is provided between the DC power supply and the DC voltage converter. When the power supply control switch is open, the electrical connection between the DC power supply and the DC voltage converter is disconnected. When the power supply control switch is closed, the DC power supply and the DC voltage converter are electrically connected.

[0061] Optionally, the digital lock-in amplifier of the present invention may further include a crystal oscillation circuit and a sampling clock circuit. The signal processing circuit may further include a phase-locked loop unit. The following will be described in conjunction with Figure 4 for illustration. Figure 4 FIG. shows a schematic diagram of a digital lock-in amplifier according to a fourth embodiment of the present invention.

[0062] In Figure 4 In the signal processing system 400 shown, the crystal oscillation circuit COC4 can generate an initial clock signal. The input terminal of the phase-locked loop unit PLL4 is electrically connected to the output terminal of the crystal oscillation circuit COC4 and receives the initial clock signal. The phase-locked loop unit PLL4 can perform frequency division processing on the initial clock signal to obtain an intermediate clock signal, and perform frequency multiplication on the intermediate clock signal to obtain a first clock signal.

[0063] The input terminal of the reference signal generation unit RSG4 is electrically connected to the first output terminal of the phase-locked loop unit PLL4 and receives the first clock signal. The reference signal generation unit RSG4 can generate a reference signal according to the first clock signal, so as to provide the reference signal to the quadrature phase discrimination subunit OP4.

[0064] The input end of the sampling clock circuit SCC4 is electrically connected to the second output end of the phase-locked loop unit PLL4 via the clock transmission interface SPI4 and receives the first clock signal. For example, the clock transmission interface SPI4 can be a serial peripheral interface. The sampling clock circuit SCC4 can generate a second clock signal with a different frequency from the first clock signal under the control of the first clock signal. For example, the second clock signal can be generated at a predetermined frequency under the control of the first clock signal.

[0065] The clock input end of the sampling circuit SC4 is electrically connected to the output end of the sampling clock circuit SCC4 and receives the second clock signal. The sampling circuit SC4 can use the second clock signal as a sampling clock to sample the signal to be measured, thereby obtaining digital signals of multiple periods.

[0066] In Figure 4 In the embodiments, the functions and connection manners of the signal input end INPUT, the sampling circuit SC4, the control end CTRL4, the serial-to-parallel conversion unit SPC4, the buffer unit CU4, the slicing unit SU4, the quadrature phase discrimination sub-unit OP4, and the low-pass filtering sub-unit LPF4 can be referred to the previous descriptions and will not be elaborated here.

[0067] Figure 5 FIG. shows a schematic diagram of a digital lock-in amplifier according to the fifth embodiment of the present invention.

[0068] In Figure 5 In the signal processing system 500 shown, the sampling circuit SC5 includes a resistor sampling unit RC5, an amplification unit AF5, and an analog-to-digital conversion unit AD5.

[0069] The input end of the resistor sampling unit RC5 is electrically connected to the signal input end INPUT and receives the signal to be measured of multiple periods. The signal to be measured is a current signal. The resistor sampling unit RC5 can sample the signal to be measured of multiple periods to obtain voltage signals of multiple periods. For example, the resistor sampling unit RC5 can be a resistor high-side sampling unit.

[0070] The input end of the amplification unit AF5 is electrically connected to the output end of the resistor sampling unit RC5 and receives the voltage signals of multiple periods. The amplification unit AF5 can amplify the voltage signals of multiple periods to obtain amplified signals of multiple periods.

[0071] The first input end of the analog-to-digital conversion unit AD5 is electrically connected to the output end of the amplification circuit and receives the amplified signal. The second input end of the analog-to-digital conversion unit AD5 is electrically connected to the output end of the sampling clock circuit SCC5 and receives the second clock signal.

[0072] The analog-to-digital conversion unit AD5 can perform analog-to-digital conversion on the amplified signals of multiple cycles under the control of the second clock signal to obtain digital signals of multiple cycles.

[0073] The embodiment of the present invention is not limited thereto. In another embodiment of the present invention, the output end of the amplification unit AF5 is electrically connected to the input end of the single-ended to differential circuit, and the output end of the single-ended to differential circuit is electrically connected to the input end of the analog-to-digital conversion unit AD5. The single-ended to differential circuit can convert the amplified signal into a differential amplified signal and output the differential amplified signal to the analog-to-digital conversion unit AD5 for analog-to-digital conversion.

[0074] In Figure 5 the embodiment of, the functions and connection manners of the crystal oscillation circuit COC5, the phase-locked loop unit PLL5, the reference signal generation unit RSG5, the control terminal CTRL, the serial-to-parallel conversion unit SPC5, the buffer unit CU5, the slicing unit SU5, the quadrature phase discrimination sub-unit OP5, the sampling clock circuit SCC5, and the low-pass filtering sub-unit LPF5 can be referred to the previous description and will not be elaborated herein. Among them, the serial-to-parallel conversion unit SPC5 caches the parallel signals at a frequency half of the second clock signal, so that the transmission speed of the serial signal output by the serial-to-parallel conversion unit SPC5 is half of the transmission speed of the parallel signal output by the analog-to-digital conversion unit AD5.

[0075] According to the embodiment of the present invention, the sampling clock circuit in the above embodiment can be used to generate two second clock signals with a 180° phase difference and a frequency of 350 MHz. For example, the sampling clock circuit can include a frequency synthesizer and a clock distributor connected in series. The frequency synthesizer is used to generate a basic clock of 700 MHz; the clock distributor is used to generate two second clock signals with a 180° phase difference and a frequency of 350 MHz. In the embodiment of the present invention, there can be multiple analog-to-digital conversion units. The multiple analog-to-digital conversion units can perform ping-pong (alternate) sampling on the amplified signals of multiple cycles under the control of the two second clock signals, so as to output digital signals of multiple cycles in parallel.

[0076] The signal processing circuit is implemented based on a programmable logic circuit, such as an FPGA (Field Programmable Gate Array). For example, the serial-to-parallel conversion unit, the buffer unit, the reference signal generation unit, the quadrature phase discrimination sub-unit, the low-pass filtering sub-unit, and the communication unit in the above embodiments can all be pure digital processing units implemented within the programmable logic circuit. In the embodiment of the present invention, by reducing the frequency of the digital signals of multiple cycles to a down-converted signal consistent with the reference signal, the signal processing circuit implemented based on the programmable logic circuit can perform real-time processing on the parallel signals output by the analog-to-digital conversion unit.

[0077] Figure 6 FIG. shows a schematic diagram of a signal processing system according to an embodiment of the present invention.

[0078] As Figure 6 shown, the signal processing system 600 of this embodiment may include a digital phase-locked amplifier PSR6 and a terminal device TE.

[0079] In the embodiment of the present invention, the digital phase-locked amplifier PSR6 may be any one of the digital phase-locked amplifiers described above, and will not be elaborated here.

[0080] Figure 7 FIG. shows a schematic diagram of a signal processing method according to an embodiment of the present invention.

[0081] As Figure 7 shown, the signal processing method of this embodiment includes: operations S710 to S760.

[0082] In operation S710, a plurality of cycles of the signal to be measured from the signal input end are sampled to obtain a plurality of cycles of digital signals.

[0083] In operation S720, under the control of the control signal received via the control end, the plurality of cycles of digital signals are down-converted to obtain a down-converted signal.

[0084] In operation S730, the down-converted signal is sliced to obtain a sliced signal.

[0085] In operation S740, based on the reference signal and the sliced signal, the amplitude signal of the sliced signal is determined.

[0086] In operation S750, the pulse slicing time information of the sliced signal is determined.

[0087] In operation S760, the amplitude signal and the pulse slicing time information are sent to the terminal device.

[0088] In the embodiment of the present invention, operations S710 to S760 are similar to the operations performed by the digital phase-locked amplifier described above, and will not be elaborated here.

[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as combinations of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0090] Those skilled in the art will appreciate that the features recited in the various embodiments and / or claims of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features recited in the various embodiments and / or claims of the present invention can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present invention.

[0091] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although the embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present invention.

Claims

1. A digital lock-in amplifier, characterized in that: include: The sampling circuit includes a signal input terminal, and is configured to sample a plurality of cycles of the signal to be measured from the signal input terminal to obtain a plurality of cycles of digital signals; each cycle of the digital signal includes a plurality of signal pulses; The signal processing circuit is connected to the sampling circuit and the terminal device and is configured as follows: Under the control of a control signal received via a control terminal, down-converting the digital signals of the plurality of cycles to obtain a down-converted signal; Slicing the down-converted signal to obtain a slice signal, and determining pulse slice time information of the slice signal; each slice signal includes a single signal pulse; Determine an amplitude signal of the slice signal based on a reference signal and the slice signal; The amplitude signal and the pulse slicing time information are sent to the terminal device so that the terminal device generates a signal waveform diagram of the signal to be tested according to the pulse slicing time information and the amplitude signal.

2. The digital lock-in amplifier according to claim 1, characterized in that: The signal processing circuit is further configured as: Under the control of the control signal, the digital signals of the multiple periods are buffered and the digital signals of the multiple periods are frequency-reduced to obtain the frequency-reduced signals; the period of the control signal is the same as the period of the signals to be tested of the multiple periods.

3. The digital lock-in amplifier according to claim 2, characterized in that: The sampling circuit comprises a plurality of signal channels, and the sampling circuit is further configured to output the digital signals of the plurality of cycles in parallel via the plurality of signal channels; The signal processing circuit comprises: a serial-to-parallel conversion unit connected to the sampling circuit via the plurality of signal channels, configured to cache a plurality of parallel cycles of digital signals under the control of the control signal, obtain an intermediate frequency-reduced signal, and output the intermediate frequency-reduced signal in a serial manner; The buffer unit is connected to the serial-to-parallel conversion unit and is configured to buffer the intermediate frequency-reduced signal to obtain the frequency-reduced signal.

4. The digital lock-in amplifier according to any one of claims 1 to 3, characterized in that: The signal processing circuit further includes: A reference signal generating unit, configured to generate the reference signal, wherein the frequency of the reference signal is consistent with the frequency of the frequency-reduced signal; The processing unit is connected to the reference signal generating unit and is configured to extract the amplitude signal of the slice signal according to the frequency of the reference signal.

5. The digital lock-in amplifier according to claim 4, characterized in that: The processing unit comprises: an orthogonal phase detector subunit, configured to extract an initial amplitude signal of the slice signal according to the frequency of the reference signal; and The low-pass filter subunit is connected to the orthogonal phase detection subunit and is configured to filter the initial amplitude signal according to a predetermined frequency to obtain the amplitude signal.

6. The digital lock-in amplifier according to claim 4, characterized in that: Also includes: a crystal oscillator circuit configured to generate an initial clock signal; The signal processing circuit further comprises a phase-locked loop unit connected to the crystal oscillator circuit and configured to perform frequency division processing on the initial clock signal to obtain an intermediate clock signal, and perform frequency multiplication on the intermediate clock signal to obtain a first clock signal; The reference signal generating unit is also connected to the phase-locked loop unit, and is further configured to generate the reference signal according to the first clock signal.

7. The digital lock-in amplifier according to claim 6, characterized in that: Also includes a sampling clock circuit, connected to the phase-locked loop unit via a clock transmission interface, configured to generate a second clock signal having a different frequency from the first clock signal under the control of the first clock signal; The signal to be measured is a current signal; The sampling circuit comprises: A resistance sampling unit, connected to the signal input terminal, configured to sample the plurality of cycles of the signal to be measured to obtain a plurality of cycles of voltage signals; an amplifying unit, connected to the resistance sampling unit, and configured to amplify the voltage signals of the multiple cycles to obtain amplified signals of the multiple cycles; The analog-to-digital conversion unit is connected to the amplifying unit and the sampling clock circuit, and is configured to receive the second clock signal from the sampling clock circuit, and under the control of the second clock signal, perform analog-to-digital conversion on the amplified signals of the multiple cycles to obtain digital signals of the multiple cycles.

8. The digital lock-in amplifier according to any one of claims 1 to 3, characterized in that: The signal processing circuit further includes: The slicing unit is configured to slice the down-converted signal according to the rising edge of the signal and the falling edge of the signal to obtain a sliced ​​signal.

9. A signal processing system, characterized in that: include: The digital lock-in amplifier according to any one of claims 1 to 8; as well as Terminal equipment; Wherein, the signal processing circuit of the digital lock-in amplifier is implemented based on a programmable logic circuit.

10. A signal processing method, characterized in that: include: Sampling a plurality of cycles of the signal to be measured from the signal input terminal to obtain a plurality of cycles of digital signals; Each cycle of the digital signal includes a plurality of signal pulses; Under the control of a control signal received via a control terminal, down-converting the digital signals of the plurality of cycles to obtain a down-converted signal; Slicing the down-converted signal to obtain a slice signal, and determining pulse slice time information of the slice signal; each slice signal includes a single signal pulse; Determine an amplitude signal of the slice signal based on a reference signal and the slice signal; The amplitude signal and the pulse slicing time information are sent to a terminal device so that the terminal device generates a signal waveform diagram of the signal to be tested according to the pulse slicing time information and the amplitude signal.

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