Real-time flow acquisition system applied to power industry
By designing a real-time traffic acquisition system with multiple modules, the traditional system has solved the problems of small number of network interfaces, low data throughput bandwidth, and low real-time monitoring capabilities, and efficient traffic acquisition and stable system operation are achieved.
Patent Information
- Application Number
- CN202411874658.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-05-09
AI Technical Summary
Traditional traffic acquisition devices have a small number of network interfaces, a low data throughput bandwidth of a single network interface, and a low real-time traffic monitoring capability, which is difficult to meet the power industry's demand for high-integration and high-performance real-time traffic acquisition systems.
A real-time flow acquisition system including a central processor module, a MCU display module, a CPLD control module, a SPI memory module, an EEPROM storage module, a network interface module, an LCD display module, a voltage and current monitoring module, an LED indicator module and an IRIGB timing module are designed. Through the coordinated work of these modules, efficient flow acquisition and real-time monitoring are achieved.
It improves the stability and data throughput of the system, enhances the real-time traffic monitoring capabilities, and meets the power industry's demand for high-performance real-time traffic acquisition systems.
Smart Images
Figure CN119966845A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of Internet of Things, and in particular to a real-time flow collection system applied to the electric power industry. Background Art
[0002] As the power industry's requirements for digitization and informatization continue to increase, the importance of real-time flow collection devices in power grid operation monitoring and management is becoming increasingly apparent. Traditional flow collection devices have a small number of open network interfaces, low data throughput bandwidth of a single network interface, and low real-time flow monitoring capabilities. Therefore, a highly integrated, high-performance real-time flow collection system is needed to improve the efficiency of real-time flow collection. Summary of the invention
[0003] The purpose of the present invention is to provide a real-time flow collection system and method for use in the electric power industry to solve the problems raised in the prior art.
[0004] In order to solve the above technical problems, the present invention provides the following technical solutions: a real-time flow acquisition system applied to the electric power industry, comprising a central processing unit module, an MCU display module, a CPLD control module, a first SPI memory module, a second SPI memory module, an EEPROM storage module, a network interface module, an LCD display module, a voltage and current monitoring module, an LED indicator module, and an IRIGB timing module; The central processing unit module, the MCU display module, the CPLD control module, the first SPI memory module, the second SPI memory module, the EEPROM storage module and the network interface module are connected; MCU display module, LCD display module and voltage and current monitoring module are connected; The CPLD control module, the LED indicator light module and the IRIGB timing module are connected.
[0005] Furthermore, the CPU control module is responsible for system startup, traffic collection, software operation, and communication with each module.
[0006] Furthermore, the MCU display module is responsible for receiving the flow data sent by the central processing unit control module and displaying the flow data in real time on the LCD display module. It is also responsible for receiving the module switching instruction sent by the central processing unit control module and switching the module to the voltage and current monitoring module, thereby displaying the voltage and current results of the precise values inside the device in real time.
[0007] Furthermore, the CPLD control module is responsible for receiving control instructions in the LED indicator light module sent by the central processing unit module, and completing the state switching in the LED indicator light module, and is also responsible for decoding the IRIGB in the IRIGB timing module and transmitting it to the central processing unit module.
[0008] Furthermore, the first SPI memory module is responsible for storing the BIOS firmware required for starting the central processing unit module.
[0009] Furthermore, the second SPI memory module is responsible for expanding the user's requirements for data storage.
[0010] Furthermore, the EEPROM storage module is responsible for storing factory information.
[0011] Furthermore, the network interface module is responsible for providing real-time traffic collection services.
[0012] Furthermore, the voltage and current monitoring module is responsible for calculating the accurate voltage and current values and inputting them into the LCD display module for display; The voltage and current monitoring module includes an operational amplifier U77, a resistor R450, a resistor R732, a resistor R451, and a capacitor C697; The 4th pin of the operational amplifier U77 and the first end of the resistor R450 are connected in parallel to VCC_12V; The 5th pin of the operational amplifier U77 and the second end of the resistor R450 are connected in parallel to VCC_12V_CORE; The third pin of the operational amplifier U77, the first end of the capacitor C697 and the first end of the resistor R732 are connected in parallel to P5V, and the second end of the capacitor C697 is grounded; The first pin of the operational amplifier U77 is connected to the second end of the resistor R732; The sixth pin of the operational amplifier U77 is connected to the first end of the resistor R451, and the second end of the capacitor R451 is connected to DC_IN_Current2; Pin 2 of the operational amplifier U77 is grounded.
[0013] Furthermore, the IRIGB timing module is responsible for timing work; The IRIGB timing module includes an input port J13, a transient suppression diode G1, a DC-DC isolation power supply module U28, a capacitor C699, a capacitor C700, a B code decoding chip U29, a light emitting diode D17, a light emitting diode D18, a light emitting diode D19, a light emitting diode D20, a resistor R456, a resistor R461, a resistor R462, a resistor R464, a capacitor C705, a resistor R465, a capacitor C706, a resistor R463, a 485 transceiver chip U30, a capacitor C701, a capacitor C702, a capacitor C703, a capacitor C704, a resistor R455, a resistor R455, a resistor R457, a resistor R458, a resistor R459, a resistor R460, a resistor R455, and a test point TP13; The first pin of input port J13 and the first pin of transient suppression diode G1 are connected in parallel to IO_UART_B_485_A; The second pin of input port J13 and the second pin of transient suppression diode G1 are connected in parallel to IO_UART_B_485_B; The third pin of the transient suppression diode G1 is grounded; The second pin of the DC-DC isolation power module U28 is connected to the positive electrode of P5V, and the first end of the capacitor C699 is located on the line between the second pin of the DC-DC isolation power module U28 and the positive electrode of P5V; The first pin of the DC-DC isolation power module U28 is connected to the negative electrode of P5V, and the second end of the capacitor C699 is located on the line between the first pin of the DC-DC isolation power module U28 and the negative electrode of P5V; The 4th pin of the DC-DC isolation power module U28, the first end of the capacitor C700 and ISO_5V are connected in parallel; The third pin of the DC-DC isolation power module U28, the second end of the capacitor C700 and ISO_GND are connected in parallel; The 4th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D17, and the first end of the light emitting diode D17 is connected to the second end of the resistor R456; The 5th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D18, and the first end of the light emitting diode D18 is connected to the second end of the resistor R461; The 6th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D19, and the first end of the light emitting diode D19 is connected to the second end of the resistor R462; A first end of the resistor R456, a first end of the resistor R461, a first end of the resistor R462, and a first end of the resistor R464 are connected in parallel to P3V3; The 7th pin of the B code decoding chip U29 is grounded; The 8th pin of the B code decoding chip U29 and the first end of the capacitor C705 are connected in parallel with P3V3, and the second end of the capacitor C705 is grounded; The 9th pin of the B code decoding chip U29 is connected in parallel with the second end of the resistor R465, the first end of the resistor R463 and the first end of the capacitor C706, the first end of the resistor R465 is connected to P3V3, the second end of the capacitor C706 is grounded, and the second end of the resistor R463 is connected to B_CORE_RST_N; The 10th pin of the B code decoding chip U29 is connected to B_CORE_IN; The 11th pin of the B code decoding chip U29 is connected to B_CORE_PPS_INT; The 12th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D20, and the first end of the light emitting diode D20 is connected to the second end of the resistor R464; The 13th pin of B code decoding chip U29 is connected to B_CORE_UART_TX; The 14th pin of the B code decoding chip U29 is connected to B_CORE_CS; The 15th pin of the B code decoding chip U29 is connected to B_CORE_SDA; The 16th pin of the B code decoding chip U29 is connected to B_CORE_SCK; The first pin of the 485 transceiver chip U30, the second end of the capacitor C701 and the second end of the capacitor C704 are connected in parallel with P3V3, and the first end of the capacitor C701 and the first end of the capacitor C704 are connected in parallel with P3V3 and grounded; The 2nd pin, the 7th pin, the 8th pin of the 485 transceiver chip U30, the first end of the resistor R458 and the first end of the resistor R457 are connected to the ground in parallel; Connect the 3rd pin of 485 transceiver chip U30 to IO_UART_B_RX The 4th pin of the 485 transceiver chip U30 is connected to the second end of the resistor R458; The 5th pin of the 485 transceiver chip U30 is connected to the second end of the resistor R457; Connect the 6th pin of the 485 transceiver chip U30 to the test point TP13; The 9th pin, the 10th pin and the 15th pin of the 485 transceiver chip U30 are connected to the ground in parallel, and the 9th pin of the 485 transceiver chip U30 is connected to the first end of the resistor R460; The 12th pin of the 485 transceiver chip U30 is connected in parallel with the first end of the resistor R459 and the second end of the resistor R455; The 13th pin of the 485 transceiver chip U30 is connected in parallel with the second end of the resistor R459 and the second end of the resistor R460; Pin 16 of the 485 transceiver chip U30, the first end of capacitor C702, the first end of capacitor C703, and the first end of resistor R455 are connected in parallel to ISO_5V, and the second end of capacitor C702 and the second end of capacitor C703 are connected in parallel to ground.
[0014] Compared with the prior art, the invention has the following beneficial effects: a voltage and current monitoring module is added to the circuit design to detect the operation of the internal circuit of the device in real time, and the monitoring data can be displayed in real time through the LCD display screen, which greatly improves the stability of the system; In addition, the entire device uses two domestically produced Netcom WX1860A4 chips, realizing a total of 8 external Gigabit network ports for traffic collection and statistical analysis, effectively improving data throughput and bandwidth; In addition, the hardware design also makes full expansion for storage, using a total of 2 SPI NOR FLASH, one of which is the main FLASH to store the BIOS firmware required for D2000 startup, and the other FLASH is designed with two chip selects on the same bus, which are switched by software control. After the system starts, the software will automatically switch the chip select, and the FLASH can subsequently store logs and user data generated by the operation; The EEPROM stores some factory information of the device, such as the serial number, production date, model and other important information of the device, and the software end of the central processor module is equipped with a reading and writing tool to facilitate flashing or reading information; Finally, the scheme used for accurate timing on the acquisition device is IRIG-B (Inter Range Instrumentation Group), which is an internationally accepted standard code for time codes and is widely used in time information transmission systems, especially in the power industry. However, the IRIG-B code has very high requirements on the real-time decoding. In the present invention, a real-time decoding system based on a CPLD control module is adopted, and an internal communication interface is provided to the central processing unit module for data transmission, which greatly improves the decoding efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 This is a structural block diagram of a real-time flow collection system applied to the power industry of the present invention; Figure 2 This is a circuit schematic diagram of a voltage and current monitoring module of a real-time flow acquisition system applied to the power industry of the present invention; Figure 3This is a schematic diagram of a signal input circuit in an IRIGB timing module of a real-time flow collection system applied to the electric power industry of the present invention; Figure 4 This is a schematic diagram of an isolated power supply circuit in an IRIGB timing module of a real-time flow collection system applied to the electric power industry of the present invention; Figure 5 This is a schematic diagram of a B code decoding circuit in an IRIGB timing module of a real-time flow collection system applied to the electric power industry of the present invention; Figure 6 The present invention is a schematic diagram of the RS485 transceiver circuit in the IRIGB timing module of the real-time flow collection system applied to the power industry. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0017] See also Figures 1 to 6 ,The present invention provides a technical solution: a real-time flow acquisition system applied to the electric power industry, comprising a central processing unit module, an MCU display module, a CPLD control module, a first SPI memory module, a second SPI memory module, an EEPROM storage module, a network interface module, an LCD display module, a voltage and current monitoring module, an LED indicator module, and an IRIGB timing module; The central processing unit module, the MCU display module, the CPLD control module, the first SPI memory module, the second SPI memory module, the EEPROM storage module and the network interface module are connected; MCU display module, LCD display module and voltage and current monitoring module are connected; The CPLD control module, the LED indicator light module and the IRIGB timing module are connected.
[0018] Among them, the CPU control module is responsible for system startup, traffic collection, software operation, and communication with each module; For example, the central processing unit control module is mainly composed of the Feiteng D2000CPU and the peripheral circuits that constitute the minimum system and the firmware and application software running on it. It realizes the system startup and the operation of the traffic collection software, and is responsible for the communication with the CPLD control module and the MCU display module. At the same time, it can also run the interface provided in the firmware to realize the reading and writing of the SPI storage module 2 and the EEPROM storage module.
[0019] Among them, the MCU display module is responsible for receiving the flow data sent by the central processing unit control module, and displaying the flow data on the LCD display module in real time. It is also responsible for receiving the module switching instruction sent by the central processing unit control module, switching the module to the voltage and current monitoring module, so as to display the voltage and current results of the precise values inside the equipment in real time; For example, the MCU display module is mainly composed of GigaDevice's GD32F103C8T6 and its peripheral circuits.
[0020] The CPLD control module is responsible for receiving the control instructions in the LED indicator module sent by the central processing unit module, and completing the state switching in the LED indicator module, and is also responsible for decoding the IRIGB in the IRIGB timing module and transmitting it to the central processing unit module; For example, the CPLD control module is mainly composed of Anlu Technology's EF2L15LG100B and its peripheral circuits.
[0021] Wherein, the first SPI memory module is responsible for storing the BIOS firmware required for starting the central processing unit module; For example, the SPI storage module 1 is mainly composed of a GD25LQ128DSIG chip produced by GigaDevice, with a total data storage capacity of 16MB, which is used to store the BIOS firmware required for the processor module to start up. The actual firmware size is about 4M, so the capacity of this type of storage chip can meet practical applications.
[0022] Among them, the second SPI memory module is responsible for expanding the user's requirements for data storage; For example, SPI storage module 2 is composed of GigaDevice's GD25LB512MEYIGR, which is mainly used to expand the user's possible requirements for data storage, and can also be used as a storage area for a backup BIOS. In terms of hardware design, SPI storage module 1 and SPI storage module 2 are on the same QSPI bus, and are distinguished by two different hardware chip select signals. By default, the FLASH storage of SPI storage module 1 is enabled. When the user wants to store data in SPI storage module 2, the application software running on the processor module will operate the physical register address in a memory-mapped manner, and switch the chip select to SPI storage module 2, thereby achieving the purpose of storing data. When the user wants to use the FLASH of SPI storage module 2 as a backup BIOS, it is necessary to add judgment logic to the PBF header file of the main BIOS. This function can be provided by Feiteng officially.
[0023] Among them, the EEPROM storage module is responsible for storing factory information; For example, the EEPROM storage module is mainly composed of a model IDCHIP AT24C02, and its internal storage space is 256B, which is mainly used to store some factory information, such as device model, serial number and factory date, etc., and the processor module has instructions to read the storage module for users to view, while the authority to erase and write such operations is only in the hands of the developer to prevent user misoperation.
[0024] Among them, the network interface module is responsible for providing real-time traffic collection services; For example, the network interface module is a Feiteng Tengrui D2000 that splits one PEU1_X16 into two PCIE X8s after being configured by the PBF firmware. Currently, only TXP0-3 and RXP0-3 are used in the two X8s, and TXP4-7 and RXP4-7 are processed by NC respectively, which is equivalent to using two PCIE X4s. The two PCIE X4 signals are connected to two Netcom WX1860A4s respectively, thus expanding a total of 8 Gigabit network ports. These 8 network ports provide real-time traffic collection services to users. The traffic collection application layer software running in the processor control module can set the collection of input traffic or output traffic for these 8 Gigabit network ports through the configuration file, or count the input and output traffic at the same time. The collected results will be counted in the input and output directions and then output. The basic traffic measurement unit is KB / s, and for real-time traffic with too much data, the measurement unit will be automatically changed to MB / s. Since it is calculated that the data of 8 network ports within one second will not exceed 1000MB / s, the GB / s unit is not set in the software. If the real-time traffic decreases, the measurement unit will also be automatically switched to KB / s. The principle of counting the input and output traffic of the network port is that the application layer traffic collection software running on the processor module will monitor the input and output traffic flowing through the network card driver in real time. The specific method is to access / proc / net / dev, the device file generated by the network card driver registration of the system kernel, match the corresponding input and output traffic through the network port name, and finally add the input and output configurations of the 8 network ports in the configuration file to get the total data per unit time. After an interval of 1s, access / proc / net / dev again, and then obtain the total input and output data per unit time in the same way. Subtract the two to get the total amount of data in the past 1s, and then the central processing unit module uses instructions through the SPI interface to pass the input and output data to the MCU display module for display.
[0025] Among them, the voltage and current monitoring module is responsible for calculating the accurate voltage and current values, and inputting them into the LCD display module for display; The voltage and current monitoring module includes an operational amplifier U77, a resistor R450, a resistor R732, a resistor R451, and a capacitor C697; The 4th pin of the operational amplifier U77 and the first end of the resistor R450 are connected in parallel to VCC_12V; The 5th pin of the operational amplifier U77 and the second end of the resistor R450 are connected in parallel to VCC_12V_CORE; The third pin of the operational amplifier U77, the first end of the capacitor C697 and the first end of the resistor R732 are connected in parallel to P5V, and the second end of the capacitor C697 is grounded; The first pin of the operational amplifier U77 is connected to the second end of the resistor R732; The sixth pin of the operational amplifier U77 is connected to the first end of the resistor R451, and the second end of the capacitor R451 is connected to DC_IN_Current2; The second pin of the operational amplifier U77 is grounded; For example, the voltage and current monitoring module is responsible for collecting the analog voltage and current signals to be tested by hardware. After amplification by the integrated operational amplifier circuit, the signal is connected to the ADC pin of the MCU display module. The external analog signal is converted into a digital signal through the ADC inside the MCU. Finally, the accurate voltage and current values are obtained through formula conversion and displayed on the LCD screen.
[0026] Among them, the IRIGB timing module is responsible for timing work; The IRIGB timing module includes an input port J13, a transient suppression diode G1, a DC-DC isolation power supply module U28, a capacitor C699, a capacitor C700, a B code decoding chip U29, a light emitting diode D17, a light emitting diode D18, a light emitting diode D19, a light emitting diode D20, a resistor R456, a resistor R461, a resistor R462, a resistor R464, a capacitor C705, a resistor R465, a capacitor C706, a resistor R463, a 485 transceiver chip U30, a capacitor C701, a capacitor C702, a capacitor C703, a capacitor C704, a resistor R455, a resistor R455, a resistor R457, a resistor R458, a resistor R459, a resistor R460, a resistor R455, and a test point TP13; The first pin of input port J13 and the first pin of transient suppression diode G1 are connected in parallel to IO_UART_B_485_A; The second pin of input port J13 and the second pin of transient suppression diode G1 are connected in parallel to IO_UART_B_485_B; The third pin of the transient suppression diode G1 is grounded; The second pin of the DC-DC isolation power module U28 is connected to the positive electrode of P5V, and the first end of the capacitor C699 is located on the line between the second pin of the DC-DC isolation power module U28 and the positive electrode of P5V; The first pin of the DC-DC isolation power module U28 is connected to the negative electrode of P5V, and the second end of the capacitor C699 is located on the line between the first pin of the DC-DC isolation power module U28 and the negative electrode of P5V; The 4th pin of the DC-DC isolation power module U28, the first end of the capacitor C700 and ISO_5V are connected in parallel; The third pin of the DC-DC isolation power module U28, the second end of the capacitor C700 and ISO_GND are connected in parallel; The 4th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D17, and the first end of the light emitting diode D17 is connected to the second end of the resistor R456; The 5th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D18, and the first end of the light emitting diode D18 is connected to the second end of the resistor R461; The 6th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D19, and the first end of the light emitting diode D19 is connected to the second end of the resistor R462; A first end of the resistor R456, a first end of the resistor R461, a first end of the resistor R462, and a first end of the resistor R464 are connected in parallel to P3V3; The 7th pin of the B code decoding chip U29 is grounded; The 8th pin of the B code decoding chip U29 and the first end of the capacitor C705 are connected in parallel with P3V3, and the second end of the capacitor C705 is grounded; The 9th pin of the B code decoding chip U29 is connected in parallel with the second end of the resistor R465, the first end of the resistor R463 and the first end of the capacitor C706, the first end of the resistor R465 is connected to P3V3, the second end of the capacitor C706 is grounded, and the second end of the resistor R463 is connected to B_CORE_RST_N; The 10th pin of the B code decoding chip U29 is connected to B_CORE_IN; The 11th pin of the B code decoding chip U29 is connected to B_CORE_PPS_INT; The 12th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D20, and the first end of the light emitting diode D20 is connected to the second end of the resistor R464; The 13th pin of B code decoding chip U29 is connected to B_CORE_UART_TX; The 14th pin of the B code decoding chip U29 is connected to B_CORE_CS; The 15th pin of the B code decoding chip U29 is connected to B_CORE_SDA; The 16th pin of the B code decoding chip U29 is connected to B_CORE_SCK; The first pin of the 485 transceiver chip U30, the second end of the capacitor C701 and the second end of the capacitor C704 are connected in parallel with P3V3, and the first end of the capacitor C701 and the first end of the capacitor C704 are connected in parallel with P3V3 and grounded; The 2nd pin, the 7th pin, the 8th pin of the 485 transceiver chip U30, the first end of the resistor R458 and the first end of the resistor R457 are connected to the ground in parallel; Connect the 3rd pin of 485 transceiver chip U30 to IO_UART_B_RX The 4th pin of the 485 transceiver chip U30 is connected to the second end of the resistor R458; The 5th pin of the 485 transceiver chip U30 is connected to the second end of the resistor R457; Connect the 6th pin of the 485 transceiver chip U30 to the test point TP13; The 9th pin, the 10th pin and the 15th pin of the 485 transceiver chip U30 are connected to the ground in parallel, and the 9th pin of the 485 transceiver chip U30 is connected to the first end of the resistor R460; The 12th pin of the 485 transceiver chip U30 is connected in parallel with the first end of the resistor R459 and the second end of the resistor R455; The 13th pin of the 485 transceiver chip U30 is connected in parallel with the second end of the resistor R459 and the second end of the resistor R460; The 16th pin of the 485 transceiver chip U30, the first end of the capacitor C702, the first end of the capacitor C703, the first end of the resistor R455 are connected in parallel to ISO_5V, and the second end of the capacitor C702 and the second end of the capacitor C703 are connected in parallel to the ground; For example, the IRIGB timing module is responsible for collecting the IRIGB signal input to the device by hardware, and the level standard is RS485. After the signal is transmitted to the CPLD control module, the CPLD control module decodes it and then converts it into a signal with TTL level standard, and notifies the processor control module to receive the data. After the processor control module receives the information, the application software running on it receives and processes the data, and converts the data into the correct format before performing timing work.
[0027] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
Claims
1. A real-time flow collection system applied to the power industry, characterized in that: The system includes a central processing unit module, an MCU display module, a CPLD control module, a first SPI memory module, a second SPI memory module, an EEPROM storage module, a network interface module, an LCD display module, a voltage and current monitoring module, an LED indicator module, and an IRIGB timing module; The central processing unit module, the MCU display module, the CPLD control module, the first SPI memory module, the second SPI memory module, the EEPROM storage module and the network interface module are connected; The MCU display module, LCD display screen module and voltage and current monitoring module are connected; The CPLD control module, the LED indicator light module and the IRIGB timing module are connected.
2. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The central processing unit control module is responsible for system startup, flow collection, software operation and communication with various modules.
3. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The MCU display module is responsible for receiving the flow data sent by the central processing unit control module and displaying the flow data in real time on the LCD display module. It is also responsible for receiving the module switching instruction sent by the central processing unit control module and switching the module to the voltage and current monitoring module, thereby displaying the voltage and current results of the precise values inside the device in real time.
4. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The CPLD control module is responsible for receiving the control instructions in the LED indicator light module sent by the central processing unit module, and completing the state switching in the LED indicator light module. It is also responsible for decoding the IRIGB in the IRIGB timing module and transmitting it to the central processing unit module.
5. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The first SPI memory module is responsible for storing the BIOS firmware required for starting the central processing unit module.
6. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The second SPI memory module is responsible for expanding the user's requirements for data storage.
7. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The EEPROM storage module is responsible for storing factory information.
8. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The network interface module is responsible for providing real-time traffic collection services.
9. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The voltage and current monitoring module is responsible for calculating accurate voltage and current values and inputting them into the LCD display module for display; The voltage and current monitoring module includes an operational amplifier U77, a resistor R450, a resistor R732, a resistor R451, and a capacitor C697; The 4th pin of the operational amplifier U77 and the first end of the resistor R450 are connected in parallel to VCC_12V; The 5th pin of the operational amplifier U77 and the second end of the resistor R450 are connected in parallel to VCC_12V_CORE; The third pin of the operational amplifier U77, the first end of the capacitor C697 and the first end of the resistor R732 are connected in parallel to P5V, and the second end of the capacitor C697 is grounded; The first pin of the operational amplifier U77 is connected to the second end of the resistor R732; The sixth pin of the operational amplifier U77 is connected to the first end of the resistor R451, and the second end of the capacitor R451 is connected to DC_IN_Current2; The second pin of the operational amplifier U77 is grounded.
10. The real-time flow collection system for the electric power industry according to claim 1 is characterized in that: The IRIGB timing module is responsible for timing work; The IRIGB timing module includes an input port J13, a transient suppression diode G1, a DC-DC isolation power supply module U28, a capacitor C699, a capacitor C700, a B code decoding chip U29, a light emitting diode D17, a light emitting diode D18, a light emitting diode D19, a light emitting diode D20, a resistor R456, a resistor R461, a resistor R462, a resistor R464, a capacitor C705, a resistor R465, a capacitor C706, a resistor R463, a 485 transceiver chip U30, a capacitor C701, a capacitor C702, a capacitor C703, a capacitor C704, a resistor R455, a resistor R455, a resistor R457, a resistor R458, a resistor R459, a resistor R460, a resistor R455, and a test point TP13; The first pin of the input port J13 and the first pin of the transient suppression diode G1 are connected in parallel to IO_UART_B_485_A; The second pin of the input port J13 and the second pin of the transient suppression diode G1 are connected in parallel to IO_UART_B_485_B; The third pin of the transient suppression diode G1 is grounded; The second pin of the DC-DC isolation power module U28 is connected to the positive electrode of P5V, and the first end of the capacitor C699 is located on the line between the second pin of the DC-DC isolation power module U28 and the positive electrode of P5V; The first pin of the DC-DC isolation power module U28 is connected to the negative electrode of P5V, and the second end of the capacitor C699 is located on the line between the first pin of the DC-DC isolation power module U28 and the negative electrode of P5V; The 4th pin of the DC-DC isolation power supply module U28, the first end of the capacitor C700 and ISO_5V are connected in parallel; The third pin of the DC-DC isolation power supply module U28, the second end of the capacitor C700 and ISO_GND are connected in parallel; The 4th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D17, and the first end of the light emitting diode D17 is connected to the second end of the resistor R456; The 5th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D18, and the first end of the light emitting diode D18 is connected to the second end of the resistor R461; The 6th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D19, and the first end of the light emitting diode D19 is connected to the second end of the resistor R462; The first end of the resistor R456, the first end of the resistor R461, the first end of the resistor R462 and the first end of the resistor R464 are connected in parallel to P3V3; The 7th pin of the B code decoding chip U29 is grounded; The 8th pin of the B code decoding chip U29 and the first end of the capacitor C705 are connected in parallel with P3V3, and the second end of the capacitor C705 is grounded; The 9th pin of the B code decoding chip U29 is connected in parallel with the second end of the resistor R465, the first end of the resistor R463 and the first end of the capacitor C706, the first end of the resistor R465 is connected to P3V3, the second end of the capacitor C706 is grounded, and the second end of the resistor R463 is connected to B_CORE_RST_N; The 10th pin of the B code decoding chip U29 is connected to B_CORE_IN; The 11th pin of the B code decoding chip U29 is connected to B_CORE_PPS_INT; The 12th pin of the B code decoding chip U29 is connected to the second end of the light emitting diode D20, and the first end of the light emitting diode D20 is connected to the second end of the resistor R464; The 13th pin of the B code decoding chip U29 is connected to B_CORE_UART_TX; The 14th pin of the B code decoding chip U29 is connected to B_CORE_CS; The 15th pin of the B code decoding chip U29 is connected to B_CORE_SDA; The 16th pin of the B code decoding chip U29 is connected to B_CORE_SCK; The first pin of the 485 transceiver chip U30, the second end of the capacitor C701 and the second end of the capacitor C704 are connected in parallel with P3V3, and the first end of the capacitor C701 and the first end of the capacitor C704 are connected in parallel with P3V3 and grounded; The second pin, the seventh pin, the eighth pin of the 485 transceiver chip U30, the first end of the resistor R458 and the first end of the resistor R457 are connected to the ground in parallel; The third pin of the 485 transceiver chip U30 is connected to IO_UART_B_RX The fourth pin of the 485 transceiver chip U30 is connected to the second end of the resistor R458; The fifth pin of the 485 transceiver chip U30 is connected to the second end of the resistor R457; The sixth pin of the 485 transceiver chip U30 is connected to the test point TP13; The 9th pin, the 10th pin and the 15th pin of the 485 transceiver chip U30 are connected to the ground in parallel, and the 9th pin of the 485 transceiver chip U30 is connected to the first end of the resistor R460; The 12th pin of the 485 transceiver chip U30 is connected in parallel with the first end of the resistor R459 and the second end of the resistor R455; The 13th pin of the 485 transceiver chip U30 is connected in parallel with the second end of the resistor R459 and the second end of the resistor R460; Pin 16 of the 485 transceiver chip U30, the first end of the capacitor C702, the first end of the capacitor C703, and the first end of the resistor R455 are connected in parallel to ISO_5V, and the second end of the capacitor C702 and the second end of the capacitor C703 are connected in parallel to the ground.