Switch architecture supporting TSN, cache management method and data scheduling method

Abstract

The invention discloses a deterministic line speed forwarding switch architecture supporting a TSN, an assembly line cache management method and a heterogeneous data scheduling method. Through a Shared-Memory-Switch (SMS) architecture, a pipeline cache management algorithm is designed: each cache unit is only assigned to at most one output port at the same time for data packet storage, so that any data packet can be taken out by the corresponding output port at any time without considering that a corresponding path is being occupied by other output ports. And after the data packet is sent by the corresponding output port, the previously occupied cache unit belongs to null. The total number of the cache units can be adjusted and designed according to the switching bandwidth, so that the problem of packet loss-free queuing buffering is solved.

Description

Technical Field

[0001] The present invention mainly relates to the field of communication technology, and in particular to a deterministic line-speed forwarding switch architecture supporting TSN, a pipeline cache management method and a heterogeneous data scheduling method. Background Art

[0002] Time-Sensitive Networking (TSN) is a set of extended standards developed by the IEEE 802.1TSN Task Group based on standard Ethernet technology. It defines four aspects including clock synchronization, bounded low latency, reliability and resource control to achieve Ethernet deterministic and real-time communication.

[0003] Unlike standard Ethernet, TSN is aimed at industrial networks. Different industrial applications divide the entire industrial Ethernet into many smaller market segments. Traditional application-specific integrated circuit design solutions (ASICs) for TSN switches are difficult to meet cost and flexibility requirements. Field programmable gate arrays (FPGAs) allow industrial equipment manufacturers to flexibly support TSN standards as well as traditional industrial Ethernet protocols due to their programmability and customizability, thereby adapting to changing workloads and protocol standards. At the same time, FPGAs can accelerate protocol connections and data exchanges to cope with the challenges that the growth of network traffic brings to data transmission, management, and conversion.

[0004] As the network scale continues to expand, the network has high link rates, and high-burst business traffic scenarios, FPGA-based TSN switches need to be scalable, support multi-port, high bandwidth (greater than 10G) with zero packet loss and zero congestion, and their switching latency determines the determinism of the entire TSN path. However, FPGA on-chip memory resources are limited. Even the high-end Xilinx FPGA, Virtex-7 XC7VX485T, has only 4.6MB of block memory in total. Therefore, TSN switches also need memory-efficient addressing and switching technologies to flexibly support TSN heterogeneous data scheduling requirements.

[0005] Chinese invention patent CN116319607A discloses a time-sensitive network switch and method based on SMS architecture. The switch adopts SMS architecture as the switching architecture of TSN switch. Although its cut-through transmission mode reduces transmission delay, the data packet content is not fully cached, and input / output ports with different rates cannot be directly connected, and packet loss is prone to occur.

[0006] Chinese invention patent CN113821516A discloses a time-sensitive network switching architecture based on virtual queues. The entire architecture consists of a scheduling information module, a scheduling module, and a parallel cache module. However, its parallel cache module only considers the conflict caused by storing multiple data streams in the same memory space at the same time, and does not explicitly consider the conflict caused by multiple ports reading the same memory space at the same time.

[0007] Chinese invention patent CN116233031A discloses a time-sensitive network switch model, including multiple inbound ports, switching structures, egress modules and outbound ports connected in sequence. The egress module of each port supports the gate mechanism defined by the IEEE802.1Qbv protocol, and uses multiple queues for storing data frames, which occupies a large amount of limited on-chip resources.

[0008] In addition, the above invention patent does not achieve deterministic switching delay, does not clearly support the capabilities of multi-port, high bandwidth, zero packet loss and zero congestion, and does not clearly consider the efficient use of limited FPGA on-chip resources. Summary of the invention

[0009] In view of the above-mentioned defects of the prior art, the technical problems to be solved by the present invention include:

[0010] How to design a switch architecture to overcome the above technical problems.

[0011] To achieve the above object, the present invention provides a deterministic wire-speed forwarding switch architecture supporting TSN, including a MAC ingress port, a MAC egress port, a data frame logic processing area, a shared buffer area, and a crossbar switch matrix ingress;

[0012] The MAC inbound port includes a MAC interface control module, a data buffer module and a frame header parsing module;

[0013] The data frame logic processing area includes a multiplexer, a MAC lookup table and a demultiplexer;

[0014] The shared cache area includes a write crossbar switch matrix, a read crossbar switch matrix, a random access memory, a write direct memory access module and a read direct memory access module;

[0015] The MAC egress port comprises an egress data buffer module, a frame header packaging module, a data buffer module and a MAC interface control module.

[0016] Furthermore, the MAC interface control module is used to control the operation of the data buffer module asynchronous FIFO module and the frame header parsing module;

[0017] The data buffer module is used to receive data frames;

[0018] The frame header parsing module is used to parse and separate the incoming data into a frame header and a valid load, and send the frame header to the data frame logic processing area and send the valid load to the write direct memory access module of the shared cache area.

[0019] Further, the multiplexer is used to send the frame headers to the MAC lookup table in sequence;

[0020] The MAC lookup table obtains a feasible RAM chip select bit selection address according to the pipeline cache management method, and sends the feasible RAM chip select bit selection address to the demultiplexer;

[0021] The demultiplexer DEMUX sends the feasible RAM chip select bit select address to the corresponding write direct memory access module.

[0022] Further, the write direct memory access module writes DMA to receive the feasible RAM chip select bit selection address and the effective load sent by the demultiplexer, and controls the operation of the write crossbar switch matrix; after the write crossbar switch matrix completes writing, the write RAM busy signal is released to the crossbar switch matrix, and the write-completed frame header and the feasible chip select bit selection address are sent together to the export data buffer module on the corresponding output port side;

[0023] The write crossbar switch matrix is ​​used to receive the feasible RAM chip select bit selection address and the effective load sent by the write direct memory access module, and write the effective load into the random access memory according to the feasible RAM chip select bit selection address;

[0024] The random access memory is used to store the payload.

[0025] Further, the read direct memory access module is used to receive the frame header and the feasible RAM chip select bit selection address sent by the egress data buffer module, read the effective load according to the feasible RAM chip select bit selection address, and send the effective load information to the frame header packaging module; once the frame header packaging module completes the processing, the read direct memory access module recycles the RAM chip select bit selection information through a multiplexer, so that the address can be reallocated;

[0026] The read crossbar switch matrix is ​​controlled by the read direct memory access module to read the effective load information in the random access.

[0027] Further, the egress data buffer module is used to receive the frame header and the feasible chip select bit selection address sent by the write direct memory access module, and send the frame header and the feasible chip select bit selection address to the read direct memory access module;

[0028] The frame header packaging module is used to receive the frame header and effective load sent by the read direct memory access module, and splice the frame header and effective load together to form a complete data frame and send it to the asynchronous FIFO module of the data buffer module.

[0029] A pipeline cache management method based on the aforementioned architecture: the RAM module is initialized to an idle state, the output port is not bound, and there are multiple idle areas, so that each RAM module can decide a feasible cache according to the scheduling requirements in each clock cycle.

[0030] Furthermore, the pipeline cache management method comprises the steps of:

[0031] S1: If there is a data frame request cache, enter S2; if there is a data frame returned to the cache, enter S3;

[0032] S2: Determine whether the RAM has been bound to the output port, if yes, go to S4, otherwise go to S5;

[0033] S3: Determine whether the RAM status is idle and whether all areas are idle. If yes, unbind the output port and return to S1. Otherwise, bind the output port unchanged and return to S1.

[0034] S4: Check whether the requested port is consistent with the bound output port. If so, proceed to S5. Otherwise, proceed to S6.

[0035] S5: Determine whether the RAM state is in an idle state and whether there is an idle area. If so, enter S7, otherwise enter S6;

[0036] S6: Allocation failed, and the system returns to S1 without any response;

[0037] S7: Take an idle area as the chip select address, and deliver the RAM's own bit select address to the arbiter, update the current bound output port to the request port, and return to S1 after successful allocation.

[0038] A heterogeneous data scheduling method based on the aforementioned architecture controls the forwarding time of queues of different flows by managing the timing of outputting frame headers on the EgressFIFO side.

[0039] Furthermore, the heterogeneous data scheduling method comprises the steps of:

[0040] S11, the frame header entering the EgressFIFO1 module can distinguish TT, AVB, BE and other data frames by identifying the Priority field in its VLAN tag, and store the frame headers of different types of data frames into different buffer queue FIFOs through DEMUX;

[0041] S12: For AVB traffic, a credit-based gate can be set at the front of its queue. This gate is only opened when the credit value of the queue is greater than zero, allowing packets to pass through; all queues are connected to a time-aware flow control gate, whose opening state is determined by the global control list.

[0042] Compared with the prior art solutions, the technical effects of the present invention are:

[0043] The present invention designs a pipeline cache management algorithm through a Shared-Memory-Switch (SMS) architecture: each cache unit is assigned to at most one output port at the same time for data packet storage, so that any data packet can be taken out by the corresponding output port at any time without considering that the corresponding path is occupied by other output ports. After the data packet is sent by the corresponding output port, the previously occupied cache unit is assigned to be empty. The total number of cache units can be adjusted and designed according to the switching bandwidth to meet the problem of no packet loss queuing buffer.

[0044] The present invention separates the external clock domain and the internal logic processing main clock domain through asynchronous FIFO. The external clock domain can be connected to multiple ports with different transmission rates. The internal clock domain can adjust the frequency to realize logic processing at different rates to meet the needs of different exchange bandwidths.

[0045] The present invention uses a Shared-Memory-Switch (SMS) architecture, and the shared cache mode adopted is: each cache unit stores the effective load data (payload) part of each frame. The EgressFIFO side only manages the frame header (HDR) of the frame and the chip selection and bit selection address of the cache unit storing the payload through a pipeline cache management algorithm to achieve efficient management of the memory unit.

[0046] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the architecture of a deterministic line-speed forwarding switch supporting TSN of the present invention.

[0048] Figure 2 It is a schematic diagram of the pipeline cache management algorithm of the present invention.

[0049] Figure 3 It is a schematic diagram of the TSN heterogeneous data scheduling method of the present invention. DETAILED DESCRIPTION

[0050] The following describes several preferred embodiments of the present invention with reference to the drawings in the specification, so that the technical content is clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0051] like Figure 1 As shown, this embodiment discloses a deterministic wire-speed forwarding switch architecture supporting TSN, and the overall architecture mainly includes four parts: MAC inlet port side, MAC outlet port side, data frame logic processing area and shared cache area. The shared cache area adopts the Shared-Memory-Switch (SMS) architecture, which consists of two levels of CROSSBAR (write CROSSBAR and read CROSSBAR) and multiple RAMs (the number of RAMs supports customization and can be flexibly adjusted according to the on-chip resource adjustment and the actual switching bandwidth requirements).

[0052] Data frames from multiple different external clock domains (1G or 10G) enter the asynchronous FIFO (for the transmission of data signals across clock domains) from the MAC ingress port side, and then enter the internal master clock domain. The data frame is parsed by the frame header, and the frame header (HDR, including 6-byte destination address, 6-byte source address, 2-byte type or length and 4-byte VLAN tag) and the payload (payload, greater than or equal to 46 bytes) are separated. The frame header enters the data frame logic processing area, while the payload is on the write DMA side, waiting to enter the shared buffer area.

[0053] The data frame logic processing area sequentially performs MAC address lookup table on the frame headers (HDR) from different input ports through the multiplexer (MUX) pipeline. The MAC lookup table queries the corresponding output port number. After the pipeline cache management algorithm, each RAM outputs a feasible cache unit (RAM) chip select address and bit select address. Multiple feasible RAM addresses output a feasible RAM chip select bit select address through the priority arbitrator. For each port, the opportunity to allocate each RAM is relatively fair. Each RAM may be selected by each port at different times, that is, shared cache can be achieved, and limited on-chip resources are efficiently utilized. The output feasible RAM chip select bit select address is delivered to the corresponding write DMA through the demultiplexer (DEMUX). The data frame logic processing area only manages the frame header (HDR), rather than the entire content of the entire frame, which greatly saves limited FPGA on-chip resources.

[0054] Each input port side corresponds to a write DMA. Each write DMA receives the payload and corresponding chip select and bit select information from each input port side, and writes the payload into the corresponding cache unit (RAM) through the write CROSSBAR module.

[0055] After each DMA write is completed, the busy signal of the write RAM is released through CROSSBAR, and the frame header (HDR) of the end of the write DMA + the write RAM chip select bit address are sent to the EgressFIFO on the corresponding output port side.

[0056] After receiving the frame header (HDR) + write RAM chip select bit address, the EgressFIFO delivers it to the read DMA on the read port side. The read DMA reads the payload information from the corresponding RAM chip select bit address and delivers it to the frame header packaging module. The frame header packaging module splices the frame header (HDR) and payload together to form a complete data frame and sends it to the asynchronous FIFO module to enter the external clock domain. In this step, the frame header packaging module is pipelined and loaded tightly, so that the frame transmission interval is less than or equal to the frame arrival interval, thereby achieving multi-port full bandwidth line rate guarantee. The IEEE 802.1Qbv protocol designs a gated operation mechanism, namely the time-aware shaper (TAS). The gated mechanism maintains a gated list (GCL) to record the gated state and duration of each queue. By designing a TSN heterogeneous data scheduling module at the EgressFIFO, the gated transmission of the queued transmission can follow the corresponding gate operation to control the forwarding time of queues with different traffic, thereby flexibly supporting the TSN heterogeneous data scheduling algorithm.

[0057] Once the frame header packaging module completes processing, the read DMA module passes the chip select bit selection information of the RAM through a MUX module to recycle the address information so that the address can be reallocated.

[0058] like Figure 2 As shown, this embodiment also discloses a pipeline cache management method based on the SMS architecture, the algorithm enables each RAM module to decide a feasible cache according to the scheduling requirements in each clock cycle. The RAM module is initialized to an idle state, the output port is not bound, and there are multiple idle areas. The embodiment specifically includes the following steps:

[0059] S1: If there is a data frame requesting the cache, go to S2; if there is a data frame returning the cache, go to S3.

[0060] S2: Determine whether the RAM has been bound to an output port, if so, enter S4, otherwise enter S5.

[0061] S3: Determine whether the RAM status is idle and whether all areas are idle. If so, unbind the output port and return to S1. Otherwise, bind the output port unchanged and return to S1.

[0062] S4: Check whether the requested port is consistent with the bound output port. If so, proceed to S5; otherwise, proceed to S6.

[0063] S5: Determine whether the RAM state is in an idle state and whether there is an idle area. If so, enter S7, otherwise enter S6.

[0064] S6: Allocation failed, and the process returns to S1 without any response.

[0065] S7: Take an idle area as the chip select address, and deliver the RAM's own bit select address to the arbiter, update the current bound output port to the request port, and return to S1 after successful allocation.

[0066] like Figure 3 As shown, the embodiment of the present invention also discloses a TSN heterogeneous data scheduling method, in which the module controls the forwarding time of queues of different flows by managing the timing of output frame header (HDR) on the EgressFIFO side. The embodiment specifically includes the following steps:

[0067] S11: The frame header (HDR) entering the EgressFIFO1 module can distinguish TT, AVB, BE and other data frames by identifying the Priority field in its VLAN tag, and store the frame headers (HDR) of different types of data frames in different buffer queue FIFOs through DEMUX. Usually, the highest priority queue is usually assigned to time-sensitive traffic (TT), the second priority is assigned to audio and video bridging traffic (AVB), and the remaining queues are used for best effort traffic (BE).

[0068] S12: For AVB traffic, a credit-based (CBS) gate can be set at the front of its queue. This gate is only opened when the credit value of the queue is greater than zero, allowing packets to pass through. All queues are connected to a time-aware flow control (TAS) gate, whose opening state is determined by the global control list (GCL). For example, in a specific time period from T0 to T1, only the gate with priority 7 remains open, while the gates of other queues remain closed. This means that during this time period, only the frame header (HDR) of the TT flow can enter the EgressFIFO2 through the MUX module and further pass through the frame header packaging module to transmit the TT data flow.

[0069] Each item in the global control list GCL defines the TAS gating state of each queue within a specific time window. In this way, a time division multiplexing mechanism is implemented to control the forwarding time of queues with different traffic flows, thereby flexibly supporting the TSN data scheduling algorithm.

[0070] This paper aims to solve the problem of deterministic line-rate switching, forwarding and loss-free queuing buffering between multiple input and output ports of TSN switches.

[0071] The present invention designs a pipeline cache management algorithm through a Shared-Memory-Switch (SMS) architecture: each cache unit is assigned to at most one output port at the same time for data packet storage, so that any data packet can be taken out by the corresponding output port at any time without considering that the corresponding path is occupied by other output ports. After the data packet is sent by the corresponding output port, the previously occupied cache unit is assigned to be empty. The total number of cache units can be adjusted and designed according to the switching bandwidth to meet the problem of packet loss-free queuing buffering. The input port selects the cache unit according to the situation that the cache unit belongs to the output port. Each cache unit is assigned to at most one output port at the same time, which can isolate the influence between data packets of different output ports. Therefore, multiple output ports will not access the same cache unit, avoiding data transmission conflicts. The design of the pipeline can ensure multi-port line rate forwarding (each input port can always find a selectable cache unit; each output port has at least one data packet sent to the port, and at least one is being forwarded).

[0072] The present invention separates the external clock domain and the internal logic processing main clock domain through asynchronous FIFO. The external clock domain can be connected to multiple ports with different transmission rates, and the internal clock domain can adjust the frequency to realize logic processing at different rates to meet the needs of different exchange bandwidths. The minimum frame arrival interval calculation method is: shortest frame length / transmission bandwidth*main clock frequency. For the shortest 64-byte data frame under the 1G port network, when the main clock frequency adopts 156.25Mhz, the minimum frame interval is considered to be 12 bytes, and its frame arrival interval is 95 clock cycles, that is, the current main clock frequency can theoretically achieve 95 1G ports full bandwidth line rate guarantee; for the 10G port network, when the main clock frequency adopts 156.25Mhz, the minimum frame interval is considered to be 12 bytes, and its frame arrival interval is 9 clock cycles, that is, the current main clock frequency can theoretically achieve 9 10G ports full bandwidth line rate guarantee. When the internal clock domain is improved, the frame arrival interval will be further increased, which not only helps to ensure the internal frame logic processing, but also increases the upper limit of the number of full bandwidth ports.

[0073] The pipeline cache management algorithm based on the SMS architecture provides a deterministic switching channel. Data packets can reach the output port within a deterministic and bounded time range ([frame length, max{N, frame length}] clock cycles, where N represents the total number of ports), thereby achieving zero packet loss queuing buffering and deterministic forwarding capabilities. The lower bound represents that in an ideal situation, after the port initiates logical frame processing, the HDR of frame header parsing responds to the MAC address lookup table through the MUX module at the first moment. The upper bound represents that in the worst case, N ports initiate logical frame processing at the same time. The MUX module based on round-robin makes a port wait for a maximum of N clock cycles to get a processing response. Bounded deterministic forwarding lays the foundation for the implementation of various TSN protocols.

[0074] The upper limit of the number of ports under full bandwidth can be theoretically calculated through the frame arrival interval, providing strong theoretical support for the realization of TSN multi-port switches.

[0075] In view of the limited on-chip resources of TSN switches, supporting TSN heterogeneous data scheduling requires efficient memory site selection and switching.

[0076] The present invention uses a Shared-Memory-Switch (SMS) architecture, and the shared cache mode adopted is: each cache unit stores the effective load data (payload) part of each frame. The EgressFIFO side only manages the frame header (HDR) of the frame and the chip select and bit select address of the cache unit storing the payload through the pipeline cache management algorithm to achieve efficient management of the memory unit. Through the Shared-Memory-Switch (SMS) architecture, all ports share data.

[0077] The data cache area improves the on-chip resource utilization. The separation of the frame header (HDR) and the payload can greatly reduce the occupied on-chip resources. Through the pipeline cache management algorithm, the output port supports the design of different TSN data scheduling algorithms by managing the chip select and bit select addresses of the cache unit that manages (HDR) and stores the payload, which improves the flexibility of cache management. Efficiently utilize limited on-chip resources and flexibly support TSN data scheduling algorithms.

[0078] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0079] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0080] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0081] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A deterministic wire-speed forwarding switch architecture supporting TSN, characterized in that: It includes MAC input port, MAC output port, data frame logic processing area, shared buffer area and crossbar switch matrix input; The MAC inbound port includes a MAC interface control module, a data buffer module and a frame header parsing module; The data frame logic processing area includes a multiplexer, a MAC lookup table and a demultiplexer; The shared cache area includes a write crossbar switch matrix, a read crossbar switch matrix, a random access memory, a write direct memory access module and a read direct memory access module; The MAC egress port comprises an egress data buffer module, a frame header packaging module, a data buffer module and a MAC interface control module.

2. The TSN-supporting deterministic wire-speed forwarding switch architecture according to claim 1, characterized in that: The MAC interface control module is used to control the operation of the asynchronous FIFO module of the data buffer module and the frame header parsing module; The data buffer module is used to receive data frames; The frame header parsing module is used to parse and separate the incoming data into a frame header and a valid load, and send the frame header to the data frame logic processing area and send the valid load to the write direct memory access module of the shared cache area.

3. The TSN-supporting deterministic wire-speed forwarding switch architecture according to claim 2, characterized in that: The multiplexer is used to send the frame headers to the MAC lookup table in sequence; The MAC lookup table obtains a feasible RAM chip select bit selection address according to the pipeline cache management method, and sends the feasible RAM chip select bit selection address to the demultiplexer; The demultiplexer DEMUX sends the feasible RAM chip select bit select address to the corresponding write direct memory access module.

4. The TSN-supporting deterministic wire-speed forwarding switch architecture according to claim 3, characterized in that: The write direct memory access module writes DMA to receive the feasible RAM chip select bit selection address and the effective load sent by the demultiplexer, and controls the operation of the write crossbar switch matrix; after the write crossbar switch matrix completes writing, it releases the busy signal of the write RAM to the crossbar switch matrix, and sends the frame header of the writing completion and the feasible chip select bit selection address together to the export data buffer module on the corresponding output port side; The write crossbar switch matrix is ​​used to receive the feasible RAM chip select bit selection address and the effective load sent by the write direct memory access module, and write the effective load into the random access memory according to the feasible RAM chip select bit selection address; The random access memory is used to store the payload.

5. The TSN-supporting deterministic wire-speed forwarding switch architecture according to claim 4, characterized in that: The read direct memory access module is used to receive the frame header and the feasible RAM chip select bit selection address sent by the egress data buffer module, read the effective load according to the feasible RAM chip select bit selection address, and send the effective load information to the frame header packaging module; once the frame header packaging module completes the processing, the read direct memory access module passes the RAM chip select bit selection information through a multiplexer to recycle the address information so that the address can be reallocated; The read crossbar switch matrix is ​​controlled by the read direct memory access module to read the effective load information in the random access.

6. The TSN-supporting deterministic wire-speed forwarding switch architecture according to claim 5, characterized in that: The egress data buffer module is used to receive the frame header and the feasible chip select bit selection address sent by the write direct memory access module, and send the frame header and the feasible chip select bit selection address to the read direct memory access module; The frame header packaging module is used to receive the frame header and effective load sent by the read direct memory access module, and splice the frame header and effective load together to form a complete data frame and send it to the asynchronous FIFO module of the data buffer module.

7. A pipeline cache management method based on the architecture as claimed in claims 1-6, characterized in that: The RAM module is initialized to an idle state, with no output ports bound and multiple idle areas, so that each RAM module can decide on a feasible cache according to scheduling requirements in each clock cycle.

8. The pipeline cache management method according to claim 7, characterized in that: Includes steps: S1: If there is a data frame request cache, enter S2; if there is a data frame returned to the cache, enter S3; S2: Determine whether the RAM has been bound to the output port, if yes, go to S4, otherwise go to S5; S3: Determine whether the RAM status is idle and whether all areas are idle. If yes, unbind the output port and return to S1. Otherwise, bind the output port unchanged and return to S1. S4: Check whether the requested port is consistent with the bound output port. If so, proceed to S5. Otherwise, proceed to S6. S5: Determine whether the RAM state is in an idle state and whether there is an idle area. If so, enter S7, otherwise enter S6; S6: Allocation failed, and the system returns to S1 without any response; S7: Take an idle area as the chip select address, and deliver the RAM's own bit select address to the arbiter, update the current bound output port to the request port, and return to S1 after successful allocation.

9. A heterogeneous data scheduling method based on the architecture as claimed in claims 1-6, characterized in that: On the EgressFIFO side, the forwarding time of queues of different traffic flows is controlled by managing the timing of outputting frame headers.

10. The heterogeneous data scheduling method according to claim 9, characterized in that: Includes steps: S11, the frame header entering the EgressFIFO1 module can distinguish TT, AVB, BE and other data frames by identifying the Priority field in its VLAN tag, and store the frame headers of different types of data frames into different buffer queue FIFOs through DEMUX; S12: For AVB traffic, a credit-based gate can be set at the front of its queue. This gate is only opened when the credit value of the queue is greater than zero, allowing packets to pass through; all queues are connected to a time-aware flow control gate, whose opening state is determined by the global control list.

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