Data transmission processing method and related equipment

Abstract

The invention discloses a data transmission processing method and related equipment, and aims to overcome the defect that a gigabit Ethernet controller and a gigabit Ethernet switch cannot receive data from a 10-gigabit Ethernet in the prior art. According to the method, 10-gigabit Ethernet data are received through an XGMII interface and written into a cache, a first state machine is used for controlling the data to be written into a specified cache block, a second state machine is used for controlling cache reading operation, and the data are read from the cache block, recombined and output to the GMII interface. In the data restructuring process, the formats of the large end and the small end of the data are redefined to ensure that the formats are consistent with the requirements of target equipment. According to the method and the related equipment, the problem of adaptation of a link layer data transmission protocol and an interface standard between Ethernet equipment with different rates is effectively solved, and the flexibility and the expansibility of application of the Ethernet equipment are improved.

Description

Technical Field

[0001] The present invention relates to the field of electrical communication technology, and in particular to a data transmission processing method and related equipment. Background Art

[0002] In the field of modern computer networks, Ethernet technology, as one of the most widely used network technologies in local area networks and wide area networks, has been continuously developing and expanding its applications. With the continuous advancement of network technology, the speed and functions of Ethernet devices are also constantly improving, from the initial 100M Ethernet to Gigabit Ethernet, and then to today's 10G Ethernet. These Ethernet devices of different speeds need to be connected and communicated with each other in actual applications to meet the network requirements in different scenarios. Therefore, how to achieve compatibility and efficient communication between Ethernet devices of different speeds has become an important technical issue.

[0003] At present, in order to achieve the connection between Ethernet devices of different speeds, the rate switching technology of Ethernet fusion port is usually adopted. This technology enables Ethernet devices of different speeds to work together in the same network by realizing automatic negotiation and switching of the rate at the physical layer. However, this rate switching technology mainly focuses on the rate matching of the physical layer, and does not effectively solve the adaptation problem of the data transmission protocol and interface standard of the link layer. For example, when a Gigabit Ethernet device using the GMII interface is connected to a 10 Gigabit Ethernet device using the XGMII interface, due to the differences in data transmission timing, protocol and interface standards between the two, direct connection will cause data transmission errors or communication failures. Therefore, the existing Ethernet fusion port rate switching technology cannot completely solve the data transmission problem between Ethernet devices of different speeds.

[0004] In order to solve the above problems, a new technical means or device is needed to achieve the adaptation of link layer data transmission protocols and interface standards between Ethernet devices of different rates. Summary of the invention

[0005] The object of the present invention is to provide a data transmission processing method and related equipment to overcome the deficiency that the prior art Gigabit Ethernet controller and switch cannot receive data from 10 Gigabit Ethernet.

[0006] In order to achieve the above object, the present invention adopts the following technical solution: In a first aspect, the present invention provides a data transmission processing method, comprising: Receive 10 Gigabit Ethernet data through the XGMII interface and write it into the cache; Writing 10 Gigabit Ethernet data into a designated cache block through the control of a first state machine; The cache read operation is controlled by the second state machine, data is read from the cache block and data is reorganized and output to the GMII interface; During the data reorganization process, the big-endian and big-endian formats of the data are redefined.

[0007] The 10 Gigabit Ethernet data is received through the XGMII interface and written into the cache, including: Initialize the state machine and monitor the link idle signal of the XGMII interface; Detect the start control word SCC signal and jump to the pre-SFD state; Detect the start frame delimiter SFD signal, determine whether the buffer space is available, and jump to the data writing state; Write the received data to the buffer until the data transfer is complete.

[0008] The step of writing the 10 Gigabit Ethernet data into the designated cache block through the first state machine control includes: Use a state machine to manage cache write operations, including allocation, writing, and release of cache blocks; The state machine writes the received data into the specified cache block according to the signal status of the XGMII interface.

[0009] The cache read operation is controlled by the second state machine, data is read from the cache block and data is reorganized and output to the GMII interface, including: Initialize the state machine and monitor the read operation start signal; After detecting the read operation start signal, data is read from the cache block and reorganized according to the requirements of the GMII interface protocol; The reorganized data is output through the GMII interface.

[0010] In the process of data reorganization, the big-endian and small-endian formats of the data are redefined, including: Detect the big-endian and small-endian formats of the data. If the big-endian and small-endian formats of the data are inconsistent with the requirements of the target device, perform big-endian and small-endian conversion. Use dedicated endian conversion logic to adjust the byte order of the data, converting the data in little-endian format to big-endian format, or converting the data in big-endian format to little-endian format; Make sure the converted data format matches the requirements of the Gigabit Ethernet device to ensure that the data can be correctly received and processed.

[0011] The cache includes 4 independent cache blocks, each of which has a storage depth of 1600 and a bit width of 36 bits, of which 4 bits are used to store the RXC control flag and 32 bits are used to store the RXD data.

[0012] The data output by the GMII interface is sent in four times through a 32-bit shift register, with 8 bits of data sent each time, and the minimum frame interval time is waited after the transmission is completed.

[0013] In a second aspect, the present invention provides a data transmission processing system, comprising: A data receiving module, used for receiving 10 Gigabit Ethernet data; A first state machine, used for controlling the writing of 10 Gigabit Ethernet data into a designated cache block; The second state machine is used to control the cache read operation, read the data from the cache block and reorganize the data, and output it to the GMII interface; The big-endian and small-endian conversion module is used to redefine the big-endian and small-endian formats of data during the data reorganization process.

[0014] In a third aspect, the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the data transmission processing method described above when executing the computer program.

[0015] In a fourth aspect, the invention provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps of the data transmission processing method described above are implemented.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a data transmission processing method and related equipment, which effectively solves the problem of link layer data transmission protocol and interface standard adaptation between Ethernet devices with different rates. Through a specially designed interface adapter and data processing logic, data transmission timing conversion and protocol adaptation from the XGMII interface of 10 Gigabit Ethernet to the GMII interface of Gigabit Ethernet are realized, overcoming the problem of direct connection data transmission error or communication failure caused by differences in data transmission timing, protocol and interface standards.

[0017] This technical solution improves the flexibility and scalability of Ethernet device applications. By flexibly redefining the big-endian and small-endian formats of data, it ensures the compatibility of data between different interfaces and improves the reliability of data transmission. This enables the original Gigabit Ethernet network products to connect to 10 Gigabit Ethernet network devices, effectively enriching the application scenarios of Ethernet devices.

[0018] In addition, the method and related devices ensure the correct reception and processing of data. The write and read operations of the cache are managed by the state machine to ensure that each cache block stores a complete data frame, thereby avoiding errors in the data transmission process. During the data reorganization process, the big-endian and small-endian formats of the data are redefined to ensure that the converted data format matches the requirements of the Gigabit Ethernet device.

[0019] The solution also optimizes the timing and protocol conversion of data transmission. Through the special state machine design, the data transmission timing of the XGMII interface and the GMII interface is precisely controlled to ensure the correctness and integrity of the data. Through the reasonable allocation and management of the cache, the efficiency and reliability of data transmission are improved.

[0020] Finally, the method and related devices are compatible with Ethernet devices of different rates. Through the design of the interface adapter, the Gigabit Ethernet device can effectively communicate with the 10 Gigabit Ethernet device, solving the compatibility problem between devices of different rates. This provides a universal solution that is suitable for network requirements in different scenarios and improves the versatility and interoperability of network devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a schematic diagram of a data transmission processing method according to an embodiment of the present invention.

[0022] Figure 2 FIG. 1 is a schematic diagram of the structure of an interface adapter in an embodiment of the present invention.

[0023] Figure 3 This is a state diagram of a 10 Gigabit Ethernet interface data processing state machine in an embodiment of the present invention.

[0024] Figure 4 This is a state diagram of a Gigabit Ethernet interface data processing state machine in an embodiment of the present invention.

[0025] Figure 5 Schematic diagram of a data transmission and processing system in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In the field of modern computer networks, Ethernet technology, as one of the most widely used network technologies in local area networks and wide area networks, has been continuously developing and expanding its applications. With the continuous advancement of network technology, the speed and functions of Ethernet devices are also constantly improving, from the initial 100M Ethernet to Gigabit Ethernet, and then to today's 10G Ethernet. These Ethernet devices of different speeds need to be connected and communicated with each other in actual applications to meet the network requirements in different scenarios. Therefore, how to achieve compatibility and efficient communication between Ethernet devices of different speeds has become an important technical issue.

[0027] At present, in order to achieve the connection between Ethernet devices of different speeds, the rate switching technology of Ethernet fusion port is usually adopted. This technology enables Ethernet devices of different speeds to work together in the same network by realizing automatic negotiation and switching of the rate at the physical layer. However, this rate switching technology mainly focuses on the rate matching of the physical layer, and does not effectively solve the adaptation problem of the data transmission protocol and interface standard of the link layer. For example, when a Gigabit Ethernet device using the GMII interface is connected to a 10 Gigabit Ethernet device using the XGMII interface, due to the differences in data transmission timing, protocol and interface standards between the two, direct connection will cause data transmission errors or communication failures. Therefore, the existing Ethernet fusion port rate switching technology cannot completely solve the data transmission problem between Ethernet devices of different speeds.

[0028] In order to solve the above problems, a new technical means or device is needed to achieve the adaptation of link layer data transmission protocols and interface standards between Ethernet devices of different speeds. This application proposes a data transmission processing method for XGMII to GMII, which realizes the data transmission timing conversion and protocol adaptation from the XGMII interface of 10 Gigabit Ethernet to the GMII interface of Gigabit Ethernet by designing a special interface adapter and data processing logic. This technical solution not only solves the problem of data interface mismatch, but also can flexibly redefine the big and small ends of the data, thereby improving the flexibility and scalability of Ethernet device applications.

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "several" is two or more, unless otherwise clearly and specifically defined.

[0031] Reference Figure 2 FIG. 1 is a block diagram of an interface adapter structure provided in a specific embodiment of the present invention, and the interface adapter includes: GMII data processing unit: responsible for processing data from Gigabit Ethernet devices, including data reception and transmission.

[0032] XGMII data processing unit: responsible for processing data from 10G physical layer devices, including data reception and transmission.

[0033] Cache (MEM0, MEM1, MEM2, MEM3): used to store data frames. Each cache block (MEM0, MEM1, MEM2, MEM3) can store a complete data frame. The cache blocks are connected by a bus, and data can be transferred between cache blocks.

[0034] The interface adapter can perform Figure 1 The data transmission processing method shown includes: S1, receives 10 Gigabit Ethernet data through the XGMII interface and writes it into the cache; Specifically, this step includes initializing the state machine and monitoring the link idle signal of the XGMII interface. After initialization, the state machine is in an idle state, waiting for the link idle signal to appear. When the link idle signal is detected, the state machine enters the receive preparation state, indicating that the link has entered the idle state and can start receiving data. Next, the state machine detects the start control word SCC signal. When the signal is detected, the state machine jumps to the pre-SFD state and prepares to receive the start frame delimiter SFD signal. In the pre-SFD state, the state machine continues to monitor the signal of the XGMII interface. When the start frame delimiter SFD signal is detected, the state machine determines whether the cache space is available. If the cache space is available, the state machine jumps to the data write state and starts to write the received data to the specified cache block. During the data writing process, the state machine continues to monitor the data transmission of the XGMII interface until the data transmission completion signal is detected, that is, at least 1 bit of RXC is 1, indicating that the data transmission is completed, and the state machine returns to the idle state.

[0035] S2, writing the 10 Gigabit Ethernet data into a designated cache block through the control of the first state machine; Specifically, this step includes using a state machine to manage the write operation of the cache, involving the allocation, writing and release of the cache block. The state machine manages the cache block through a 4-bit signal to mark the cache as not empty, and each bit corresponds to a cache space. When the write operation is completed, the non-empty flag bit corresponding to the current write operation cache space is set; when the read operation is completed, the non-empty flag bit corresponding to the current read operation cache space is cleared. The state machine also uses a 4-bit write pointer signal to mark which cache space is currently being written. The write pointer is initially 4'b0001, indicating the first cache space. When the write operation starts, the write pointer moves left and maintains the current value until the next write operation. When the write pointer is 4'b1000, if the write operation is performed again, the write pointer is updated to 4'b0001, and the cache block is used cyclically. The state machine writes the received data into the specified cache block according to the signal state of the XGMII interface to ensure that each cache block stores a complete data frame.

[0036] S3, controlling the cache read operation through the second state machine, reading data from the cache block and reorganizing the data, and outputting the data to the GMII interface; Specifically, this step includes initializing the state machine and monitoring the read operation start signal. After initialization, the state machine is in an idle state, waiting for the read operation start signal to appear. When the read operation start signal is detected, the state machine reads the data from the cache block and reorganizes the data according to the requirements of the GMII interface protocol. The reorganization process includes sending a preamble, SFD signal and data frame, and performing data verification. The reorganized data is sent to the Gigabit Ethernet device through the GMII interface. The state machine ensures the correctness and integrity of the data and complies with the timing requirements of the GMII interface.

[0037] S4, during the data reorganization process, the big-endian and big-endian formats of the data are redefined.

[0038] Specifically, this step includes detecting the big-endian and small-endian formats of the data, and performing big-endian conversion if the big-endian and small-endian formats of the data are inconsistent with the requirements of the target device. During the data reorganization process, the state machine uses a dedicated big-endian and small-endian conversion logic to adjust the byte order of the data. For example, data in the little-endian format is converted to the big-endian format, or data in the big-endian format is converted to the little-endian format. The converted data format matches the requirements of the Gigabit Ethernet device to ensure that the data can be correctly received and processed. The big-endian and small-endian conversion ensures the compatibility of data between different interfaces and improves the reliability of data transmission.

[0039] In a specific embodiment of the present invention, Figure 2The interface adapter of the structure shown works at a clock frequency of 312.5MHz and uses a memory to cache the data to be processed. The cache width is set to 36-bit to store the 4-bit RXC control flag and 32-bit RXD data; the depth is 1600, which is divided into 4 cache spaces to ensure that one cache space can completely store a standard length Ethernet data frame. The maintenance of the cache is divided into the following three aspects: First, a 4-bit signal is used to mark the cache as not empty, and each bit corresponds to a cache space. When the write operation is completed, the non-empty flag bit corresponding to the current write operation cache space is set; when the read operation is completed, the non-empty flag bit corresponding to the current read operation cache space is cleared.

[0040] Secondly, a 4-bit write pointer signal is used to mark which cache space is currently being written. The write pointer is initially 4'b0001. When the write operation starts, the write pointer moves left and keeps the current value until the next write operation. When the write pointer is 4'b1000, if the write operation is performed again, the write pointer is updated to 4'b0001.

[0041] Thirdly, a 4-bit read pointer signal is used to mark which cache space is currently being read. The read pointer is initially 4'b0001. After the read operation is completed, the read pointer is shifted left and updated. The read pointer signal and the cache mark non-empty signal are ANDed. If it is not 0, it means that the write operation of the cache space to be read has been completed, and the cache space is not empty, which is used as the start instruction of the read operation.

[0042] The data write and read operations on the memory are controlled by the front and back two-level state machines. In this process, the transmission protocol support for GMII and XGMII is realized, and the conversion of interface protocol and the conversion of big and small end are completed. The specific operations are as follows: First, data is received from the XGMII interface and written into the cache.

[0043] like Figure 3 As shown, the 10 Gigabit Ethernet interface data processing state machine is set, and four states, IDLE, DET_SCC, PRE_SFD and DATA, are set respectively.

[0044] The IDLE state is set to be in the IDLE state after the state machine is initialized. In this state, the XGMII interface value is monitored. When RXC=4'b1111 and RXD=32'h07070707 is detected, it indicates that the link has entered the idle state and can support data reception. The state machine will jump to the DET_SCC state.

[0045] DET_SCC state. In this state, the receiving SCC is monitored on the XGMII interface. That is, RXC=4'b0001,RXD=32'h555555FB is detected, and the state jumps to PRE_SFD state.

[0046] PRE_SFD state. In this state, the receiving SFD is monitored on the XGMII interface, that is, RXC=4'b1000, RXD=32'hFD555555 is detected. In order to avoid reading and writing the same cache space at the same time, which may cause data reading errors, it is necessary to determine whether the cache space to be written has completed the read operation at this time, and then jump to the DATA state; otherwise, return to the IDLE state and give up receiving the current frame.

[0047] DATA state: In this state, the received data is written to the cache. If at least one bit of RXC is detected to be 1, it means that the data transmission is completed, and the state jumps to IDLE state. The write cache operation is completed.

[0048] The data is then read from the buffer and sent to the GMII interface.

[0049] like Figure 4 As shown, the Gigabit Ethernet interface data processing state machine is set, and the IDLE, PRE, PRE_RD, PRE_JUD, SFD, OUTPUT, RD, RD_JUD, WAIT, LAST and FRA_INTV states are set respectively.

[0050] Among them, in the IDLE state, the state machine is initially in the IDLE state. When the read operation start mark is detected (the result of the sum of the read pointer signal and the cache mark non-empty signal is not 0), the state machine jumps from the IDLE state to the PRE state.

[0051] PRE state, at this time, set the rxdv signal of the GMII interface, and send a 5-beat preamble (8'h55) through phy_rxd[7:0], and then jump to the PRE_RD state.

[0052] In the PRE_RD state, a read operation is initiated on the cache to read out the 4-bit RXC and 32-bit RXD. The next beat enters the PRE_JUD state and sends a beat of preamble code.

[0053] PRE_JUD state, the next beat jumps to SFD state, and sends a beat of preamble code. So far, the sending of 7 beats of preamble code is completed.

[0054] In the SFD state, SFD is sent and the read data RXC is judged to be 4'b0000. If it is not 4'b0000, it means that the current data frame data is wrong, jump to the IDLE state, clear the rxdv signal, abandon the current transmission error data frame, and wait for the next transmission; if it is, jump to the OUTPUT state.

[0055] OUTPUT state, in this state, 32-bit RXD is stored in each clock beat, and 8-bit data is output and shifted in the next beat using the shift register. Each time the memory is read, the read data is sent in 4 times until RXC is read as non-all 0 (using a 32-bit shift register, sending the lower 8-bit data each time, then right shifting 8 bits, and reading the memory once every 3 right shifts). When RXC is not all 0, there are two cases. One is that RXC is all 1, then it jumps back to the IDLE state, indicating that the 4-byte data read this time is exactly the last 4 bytes of the current transmission data frame; the other is that RXC is not all 0 or all 1, and enters the LAST state, indicating that the 4-byte data of the last beat contains valid data of the data frame and a status word. In this process, the big and small ends of the transmission data can be redefined according to application needs.

[0056] In the LAST state, in the read-out data, the data byte corresponding to RXC being 0 (i.e., the valid byte of the data frame) is taken out as phy_rxd and output through the GMII interface. After all the data bytes corresponding to RXC being 0 are sent, jump to the FRA_INTV state and clear the rxdv signal of the GMII interface.

[0057] In the FRA_INTV state, since the Ethernet protocol requires a minimum frame interval, it is necessary to wait for 12 clock cycles before returning to the IDLE state.

[0058] In this specific implementation, the interface adapter receives data from the 10G physical layer device via the XGMII interface and internally receives data via the XGMII interface. Figure 3 The 10G Ethernet interface processing logic unit is based on the state machine shown in the figure, which realizes the writing of data to the specified cache address. Figure 4 The Gigabit Ethernet data interface processing logic unit with the read operation state machine as the core will read data from the cache and convert it into GMII interface timing, send data to the Gigabit Ethernet device, and realize the connection between the Gigabit Ethernet device and the 10 Gigabit physical layer device.

[0059] Existing Gigabit network devices use GMII (Gigabit Media Independent Interface) to exchange data with the physical layer, while 10G network devices use XGMII (10G Media Independent Interface) to exchange data with the physical layer. When using Gigabit network devices to connect to 10G network physical layer devices, there will be a problem of data interface mismatch.

[0060] The GMII interface uses phy_rxdv to indicate data validity and phy_rxd[7:0] to indicate the transmitted data. Data is transmitted continuously until the end.

[0061] The XGMII interface uses RXC[3:0] to indicate the type of data to be transmitted, and uses RXD[31:0] to indicate the data to be transmitted. Each bit of RXC corresponds to an 8-bit data of RXD. When the RXC bit is 1, it indicates that the corresponding 8-bit data of RXD is a control word; when the RXC bit is 0, it indicates that the corresponding 8-bit data of RXD is the transmitted data.

[0062] The XGMII transmission process is as follows: (1) RXC = 4'b1111, RXD = 32'h07070707 means the transmission link is idle; (2) RXC = 4'b0001, RXD = 32'h555555FB indicates SCC, and transmission starts; (3) RXC = 4'b1000, RXD = 32'hd5555555 indicates SFD, after which data transmission will begin; (4) RXC = 4'b0000, RXD is the transmitted data content; (5) RXC[n]=1, RXD[corresponding bit]=FD, other bits RXC=0, RXD=data, indicating the end of data transmission (6) RXC = 4'b1111, RXD = 32'h07070707 indicates that the transmission link enters the idle state again.

[0063] When using Gigabit network products, when it comes to scenarios where data needs to be received from 10 Gigabit Ethernet, the data interface timing cannot be matched and the data cannot be received correctly. A timing conversion method from XGMII (10 Gigabit Media Independent Interface) of 10 Gigabit Ethernet to GMII (Gigabit Media Independent Interface) of Gigabit Ethernet is proposed. During the conversion process, the big and small ends of the data can also be redefined.

[0064] The present invention effectively solves the problem that Gigabit Ethernet controllers and switches cannot receive data from 10 Gigabit Ethernet, so that the original Gigabit Ethernet network products can be connected to 10 Gigabit Ethernet network devices. At the same time, the large and small ends of the interface can be flexibly redefined, which effectively enriches the flexibility of Ethernet device applications and expands the application scenarios of Ethernet devices.

[0065] like Figure 5 As shown, a specific embodiment of the present invention also provides a data transmission processing system, including: A data receiving module, used for receiving 10 Gigabit Ethernet data; A first state machine, used for controlling the writing of 10 Gigabit Ethernet data into a designated cache block; The second state machine is used to control the cache read operation, read the data from the cache block and reorganize the data, and output it to the GMII interface; The big-endian and small-endian conversion module is used to redefine the big-endian and small-endian formats of data during the data reorganization process.

[0066] A computer device is also provided in a specific embodiment of the present invention. Specifically, the computer device includes a processor and a memory, the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, and is specifically suitable for loading and executing one or more instructions to implement corresponding method processes or corresponding functions; the processor described in the embodiment of the present invention can be used for the operation of the data transmission processing method, including the following steps: receiving 10 Gigabit Ethernet data and writing it into the cache through the XGMII interface; controlling the 10 Gigabit Ethernet data to be written into the specified cache block through the first state machine; controlling the cache read operation through the second state machine, reading data from the cache block and reorganizing the data, and outputting it to the GMII interface; in the data reorganization process, redefining the big-endian and small-endian formats of the data.

[0067] A storage medium is also provided in a specific embodiment of the present invention, specifically, a computer-readable storage medium, which is a memory device in a terminal device for storing programs and data. It is understandable that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and the extended storage medium supported by the terminal device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory, or a non-volatile memory, such as at least one disk memory. One or more instructions stored in a computer-readable storage medium can be loaded and executed by a processor to implement the corresponding steps of the data transmission processing method in the above embodiment; one or more instructions in the computer-readable storage medium are loaded by the processor and the following steps are executed: receiving 10 Gigabit Ethernet data through the XGMII interface and writing it into the cache; writing the 10 Gigabit Ethernet data into a designated cache block through the first state machine control; controlling the cache read operation through the second state machine, reading data from the cache block and reorganizing the data, and outputting it to the GMII interface; in the data reorganization process, redefining the big-endian and little-endian formats of the data.

[0068] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0069] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0070] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0071] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A data transmission processing method, characterized in that: include: Receive 10 Gigabit Ethernet data through the XGMII interface and write it into the cache; Writing the 10 Gigabit Ethernet data into a designated cache block through the control of a first state machine; Controlling the cache read operation through the second state machine, reading data from the cache block and reorganizing the data, and outputting the data to the GMII interface; During the data reorganization process, the big-endian and big-endian formats of the data are redefined.

2. A data transmission processing method according to claim 1, characterized in that: The step of receiving 10 Gigabit Ethernet data through the XGMII interface and writing it into the cache comprises: Initialize the state machine and monitor the link idle signal of the XGMII interface; Detect the start control word SCC signal and jump to the pre-SFD state; Detect the start frame delimiter SFD signal, determine whether the buffer space is available, and jump to the data writing state; Write the received data to the buffer until the data transfer is complete.

3. The data transmission processing method according to claim 1, characterized in that: The step of controlling the writing of the 10 Gigabit Ethernet data into a designated cache block through the first state machine includes: Use a state machine to manage cache write operations, including allocation, writing, and release of cache blocks; The state machine writes the received data into the specified cache block according to the signal status of the XGMII interface.

4. The data transmission processing method according to claim 1, characterized in that: The second state machine is used to control the cache read operation, read data from the cache block, reorganize the data, and output it to the GMII interface, including: Initialize the state machine and monitor the read operation start signal; After detecting the read operation start signal, data is read from the cache block and reorganized according to the requirements of the GMII interface protocol; The reorganized data is output through the GMII interface.

5. The data transmission processing method according to claim 1, characterized in that: In the data reorganization process, the big-endian and small-endian formats of the data are redefined, including: Detect the big-endian and small-endian formats of the data. If the big-endian and small-endian formats of the data are inconsistent with the requirements of the target device, perform big-endian and small-endian conversion. Use dedicated endian conversion logic to adjust the byte order of the data, converting the data in little-endian format to big-endian format, or converting the data in big-endian format to little-endian format; Make sure the converted data format matches the requirements of the Gigabit Ethernet device to ensure that the data can be correctly received and processed.

6. The data transmission processing method according to claim 1, characterized in that: The cache includes 4 independent cache blocks, each of which has a storage depth of 1600 and a bit width of 36 bits, of which 4 bits are used to store RXC control flags and 32 bits are used to store RXD data.

7. The data transmission processing method according to claim 1, characterized in that: The data output by the GMII interface is sent in 4 times through a 32-bit shift register, with 8 bits of data sent each time, and the minimum frame interval time is waited after the sending is completed.

8. A data transmission processing system, characterized in that: include: A data receiving module, used for receiving 10 Gigabit Ethernet data; A first state machine, used for controlling the writing of the 10 Gigabit Ethernet data into a designated cache block; A second state machine is used to control a cache read operation, read data from the cache block, reorganize the data, and output it to the GMII interface; The big-endian and small-endian conversion module is used to redefine the big-endian and small-endian formats of data during the data reorganization process.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the data transmission processing method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the data transmission processing method according to any one of claims 1 to 7 are implemented.

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