Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate; an active pattern extending in a first horizontal direction on the substrate; a plurality of nanosheets stacked on the active pattern to be spaced apart from each other in a vertical direction; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets; a source / drain region disposed on the active pattern on at least one side of the gate electrode; a first inner spacer disposed between the plurality of nanosheets between the source / drain region and the gate electrode, the first inner spacer being in contact with the source / drain region; and a second inner spacer disposed between the first inner spacer and the gate electrode between the plurality of nanosheets, the second inner spacer including a material different from a material of the first inner spacer, each of an upper surface and a lower surface of the second inner spacer being in contact with the first inner spacer.

Description

[0001] This application claims priority to and all rights arising from Korean Patent Application No. 10-2023-0148823 filed in the Korean Intellectual Property Office on November 1, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor memory device. Specifically, the present disclosure relates to a semiconductor memory device including an MBCFET TM (Multi-bridge channel field effect transistor) semiconductor device. Background Art

[0003] As one of scaling technologies for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed in which a silicon body having a fin shape or a nanowire shape is formed on a substrate and a gate is formed on a surface of the silicon body.

[0004] Since such a multi-gate transistor utilizes a three-dimensional channel, it is easy to perform scaling. In addition, the current control capability can be improved even without increasing the gate length of the multi-gate transistor. In addition, the SCE (short channel effect) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0005] An aspect of the present disclosure provides a semiconductor device in which reliability is improved by forming an inner spacer including a double film including materials different from each other and effectively controlling a thickness of the inner spacer.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes: a substrate, provided with an active pattern extending in a first horizontal direction parallel to an upper surface of the substrate; a plurality of nanosheets, provided on the active pattern and stacked to be spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; a gate electrode, provided on the active pattern and extending in a second horizontal direction parallel to the upper surface of the substrate and different from the first horizontal direction, the gate electrode surrounding each of the plurality of nanosheets; a source / drain region, provided on the active pattern and provided on a first side of the gate electrode; a first inner spacer, provided between the source / drain region and a first portion of the gate electrode, the first portion of the gate electrode being provided in a space between two adjacent nanosheets of the plurality of nanosheets, the first inner spacer being in contact with the source / drain region, and the first portion of the gate electrode being lower than an upper surface of the source / drain region; and a second inner spacer, provided between the first inner spacer and the first portion of the gate electrode, the second inner spacer comprising a material different from that of the first inner spacer, and each of an upper surface and a lower surface of the second inner spacer being in contact with the first inner spacer.

[0007] According to aspects of the present disclosure, a semiconductor device includes: a substrate provided with an active pattern extending in a first horizontal direction parallel to an upper surface of the substrate; a plurality of nanosheets provided on the active pattern and stacked to be spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; a gate electrode provided on the active pattern and extending in a second horizontal direction parallel to the upper surface of the substrate and different from the first horizontal direction, the gate electrode surrounding each of the plurality of nanosheets; a gate insulating layer provided between a first portion of the gate electrode and each of two adjacent nanosheets of the plurality of nanosheets, wherein the first portion of the gate electrode is lower than the upper surface of the substrate; a source / drain region provided on the active pattern and provided between the gate electrode and the active pattern; on a first side of the electrode; a first inner spacer, disposed between two adjacent nanosheets among the plurality of nanosheets in a space between the source / drain region and the gate insulating layer, the first inner spacer comprising a first sidewall in contact with the source / drain region and a second sidewall in contact with the gate insulating layer; and a second inner spacer, disposed between the two adjacent nanosheets among the plurality of nanosheets in a space between the first inner spacer and the gate insulating layer, the second inner spacer comprising a material different from that of the first inner spacer, the second inner spacer comprising a first sidewall in contact with the first inner spacer and a second sidewall in contact with the gate insulating layer, and the second inner spacer being spaced apart from each of the plurality of nanosheets in a vertical direction.

[0008] According to aspects of the present disclosure, a semiconductor device includes: a substrate provided with an active pattern extending in a first horizontal direction parallel to an upper surface of the substrate; a plurality of nanosheets provided on the active pattern and stacked to be spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; a gate electrode provided on the active pattern and extending in a second horizontal direction parallel to the upper surface of the substrate and different from the first horizontal direction, the gate electrode surrounding each of the plurality of nanosheets; a gate insulating layer provided between a first portion of the gate electrode and each of two adjacent nanosheets of the plurality of nanosheets; a source / drain region provided on the active pattern, and A first inner spacer is disposed on a first side of the gate electrode; a first inner spacer is disposed in a space between the source / drain region and the gate insulating layer between the two adjacent nanosheets among the plurality of nanosheets, the first inner spacer contacts each of the source / drain region and the gate insulating layer; and a second inner spacer is disposed in a space between the first inner spacer and the gate insulating layer between the two adjacent nanosheets among the plurality of nanosheets, the second inner spacer includes a material different from that of the first inner spacer, a sidewall of the second inner spacer contacts the gate insulating layer, and each of an upper surface and a lower surface of the second inner spacer contacts the first inner spacer. The second inner spacer is spaced apart from each of the plurality of nanosheets in a vertical direction. The second inner spacer is spaced apart from the source / drain region in a first horizontal direction. The sidewall of the first inner spacer in contact with the source / drain region is formed into a shape concave toward the gate electrode. The sidewall of the second inner spacer in contact with the gate insulating layer is formed into a shape concave toward the source / drain region.

[0009] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0013] Figure 3 yes Figure 2 Magnified view of region R1.

[0014] Figure 4 It is along Figure 1A cross-sectional view taken along line BB'.

[0015] Figures 5 to 27 are diagrams of intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0016] Fig.28 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0017] Fig.29 yes Fig.28 Magnified view of region R2.

[0018] Fig.30 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0019] Fig.31 yes Fig.30 An enlarged view of region R3.

[0020] Fig.32 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0021] Fig.33 yes Fig.32 An enlarged view of region R4.

[0022] Fig.34 and Fig.36 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0023] Fig.35 yes Fig.34 An enlarged view of region R5.

[0024] Fig.37 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0025] Fig.38 yes Fig.37 An enlarged view of region R6.

[0026] Fig.39 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0027] Fig.40 yes Fig.39 An enlarged view of region R7.

[0028] Fig.41 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0029] Fig.42 yes Fig.41Magnified view of region R8.

[0030] Fig.43 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure.

[0031] Fig.44 yes Fig.43 Magnified view of region R9. DETAILED DESCRIPTION

[0032] In the following, reference will be made to Figures 1 to 4 Semiconductor devices according to some embodiments of the present disclosure are described.

[0033] Figure 1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 yes Figure 2 Magnified view of region R1. Figure 4 It is along Figure 1 A cross-sectional view taken along line BB'.

[0034] Reference Figures 1 to 4 , a semiconductor device according to some embodiments of the present disclosure includes a substrate 100, an active pattern 101, a field insulating layer 105, a plurality of nanosheets NW1, NW2 and NW3, a gate electrode G, a gate spacer 111, a gate insulating layer 112, a capping pattern 113, a source / drain region SD, an inner spacer 120, a first etch stop layer 130, a first interlayer insulating layer 140, a source / drain contact CA, a silicide layer SL, a gate contact CB, a second etch stop layer 150, a second interlayer insulating layer 160, and a first via V1 and a second via V2.

[0035] The substrate 100 may be a silicon substrate or a silicon on insulator (SOI). In some embodiments, the substrate 100 may include or be formed of silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.

[0036] Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be defined as a direction parallel to the upper surface of the substrate 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. In some embodiments, the second horizontal direction DR2 may be perpendicular to the first horizontal direction DR1. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 may be defined as a direction perpendicular to the upper surface of the substrate 100.

[0037] The substrate 100 may be provided with an active pattern 101 extending on the substrate 100 in the first horizontal direction DR1. The active pattern 101 may protrude from the upper surface of the substrate 100 in the vertical direction DR3. In some embodiments, the active pattern 101 may be a portion of the substrate 100. The active pattern 101 may be formed by patterning the substrate 100. In some embodiments, the active pattern 101 may include an epitaxial layer grown from the substrate 100.

[0038] The field insulating layer 105 may be disposed on the upper surface of the substrate 100. The field insulating layer 105 may surround the sidewalls of the active pattern 101. For example, the upper surface of the active pattern 101 may protrude beyond the upper surface of the field insulating layer 105 in the vertical direction DR3, but the present disclosure is not limited thereto. In some embodiments, the upper surface of the active pattern 101 may be formed on the same plane as the upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combined film thereof, or may be composed of, for example, an oxide film, a nitride film, an oxynitride film.

[0039] A plurality of nanosheets NW1, NW2, and NW3 may be disposed on the active pattern 101. The plurality of nanosheets NW1, NW2, and NW3 may be stacked on the active pattern 101 to be spaced apart from each other in the vertical direction DR3. For example, the plurality of nanosheets NW1, NW2, and NW3 may include a first nanosheet NW1, a second nanosheet NW2, and a third nanosheet NW3. The first nanosheet NW1 may be spaced apart from the active pattern 101 in the vertical direction DR3 on the active pattern 101. The second nanosheet NW2 may be spaced apart from the first nanosheet NW1 in the vertical direction DR3 on the first nanosheet NW1. The third nanosheet NW3 may be spaced apart from the second nanosheet NW2 in the vertical direction DR3 on the second nanosheet NW2.

[0040] Although multiple nanosheets NW1, NW2 and NW3 Figure 2 and Figure 4In the figure, it is shown as including three nanosheets stacked and spaced apart from each other in the vertical direction DR3, but this is for convenience of explanation, and the present disclosure is not limited thereto. In some embodiments, the plurality of nanosheets may include four or more nanosheets stacked and spaced apart from each other in the vertical direction DR3. In some embodiments, each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 may include silicon (Si) or may be formed of silicon (Si). However, the present disclosure is not limited thereto. In some embodiments, each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 may include silicon germanium (SiGe) or may be formed of silicon germanium (SiGe).

[0041] The gate electrode G may extend in the second horizontal direction DR2 on the active pattern 101 and the field insulating layer 105. The gate electrode G may surround each of the plurality of nanosheets NW1, NW2, and NW3. The gate electrode G may include, for example, at least one of the following or may be formed of, for example, at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC ), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof. The gate electrode G may include a conductive metal oxide, a conductive metal oxynitride, etc., and may include oxidized forms of the above materials.

[0042] The gate spacer 111 may extend in the second horizontal direction DR2 on the upper surface of the uppermost nanosheet among the plurality of nanosheets NW1, NW2, and NW3 and on the field insulating layer 105 along the opposite sidewalls of the gate electrode G. For example, the gate spacer 111 may extend in the second horizontal direction DR2 on the upper surface of the third nanosheet NW3 and the field insulating layer 105 along the opposite sidewalls of the gate electrode G. The gate spacer 111 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof, or may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. However, the present disclosure is not limited thereto.

[0043] The source / drain region SD may be disposed on the active pattern 101 on at least one side of the gate electrode G. For example, the source / drain region SD may be disposed on the active pattern 101 on the opposite side of the gate electrode G. The source / drain region SD may contact the opposite sidewalls of each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1. For example, the upper surface of the source / drain region SD may be formed to be higher than the upper surface of the third nanosheet NW3. Unless otherwise indicated by the context, the term "contact" as used herein refers to direct connection (i.e., physical contact).

[0044] The gate insulating layer 112 may be disposed between the gate electrode G and the gate spacer 111. The gate insulating layer 112 may be disposed between the gate electrode G and the active pattern 101. The gate insulating layer 112 may be disposed between the gate electrode G and the field insulating layer 105. The gate insulating layer 112 may be disposed between the gate electrode G and each of the plurality of nanosheets NW1, NW2, and NW3. The gate insulating layer 112 may be disposed between the gate electrode G and the source / drain region SD. The gate insulating layer 112 may contact each of the gate electrode G, the plurality of nanosheets NW1, NW2, and NW3, the active pattern 101, and the field insulating layer 105.

[0045] The gate insulating layer 112 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide, or may be formed of at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0046] The semiconductor device according to some embodiments may include an NC (Negative Capacitance) FET using a negative capacitor. For example, the gate insulating layer 112 may include a ferroelectric material film having a ferroelectric property and a paraelectric material film having a paraelectric property.

[0047] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced from the capacitance of each of the individual capacitors (i.e., is smaller than the capacitance of each of the individual capacitors). On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each of the individual capacitances while having a positive value.

[0048] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series can be increased. The increased total capacitance value can allow a transistor including the ferroelectric material film to have a subthreshold swing (SS) of less than 60 millivolts per decade (mV / decade) at room temperature.

[0049] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0050] The ferroelectric material film may further include a dopant that is doped. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on what type of ferroelectric material is included in the ferroelectric material film.

[0051] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0052] When the dopant is aluminum (Al), the ferroelectric material film may include 3 at % (atomic %) to 8 at % (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0053] When the dopant is silicon (Si), the ferroelectric material film may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50at% to 80at% zirconium.

[0054] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, but not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0055] The ferroelectric material film and the paraelectric material film may include the same material, or may be formed of the same material. The ferroelectric material film has ferroelectric properties, while the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0056] The ferroelectric material film may have a thickness having ferroelectric properties. The thickness of the ferroelectric material film may be, for example but not limited to, 0.5 nm to 10 nm. Since the critical thickness of the ferroelectric material film at which it exhibits ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material. As an example, the gate insulating layer 112 may include a ferroelectric material film. As another example, the gate insulating layer 112 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating layer 112 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0057] The inner spacer 120 may be disposed between the source / drain region SD and the gate electrode G between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3. Specifically, the inner spacer 120 may be disposed between the source / drain region SD and the gate insulating layer 112 between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3. The inner spacer 120 may also be disposed between the source / drain region SD and the gate electrode G between the active pattern 101 and the first nanosheet NW1. Specifically, the inner spacer 120 may be disposed between the source / drain region SD and the gate insulating layer 112 between the active pattern 101 and the first nanosheet NW1. In some embodiments, the inner spacer 120 may be disposed in a first space between two adjacent nanosheets NW1 and NW2 in the vertical direction DR3, and may be disposed in a space between a first portion of the gate electrode G and a first portion of the source / drain region SD in the first horizontal direction DR1. The first portion of the gate electrode G and the first portion of the source / drain region SD may be disposed in the space between the two adjacent nanosheets NW1 and NW2. The inner spacer 120 may also be disposed in the second space between the first nanosheet NW1 and the active pattern 101 and in the third space between the second nanosheet NW2 and the third nanosheet NW3. For example, the inner spacer 120 may be disposed in each of the first space between the two adjacent nanosheets NW1 and NW2, the second space between the first nanosheet NW1 and the active pattern 101, and the third space between the second nanosheet NW2 and the third nanosheet NW3.

[0058] The inner spacer 120 may contact the source / drain region SD and the gate insulating layer 112 between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3. The inner spacer 120 may also contact each of the source / drain region SD and the gate insulating layer 112 between the active pattern 101 and the first nanosheet NW1. The inner spacer 120 may include a first inner spacer 121 and a second inner spacer 122.

[0059] The first inner spacer 121 may be disposed between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3, between the source / drain region SD and the gate insulating layer 112. The first inner spacer 121 may also be disposed between the source / drain region SD and the gate insulating layer 112 between the active pattern 101 and the first nanosheet NW1. The first inner spacer 121 may contact each of the plurality of nanosheets NW1, NW2, and NW3, and may be disposed between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3. The first inner spacer 121 may contact the active pattern 101 between the active pattern 101 and the first nanosheet NW1.

[0060] The first inner spacer 121 may include a first sidewall 121s1 and a second sidewall 121s2 opposite to the first sidewall 121s1 in the first horizontal direction DR1. The first sidewall 121s1 of the first inner spacer 121 may be in contact with the source / drain region SD. For example, the first sidewall 121s1 of the first inner spacer 121 may be formed in a shape that is concave toward the gate electrode G (i.e., a portion of the gate electrode G disposed in a space between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3). For example, a sidewall of the source / drain region SD in contact with the first sidewall 121s1 of the first inner spacer 121 may be formed closer to the gate electrode G than a sidewall of each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1.

[0061] The second sidewall 121s2 of the first inner spacer 121 may contact the gate insulating layer 112. For example, at least a portion of the second sidewall 121s2 of the first inner spacer 121 may overlap the gate electrode G in the vertical direction DR3. That is, at least a portion of the first inner spacer 121 may overlap the gate electrode G in the vertical direction DR3. The first inner spacer 121 may include a low dielectric constant material. For example, the first inner spacer 121 may include silicon oxide (SiO 2 ) or can be made of silicon oxide (SiO 2 )form.

[0062] The second inner spacer 122 may be disposed between the first inner spacer 121 and the gate insulating layer 112, between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3. The second inner spacer 122 may also be disposed between the first inner spacer 121 and the gate insulating layer 112, between the active pattern 101 and the first nanosheet NW1. The second inner spacer 122 may be spaced apart from the source / drain region SD in the first horizontal direction DR1. That is, the second inner spacer 122 may not contact the source / drain region SD.

[0063] The second inner spacer 122 may be spaced apart from each of the plurality of nanosheets NW1, NW2, and NW3 in the vertical direction DR3, and may be disposed between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3. The second inner spacer 122 may also be spaced apart from each of the active pattern 101 and the first nanosheet NW1 in the vertical direction DR3, and disposed between the active pattern 101 and the first nanosheet NW1. That is, the second inner spacer 122 may not contact each of the active pattern 101 and each of the plurality of nanosheets NW1, NW2, and NW3.

[0064] The second inner spacer 122 may be in contact with each of the first inner spacer 121 and the gate insulating layer 112. For example, the second inner spacer 122 may include a first sidewall 122s1 and a second sidewall 122s2 opposite to the first sidewall 122s1 in the first horizontal direction DR1. The first sidewall 122s1 of the second inner spacer 122 may be in contact with the first inner spacer 121. The second sidewall 122s2 of the second inner spacer 122 may be in contact with the gate insulating layer 112. For example, the second sidewall 122s2 of the second inner spacer 122 may be formed in a shape that is concave toward the source / drain region SD (i.e., a portion of the source / drain region SD disposed between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3).

[0065] Each of the upper surface 122u and the lower surface 122b of the second inner spacer 122 may be in contact with the first inner spacer 121. That is, the first inner spacer 121 may be disposed between the second inner spacer 122 and each of the plurality of nanosheets NW1, NW2, and NW3. In addition, the first inner spacer 121 may be disposed between the second inner spacer 122 and the active pattern 101.

[0066] The second inner spacer 122 may include a low dielectric constant material, or may be formed of a low dielectric constant material. The second inner spacer 122 may include a material having an etching selectivity to the first inner spacer 121, or may be formed of a material having an etching selectivity to the first inner spacer 121. That is, the second inner spacer 122 may include a material different from that of the first inner spacer 121, or may be formed of a material different from that of the first inner spacer 121. For example, the second inner spacer 122 may include silicon nitride (SiN), or may be formed of silicon nitride (SiN). In some embodiments, the second inner spacer 122 may include any one of silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and silicon carbonitride (SiCN), or may be formed of any one of silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and silicon carbonitride (SiCN).

[0067] The first etch stop layer 130 may be disposed on the sidewall of the gate spacer 111 in the first horizontal direction DR1. Although not shown, the first etch stop layer 130 may be disposed on the upper surface of the field insulating layer 105 in a region where the gate spacer 111 is not disposed. The first etch stop layer 130 may be disposed on the surface of the source / drain region SD. For example, the first etch stop layer 130 may be formed conformally. The first etch stop layer 130 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material, or may be formed of, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0068] The capping pattern 113 may extend in the second horizontal direction DR2 on each of the gate spacer 111, the gate insulating layer 112, the gate electrode G, and the first etch stop layer 130. For example, a lower surface of the capping pattern 113 may contact the first etch stop layer 130. However, the present disclosure is not limited thereto. In some embodiments, a sidewall of the capping pattern 113 may contact the first etch stop layer 130. The capping pattern 113 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof, or may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. However, the present disclosure is not limited thereto.

[0069] The first interlayer insulating layer 140 may be disposed on the first etch stop layer 130. The first interlayer insulating layer 140 may surround the sidewalls of the capping pattern 113. For example, an upper surface of the first interlayer insulating layer 140 may be formed on the same plane as an upper surface of the capping pattern 113. The first interlayer insulating layer 140 may include, or may be formed of, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluorinated silicate glass), polyimide nanofoam, polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, and at least one of a combination thereof. However, the present disclosure is not limited thereto.

[0070] The source / drain contact CA may penetrate the first interlayer insulating layer 140 and the first etch stop layer 130 in the vertical direction DR3 and may be connected to the source / drain region SD. The source / drain contact CA may be electrically connected to the source / drain region SD. For example, the upper surface of the source / drain contact CA may be formed on the same plane as the upper surface of the first interlayer insulating layer 140, but the present disclosure is not limited thereto. Although the source / drain contact CA may be formed on the upper surface of the first interlayer insulating layer 140, the source / drain contact CA may be formed on the upper surface of the first interlayer insulating layer 140. Figure 2 1 and 2. In some embodiments, the source / drain contacts CA may be formed of a plurality of films.

[0071] The source / drain contact CA may include, for example, at least one of the following or may be formed of, for example, at least one of the following: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), aluminum (Al), copper (Cu), and molybdenum (Mo). The silicide layer SL may be disposed between the source / drain contact CA and the source / drain region SD. The silicide layer SL may include, for example, a metal silicide material or may be formed of, for example, a metal silicide material.

[0072] The gate contact CB may penetrate the capping pattern 113 in the vertical direction DR3 and be connected to the gate electrode G. For example, the upper surface of the gate contact CB may be formed on the same plane as the upper surface of the first interlayer insulating layer 140, but the present disclosure is not limited thereto. Figure 4 4 is shown as being formed of a single film, but the present disclosure is not limited thereto. In some embodiments, the gate contact CB may be formed of a plurality of films.

[0073] The gate contact CB may include, for example, at least one of the following or may be formed of, for example, at least one of the following: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), aluminum (Al), copper (Cu), and molybdenum (Mo).

[0074] The second etch stop layer 150 may be disposed on each of the first interlayer insulating layer 140, the capping pattern 113, the source / drain contacts CA, and the gate contact CB. Figure 2 and Figure 4 150 is shown as being formed by a single film, but the present disclosure is not limited thereto. In some embodiments, the second etch stop layer 150 may be formed by a plurality of films. The second etch stop layer 150 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material, or may be formed by, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The second interlayer insulating layer 160 may be disposed on the second etch stop layer 150. The second interlayer insulating layer 160 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0075] The first via hole V1 penetrates the second interlayer insulating layer 160 and the second etch stop layer 150 in the vertical direction DR3 and may be connected to the source / drain contact CA. The second via hole V2 penetrates the second interlayer insulating layer 160 and the second etch stop layer 150 in the vertical direction DR3 and may be connected to the gate contact CB. Figure 2 and Figure 4 In the figure, it is shown as being formed of a single film, but the present disclosure is not limited thereto. In some embodiments, each of the first via hole V1 and the second via hole V2 may be formed of a plurality of films. Each of the first via hole V1 and the second via hole V2 may include a conductive material or may be formed of a conductive material.

[0076] In the following, reference will be made to Figures 2 to 27 A method of manufacturing a semiconductor device according to some embodiments of the present disclosure is described.

[0077] Figures 5 to 27 are diagrams of intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0078] Reference Figure 5 and Figure 6 , a stacked structure 10 may be formed on a substrate 100. The stacked structure 10 may include a sacrificial layer 11 and a semiconductor layer 12 alternately stacked on the substrate 100. For example, the sacrificial layer 11 may be formed at the bottom of the stacked structure 10, and the semiconductor layer 12 may be formed at the top of the stacked structure 10. However, the present disclosure is not limited thereto. In some embodiments, the sacrificial layer 11 may also be formed on the top of the stacked structure 10. The sacrificial layer 11 may include, for example, silicon germanium (SiGe) or may be formed of, for example, silicon germanium (SiGe). The semiconductor layer 12 may include, for example, silicon (Si) or may be formed of, for example, silicon (Si).

[0079] Then, a portion of the stacked structure 10 may be etched. While etching the stacked structure 10, a portion of the substrate 100 may also be etched. Through such an etching process, an active pattern 101 may be defined on the upper surface of the substrate 100 below the stacked structure 10. The active pattern 101 may extend in the first horizontal direction DR1. Subsequently, a field insulating layer 105 may be formed on the upper surface of the substrate 100. The field insulating layer 105 may surround the sidewalls of the active pattern 101. For example, the upper surface of the active pattern 101 may be formed to be higher than the upper surface of the field insulating layer 105.

[0080] Subsequently, a pad oxide layer 20 may be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls of the active pattern 101, and the sidewalls and upper surface of the stacked structure 10. For example, the pad oxide layer 20 may be conformally formed. The pad oxide layer 20 may include, for example, silicon oxide (SiO 2 ) or may be made of, for example, silicon oxide (SiO 2 )form.

[0081] Reference Figure 7 and Figure 8 , a dummy gate DG and a dummy capping pattern DC extending in the second horizontal direction DR2 on the pad oxide layer 20 may be formed on the stacked structure 10 and the field insulating layer 105. The dummy capping pattern DC may be disposed on the dummy gate DG. While forming the dummy gate DG and the dummy capping pattern DC, the remaining pad oxide layer 20 on the substrate 100 except for a portion overlapping the dummy gate DG in the vertical direction DR3 may be removed.

[0082] Next, a spacer material layer SM may be formed to cover the sidewalls of the dummy gate DG, the sidewalls and upper surfaces of the dummy cover pattern DC, the exposed sidewalls and upper surfaces of the stacked structure 10, and the upper surface of the field insulating layer 105. For example, the spacer material layer SM may be conformally formed. The spacer material layer SM may include, for example, at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and combinations thereof, or may be formed of, for example, at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and combinations thereof.

[0083] Reference Fig. 9 , the dummy gate DG and the dummy capping pattern DC may be used as a mask to etch Figure 7 The stacked structure 10 is formed to form a source / drain trench ST. For example, the source / drain trench ST may extend into the active pattern 101. During the formation of the source / drain trench ST, the dummy capping pattern DC may be etched. Figure 7 In addition, during the formation of the source / drain trenches ST, portions of the opposite sidewalls of the sacrificial layer 11 in the first horizontal direction DR1 may be etched. Therefore, the opposite sidewalls of the sacrificial layer 11 in the first horizontal direction DR1 may be formed to be recessed toward the center of the sacrificial layer 11.

[0084] For example, the dummy gate DG and the dummy capping pattern DC remain on the sidewall of each. Figure 7 The spacer material layer SM may be defined as a gate spacer 111. For example, after forming the source / drain trench ST, the spacer material layer SM remaining under the dummy gate DG on the active pattern 101 may be defined as a gate spacer 111. Figure 7 The semiconductor layer 12 may be defined as a first nanosheet NW1, a second nanosheet NW2, and a third nanosheet NW3, respectively.

[0085] Reference Fig.10 , available in Fig. 9A source / drain region SD is formed inside the source / drain trench ST. For example, the source / drain region SD may be in contact with a sidewall of each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 in the first horizontal direction DR1. In addition, the source / drain region SD may be in contact with a sidewall of the sacrificial layer 11 in the first horizontal direction DR1. For example, the source / drain region SD may include a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region are spaced apart from each other in the first horizontal direction DR1, and the first source / drain region and the second source / drain region are respectively disposed on opposite sidewalls of the sacrificial layer 11.

[0086] Reference Fig.11 , a first etch stop layer 130 may be formed on the surface of the source / drain region SD and the sidewall of the gate spacer 111. Although not shown, the first etch stop layer 130 may also be formed on the upper surface of the field insulating layer 105. For example, the first etch stop layer 130 may be conformally formed. Next, a first interlayer insulating layer 140 may be formed on the first etch stop layer 130. Next, the upper surface of the dummy gate DG may be exposed by a planarization process.

[0087] Reference Fig.12 and Fig.13 , can be etched Fig.11 The dummy gate DG, Fig.11 The pad oxide layer 20 and Fig.11 Each of the sacrificial layers 11. Fig.11 The dummy gate DG, Fig.11 The pad oxide layer 20 and Fig.11 The removed portions of the sacrificial layer 11 may be collectively defined as a gate trench GT.

[0088] Reference Figures 14 to 16 , a first inner spacer material layer 121M may be conformally formed inside the gate trench GT. For example, the first inner spacer material layer 121M may be formed in a liner shape. For example, the first inner spacer material layer 121M may be formed on the surface of the source / drain region SD exposed to the inside of the gate trench GT. The first inner spacer material layer 121M may be formed on the surface of the field insulation layer 105 exposed to the inside of the gate trench GT, the surface of the active pattern 101, and the surface of each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3. The first inner spacer material layer 121M may be formed on the sidewall of the gate spacer 111 exposed to the inside of the gate trench GT. In addition, the first inner spacer material layer 121M may be formed on the upper surface of the gate spacer 111 and the upper surface of the first interlayer insulating layer 140.

[0089] For example, Fig.14 and Fig.15 As shown in FIG. 1 , in a cross section taken along the first horizontal direction DR1, the thickness of the first inner spacer material layer 121M formed on the sidewalls of the source / drain region SD in the first horizontal direction DR1 may be greater than the thickness of the first inner spacer material layer 121M formed on the upper surface of the active pattern 101 and each of the upper and lower surfaces of each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 in the vertical direction DR3. The first inner spacer material layer 121M may include or may be formed of a low dielectric constant material. For example, the first inner spacer material layer 121M may include silicon oxide (SiO 2 ) or can be made of silicon oxide (SiO 2 )form.

[0090] Reference Figures 17 to 19 , the second inner spacer material layer 122M may be conformally formed on the first inner spacer material layer 121M. The second inner spacer material layer 122M may be formed in a pad shape. For example, the second inner spacer material layer 122M may be formed on the first inner spacer material layer 121M inside the gate trench GT. For example, the second inner spacer material layer 122M may be formed on the first inner spacer material layer 121M on the upper surface of the gate spacer 111 and the upper surface of the first interlayer insulating layer 140.

[0091] For example, Fig.17 and Fig.18 As shown in FIG. 1 , in a cross section taken along the first horizontal direction DR1, the thickness of the second inner spacer material layer 122M formed on the sidewall of the source / drain region SD in the first horizontal direction DR1 may be greater than the thickness of the second inner spacer material layer 122M formed on the upper surface of the active pattern 101 and each of the upper and lower surfaces of each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 in the vertical direction DR3. The second inner spacer material layer 122M may include a low dielectric constant material, or may be formed of a low dielectric constant material. For example, the second inner spacer material layer 122M may include a material different from that of the first inner spacer material layer 121M, or may be formed of a material different from that of the first inner spacer material layer 121M. For example, the second inner spacer material layer 122M may include any one of silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN) and silicon carbonitride (SiCN), or may be formed of any one of silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN) and silicon carbonitride (SiCN).

[0092] Reference Figure 20 to Figure 22 , a third inner spacer material layer 123M may be conformally formed on the second inner spacer material layer 122M. The third inner spacer material layer 123M may be formed in a pad shape. For example, the third inner spacer material layer 123M may be formed on the second inner spacer material layer 122M inside the gate trench GT. For example, the third inner spacer material layer 123M may be formed on the second inner spacer material layer 122M on the upper surface of the gate spacer 111 and the upper surface of the first interlayer insulating layer 140.

[0093] For example, Fig. 20 and Fig.21 As shown in FIG. 1 , in a cross section taken along the first horizontal direction DR1, the thickness of the third inner spacer material layer 123M formed on the sidewalls of the source / drain region SD in the first horizontal direction DR1 may be greater than the thickness of the third inner spacer material layer 123M formed on the upper surface of the active pattern 101 and each of the upper and lower surfaces of each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 in the vertical direction DR3. The third inner spacer material layer 123M may include a low dielectric constant material. For example, the third inner spacer material layer 123M may include silicon oxide (SiO 2 ).

[0094] although Figure 20 to Figure 22 It is shown that the third inner spacer material layer 123M is formed on the second inner spacer material layer 122M, but the present disclosure is not limited thereto. In some embodiments, the formation of the third inner spacer material layer 123M may be omitted.

[0095] Reference Figure 23 to Figure 25 , a wet etching process may be performed to etch Figure 20 to Figure 22 The first inner spacer material layer 121M and Figure 20 to Figure 22 In addition, when the second inner spacer material layer 122M is formed in the previously performed process Figure 20 to Figure 22 The third inner spacer material layer 123M can be completely etched Figure 20 to Figure 22The third inner spacer material layer 123M is formed by etching the active pattern 101. After performing such an etching process, in a cross section taken along the first horizontal direction DR1, the upper surface of the active pattern 101 and the upper and lower surfaces of each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 may be exposed. In addition, after performing such an etching process, in a cross section taken along the first horizontal direction DR1, the sidewall and the upper surface of the gate spacer 111 and the upper surface of the first interlayer insulating layer 140 may be exposed. In addition, after performing such an etching process, in a cross section taken along the second horizontal direction DR2, the upper surface of the field insulating layer 105, the surface of the active pattern 101, and the surface of each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 may be exposed.

[0096] After performing such an etching process, the active pattern 101 and each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 remain on the sidewalls of the source / drain region SD. Figure 20 to Figure 22 The first inner spacer material layer 121M may be defined as the first inner spacer 121. In addition, after performing such an etching process, the active pattern 101 and each of the first nanosheet NW1, the second nanosheet NW2, and the third nanosheet NW3 may remain on the sidewall of the source / drain region SD. Figure 20 to Figure 22 The second inner spacer material layer 122M may be defined as a second inner spacer 122. Thus, the inner spacer 120 including the first inner spacer 121 and the second inner spacer 122 may be formed on the sidewalls of the source / drain region SD.

[0097] Reference Fig.26 and Fig. 27 , available in Fig.23 A gate insulating layer 112 , a gate electrode G, and a capping pattern 113 are sequentially formed inside the gate trench GT. For example, the gate insulating layer 112 may contact each of the sidewalls of the first inner spacer 121 and the second inner spacer 122 .

[0098] Reference Figures 2 to 4 , a source / drain contact CA penetrating the first interlayer insulating layer 140 in the vertical direction DR3 and connected to the source / drain region SD may be formed. In addition, a silicide layer SL may be formed between the source / drain region SD and the source / drain contact CA. In addition, a gate contact CB penetrating the capping pattern 113 in the vertical direction DR3 and connected to the gate electrode G may be formed. Subsequently, a second etch stop layer 150 and a second interlayer insulating layer 160 may be sequentially formed on an upper surface of each of the first interlayer insulating layer 140, the capping pattern 113, the source / drain contact CA, and the gate contact CB.

[0099] Next, a first via hole V1 penetrating the second etch stop layer 150 and the second interlayer insulating layer 160 in the vertical direction DR3 and connected to the source / drain contact CA may be formed. In addition, a second via hole V2 penetrating the second etch stop layer 150 and the second interlayer insulating layer 160 in the vertical direction DR3 and connected to the gate contact CB may be formed. Through such a manufacturing process, a Figures 2 to 4 The semiconductor device shown in .

[0100] When the inner spacer 120 is formed on the sidewall of the sacrificial layer 11 before forming the source / drain region SD, a problem occurs in the reliability of the source / drain region SD because the source / drain region SD does not epitaxially grow from the sacrificial layer 11. In the semiconductor device according to some embodiments of the present disclosure, the inner spacer 120 may be formed on the sidewall of the source / drain region SD after removing the dummy gate DG. That is, in the semiconductor device according to some embodiments of the present disclosure, after forming the source / drain region SD, the inner spacer 120 may be formed on the sidewall of the source / drain region SD.

[0101] In the semiconductor device according to some embodiments of the present disclosure, the inner spacer 120 may include a first inner spacer 121 and a second inner spacer 122, and the first inner spacer 121 and the second inner spacer 122 include materials different from each other. In the semiconductor device according to some embodiments of the present disclosure, after removing the dummy gate DG, the first inner spacer 121 and the second inner spacer 122 including materials different from each other may be formed on the sidewalls of the source / drain region SD. Therefore, the thickness of the inner spacer 120 can be effectively adjusted to improve the reliability of the semiconductor device.

[0102] In the semiconductor devices according to some embodiments of the present disclosure manufactured by the above-mentioned manufacturing method, the inner spacer 120 includes a first inner spacer 121 and a second inner spacer 122 including materials different from each other, and each of the upper surface and the lower surface of the second inner spacer 122 in contact with the gate insulation layer 112 may be in contact with the first inner spacer 121 in contact with the source / drain region SD.

[0103] In the following, reference will be made to Fig.28 and Fig.29 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figures 1 to 4 The semiconductor devices shown in FIG.

[0104] Fig.28 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.29 yes Fig.28 Magnified view of region R2.

[0105] Reference Fig.28 and Fig.29 , in the semiconductor device according to some embodiments of the present disclosure, the sidewall 221s1 of the first inner spacer 221 contacting the source / drain region SD may extend along a straight line extending in the vertical direction DR3.

[0106] For example, the inner spacer 220 may include a first inner spacer 221 and a second inner spacer 122. The first inner spacer 221 may include a first sidewall 221s1 and a second sidewall 221s2 opposite to the first sidewall 221s1 in the first horizontal direction DR1. The first sidewall 221s1 of the first inner spacer 221 may contact the source / drain region SD. The first sidewall 221s1 of the first inner spacer 221 may extend along a straight line extending in the vertical direction DR3. The second sidewall 221s2 of the first inner spacer 221 may contact the gate insulating layer 112.

[0107] In the following, reference will be made to Fig.30 and Fig.31 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figures 1 to 4 The semiconductor devices shown in FIG.

[0108] Fig.30 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.31 yes Fig.30 An enlarged view of region R3.

[0109] Reference Fig.30 and Fig.31 In the semiconductor device according to some embodiments of the present disclosure, the sidewall 321s1 of the first inner spacer 321 in contact with the source / drain region SD may be formed in a shape protruding toward the source / drain region SD (i.e., a portion of the source / drain region SD disposed in a space between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3).

[0110] For example, the inner spacer 320 may include a first inner spacer 321 and a second inner spacer 122. The first inner spacer 321 may include a first sidewall 321s1 and a second sidewall 321s2 opposite to the first sidewall 321s1 in the first horizontal direction DR1. The first sidewall 321s1 of the first inner spacer 321 may be in contact with the source / drain region SD. The first sidewall 321s1 of the first inner spacer 321 may be formed in a shape protruding toward the source / drain region SD (i.e., a portion of the source / drain region SD disposed in a space between two adjacent nanosheets among the plurality of nanosheets NW1, NW2, and NW3). The second sidewall 321s2 of the first inner spacer 321 may be in contact with the gate insulating layer 112.

[0111] In the following, reference will be made to Fig.32 and Fig.33 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figures 1 to 4 The semiconductor devices shown in FIG.

[0112] Fig.32 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.33 yes Fig.32 An enlarged view of region R4.

[0113] Reference Fig.32 and Fig.33 , in the semiconductor device according to some embodiments of the present disclosure, the sidewall 422s2 of the second inner spacer 422 contacting the gate insulating layer 112 may extend in the vertical direction DR3.

[0114] For example, the inner spacer 420 may include a first inner spacer 421 and a second inner spacer 422. The first inner spacer 421 may include a first sidewall 421s1 and a second sidewall 421s2 opposite to the first sidewall 421s1 in the first horizontal direction DR1. The first sidewall 421s1 of the first inner spacer 421 may contact the source / drain region SD. The first sidewall 421s1 of the first inner spacer 421 may be formed in a shape concave toward the gate electrode G. The second sidewall 421s2 of the first inner spacer 421 may contact the gate insulating layer 112.

[0115] For example, the second inner spacer 422 may include a first sidewall 422s1 and a second sidewall 422s2 opposite to the first sidewall 422s1 in the first horizontal direction DR1. The first sidewall 422s1 of the second inner spacer 422 may contact the first inner spacer 421. The second sidewall 422s2 of the second inner spacer 422 may contact the gate insulating layer 112. The second sidewall 422s2 of the second inner spacer 422 may extend in the vertical direction DR3. Each of the upper surface 422u and the lower surface 422b of the second inner spacer 422 may contact the first inner spacer 421.

[0116] In the following, reference will be made to Figure 34 to Figure 36 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figures 1 to 4 The semiconductor devices shown in FIG.

[0117] Fig.34 and Fig.36 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.35 yes Fig.34 An enlarged view of region R5.

[0118] Reference Figure 34 to Figure 36 In the semiconductor device according to some embodiments of the present disclosure, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 512 may overlap each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1.

[0119] For example, in a cross section taken along the first horizontal direction DR1, the gate electrode G5 may protrude toward the upper and lower surfaces of each of the plurality of nanosheets NW1, NW2, and NW3 in the vertical direction DR3. In a cross section taken along the first horizontal direction DR1, the gate electrode G5 may protrude toward the upper surface of the active pattern 101 in the vertical direction DR3.

[0120] For example, the gate insulating layer 512 may be disposed between the gate electrode G5 and each of the plurality of nanosheets NW1, NW2, and NW3. The surface of each of the plurality of nanosheets NW1, NW2, and NW3 that contacts the gate insulating layer 512 may be formed to be recessed toward the center of each of the plurality of nanosheets NW1, NW2, and NW3 in the vertical direction DR3. The gate insulating layer 512 may contact the surface of each of the plurality of nanosheets NW1, NW2, and NW3 that is formed to be recessed toward the center of each of the plurality of nanosheets NW1, NW2, and NW3 in the vertical direction DR3. For example, the gate insulating layer 512 may contact the recessed upper and lower surfaces of each of the plurality of nanosheets NW1, NW2, and NW3. Therefore, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 512 may overlap each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1.

[0121] In addition, a gate insulating layer 512 may be disposed between the gate electrode G5 and the active pattern 101. An upper surface of the active pattern 101 in contact with the gate insulating layer 512 may be formed to be recessed toward the substrate 100 in the vertical direction DR3. The gate insulating layer 512 may be in contact with an upper surface of the active pattern 101 formed to be recessed toward the substrate 100 in the vertical direction DR3. For example, the gate insulating layer 512 may contact the recessed upper surface of the active pattern 101. Therefore, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 512 may overlap the active pattern 101 in the first horizontal direction DR1.

[0122] In the following, reference will be made to Fig.37 and Fig.38 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figures 1 to 4 The semiconductor devices shown in FIG.

[0123] Fig.37is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.38 yes Fig.37 An enlarged view of region R6.

[0124] Reference Fig.37 and Fig.38 In the semiconductor device according to some embodiments of the present disclosure, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 612 may overlap each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1.

[0125] For example, in a cross section taken along the first horizontal direction DR1, the gate electrode G6 may protrude toward the upper surface and the lower surface of each of the plurality of nanosheets NW1, NW2, and NW3 in the vertical direction DR3. In the cross section taken along the first horizontal direction DR1, the surface of the gate electrode G6 facing the upper surface and the lower surface of each of the plurality of nanosheets NW1, NW2, and NW3 may have a curved shape. In addition, in a cross section taken along the first horizontal direction DR1, the gate electrode G6 may protrude toward the upper surface of the active pattern 101 in the vertical direction DR3. In the cross section taken along the first horizontal direction DR1, the surface of the gate electrode G facing the upper surface of the active pattern 101 may have a curved shape.

[0126] For example, the gate insulating layer 612 may be disposed between the gate electrode G6 and each of the plurality of nanosheets NW1, NW2, and NW3. The surface of each of the plurality of nanosheets NW1, NW2, and NW3 in contact with the gate insulating layer 612 may be formed to be recessed toward the center of each of the plurality of nanosheets NW1, NW2, and NW3 in the vertical direction DR3. In a cross section taken along the first horizontal direction DR1, the surface of each of the plurality of nanosheets NW1, NW2, and NW3 in contact with the gate insulating layer 612 may be recessed in the vertical direction DR3 to have a curved shape. The gate insulating layer 612 may contact the surface of each of the plurality of nanosheets NW1, NW2, and NW3 formed to be recessed toward the center of each of the plurality of nanosheets NW1, NW2, and NW3 in the vertical direction DR3. For example, the gate insulating layer 612 may contact the recessed upper and lower surfaces of each of the plurality of nanosheets NW1, NW2, and NW3. The upper and lower surfaces of the recesses of each of the nanosheets NW1, NW2, and NW3 are flat. Fig.34 and Fig.35 The embodiments are different. Fig.37 and Fig.38The upper and lower surfaces of the recess of each of the nanosheets NW1, NW2, and NW3 may be curved. Therefore, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 612 may overlap each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1.

[0127] In addition, the gate insulating layer 612 may be disposed between the gate electrode G6 and the active pattern 101. The upper surface of the active pattern 101 in contact with the gate insulating layer 612 may be formed to be recessed toward the substrate 100 in the vertical direction DR3. In a cross-section taken along the first horizontal direction DR1, the upper surface of the active pattern 101 in contact with the gate insulating layer 612 may be recessed in the vertical direction DR3 to have a curved shape. The gate insulating layer 612 may be in contact with the upper surface of the active pattern 101 formed to be recessed toward the substrate 100 in the vertical direction DR3. For example, the gate insulating layer 612 may contact the recessed upper surface of the active pattern 101. The recessed upper surface of the active pattern 101 may be flat with respect to the recessed upper surface of the active pattern 101. Fig.34 and Fig.35 The embodiments are different. Fig.37 and Fig.38 The recessed upper surface of the active pattern 101 may be curved. Therefore, in a cross-section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 612 may overlap the active pattern 101 in the first horizontal direction DR1.

[0128] In the following, reference will be made to Fig.39 and Fig.40 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figure 34 to Figure 36 The semiconductor devices shown in FIG.

[0129] Fig.39 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.40 yes Fig.39 An enlarged view of region R7.

[0130] Reference Fig.39 and Fig.40 In the semiconductor device according to some embodiments of the present disclosure, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 512 may overlap each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1. In addition, a sidewall 721s1 of the first inner spacer 721 in contact with the source / drain region SD may extend in the vertical direction DR3. For example, the sidewall 721s1 may be a flat surface extending in the vertical direction DR3.

[0131] For example, the inner spacer 720 may include a first inner spacer 721 and a second inner spacer 122. The first inner spacer 721 may include a first sidewall 721s1 and a second sidewall 721s2 opposite to the first sidewall 721s1 in the first horizontal direction DR1. The first sidewall 721s1 of the first inner spacer 721 may contact the source / drain region SD. The first sidewall 721s1 of the first inner spacer 721 may extend in the vertical direction DR3. The first sidewall 721s1 may be a flat surface extending in the vertical direction DR3. The second sidewall 721s2 of the first inner spacer 721 may contact the gate insulating layer 512.

[0132] In the following, reference will be made to Fig.41 and Fig.42 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figure 34 to Figure 36 The semiconductor devices shown in FIG.

[0133] Fig.41 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.42 yes Fig.41 Magnified view of region R8.

[0134] Reference Fig.41 and Fig.42 In the semiconductor device according to some embodiments of the present disclosure, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 512 may overlap each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1. In addition, a sidewall 821s1 of the first inner spacer 821 contacting the source / drain region SD may be formed in a shape protruding toward the source / drain region SD.

[0135] For example, the inner spacer 820 may include a first inner spacer 821 and a second inner spacer 122. The first inner spacer 821 may include a first sidewall 821s1 and a second sidewall 821s2 opposite to the first sidewall 821s1 in the first horizontal direction DR1. The first sidewall 821s1 of the first inner spacer 821 may contact the source / drain region SD. The first sidewall 821s1 of the first inner spacer 821 may be formed in a shape protruding toward the source / drain region SD. The second sidewall 821s2 of the first inner spacer 821 may contact the gate insulating layer 512.

[0136] In the following, reference will be made to Fig.43 and Fig.44 Semiconductor devices according to some embodiments of the present disclosure are described. The explanation will focus on Figure 34 to Figure 36 The semiconductor devices shown in FIG.

[0137] Fig.43is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig.44 yes Fig.43 Magnified view of region R9.

[0138] Reference Fig.43 and Fig.44 In the semiconductor device according to some embodiments of the present disclosure, in a cross section taken along the first horizontal direction DR1, at least a portion of the gate insulating layer 512 may overlap each of the plurality of nanosheets NW1, NW2, and NW3 in the first horizontal direction DR1. A sidewall 922s2 of the second inner spacer 922 in contact with the gate insulating layer 512 may extend in the vertical direction DR3.

[0139] For example, the inner spacer 920 may include a first inner spacer 921 and a second inner spacer 922. The first inner spacer 921 may include a first sidewall 921s1 and a second sidewall 921s2 opposite to the first sidewall 921s1 in the first horizontal direction DR1. The first sidewall 921s1 of the first inner spacer 921 may contact the source / drain region SD. The first sidewall 921s1 of the first inner spacer 921 may be formed in a shape concave toward the gate electrode G5. The second sidewall 921s2 of the first inner spacer 921 may contact the gate insulating layer 512.

[0140] For example, the second inner spacer 922 may include a first sidewall 922s1 and a second sidewall 922s2 opposite to the first sidewall 922s1 in the first horizontal direction DR1. The first sidewall 922s1 of the second inner spacer 922 may contact the first inner spacer 921. The second sidewall 922s2 of the second inner spacer 922 may contact the gate insulating layer 512. The second sidewall 922s2 of the second inner spacer 922 may extend in the vertical direction DR3. Each of the upper surface 922u and the lower surface 922b of the second inner spacer 922 may contact the first inner spacer 921.

[0141] Although the embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be manufactured in various forms. It will be understood by those skilled in the art that the present disclosure can be implemented in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, the above embodiments should be understood in all aspects as illustrative rather than restrictive.

Claims

1. A semiconductor device, comprising: A substrate provided with an active pattern extending in a first horizontal direction parallel to an upper surface of the substrate; a plurality of nanosheets disposed on the active pattern and stacked to be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate electrode disposed on the active pattern and extending in a second horizontal direction parallel to the upper surface of the substrate and different from the first horizontal direction, the gate electrode surrounding each of the plurality of nanosheets; a source / drain region disposed on the active pattern and on a first side of the gate electrode; A first inner spacer is disposed between the source / drain region and a first portion of the gate electrode, the first portion of the gate electrode is disposed in a space between two adjacent nanosheets among the plurality of nanosheets, the first inner spacer is in contact with the source / drain region, and the first portion of the gate electrode is lower than an upper surface of the source / drain region; as well as A second inner spacer is disposed between the first inner spacer and the first portion of the gate electrode, the second inner spacer includes a material different from that of the first inner spacer, and each of an upper surface and a lower surface of the second inner spacer contacts the first inner spacer.

2. The semiconductor device according to claim 1, in, The second inner spacer is spaced apart from each of the plurality of nanosheets in a vertical direction.

3. The semiconductor device according to claim 1, in, The second inner spacer is spaced apart from the source / drain region in the first horizontal direction.

4. The semiconductor device according to claim 1, further comprising: a gate insulating layer disposed in a space between an upper nanosheet of the two adjacent nanosheets and the first portion of the gate electrode, a space between a lower nanosheet of the two adjacent nanosheets and the first portion of the gate electrode, and a space between the second inner spacer and the first portion of the gate electrode, and The gate insulating layer contacts the two adjacent nanosheets, the first portion of the gate electrode, the first inner spacer, and the second inner spacer.

5. The semiconductor device according to claim 4, in, In a cross-section taken along the first horizontal direction, at least a portion of the gate insulating layer overlaps each of the two adjacent nanosheets of the plurality of nanosheets in the first horizontal direction.

6. The semiconductor device according to claim 4, in, In a cross-section taken along a first horizontal direction, a side wall of the second inner spacer in contact with the gate insulating layer is formed into a shape that is partially recessed toward the source / drain region, and wherein the portion of the source / drain region is in contact with the first inner spacer and is disposed in a space between the two adjacent nanosheets among the plurality of nanosheets.

7. The semiconductor device according to claim 1, in, A sidewall of the source / drain region in contact with the first inner spacer is closer to the first portion of the gate electrode than sidewalls of the two adjacent nanosheets in a first horizontal direction, and The side walls of the two adjacent nanosheets are adjacent to the first side of the gate electrode in a first horizontal direction.

8. The semiconductor device according to claim 1, in, At least portions of the first inner spacers between the plurality of nanosheets overlap with the first portion of the gate electrode in a vertical direction.

9. The semiconductor device according to claim 1, in, A sidewall of the first inner spacer contacting the source / drain region is formed in a shape recessed toward the first portion of the gate electrode.

10. The semiconductor device according to claim 1, in, A sidewall of the first inner spacer in contact with a portion of the source / drain region is formed in a shape protruding toward the portion of the source / drain region, and The portion of the source / drain region is disposed in a space between two adjacent nanosheets among the plurality of nanosheets.

11. A semiconductor device, comprising: A substrate provided with an active pattern extending in a first horizontal direction parallel to an upper surface of the substrate; a plurality of nanosheets disposed on the active pattern and stacked to be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate electrode disposed on the active pattern and extending in a second horizontal direction parallel to the upper surface of the substrate and different from the first horizontal direction, the gate electrode surrounding each of the plurality of nanosheets; a gate insulating layer disposed between a first portion of the gate electrode and each of two adjacent nanosheets of the plurality of nanosheets, wherein the first portion of the gate electrode is lower than an upper surface of the substrate; a source / drain region disposed on the active pattern and on a first side of the gate electrode; A first inner spacer disposed between the two adjacent nanosheets among the plurality of nanosheets in a space between the source / drain region and the gate insulating layer, the first inner spacer comprising a first sidewall in contact with the source / drain region and a second sidewall in contact with the gate insulating layer; and A second inner spacer is disposed between the two adjacent nanosheets among the plurality of nanosheets in the space between the first inner spacer and the gate insulating layer, the second inner spacer includes a material different from that of the first inner spacer, the second inner spacer includes a first sidewall in contact with the first inner spacer and a second sidewall in contact with the gate insulating layer, and the second inner spacer is spaced apart from each of the plurality of nanosheets in a vertical direction.

12. The semiconductor device according to claim 11, in, Each of an upper surface and a lower surface of the second inner spacer is in contact with the first inner spacer.

13. The semiconductor device according to claim 11, in, The second inner spacer is spaced apart from a portion of the source / drain region in a first horizontal direction, and The portion of the source / drain region is disposed in a space between two adjacent nanosheets among the plurality of nanosheets.

14. The semiconductor device according to claim 11, in, A first sidewall of the first inner spacer is formed in a shape recessed toward the gate electrode.

15. The semiconductor device according to claim 11, in, The first side wall of the first inner partition extends along a straight line extending in the vertical direction.

16. The semiconductor device according to claim 11, in, The first sidewall of the first inner spacer is formed in a shape protruding toward the source / drain region.

17. The semiconductor device according to claim 11, in, The second sidewall of the second inner spacer is formed in a shape recessed toward the source / drain region.

18. The semiconductor device according to claim 11, in, The second side wall of the second inner partition extends in the vertical direction.

19. The semiconductor device according to claim 11, in, In a cross-section taken along the first horizontal direction, at least a portion of the gate insulating layer overlaps the two adjacent nanosheets of the plurality of nanosheets in the first horizontal direction.

20. A semiconductor device, comprising: A substrate provided with an active pattern extending in a first horizontal direction parallel to an upper surface of the substrate; a plurality of nanosheets disposed on the active pattern and stacked to be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate electrode disposed on the active pattern and extending in a second horizontal direction parallel to the upper surface of the substrate and different from the first horizontal direction, the gate electrode surrounding each of the plurality of nanosheets; a gate insulating layer disposed between the first portion of the gate electrode and each of two adjacent nanosheets of the plurality of nanosheets; a source / drain region disposed on the active pattern and on a first side of the gate electrode; a first inner spacer disposed between the two adjacent nanosheets among the plurality of nanosheets in a space between the source / drain region and the gate insulating layer, the first inner spacer being in contact with each of the source / drain region and the gate insulating layer; as well as a second inner spacer disposed between the two adjacent nanosheets among the plurality of nanosheets in a space between the first inner spacer and the gate insulating layer, the second inner spacer comprising a material different from that of the first inner spacer, the second inner spacer comprising a sidewall in contact with the gate insulating layer, and each of an upper surface and a lower surface of the second inner spacer in contact with the first inner spacer, wherein the second inner spacer is spaced apart from each of the plurality of nanosheets in a vertical direction, wherein the second inner spacer is spaced apart from the source / drain region in a first horizontal direction, wherein the sidewall of the first inner spacer in contact with the source / drain region is formed in a shape concave toward the gate electrode, and The sidewall of the second inner spacer in contact with the gate insulating layer is formed in a shape concave toward the source / drain region.

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