Semiconductor device, array substrate and display panel

Abstract

The invention relates to a semiconductor device, an array substrate and a display panel. The semiconductor device comprises an active layer, a grid electrode, a source electrode and a drain electrode; the grid electrode is arranged on one side of the active layer; the source electrode and the drain electrode are respectively connected with two opposite sides of the active layer; wherein the active layer comprises at least one first sub-layer, the material of the first sub-layer comprises a metal oxide conductive material and an electrical property adjusting element doped in the metal oxide conductive material, and the electrical property adjusting element comprises at least one of VIII group metal elements; according to the invention, the electrical property adjusting element is doped in the metal oxide conductive material of the active layer, so that the defect state in the metal oxide conductive material can be reduced, and the metal oxide conductive material is converted into a semiconductor material; meanwhile, the metal oxide conductive material has high electron concentration, so that the active layer has high mobility, and the charging efficiency of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device, an array substrate and a display panel. Background Art

[0002] Oxide semiconductor thin film transistors have attracted widespread attention due to their advantages such as high electron mobility, excellent uniformity, good transparency and low cost.

[0003] For example, indium gallium zinc oxide (IGZO) semiconductor materials are already in the mass production stage; however, due to material and process limitations, it is currently difficult to achieve thin-film transistor devices with higher mobility using oxide semiconductor materials. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device, an array substrate and a display panel, which can improve the mobility of the active layer and improve the charging efficiency of the semiconductor device.

[0005] An embodiment of the present application provides a semiconductor device, comprising:

[0006] Active layer;

[0007] A gate, disposed on one side of the active layer;

[0008] A source electrode and a drain electrode, respectively connected to opposite sides of the active layer;

[0009] The active layer includes at least one first sublayer, the material of the first sublayer includes a metal oxide conductive material and an electrical property regulating element doped in the metal oxide conductive material, and the electrical property regulating element includes at least one of the Group VIII metal elements.

[0010] In one embodiment of the present application, the metal oxide conductive material includes at least one of indium tin oxide, antimony tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide and indium-doped zinc oxide.

[0011] In one embodiment of the present application, the metal oxide conductive material is doped with at least one of a single substance of the electrical property regulating element and a compound of the electrical property regulating element.

[0012] In one embodiment of the present application, the metal oxide conductive material is doped with at least one of a single substance of the electrical property regulating element and an oxide of the electrical property regulating element.

[0013] In one embodiment of the present application, the metal oxide conductive material is doped with at least one of iron and iron oxide.

[0014] In one embodiment of the present application, the active layer includes a channel and a first contact portion and a second contact portion located on opposite sides of the channel, the gate is arranged in alignment with the channel, the source is connected to the first contact portion, the drain is connected to the second contact portion, and the electrical regulation element is distributed in the channel, the first contact portion and the second contact portion.

[0015] In one embodiment of the present application, the channel, the first contact portion, and the second contact portion are all semiconductors;

[0016] The semiconductor device further comprises:

[0017] A substrate, the gate is disposed on the substrate;

[0018] A first gate insulating layer is arranged on the substrate and covers the gate, the active layer is arranged on a side of the first gate insulating layer away from the gate, at least the orthographic projection of the channel on the substrate is located within the orthographic projection of the gate on the substrate, and the source and the drain are arranged on a side of the first gate insulating layer away from the substrate and are respectively connected to the first contact portion and the second contact portion.

[0019] In one embodiment of the present application, the channel is a semiconductor, and the first contact portion and the second contact portion are conductors;

[0020] Among them, the material of the channel includes the metal oxide conductive material and the electrical regulating element doped in the metal oxide conductive material, and the material of the first contact part and the material of the second contact part both include the metal oxide conductive material and the electrical regulating element and the conductor element doped in the metal oxide conductive material.

[0021] In one embodiment of the present application, the semiconductor device further includes:

[0022] a substrate, the active layer being disposed on the substrate;

[0023] A second gate insulating layer is arranged on a side of the active layer away from the substrate and covers the active layer, the gate is arranged on a side of the second gate insulating layer away from the channel, the source and the drain are arranged on a side of the second gate insulating layer away from the active layer and are respectively connected to the first contact portion and the second contact portion.

[0024] In one embodiment of the present application, the proportion of metal atoms of the electrical property adjustment element in the first sub-layer is greater than or equal to 0.1% and less than or equal to 10%.

[0025] In one embodiment of the present application, the carrier concentration of the first sublayer is greater than or equal to 1E14 cm -3 , and less than or equal to 5E19cm -3 ;

[0026] The resistance of the first sublayer is greater than or equal to 1E4Ω / □ and less than or equal to 1E10Ω / □;

[0027] The Hall mobility of the first sublayer is greater than or equal to 30 cm 2 / Vs, and less than or equal to 70cm 2 / Vs.

[0028] In one embodiment of the present application, the active layer further includes at least one second sublayer, the at least one second sublayer is stacked with at least one first sublayer, and the material of the second sublayer includes a metal oxide semiconductor material.

[0029] In an embodiment of the present application, the Hall mobility of the second sub-layer is smaller than the Hall mobility of the first sub-layer.

[0030] In an embodiment of the present application, the active layer includes a plurality of the second sub-layers, and the first sub-layer is located between two adjacent second sub-layers.

[0031] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides an array substrate, which includes the semiconductor device.

[0032] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a display panel, and the display panel includes the array substrate.

[0033] The present application provides a semiconductor device, an array substrate and a display panel. By doping electrical property regulating elements in the metal oxide conductive material of the active layer, the defect states in the metal oxide conductive material can be reduced, so that it can be converted into a semiconductor material; at the same time, since the metal oxide conductive material has a high electron concentration, the active layer can have a high mobility, thereby improving the charging efficiency of the semiconductor device.

[0034] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0036] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0037] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of the structure of an active layer provided in an embodiment of the present application;

[0039] Figure 3 Another structural schematic diagram of the active layer provided in an embodiment of the present application;

[0040] Figure 4 Another schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of a planar distribution of an array substrate provided in an embodiment of the present application;

[0042] Figure 6 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0043] Description of reference numerals:

[0044] 10. semiconductor device; 11. active layer; 111. channel; 112. first contact portion; 113. second contact portion; 114. first sublayer; 115. second sublayer; 12. gate; 13. source; 14. drain; 101. pixel arrangement area; 102. non-pixel arrangement area; 1021. drive circuit subarea;

[0045] 21. substrate; 22. first gate insulating layer; 23. first insulating layer; 24. barrier layer; 25. second gate insulating layer; 26. interlayer dielectric layer; 27. second insulating layer;

[0046] 31. Shading layer;

[0047] 40. Display panel; 400. Array substrate. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0049] Please refer to Figure 1 and Figure 2 An embodiment of the present application provides a semiconductor device 10, which includes an active layer 11, a gate 12, a source 13 and a drain 14; the gate 12 is arranged on one side of the active layer 11; the source 13 and the drain 14 are respectively connected to the opposite sides of the active layer 11.

[0050] The active layer 11 includes at least one first sublayer 114, the material of the first sublayer 114 includes a metal oxide conductive material and an electrical property regulating element doped in the metal oxide conductive material, and the electrical property regulating element includes at least one of the Group VIII metal elements.

[0051] During the implementation and application process, the embodiment of the present application can reduce the defect states in the metal oxide conductive material by doping the electrical regulating element in the metal oxide conductive material of the active layer 11, thereby converting it into a semiconductor material; at the same time, since the metal oxide conductive material has a higher electron concentration, the active layer 11 can have a high mobility, thereby improving the charging efficiency of the semiconductor device 10; in addition, the embodiment of the present application can reduce the defect states in the metal oxide conductive material by doping the electrical regulating element, thereby improving the light stability of the active layer 11 and improving the phenomenon that the threshold voltage Vth of the active layer 11 is negatively biased due to light.

[0052] Specifically, please continue to combine Figure 1 as well as Figure 2 The semiconductor device 10 is a thin film transistor. In the semiconductor device 10, the active layer 11 includes a channel 111 and a first contact portion 112 and a second contact portion 113 located on opposite sides of the channel 111; the gate 12 is aligned with the channel 111 of the active layer 11, the source 13 is connected to the first contact portion 112, and the drain 14 is connected to the second contact portion 113.

[0053] Among them, at least the channel 111 is a semiconductor, and by controlling the voltage loaded on the gate 12, it can be controlled whether the channel 111 generates a current channel, and when the channel 111 generates a current channel, the first contact portion 112 and the second contact portion 113 can be turned on, and then the source 13 and the drain 14 can be turned on to realize signal transmission.

[0054] In some embodiments, the semiconductor device 10 may further include a substrate 21 supporting the active layer 11 , the gate 12 , the source 13 , and the drain 14 , and an insulating layer separating the above devices.

[0055] In a specific embodiment, please refer to Figure 1 The semiconductor device 10 may include a substrate 21, the gate 12 disposed on the substrate 21, a first gate insulating layer 22 disposed on the substrate 21 and covering the gate 12, an active layer 11 disposed on a side of the first gate insulating layer 22 away from the gate 12, the source 13 and the drain 14 disposed on a side of the first gate insulating layer 22 away from the substrate 21, and a first insulating layer 23 disposed on the first gate insulating layer 22 and covering the active layer 11, the source 13 and the drain 14, wherein the source 13 and the drain 14 are respectively connected to the first contact portion 112 and the second contact portion 113.

[0056] In this embodiment, the active layer 11 includes at least one first sublayer 114, and the material of the first sublayer 114 includes a metal oxide conductive material and an electrical property adjustment element doped in the metal oxide conductive material, the electrical property adjustment element includes at least one of the Group VIII metal elements, and the Group VIII metal elements have a strong bonding ability with oxygen atoms. By doping the electrical property adjustment element in the metal oxide conductive material, the defect states in the metal oxide conductive material can be reduced, so that it is converted into a semiconductor material; at the same time, since the metal oxide conductive material has a high electron concentration, the active layer can have a high mobility, thereby improving the charging efficiency of the semiconductor device 10; in addition, the embodiment of the present application can reduce the defect states in the metal oxide conductive material by doping the electrical property adjustment element, thereby improving the light stability of the active layer 11, improving the phenomenon that the threshold voltage Vth of the active layer 11 is negatively biased due to light, and improving the subthreshold swing of the semiconductor device 10.

[0057] Among them, the electrical property adjustment element is distributed in the channel 111, the first contact portion 112 and the second contact portion 113, that is, the electrical property adjustment element can be evenly distributed in the first sublayer 114, and the channel 111, the first contact portion 112 and the second contact portion 113 can all be semiconductors.

[0058] In some embodiments, the orthographic projection of the channel 111 on the substrate 21 is located within the orthographic projection of the gate 12 on the substrate 21. Furthermore, the orthographic projection of the first contact portion 112 on the substrate 21 and the orthographic projection of the second contact portion 113 on the substrate 21 both partially overlap with the orthographic projection of the gate 12 on the substrate 21.

[0059] In some embodiments, the metal oxide conductive material includes at least one of indium tin oxide (ITO), antimony tin oxide (ATO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), and indium-doped zinc oxide (IZO); the electrical property regulating element may include at least one of iron, cobalt, nickel, ruthenium, rhodium, palladium, osmium, iridium, and platinum.

[0060] In some embodiments, the metal oxide conductive material is doped with at least one of a single substance of the electrical property regulating element and a compound of the electrical property regulating element.

[0061] In some embodiments, the metal oxide conductive material is doped with at least one of a single substance of the electrical property regulating element and an oxide of the electrical property regulating element; for example, when the electrical property regulating element is iron, the metal oxide conductive material can be doped with at least one of a single substance of iron and iron oxide.

[0062] In some embodiments, the proportion of metal atoms of the electrical property regulating element in the first sublayer 114 is greater than or equal to 0.1% and less than or equal to 10%; for example, the proportion of metal atoms of the electrical property regulating element in the first sublayer 114 can be 0.1%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%.

[0063] It can be understood that the above-mentioned metal atomic ratio refers to the atomic ratio of the electrical property adjustment element in the total metal atoms in the first sub-layer 114 .

[0064] In some embodiments, the carrier concentration of the first sublayer 114 is greater than or equal to 1E14 cm -3 , and less than or equal to 5E19cm -3 It can be understood that when the carrier concentration of the film layer is too high, for example, the carrier concentration of the film layer is 1E20cm -3 To 1E21cm -3 When the film layer is within the range of , the film layer has conductor characteristics. In the embodiment of the present application, the electrical property regulating element in the metal oxide conductive material with a high carrier concentration can reduce the carrier concentration, thereby realizing the semiconductorization of the conductor material.

[0065] It should be noted that 1E14 cm -3It means 1*10 14 cm -3 , 5E19 cm -3 It means 5*10 19 cm -3 .

[0066] In some embodiments, the resistance of the first sublayer 114 is greater than or equal to 1E4Ω / □ and less than or equal to 1E10Ω / □. It should be noted that the resistance mentioned above refers to square resistance, that is, the resistance value per unit area. For example, 1E4Ω / □ refers to 1*10 4 Ω / m 2 , 1E10Ω / □ means 1*10 10 Ω / m 2 .

[0067] In some embodiments, the Hall mobility of the first sub-layer 114 is greater than or equal to 30 cm 2 / Vs, and less than or equal to 70cm 2 / Vs; It is understandable that when the Hall mobility of the film layer is too high, for example, the Hall mobility of the film layer is greater than 100cm 2 / (V·s), the film layer has conductor characteristics. The Hall mobility of the first semiconductor layer 3 provided in the embodiment of the present application is 30cm 2 / Vs to 70cm 2 / Vs, indicating that the first semiconductor layer 3 has semiconductor characteristics.

[0068] That is, the embodiment of the present application can form a semiconductor material with a large carrier concentration and a high mobility by doping the electrical property adjustment element into the metal oxide conductive material, so as to realize the active layer 11 with high mobility.

[0069] In some embodiments, please refer to Figure 1 as well as Figure 2 The active layer 11 may further include at least one second sub-layer 115, and the at least one second sub-layer 115 is stacked with the at least one first sub-layer 114, and the material of the second sub-layer 115 includes a metal oxide semiconductor material.

[0070] The Hall mobility of the second sub-layer 115 is smaller than the Hall mobility of the first sub-layer 114 , and the material of the second sub-layer 115 may include Indium Gallium Zinc Oxide (IGZO).

[0071] Further, when the active layer 11 includes a stacked first sublayer 114 and a stacked second sublayer 115, the first sublayer 114 may be located between the second sublayer 115 and the first gate insulating layer 22; or, the second sublayer 115 may be located between the first sublayer 114 and the first gate insulating layer 22. It should be noted that at this time, at least one side of the active layer 11 is the second sublayer 115, and the second sublayer 115 is made of metal oxide semiconductor material, so that the second sublayer 115 in the active layer 11 is in contact with other film layers, which is beneficial to reducing the defects of the contact interface between the active layer 11 and the adjacent film layers, thereby improving the stability of the semiconductor device 10 and avoiding the negative bias of the threshold voltage Vth of the semiconductor device 10, thereby further improving the performance and reliability of the semiconductor device 10; on the other hand, by adding the second sublayer 115 to the active layer 11, it is beneficial to reduce the thickness of the first sublayer 114, thereby helping to reduce the overall thickness of the active layer 11 with high mobility, and thus helping to avoid the negative bias of the threshold voltage Vth caused by the excessive thickness of the active layer 11, thereby improving the stability of the semiconductor device 10.

[0072] In some embodiments, please refer to Figure 1 as well as Figure 3 When the active layer 11 includes multiple second sub-layers 115, the first sub-layer 114 is located between two adjacent second sub-layers 115, and then the second sub-layers 115 in the active layer 11 that are in contact with the adjacent film layers are all made of metal oxide semiconductor materials, which is beneficial to reducing the defects of the contact interface between the active layer 11 and the adjacent film layers, thereby improving the stability of the semiconductor device 10 and avoiding the negative bias of the threshold voltage Vth of the semiconductor device 10, thereby further improving the performance and reliability of the semiconductor device 10.

[0073] It should be noted that Figure 1 The semiconductor device 10 in the illustrated embodiment is a thin film transistor device with a bottom gate structure, while the semiconductor device 10 provided in the embodiment of the present application may also be a top gate thin film transistor device, as described below.

[0074] Please combine Figure 2 , Figure 3 as well as Figure 4As shown, in another specific embodiment of the present application, the semiconductor device 10 may include a substrate 21, the light shielding layer 31 disposed on the substrate 21, a barrier layer 24 disposed on the substrate 21 and covering the light shielding layer 31, an active layer 11 disposed on the barrier layer 24, a second gate insulating layer 25 disposed on a side of the active layer 11 away from the substrate 21 and covering the active layer 11, a gate 12 disposed on a side of the second gate insulating layer 25 away from the channel 111, an interlayer dielectric layer 26 covering the active layer 11 and the gate 12, a source 13 and a drain 14 disposed on a side of the interlayer dielectric layer 26 away from the active layer 11, and a second insulating layer 27 disposed on the interlayer dielectric layer 26 and covering the source 13 and the drain 14; wherein the source 13 and the drain 14 are respectively connected to the first contact portion 112 and the second contact portion 113 through the interlayer dielectric layer 26.

[0075] The second gate insulating layer 25 at least covers the channel 111 , the gate 12 is located on a side of the second gate insulating layer 25 away from the channel 111 , the source 13 is connected to the first contact portion 112 through the interlayer dielectric layer 26 , and the drain 14 is connected to the second contact portion 113 through the interlayer dielectric layer 26 .

[0076] In this embodiment, the active layer 11 includes at least one first sublayer 114, and the material of the first sublayer 114 includes a metal oxide conductive material and an electrical property regulating element doped in the metal oxide conductive material, and the electrical property regulating element includes a Group VIII metal element; wherein, doping the electrical property regulating element in the metal oxide conductive material can reduce the defect states in the metal oxide conductive material and convert it into a semiconductor material; at the same time, since the metal oxide conductive material has a higher electron concentration, the active layer can have a high mobility, thereby improving the charging efficiency of the semiconductor device 10; in addition, the embodiment of the present application can reduce the defect states in the metal oxide conductive material by doping the electrical property regulating element, thereby improving the light stability of the active layer 11 and improving the phenomenon that the threshold voltage Vth of the active layer 11 is negatively biased due to light.

[0077] In some embodiments, the material of the channel 111 includes the metal oxide conductive material and the electrical regulating element doped in the metal oxide conductive material, and thus the channel 111 is a semiconductor; the material of the first contact portion 112 and the material of the second contact portion 113 both include the metal oxide conductive material and the electrical regulating element and the conductive element doped in the metal oxide conductive material, wherein the conductive element is doped in the first contact portion 112 and the second contact portion 113 to make the semiconductor conductive, so as to achieve electrical connection between the first contact portion 112 and the source 13 and between the second contact portion 113 and the drain 14.

[0078] In some embodiments, the conductive element includes at least one of B, Ne, P and Ar.

[0079] Among them, in the manufacturing process of the semiconductor device 10, the single substance or oxide of the electrical property regulating element can be mixed with the metal oxide conductive material first, and then deposited to obtain the active layer 11, so that the electrical property regulating element can be evenly distributed in the active layer 11; then, the area of ​​the active layer 11 corresponding to the first contact portion 112 and the second contact portion 113 can be conductorized, for example, by using an ion implantation process.

[0080] It should be noted that Figure 4 In the embodiment shown, the active layer 11 can also be provided with the second sub-layer 115, and Figure 4 The structures and positions of the first sub-layer 114 and the second sub-layer 115 in the active layer 11 in the embodiment shown in the figure can be the same as those in the embodiment shown in the figure. Figure 1 The same configurations in the illustrated embodiment will not be described in detail here; in addition, Figure 4 In the illustrated embodiment, the first sub-layer 114 and the second sub-layer 115 may be doped with conductive elements at positions corresponding to the first contact portion 112 and the second contact portion 113 to perform a conductive process.

[0081] In summary, the embodiment of the present application can reduce the defect states in the metal oxide conductive material by doping the electrical property regulating element in the metal oxide conductive material of the active layer 11, thereby converting it into a semiconductor material; at the same time, since the metal oxide conductive material has a higher electron concentration, the active layer can have a high mobility, thereby improving the charging efficiency of the semiconductor device 10; in addition, the embodiment of the present application can reduce the defect states in the metal oxide conductive material by doping the electrical property regulating element, thereby improving the light stability of the active layer 11 and improving the phenomenon that the threshold voltage Vth of the active layer 11 is negatively biased due to light.

[0082] Also, please refer to Figure 1 as well as Figure 5 The embodiment of the present application further provides an array substrate 400, and the array substrate 400 includes the semiconductor device 10 described in the above embodiment.

[0083] In some embodiments, the array substrate 400 includes a pixel arrangement area 101 and a non-pixel arrangement area 102 adjacent to the pixel arrangement area 101, and the non-pixel arrangement area 102 includes a driving circuit sub-area 1021; the pixel arrangement area 101 of the array substrate is used to set a plurality of pixel circuits, and the non-pixel arrangement area 102 of the array substrate can be used to set functional circuits and signal routing devices, for example, the driving circuit sub-area 1021 in the non-pixel arrangement area 102 can be used to set functional circuits and signal routing devices. For example, functional circuits such as gate driving circuits and multiplexing circuits can be set.

[0084] Among them, the semiconductor device 10 can be used in at least the gate driving circuit and the multiplexing circuit to form a thin film transistor with high mobility in the gate driving circuit and the multiplexing circuit, thereby improving the performance and electrical signal transmission capability of the gate driving circuit and the multiplexing circuit.

[0085] In some embodiments, the array substrate further includes a scan signal line, one end of which is connected to the gate drive circuit, and the other end of which extends into the pixel arrangement area 101 and is connected to the pixel circuit, and the gate drive circuit includes an output transistor connected to the scan signal line, and at least the output transistor in the gate drive circuit is the semiconductor device 10 to meet the signal output efficiency of the output transistor. Further, all thin film transistors in the gate drive circuit can be the semiconductor device 10; for example, the gate drive circuit can include a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintenance module, then the thin film transistor in the pull-up control module, the thin film transistor in the pull-up module, the thin film transistor in the pull-down module, and the thin film transistor in the pull-down maintenance module can all be the semiconductor device 10.

[0086] In some embodiments, the thin film transistor in the pixel circuit may also be the semiconductor device 10 .

[0087] Also, please refer to Figure 1 as well as Figure 6 The embodiment of the present application further provides a display panel 40, and the display panel 40 includes the array substrate 400 described in the above embodiment.

[0088] In some embodiments, the display panel 40 may be an organic light emitting diode display panel, and the display panel further includes film layers such as an anode layer, an organic light emitting layer, a cathode layer, and an encapsulation layer disposed on the array substrate 400.

[0089] In some embodiments, the display panel 40 can be a liquid crystal display panel, and the display panel also includes a pixel electrode arranged on the array substrate 400, a liquid crystal layer arranged on the side of the pixel electrode away from the array substrate 400, a color film substrate arranged on the side of the liquid crystal layer away from the array substrate 400, and a common electrode arranged on the array substrate 400 and / or the color film substrate.

[0090] It can be understood that the display panel 40 includes the same array substrate 400 and the semiconductor device 10 as those in the above embodiment. Therefore, the display panel 40 can have the same beneficial effects as those in the above embodiment, which will not be described in detail.

[0091] Among them, mobility is one of the important indicators for measuring the semiconductor device 10, which determines the speed at which the charge moves in the semiconductor device 10, so high mobility means faster response speed and higher work efficiency, which is crucial to improving the overall performance of electronic equipment. At the same time, the greater the mobility, the smaller the resistivity, and the smaller the power consumption when the same current passes, which means that in the semiconductor device 10 with high mobility, the device can complete the same task with lower power consumption, thereby reducing energy waste and heat generation. In addition, mobility directly affects the switching conversion speed and cut-off frequency of the semiconductor device 10, so the semiconductor device 10 with high mobility can shorten the time for minority carriers to cross the base region, thereby improving the switching speed and frequency response characteristics of the semiconductor device 10.

[0092] In the embodiment of the present application, since the semiconductor device 10 provided in the aforementioned embodiment has high mobility and light stability, it is beneficial to improve the response speed, working efficiency and stability of the display panel 40 and can reduce the power consumption of the display panel 40.

[0093] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0094] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0096] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that: include: Active layer; A gate, disposed on one side of the active layer; A source electrode and a drain electrode, respectively connected to opposite sides of the active layer; The active layer includes at least one first sublayer, the material of the first sublayer includes a metal oxide conductive material and an electrical property regulating element doped in the metal oxide conductive material, and the electrical property regulating element includes at least one of the Group VIII metal elements.

2. The semiconductor device according to claim 1, wherein: The metal oxide conductive material includes at least one of indium tin oxide, antimony tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide and indium-doped zinc oxide.

3. The semiconductor device according to claim 1, wherein: The metal oxide conductive material is doped with at least one of a simple substance of the electrical property regulating element and a compound of the electrical property regulating element.

4. The semiconductor device according to claim 3, characterized in that The metal oxide conductive material is doped with at least one of a simple substance of the electrical property adjustment element and an oxide of the electrical property adjustment element.

5. The semiconductor device according to claim 3, characterized in that The metal oxide conductive material is doped with at least one of iron and iron oxide.

6. The semiconductor device according to claim 1, wherein: The active layer includes a channel and a first contact portion and a second contact portion located on opposite sides of the channel, the gate is arranged in alignment with the channel, the source is connected to the first contact portion, the drain is connected to the second contact portion, and the electrical regulation element is distributed in the channel, the first contact portion and the second contact portion.

7. The semiconductor device according to claim 6, characterized in that The channel, the first contact portion and the second contact portion are all semiconductors; The semiconductor device further comprises: A substrate, the gate is disposed on the substrate; A first gate insulating layer is arranged on the substrate and covers the gate, the active layer is arranged on a side of the first gate insulating layer away from the gate, at least the orthographic projection of the channel on the substrate is located within the orthographic projection of the gate on the substrate, and the source and the drain are arranged on a side of the first gate insulating layer away from the substrate and are respectively connected to the first contact portion and the second contact portion.

8. The semiconductor device according to claim 6, characterized in that The channel is a semiconductor, and the first contact portion and the second contact portion are conductors; Among them, the material of the channel includes the metal oxide conductive material and the electrical regulating element doped in the metal oxide conductive material, and the material of the first contact part and the material of the second contact part both include the metal oxide conductive material and the electrical regulating element and the conductor element doped in the metal oxide conductive material.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device further comprises: a substrate, the active layer being disposed on the substrate; A second gate insulating layer is arranged on a side of the active layer away from the substrate and covers the active layer, the gate is arranged on a side of the second gate insulating layer away from the channel, the source and the drain are arranged on a side of the second gate insulating layer away from the active layer and are respectively connected to the first contact portion and the second contact portion.

10. The semiconductor device according to claim 1, wherein: The proportion of metal atoms of the electrical property adjustment element in the first sublayer is greater than or equal to 0.1% and less than or equal to 10%.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that: The carrier concentration of the first sublayer is greater than or equal to 1E14 cm -3 , and less than or equal to 5E19cm -3 ; The resistance of the first sublayer is greater than or equal to 1E4Ω / □ and less than or equal to 1E10Ω / □; The Hall mobility of the first sublayer is greater than or equal to 30 cm 2 / Vs, and less than or equal to 70cm 2 / Vs.

12. The semiconductor device according to any one of claims 1 to 10, characterized in that: The active layer further includes at least one second sub-layer, which is stacked with at least one first sub-layer, and the material of the second sub-layer includes a metal oxide semiconductor material.

13. The semiconductor device according to claim 12, characterized in that The Hall mobility of the second sub-layer is smaller than the Hall mobility of the first sub-layer.

14. The semiconductor device according to claim 12, wherein: The active layer includes a plurality of the second sub-layers, and the first sub-layer is located between two adjacent second sub-layers.

15. An array substrate, characterized in that: The array substrate comprises the semiconductor device according to any one of claims 1 to 14.

16. A display panel, characterized in that: The display panel includes the array substrate as claimed in claim 15.

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