Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and is used for improving the load uniformity of scanning lines. The display panel comprises a display area which comprises a second display area, and the second display area comprises a light hole and a sub-area; the first scanning line is at least located in the display area and comprises a wiring part, the wiring part comprises a first sub-wiring and a second sub-wiring which are electrically connected, and the first sub-wiring and the second sub-wiring in the wiring part are overlapped; the first scanning line comprises a second sub-scanning line, and at least part of the second sub-scanning line is located in the second display area; the second scanning sub-line comprises at least two wiring parts, one wiring part corresponds to one sub-area, the second scanning sub-line further comprises a first winding wire, and the wiring parts on the two sides of the light hole are connected through the first winding wire; the wiring part of at least one second sub-scanning line comprises a first wiring part, the first wiring part comprises a first side and a second side which are opposite to each other, and a first sub-wire and a second sub-wire in the first wiring part are connected on the first side and are not connected on the second side.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes a pixel circuit and a scanning line electrically connected to the pixel circuit. When the display area of ​​the display panel includes a light-transmitting hole, the scanning line needs to be designed to be wound around the light-transmitting hole.

[0003] However, this winding design may cause the scanning lines in different display areas to have inconsistent loads, thereby affecting display uniformity. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device, which are used to improve the load uniformity of scan lines in the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including: substrate; A display area, comprising a first display area and a second display area arranged along a first direction, wherein the second display area comprises light-transmitting holes and sub-areas arranged along the second direction, an opposite side of the light-transmitting holes comprises the sub-areas, and the first direction intersects the second direction; the display area comprises the pixel circuit; a first scan line, at least partially located in the display area and electrically connected to the pixel circuit, the first scan line comprising at least one routing portion, the routing portion comprising a first sub-routing and a second sub-routing that are electrically connected, and in a direction perpendicular to the plane where the substrate is located, the first sub-routing and the second sub-routing in the same routing portion at least partially overlap; The first scan line includes a first sub-scan line and a second sub-scan line, the first sub-scan line is at least partially located in the first display area, and the second sub-scan line is at least partially located in the second display area; The first sub-scan line includes one routing portion, the first sub-routing line and the second sub-routing line in the same routing portion penetrate the first display area along the second direction, and the first sub-routing line and the second sub-routing line are connected at both ends; The second sub-scan line includes at least two routing portions, and the second sub-scan line also includes a first winding surrounding the light-transmitting hole. In the same second sub-scan line, one routing portion corresponds to one sub-area, and the two routing portions on both sides of the light-transmitting hole are connected through the first winding; and the routing portion in at least one of the second sub-scan lines includes a first routing portion, and the first routing portion includes a first side and a second side opposite to each other in the second direction, and the first sub-routing and the second sub-routing in the first routing portion are connected on the first side and not connected on the second side.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0007] The technical solution provided by the embodiment of the present invention has the following beneficial effects: In an embodiment of the present invention, the second sub-scan line includes a first routing portion, and the first sub-routing and the second sub-routing in the first routing portion are connected only on one side, and are not connected on the other side. Compared with the design method in the prior art in which the first sub-routing and the second sub-routing in the routing portion on one side of the light-transmitting hole are connected at both ends, the first sub-routing and the second sub-routing in the first routing portion will not form a parallel structure, thereby increasing the overall load of the second sub-scan line, and then using the effect of the first routing portion on the load increase of the second sub-scan line to offset the effect of the winding design on the load reduction of the second sub-scan line, so that the load of the second sub-scan line tends to be consistent with the load of the first sub-scan line, thereby weakening the load difference between the first scan lines in different display areas, and effectively improving the display uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0009] Figure 1 A schematic diagram of a structure of a display panel in the prior art; Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Figure 3 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Figure 4 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Figure 5for Figure 3 and Figure 4 A corresponding signal transmission schematic diagram; Figure 6 for Figure 3 and Figure 4 Another corresponding signal transmission schematic diagram; Figure 7 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Figure 8 for Figure 7 A corresponding signal transmission schematic diagram; Fig. 9 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.10 for Fig. 9 A corresponding signal transmission schematic diagram; Fig.11 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention; Fig.12 for Fig.11 A corresponding timing diagram; Fig.13 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention; Fig.14 for Fig.13 A cross-sectional view along the A1-A2 direction; Fig.15 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.16 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.17 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention; Fig.18 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.19 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig. 20 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.21 A schematic diagram of the structure of a second sub-scan line provided by an embodiment of the present invention; Fig. 22 for Fig.21 A cross-sectional view along the B1-B2 direction; Fig.23 Another structural schematic diagram of the second sub-scan line provided by an embodiment of the present invention; Fig.24 for Fig.23 A cross-sectional view along the C1-C2 direction; Fig.25 A schematic diagram of another structure of the second sub-scan line provided by an embodiment of the present invention; Fig.26 for Fig.25 A cross-sectional view along the D1-D2 direction; Fig. 27 A schematic diagram of another structure of a second sub-scan line provided by an embodiment of the present invention; Fig.28 for Fig. 27 A cross-sectional view along the direction E1-E2; Fig.29 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.30 for Fig.29 A cross-sectional view along the F1-F2 direction; Fig.31 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.32 for Fig.31 A cross-sectional view along the G1-G2 direction; Fig.33 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.34 for Fig.33 A cross-sectional view along the H1-H2 direction; Fig.35 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.36 for Fig.35 A cross-sectional view along the direction I1-I2; Fig.37 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.38 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.39 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.40 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.41 A schematic diagram of another structure of a second sub-scan line provided by an embodiment of the present invention; Fig.42 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.43 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0011] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0012] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0013] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0014] The display panel includes a pixel circuit and a scan line electrically connected to the pixel circuit. At present, at least one scan line can adopt a double-layer wiring design. The following is an introduction to a structural design adopted by such a scan line in the prior art.

[0015] like Figure 1 As shown, Figure 1 This is a schematic diagram of a structure of a display panel in the prior art, wherein the display area of ​​the display panel includes a first display area 01 and a second display area 02 arranged along a first direction x. The second display area 02 includes a light-transmitting hole 03 and sub-areas 04 located on opposite sides of the light-transmitting hole 03 along a second direction y, and the second direction y intersects with the first direction x.

[0016] The display panel further includes a substrate 05, a pixel circuit 06 and a first scan line 07. The first scan line 07 is electrically connected to the pixel circuit 06, and includes a first sub-wire 08 and a second sub-wire 09. In a direction perpendicular to the plane where the substrate 05 is located, the first sub-wire 08 and the second sub-wire 09 at least partially overlap.

[0017] For the first scan line 07 in the first display area 01, since the first display area 01 is not provided with a light-transmitting hole 03, the first sub-routing 08 and the second sub-routing 09 in this part of the first scan line 07 both horizontally penetrate the first display area 01, and the first sub-routing 08 and the second sub-routing 09 in the same first scan line 07 are connected at both ends.

[0018] For the first scan line 07 in the second display area 02, since the light-transmitting hole 03 is provided in the second display area 02, this part of the first scan line 07 needs to adopt a winding design at the light-transmitting hole 03. In the first scan line 07 in the second display area 02, the first sub-route 08 in the same first scan line 07 is disconnected at both sides of the light-transmitting hole 03 to form a discontinuous route, and the first sub-route 08 disconnected on one side of the light-transmitting hole 03 is connected to the second sub-route 09 at both ends, and then, the second sub-route 09 is connected to the second sub-route 09 on the other side of the light-transmitting hole 03 through the winding 010, forming a continuous signal transmission path.

[0019] However, the inventors have found that, with the above design, the loads of the first scan line 07 in different display areas will be significantly different: In order to improve the transmittance of the light-transmitting hole 03, sub-pixels are usually not arranged in the light-transmitting hole 03 or the density of the arranged sub-pixels is very small, which makes the winding 010 in the first scanning line 07 of the second display area 02 not connected or only connected to a small number of pixel circuits 06, and the coupling between the winding 010 and the pixel circuit 06 is also very small, so that the load of the first scanning line 07 in the second display area 02 is significantly smaller than that of the first scanning line 07 in the first display area 01. This load difference between the first scanning lines 07 will further lead to display differences between the second display area 02 and the first display area 01, causing obvious lateral mura phenomenon to appear on the display panel.

[0020] In this regard, an embodiment of the present invention provides a display panel, such as Figure 2~Figure 4 As shown, Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 3 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 4 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. The display panel includes a substrate 1. The substrate 1 may be a rigid substrate such as glass, or a flexible substrate such as polyimide.

[0021] The display panel also includes a display area AA, and the display area AA includes a first display area AA1 and a second display area AA2 arranged along a first direction x. The second display area AA2 includes a light-transmitting hole 2 and a sub-area 3 arranged along a second direction y, and an optical component such as a camera is correspondingly arranged at the light-transmitting hole 2, and the opposite side of the light-transmitting hole 2 includes the sub-area 3, and the first direction x intersects with the second direction y.

[0022] In other words, the second display area AA2 includes m light-transmitting holes 2 and m+1 sub-areas 3, m≥1, for example, m=1, 2, 3, etc., the sub-areas 3 and the light-transmitting holes 2 are alternately arranged along the second direction y, and a sub-area 3 is provided on opposite sides of each light-transmitting hole 2. The embodiment of the present invention is schematically described by taking the second display area AA2 including one light-transmitting hole 2 as an example.

[0023] The display area AA further includes a pixel circuit 4 .

[0024] The display panel further includes a first scan line 5, at least part of which is located in the display area AA and electrically connected to the pixel circuit 4. The first scan line 5 includes at least one routing portion 6, and the routing portion 6 includes a first sub-routing 7 and a second sub-routing 8 that are electrically connected, and in a direction perpendicular to the plane where the substrate 1 is located, the first sub-routing 7 and the second sub-routing 8 in the same routing portion 6 at least partially overlap.

[0025] The first scan line 5 includes a first sub-scan line 5-1 and a second sub-scan line 5-2. The first sub-scan line 5-1 is at least partially located in the first display area AA1, and the second sub-scan line 5-2 is at least partially located in the second display area AA2.

[0026] For the first sub-scan line 5-1, the first sub-scan line 5-1 includes a routing portion 6, and the first sub-routing 7 and the second sub-routing 8 in the same routing portion 6 pass through the first display area AA1 along the second direction y, and the first sub-routing 7 and the second sub-routing 8 in the same routing portion 6 are connected at both ends.

[0027] Exemplarily, in a more specific structure, the display panel also includes a first non-display area NAA1 surrounding the display area AA. In the same routing section 6 of the first sub-scan line 5-1, the first sub-routing 7 and the second sub-routing 8 both transversely penetrate the first display area AA1, and extend to the first non-display area NAA1 on both sides of the first display area AA1. The first sub-routing 7 and the second sub-routing 8 in the routing section 6 are connected at both ends, which specifically means that the first sub-routing 7 and the second sub-routing 8 are connected in the first non-display area NAA1 on one side of the first display area AA1, and are also connected in the first non-display area NAA1 on the other side of the first display area AA1.

[0028] For the second sub-scan line 5-2, the second sub-scan line 5-2 includes at least two routing portions 6, and the second sub-scan line 5-2 also includes a first winding 9 surrounding the light-transmitting hole 2. In the same second sub-scan line 5-2, one routing portion 6 corresponds to one sub-area 3, and the two routing portions 6 on both sides of the light-transmitting hole 2 are connected by the first winding 9. Among them, the routing portion 6 in at least one second sub-scan line 5-2 includes a first routing portion 10, and the first routing portion 10 includes a first side fd and a second side sd opposite to each other in the second direction y, and the first sub-routing 7 and the second sub-routing 8 in the first routing portion 10 are connected on the first side fd and are not connected on the second side sd.

[0029] Exemplarily, in a more specific structure, the display panel further includes a first non-display area NAA1 surrounding the display area AA, and the display area AA further includes a second non-display area NAA2 surrounding the light-transmitting hole 2, and the second non-display area NAA2 is located between the light-transmitting hole 2 and the sub-area 3. In the same first routing portion 10 of the second sub-scanning line 5-2, the first sub-routing 7 and the second sub-routing 8 both transversely penetrate the sub-area 3 where they are located, and extend to the first non-display area NAA1 and the second non-display area NAA2 on both sides of the sub-area 3. Among them, one of the first side fd and the second side sd of the first routing portion 10 can be understood as the first non-display area NAA1 located on one side of the sub-area 3, and the other side can be understood as the second non-display area NAA2 located on the other side of the sub-area 3. The first sub-route 7 and the second sub-route 8 in the first routing portion 10 are connected on the first side fd and are not connected on the second side sd. Specifically, it means that the first sub-route 7 and the second sub-route 8 are connected in the first non-display area NAA1 on one side of the sub-area 3 and are not connected in the second non-display area NAA2 on the other side of the sub-area 3, or the first sub-route 7 and the second sub-route 8 are connected in the second non-display area NAA2 on one side of the sub-area 3 and are not connected in the first non-display area NAA1 on the other side of the sub-area 3.

[0030] In the technical solution provided in the embodiment of the present invention, the second sub-scan line 5-2 includes a first routing portion 10, and the first sub-routing 7 and the second sub-routing 8 in the first routing portion 10 are connected only on one side and not on the other side. The first sub-routing 7 and the second sub-routing 8 in the first routing portion 10 do not form a parallel structure. Figure 1 The structure shown in the figure will increase the load of the second sub-scan line 5-2, and then the effect of the first routing portion 10 on the increased load of the second sub-scan line 5-2 can be used to offset the effect of the winding design on the reduced load of the second sub-scan line 5-2, so that the load of the second sub-scan line 5-2 tends to be consistent with the load of the first sub-scan line 5-1, thereby weakening the load difference between the first scan lines 5 in different display areas AA, and effectively improving the display uniformity of the display panel.

[0031] In one possible implementation, see Figure 3 and Figure 4 The first side fd is the side of the first wiring portion 10 close to the light-transmitting hole 2. That is, the first sub-wiring 7 and the second sub-wiring 8 in the first wiring portion 10 are connected on the side close to the light-transmitting hole 2, and are not connected on the side away from the light-transmitting hole 2.

[0032] Combination Figure 5 and Figure 6 The display panel further includes a first shift register 12, which is electrically connected to the first sub-scan line 5-1 and the second sub-scan line 5-2 and is used to provide a first scan signal to the first sub-scan line 5-1 and the second sub-scan line 5-2.

[0033] In the embodiment of the present invention, the first shift register 12 performs unilateral driving on the first scan line 5 connected thereto, that is, the first scan line 5 is electrically connected to one first shift register 12 only on one side. Fig.18 The details are described in the relevant embodiments.

[0034] Take the connection between the first shift register 12 and the first wiring portion 10 in the second sub-scan line 5 - 2 as an example.

[0035] When the first side fd is a side of the first wiring portion 10 close to the light-transmitting hole 2, in one case, combined with Figure 3 , Figure 4 and Figure 5 , Figure 5 for Figure 3 and Figure 4 A corresponding signal transmission schematic diagram, the first shift register 12 is connected to the first sub-route 7 in the first routing section 10. The first scanning signal provided by the first shift register 12 first flows to the first sub-route 7 in the first routing section 10, and when it is transmitted to the end of the first sub-route 7 close to the light-transmitting hole 2, it will continue to be transmitted to the routing section 6 on the other side of the light-transmitting hole 2 through the first winding 9, and transmitted to the second sub-route 8 in the first routing section 10, so as to realize that each first sub-route 7 and each second sub-route 8 in the second sub-scanning line 5-2 normally receives the first scanning signal.

[0036] In another case, combined Figure 3 , Figure 4 and Figure 6 , Figure 6 for Figure 3 and Figure 4Correspondingly, another signal transmission schematic diagram shows that the first shift register 12 is connected to the second sub-route 8 in the first routing section 10. The first scanning signal provided by the first shift register 12 first flows to the second sub-route 8 in the first routing section 10, and when it is transmitted to the end of the second sub-route 8 close to the light-transmitting hole 2, it will continue to be transmitted to the routing section 6 on the other side of the light-transmitting hole 2 through the first winding 9, and transmitted to the first sub-route 7 in the first routing section 10, so as to realize that each first sub-route 7 and each second sub-route 8 in the second sub-scan line 5-2 normally receives the first scanning signal.

[0037] Among them, R1' shown in the accompanying drawings represents the resistance of the first sub-route 7 of the routing portion 6 in the first sub-scan line 5-1, R2' represents the resistance of the second sub-route 8 of the routing portion 6 in the first sub-scan line 5-1, R1 represents the resistance of the first sub-route 7 of the routing portion 6 in the second sub-scan line 5-2, R2 represents the resistance of the second sub-route 8 of the routing portion 6 in the second sub-scan line 5-2, and R3 represents the resistance of the first winding 9 in the second sub-scan line 5-2.

[0038] It should be noted that, in the same second sub-scan line 5-2, the values ​​of the resistors R1 corresponding to the first sub-routings 7 in different routing sections 5 may be the same or different, and the values ​​of the resistors R2 corresponding to the second sub-routings 8 in different routing sections 5 may be the same or different.

[0039] For example, the display area 1 includes a first side and a second side that are opposite to each other along the second direction y. In one case, along the second direction y, the distance between the light-transmitting hole 2 and the first side is equal to the distance between the light-transmitting hole 2 and the second side. Then, in the same second sub-scanning line 5-2, the values ​​of the resistors R1 corresponding to the first sub-routings 7 in different routing sections 5 may be equal, and the values ​​of the resistors R2 corresponding to the second sub-routings 8 in different routing sections 5 may also be equal. Alternatively, in another case, along the second direction y, the distance between the light-transmitting hole 2 and the first side is not equal to the distance between the light-transmitting hole 2 and the second side. Then, in the same second sub-scanning line 5-2, the values ​​of the resistors R1 corresponding to the first sub-routings 7 in different routing sections 5 may also be unequal, and the values ​​of the resistors R2 corresponding to the second sub-routings 8 in different routing sections 5 may also be unequal.

[0040] When the display panel includes at least two light-transmitting holes 2, it means that the same second sub-scan line 5-2 includes at least two first windings 9. In the same second sub-scan line 5-2, the values ​​of the resistors R3 corresponding to different first windings 9 may be the same or different. For example, when the shapes and areas of at least two light-transmitting holes 2 are the same, the values ​​of the resistors R3 corresponding to different first windings 9 in the same second sub-scan line 5-2 may be equal. Alternatively, when the shapes and areas of at least two light-transmitting holes 2 are different, the values ​​of the resistors R3 corresponding to different first windings 9 in the same second sub-scan line 5-2 may also be unequal.

[0041] Or, in another feasible implementation, as Figure 7~Figure 10 As shown, Figure 7 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 8 for Figure 7 A corresponding signal transmission diagram, Fig. 9 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.10 for Fig. 9 A corresponding signal transmission schematic diagram, the first side fd is the side of the first routing portion 10 away from the light-transmitting hole 2. That is, the first sub-routing 7 and the second sub-routing 8 in the first routing portion 10 are connected on the side away from the light-transmitting hole 2, and are not connected on the side close to the light-transmitting hole 2.

[0042] Combination Figure 8 and Fig.10 The display panel includes a first shift register 12, which is electrically connected to the first sub-scan line 5-1 and the second sub-scan line 5-2 and is used to provide a first scan signal to the first sub-scan line 5-1 and the second sub-scan line 5-2.

[0043] Take the connection between the first shift register 12 and the first wiring portion 10 in the second sub-scan line 5 - 2 as an example.

[0044] When the first side fd is a side of the first wiring portion 10 away from the light-transmitting hole 2, in one case, combined with Figure 7 and Figure 8 , the first winding 9 is connected to the first sub-route 7. The first scanning signal provided by the first shift register 12 flows to the first sub-route 7 and the second sub-route 8 in the first routing portion 10 at the same time. When the first scanning signal is transmitted to the end of the second sub-route 8 close to the light-transmitting hole 2, it will no longer continue to be transmitted backward. When the first scanning signal is transmitted to the end of the first sub-route 7 close to the light-transmitting hole 2, it will continue to be transmitted to the routing portion 6 on the other side of the light-transmitting hole 2 via the first winding 9, so as to realize that each first sub-route 7 and each second sub-route 8 in the second sub-scan line 5-2 normally receives the first scanning signal.

[0045] In another case, combined Fig. 9 and Fig.10 , the first winding 9 is connected to the second sub-route 8. The first scanning signal provided by the first shift register 12 flows to the first sub-route 7 and the second sub-route 8 in the first routing portion 10 at the same time. When the first scanning signal is transmitted to the end of the first sub-route 7 close to the light-transmitting hole 2, it will no longer be transmitted backwards. When the first scanning signal is transmitted to the end of the second sub-route 8 close to the light-transmitting hole 2, it will continue to be transmitted to the routing portion 6 on the other side of the light-transmitting hole 2 via the first winding 9, so as to realize that each first sub-route 7 and each second sub-route 8 in the second sub-scan line 5-2 normally receives the first scanning signal.

[0046] The above two embodiments respectively illustrate the case where the first side fd is a side away from the light-transmitting hole 2 , and the case where the first side fd is a side close to the light-transmitting hole 2 .

[0047] It should be further explained that when the first side fd is the side close to the light-transmitting hole 2, a further effect can be achieved in the load design of the second sub-scanning line 5-2.

[0048] Specifically, in the first sub-scan line 5-1, the first sub-route 7 and the second sub-route 8 included in its routing portion 6 both transversely penetrate the entire first display area AA1 and are both relatively long. Therefore, the charging rate of the first sub-route 7 and the second sub-route 8 in the first sub-scan line 5-1 will be slightly slower.

[0049] In the second sub-scan line 5-2, combined Figure 3~Figure 6 When the first side fd is the side close to the light-transmitting hole 2, the first sub-wire 7 and the second sub-wire 8 in the first wiring portion 10 are connected at the side close to the light-transmitting hole 2. Figure 3 , Figure 4 and Figure 5 In the example, when the first scanning signal is transmitted to the end of the first sub-route 7 in the first routing section 10 near the light-transmitting hole 2, it will be transmitted backward through the first winding 9 and to the second sub-route 8 in the first routing section 10 at the same time. This can make the charging rate of the first sub-route 7 and the second sub-route 8 in the first routing section 10 slightly slower, and then the charging rate of the first sub-route 7 and the second sub-route 8 in the first sub-scan line 5-1 tends to be consistent, which helps to improve the charging consistency of different sub-routes. Similarly, in Figure 3 , Figure 4 and Figure 6When the first scanning signal is transmitted to the end of the second sub-route 8 in the first routing section 10 close to the light-transmitting hole 2, it will continue to be transmitted backward through the first winding 9 and to the first sub-route 7 of the first routing section 10 at the same time. In this way, the charging rate of the first sub-route 7 and the second sub-route 8 in the first routing section 10 will be slightly slower, and will be consistent with the charging rate of the first sub-route 7 and the second sub-route 8 in the first sub-scan line 5-1, so as to improve the charging consistency of different sub-routes.

[0050] In a possible implementation, Figure 11~Figure 14 As shown, Fig.11 A schematic diagram of the structure of a pixel circuit 4 provided in an embodiment of the present invention is shown in FIG. Fig.12 for Fig.11 A corresponding timing diagram, Fig.13 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention, Fig.14 for Fig.13 In a cross-sectional view along the A1-A2 direction, the pixel circuit 4 includes a first transistor T0, and the active layer ac of the first transistor T0 includes an oxide semiconductor material, that is, the active layer ac of the first transistor T0 is located in the oxide semiconductor layer oxy. The off-state leakage current of the first transistor T0 is small, which helps to improve the stability of the node voltage in the pixel circuit 4.

[0051] In the embodiment of the present invention, the active layer ac of the first transistor T0 may include an indium gallium zinc oxide (IGZO) material. In this case, the first transistor T0 is an IGZO transistor.

[0052] The gate of the first transistor T0 is electrically connected to the first scan line 5. The gate of the first transistor T0 includes a top gate g1 and a bottom gate g2, the top gate g1 is located in the first metal layer MG, and the bottom gate g2 is located in the second metal layer Mc. The first metal layer MG is located on the side of the active layer ac away from the substrate 1, that is, on the side of the oxide semiconductor layer oxy away from the substrate 1; the second metal layer Mc is located on the side of the active layer ac close to the substrate 1, that is, on the side of the oxide semiconductor layer oxy close to the substrate 1.

[0053] In the first scan line 5 , the first sub-wire 7 is located in the first metal layer MG and is partially reused as the top gate g1 , and the second sub-wire 8 is located in the second metal layer Mc and is partially reused as the bottom gate g2 .

[0054] In the embodiments of the present invention, see Fig.13 and Fig.14The active layer ac of the first transistor T0 can be electrically connected to other transistors or other signal lines through a connecting wire 50 . The connecting wire 50 is located in the third metal layer SD. The third metal layer SD is located on a side of the first metal layer MG away from the substrate 1 .

[0055] The first transistor T0 is a top-bottom dual-gate structure, and the first sub-wire 7 and the second sub-wire 8 are used to provide signal input for the top gate g1 and the bottom gate g2, respectively, which can increase the channel control capability of the first transistor T0, thereby improving the working reliability of the first transistor T0. In addition, the first sub-wire 7 is located in the first metal layer MG and is partially reused as the top gate g1, and the second sub-wire 8 is located in the second metal layer Mc and is partially reused as the bottom gate g2, which can also simplify the wiring method of the first scan line 5 and the gate of the first transistor T0, and the layout design is better.

[0056] In a possible implementation, Fig.15 As shown, Fig.15 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention, where the first side fd is a side of the first wiring portion 10 close to the light-transmitting hole 2. That is, the first sub-wiring 7 and the second sub-wiring 8 in the first wiring portion 10 are connected on the side close to the light-transmitting hole 2, and are not connected on the side away from the light-transmitting hole 2.

[0057] The display panel further includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2 and used to provide a first scan signal to the second sub-scan line 5-2. At the same time, the first shift register 12 is also electrically connected to the first sub-scan line 5-1 and used to provide a first scan signal to the first sub-scan line 5-1.

[0058] The first shift register 12 is located on a side of the first sub-routing 7 of the second sub-scanning line 5 - 2 connected thereto, away from the light-transmitting hole 2 , and in the first routing portion 10 , the second sub-routing 8 is connected to the first shift register 12 through the first sub-routing 7 .

[0059] The first shift register 12 is electrically connected to the first scan line 5 through the first connection line 15 .

[0060] The above-mentioned “in the first routing section 10, the second sub-routing 8 is connected to the first shift register 12 through the first sub-routing 7” specifically means that in the first routing section 10, the first sub-routing 7 is connected to the first connecting line 15, and the second sub-routing 8 is not connected to the first connecting line 15, and the first scanning signal provided by the first shift register 12 is first transmitted to the first sub-routing 7 via the first connecting line 15, and then transmitted to the second sub-routing 8, that is, the first scanning signal received by the second sub-routing 8 is transmitted by the first sub-routing 7.

[0061] First, combined with the previous Figure 3~Figure 6It can be seen from the description that when the first side fd is the side of the first routing section 10 close to the light-transmitting hole 2, the charging rate of the first sub-routing 7 and the second sub-routing 8 in the first routing section 10 is close to the charging rate of the first sub-routing 7 and the second sub-routing 8 in the first sub-scanning line 5-1, which can improve the charging consistency of the top gate g1 and the charging consistency of the bottom gate g2 of the first transistor T0 in different regions. Further, in the transistor with a top-bottom double-gate structure, the top gate g1 is more sensitive to the modulation of channel carriers than the bottom gate g2, so the top gate g1 has a greater impact on the switching characteristics of the transistor. The first sub-routing 7 in the first scanning line 5 is used to provide a signal to the top gate g1. Therefore, in the first sub-routing 7 section, the first sub-routing 7 is connected to the first shift register 12, so that the first sub-routing 7 can directly receive the first scanning signal provided by the first shift register 12, thereby reducing the signal voltage drop on the top gate g1 of the first transistor T0 in the sub-region 3.

[0062] Or, in another feasible implementation, as Fig.16 As shown, Fig.16 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention, where the first side fd is a side of the first wiring portion 10 close to the light-transmitting hole 2. That is, the first sub-wiring 7 and the second sub-wiring 8 in the first wiring portion 10 are connected on the side close to the light-transmitting hole 2, and are not connected on the side away from the light-transmitting hole 2.

[0063] The display panel further includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2 and used to provide a first scan signal to the second sub-scan line 5-2. At the same time, the first shift register 12 is also electrically connected to the first sub-scan line 5-1 and used to provide a first scan signal to the first sub-scan line 5-1.

[0064] The first shift register 12 is located on a side of the first sub-wire 7 in the second sub-scan line 5 - 2 connected thereto, away from the light-transmitting hole 2 , and in the first wiring portion 10 , the first sub-wire 7 is connected to the first shift register 12 through the second sub-wire 8 .

[0065] The first shift register 12 is electrically connected to the first scan line 5 through the first connection line 15 .

[0066] The above-mentioned “in the first routing section 10, the first sub-routing 7 is connected to the first shift register 12 through the second sub-routing 8” specifically means that in the first routing section 10, the second sub-routing 8 is connected to the first connecting line 15, and the first sub-routing 7 is not connected to the first connecting line 15, and the first scanning signal provided by the first shift register 12 is first transmitted to the second sub-routing 8 via the first connecting line 15, and then transmitted to the first sub-routing 7, that is, the first scanning signal received by the first sub-routing 7 is transmitted by the second sub-routing 8.

[0067] Combined with the previous Figure 3~Figure 6 It can be seen from the description that when the first side fd is the side of the first routing portion 10 close to the light-transmitting hole 2, the charging rates of the first sub-routing 7 and the second sub-routing 8 in the first routing portion 10 are closer to the charging rates of the first sub-routing 7 and the second sub-routing 8 in the first sub-scanning line 5-1, which can improve the charging consistency of the top gate g1 and the charging consistency of the bottom gate g2 of the first transistor T0 in different regions.

[0068] In this structure, although the first sub-route 7 in the first routing section 10 is not directly connected to the first shift register 12, the transmission path of the signal output by the first shift register 12 to the first sub-route 7 is still relatively short, so the signal voltage drop of the top gate g1 of the first transistor T0 in the partition will not be too large.

[0069] In one possible implementation, see again Fig.13 , the line width of the second sub-routing 8 is greater than the line width of the first sub-routing 7 .

[0070] Part of the second sub-route 8 is reused as the bottom gate g2 of the first transistor T0, and is located below the active layer ac of the first transistor T0. The wider the second sub-route 8 is, the flatter the active layer ac of the first transistor T0 is, the more regular the transmission path of the carriers in the active layer ac is, and the fewer obstacles the carriers encounter when moving in the active layer ac. Therefore, designing the line width of the first sub-route 7 to be larger helps to increase the conductivity of the first transistor T0, thereby achieving higher switching speeds and lower power consumption.

[0071] In one possible implementation, see again Fig.11 , the pixel circuit 4 includes a driving transistor T1.

[0072] The first transistor T0 includes a threshold compensation transistor T2, which is electrically connected between the second electrode of the driving transistor T1 and the gate of the driving transistor T1. The first scan line 5 includes a threshold compensation scan line S2N electrically connected to the threshold compensation transistor T2.

[0073] And / or, the first transistor T0 includes a gate reset transistor T3, which is electrically connected between the first reset line Ref1 and the gate of the driving transistor T1. The first scan line 5 includes a reset scan line S1N electrically connected to the gate reset transistor T3.

[0074] The threshold compensation transistor T2 and the gate reset transistor T3 are both electrically connected to the gate of the driving transistor T1, so the off-state leakage current of these two transistors has a greater impact on the gate potential of the driving transistor T1. To this end, the embodiment of the present invention designs the threshold compensation transistor T2 and / or the gate reset transistor T3 as a transistor structure with a top-bottom double gate, which can effectively reduce the impact of the off-state leakage current of these two transistors on the gate potential of the driving transistor T1, thereby ensuring the stability of the working state of the driving transistor T1.

[0075] In addition, see again Fig.11 , the pixel circuit 4 may further include: The data writing transistor T4 has a gate electrically connected to the writing scanning line Sp, a first electrode electrically connected to the data line Data, and a second electrode electrically connected to the first electrode of the driving transistor T1.

[0076] The first light emitting control transistor T5 has a gate electrically connected to the light emitting control scanning line Emit, a first electrode electrically connected to the power line PVDD, and a second electrode electrically connected to the first electrode of the driving transistor T1.

[0077] The second light emitting control transistor T6 has a gate electrically connected to the light emitting control scanning line Emit, a first electrode electrically connected to the second electrode of the driving transistor T1 , and a second electrode electrically connected to the light emitting element 1616 .

[0078] The anode reset transistor T7 has a gate electrically connected to the write scan line Sp, a first electrode electrically connected to the second reset line Ref2 , and a second electrode electrically connected to the light emitting element 16 .

[0079] The storage capacitor Cst has a first plate electrically connected to the power line PVDD and a second plate electrically connected to the gate of the driving transistor T1.

[0080] The bias transistor T8 has a gate electrically connected to the bias scanning line Sp*, a first electrode electrically connected to the bias signal line DVH, and a second electrode electrically connected to the first electrode of the driving transistor T1.

[0081] The light emitting element 16 may be various types of devices such as an organic light emitting diode (OLED), a light emitting diode (LED), etc.

[0082] In one possible structure, see Fig.11The first transistor T0 includes a threshold compensation transistor T2 and a gate reset transistor T3. The threshold compensation transistor T2 is turned on and turned off at a low level in response to a high level provided by a threshold compensation scan line S2N. The gate reset transistor T3 is turned on and turned off at a low level in response to a high level provided by a reset scan line S1N.

[0083] The pixel circuit further includes a second transistor T0', the active layer of which includes a silicon semiconductor material, for example, the active layer of which includes a low temperature polysilicon material, and the second transistor T0' is a low temperature polysilicon (LTPS) transistor.

[0084] The second transistor T0' comprises at least one of a driving transistor T1, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, an anode reset transistor T7 and a bias transistor T8. The second transistor T0' is turned on in response to a low level provided by the scan line connected thereto and turned off in response to a high level.

[0085] The embodiment of the present invention is illustrated by taking the example that the second transistor T0 ′ includes a driving transistor T1 , a data writing transistor T4 , a first light emission control transistor T5 , a second light emission control transistor T6 , an anode reset transistor T7 and a bias transistor T8 .

[0086] Combination Fig.11 and Fig.12 , the driving cycle of the pixel circuit 4 includes a writing frame F1 and a holding frame F2.

[0087] The writing frame F1 includes a first non-luminous period t11 and a first luminous period t21, wherein the first non-luminous period t11 includes a reset period t1 and a charging period t2. In the reset period t1, the gate reset transistor T3 is turned on to reset the gate of the driving transistor T1. In the charging period t2, the threshold compensation transistor T2, the data writing transistor T4 and the anode reset transistor T7 are turned on, and the driving transistor T1 is charged and the threshold compensation is performed on the driving transistor T1 by using the threshold compensation transistor T2 and the data writing transistor T4, and the anode of the light-emitting element 16 is reset by using the anode reset transistor T7. In the first luminous period t21, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on to transmit the driving current converted by the driving transistor T1 to the light-emitting element 16.

[0088] The holding frame F2 includes a second non-luminous period t12 and a second luminous period t22, wherein the second non-luminous period t12 includes a bias adjustment period t3. During the bias adjustment period t3, the bias transistor T8 is turned on to adjust the bias state of the driving transistor T1. During the second luminous period t22, the first luminous control transistor T5 and the second luminous control transistor T6 are turned on to transmit the driving current converted by the driving transistor T1 to the light emitting element 16.

[0089] It should be noted that the driving process of the above pixel circuit is only for schematic illustration. In other feasible driving modes, the bias transistor T8 can also be turned on in the first non-luminous period t11 of the writing frame F1, and the bias transistor T8 can be turned on once, twice or more times in the first non-luminous period t11 and / or the second non-luminous period t12.

[0090] Based on the above structure, Fig.17 As shown, Fig.17 Another schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, the display panel further includes a silicon semiconductor layer ss and a fourth metal layer M1, the fourth metal layer M1 is located on a side of the silicon semiconductor layer ss away from the substrate 1, and the second metal layer Mc is located on a side of the fourth metal layer M1 away from the substrate 1.

[0091] The silicon semiconductor layer ss includes the active layer ac' of the second transistor T0', and the fourth metal layer M1 includes the gate g' of the second transistor T0'. The active layer ac' of the second transistor T0' can be electrically connected to other transistors or other signal lines through the connecting wire 50, and the connecting wire 50 is located in the third metal layer SD.

[0092] In addition, the display panel may further include a fifth metal layer M0, which is located between the silicon semiconductor layer ss and the substrate 1. The fifth metal layer M0 includes a shielding metal 60. In a direction perpendicular to the plane of the substrate 1, at least a portion of the shielding metal 60 overlaps with the channel of the active layer ac' of the second transistor T0', thereby preventing external light from irradiating the channel of the second transistor T0' and affecting the characteristics of the second transistor T0'.

[0093] Based on the above circuit structure, Fig.18 As shown, Fig.18 This is another structural diagram of a display panel provided by an embodiment of the present invention. The first shift register 12 includes a first sub-shift register 12-1 electrically connected to the threshold compensation scan line S2N and a second sub-shift register 12-2 electrically connected to the reset scan line S1N.

[0094] The display panel further includes a second shift register 16 electrically connected to the write scan line Sp, a third shift register 17 electrically connected to the light emission control scan line Emit, and a fourth shift register 18 electrically connected to the bias scan line Sp*.

[0095] In one configuration, the display panel includes two second shift registers 16, which are respectively located at opposite sides of the display area AA, and perform bilateral driving on the write scan line Sp to improve the driving capability of the write scan line.

[0096] The display panel includes a first sub-shift register 12-1, a second sub-shift register 12-2, a third shift register 17 and a fourth shift register 18. Among them, two of the four shift registers are located on one side of the display area AA, and the other two are located on the other side of the display area AA. The four shift registers perform unilateral driving on the scan lines connected thereto.

[0097] In a possible implementation, Fig.19 and Fig. 20 As shown, Fig.19 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig. 20 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. The display area AA includes a plurality of circuit rows 19 arranged along a first direction x. The circuit row 19 includes a plurality of pixel circuits 4 arranged along a second direction y.

[0098] The display panel also includes a first shift register 12, which includes a plurality of cascaded first shift units 20, wherein one first shift unit 20 is electrically connected to the second sub-scanning lines 5-2 corresponding to m circuit rows 19, m≥2, and the m routing portions 6 located on the same side of the light-transmitting hole 2 in the m second sub-scanning lines 5-2 are connected to the same first winding 9. In other words, the first windings 9 included in the m second sub-scanning lines 5-2 are the same first windings 9. In this way, the number of first windings 9 required to be set in the second sub-scanning lines 5-2 can be reduced, thereby reducing the wiring space occupied by the first windings 9.

[0099] In addition, the first shift register 12 further includes a plurality of cascaded second shift units 21 , and one second shift unit 21 is electrically connected to the first sub-scanning lines 5 - 1 corresponding to the m circuit rows 19 .

[0100] Further, see Fig. 20 Among the m second sub-scan lines 5-2 electrically connected to the same first shift unit 20, the m second sub-scan lines 5-2 all include the first routing portion 10, so that the loads of the m second sub-scan lines 5-2 tend to be consistent, thereby improving the load consistency of different second sub-scan lines 5-2.

[0101] Further, see Fig. 20 , among the m second sub-scanning lines 5-2 electrically connected to the same first shift unit 20, the first wiring portions 10 in the m second sub-scanning lines 5-2 overlap along the first direction x. That is, the first wiring portions 10 in the m second sub-scanning lines 5-2 are either all on the left side of the light-transmitting hole 2 or all on the right side of the light-transmitting hole 2. In this way, no matter whether the first shift register 12 is located on the side of the first wiring portion 10 away from the light-transmitting hole 2 or on the side of the first wiring portion 10 close to the light-transmitting hole 2, the flow direction of the signals in the m second sub-scanning lines 5-2 is consistent, thereby weakening the difference in signal voltage drops at different positions in the m second sub-scanning lines 5-2.

[0102] In one possible implementation, see Figure 21~Figure 27 The first wiring portion 10 is connected to the first via hole 22 and the second via hole 23 respectively.

[0103] On the first side fd of the first routing portion 10, the first sub-routing 7 and the second sub-routing 8 are connected through the first via 22; on the second side sd of the first routing portion 10, one of the first sub-routing 7 and the second sub-routing 8 is connected to the second via 23, and the other is not connected to the second via 23, thereby realizing the disconnection of the first sub-routing 7 and the second sub-routing 8 on the second side sd, and the signal in the first sub-routing 7 cannot be directly transmitted to the second sub-routing 8 via the second via 23 on the second side, or the signal in the second sub-routing 8 cannot be directly transmitted to the first sub-routing 7 via the second via 23 on the second side.

[0104] In a possible implementation, Figure 21~Figure 24 As shown, Fig.21 A schematic diagram of the structure of the second sub-scan line 5-2 provided in an embodiment of the present invention, Fig. 22 for Fig.21 A cross-sectional view along the B1-B2 direction, Fig.23 Another structural schematic diagram of the second sub-scan line 5-2 provided in an embodiment of the present invention is shown in FIG. Fig.24 for Fig.23 In a cross-sectional view along the C1-C2 direction, the first sub-wire 7 is located on the first metal layer MG, the second sub-wire 8 is located on the second metal layer Mc, and the first metal layer MG is located on the side of the second metal layer Mc away from the substrate 1. For example, the first metal layer MG is located on the side of the oxide semiconductor layer oxy away from the substrate 1, and the second metal layer Mc is located on the side of the oxide semiconductor layer oxy close to the substrate 1.

[0105] The display panel includes a first connection portion 24 and a second connection portion 25 . The first connection portion 24 and the second connection portion 25 are located in a third metal layer SD. The third metal layer SD is located on a side of the first metal layer MG away from the substrate 1 .

[0106] There is at least one insulating layer 26 between the third metal layer SD and the first metal layer MG, and there are at least two insulating layers 26 between the third metal layer SD and the second metal layer Mc.

[0107] The first via 22 and the second via 23 each include a first sub-via 27 and a second sub-via 28. The first sub-via 27 penetrates the insulating layer 26 between the third metal layer SD and the first metal layer MG, and the second sub-via 28 penetrates the insulating layer 26 between the third metal layer SD and the second metal layer Mc.

[0108] See also Figure 21~Figure 24 , on the first side fd of the first routing portion 10 , the first connecting portion 24 is electrically connected to the first sub-routing 7 through the first sub-via 27 in the first via 22 , and the first connecting portion 24 is also electrically connected to the second sub-routing 8 through the second sub-via 28 in the first via 22 .

[0109] That is, see Fig. 22 and Fig.24 , on the first side fd of the first routing portion 10, in a direction perpendicular to the plane of the substrate 1, the first connecting portion 24 overlaps with the first sub-via 27 and the second sub-via 28 in the first via 22, the first sub-routing 7 in the first routing portion 10 overlaps with the first sub-via 27 in the first via 22, and is then connected to the first connecting portion 24 through the first sub-via 27, the second sub-routing 8 in the first routing portion 10 overlaps with the second sub-via 28 in the first via 22, and is then connected to the first connecting portion 24 through the second sub-via 28.

[0110] See also Fig.21 and Fig. 22 , on the second side sd of the first routing portion 10, the second connecting portion 25 is electrically connected to the first sub-routing 7 through the first sub-via 27 in the second via 23, and the second connecting portion 25 is also connected to the second sub-via 28 in the second via 23, and in a direction perpendicular to the plane where the substrate 1 is located, there is a gap between the second sub-routing 8 and the second sub-via 28 in the second via 23.

[0111] That is, on the second side sd of the first routing portion 10, in a direction perpendicular to the plane of the substrate 1, the second connecting portion 25 overlaps with both the first sub-via 27 and the second sub-via 28 in the second via 23, the first sub-routing 7 in the first routing portion 10 overlaps with the first sub-via 27 in the second via 23, and is then connected to the second connecting portion 25 through the first sub-via 27, while the second sub-routing 8 in the first routing portion 10 does not overlap with the second sub-via 28 in the second via 23, and there is a gap between the projection of the second sub-routing 8 in the first routing portion 10 and the projection of the second sub-via 28 in the second via 23, the second sub-routing 8 is not connected to the second sub-via 28, and thus the second sub-routing 8 is not connected to the second connecting portion 25.

[0112] Alternatively, see Fig.23 and Fig.24 , on the second side sd of the first routing portion 10, the second connecting portion 25 is electrically connected to the second sub-routing 8 through the second sub-via 28 in the second via 23, and the second connecting portion 25 is also connected to the first sub-via 27 in the second via 23, and in a direction perpendicular to the plane where the substrate 1 is located, there is a gap between the first sub-routing 7 and the first sub-via 27 in the second via 23.

[0113] That is, on the second side sd of the first routing portion 10, in a direction perpendicular to the plane of the substrate 1, the second connecting portion 25 overlaps with both the first sub-via 27 and the second sub-via 28 in the second via 23, the second sub-routing 8 in the first routing portion 10 overlaps with the second sub-via 28 in the second via 23, and is then connected to the second connecting portion 25 through the second sub-via 28, while the first sub-routing 7 in the first routing portion 10 does not overlap with the first sub-via 27 in the second via 23, and there is a gap between the projection of the first sub-routing 7 in the first routing portion 10 and the projection of the first sub-via 27 in the second via 23, the first sub-routing 7 is not connected to the first sub-via 27, and thus the first sub-routing 7 is not connected to the second connecting portion 25.

[0114] In the above structure, the first sub-line 7 and the second sub-line 8 are connected by transition metal (the first connection portion 24 and the second connection portion 25 ).

[0115] When the second sub-scan line 5-2 adopts Figure 1In the design concept of the structure shown, on the first side fd of the first routing portion 10, the first connection portion 24 is electrically connected to the first sub-routing 7 through the first sub-via 27 in the first via 22, and is electrically connected to the second sub-routing 8 through the second sub-via 28 in the first via 22. On the second side sd of the first routing portion 10, the second connection portion 25 is electrically connected to the first sub-routing 7 through the first sub-via 27 in the second via 23, and is electrically connected to the second sub-routing 8 through the second sub-via 28 in the second via 23. Therefore, on both the first side fd and the second side sd, there are mask patterns of the connection portion and mask patterns of the sub-vias.

[0116] When the second sub-scan line 5-2 adopts Fig.21 and Fig.23 In the design idea, although the first sub-routing 7 and the second sub-routing 8 are not connected on the second side sd of the first routing portion 10, the second connecting portion 25 and the second via 23 connected to the second connecting portion 25 are retained on the second side sd. In this way, it is not necessary to readjust the mask pattern of the third metal layer SD, and it is not necessary to adjust the mask pattern of the second via 23, and it is not necessary to replace the mask plate, saving process costs. Moreover, retaining the second connecting portion 25 and the second via 23 on the second side sd can also make the overall distribution of the connecting portion and the via more uniform, and the layout design is better.

[0117] Or, in another feasible implementation, as Figure 25~Figure 28 As shown, Fig.25 FIG. 5 is another structural diagram of the second sub-scan line 5-2 provided in an embodiment of the present invention. Fig.26 for Fig.25 A cross-sectional view along the D1-D2 direction, Fig. 27 This is another structural schematic diagram of the second sub-scan line 5-2 provided in an embodiment of the present invention. Fig.28 for Fig. 27 In a cross-sectional view along the E1-E2 direction, the first sub-wire 7 is located on the first metal layer MG, the second sub-wire 8 is located on the second metal layer Mc, and the first metal layer MG is located on the side of the second metal layer Mc away from the substrate 1. For example, the first metal layer MG is located on the side of the oxide semiconductor layer oxy away from the substrate 1, and the second metal layer Mc is located on the side of the oxide semiconductor layer oxy close to the substrate 1. At least one insulating layer 26 is spaced between the first metal layer MG and the second metal layer Mc.

[0118] The first via hole 22 and the second via hole 23 both penetrate the insulating layer 26 between the first metal layer MG and the second metal layer Mc.

[0119] See also Fig.25 and Fig.26, at the second side sd of the first routing portion 10 , the first sub-routing 7 is connected to the second via 23 , and in a direction perpendicular to the plane where the substrate 1 is located, there is a gap between the second sub-routing 8 and the second via 23 .

[0120] That is, on the second side sd of the first routing portion 10, in a direction perpendicular to the plane of the substrate 1, the first sub-routing 7 in the first routing portion 10 overlaps and is connected to the second via 23, but the second sub-routing 8 in the first routing portion 10 does not overlap with the second via 23, and there is a gap between the projection of the second sub-routing 8 in the first routing portion 10 and the projection of the second via 23, and the second sub-routing 8 is not connected to the first sub-routing 7 through the second via 23.

[0121] Alternatively, see Fig. 27 and Fig.28 , at the second side sd of the first routing portion 10 , the second sub-routing 8 is connected to the second via 23 , and in a direction perpendicular to the plane where the substrate 1 is located, there is a gap between the first sub-routing 7 and the second via 23 .

[0122] That is, on the second side sd of the first routing portion 10, in a direction perpendicular to the plane of the substrate 1, the second sub-routing 8 in the first routing portion 10 overlaps with the second via 23, but the first sub-routing 7 in the first routing portion 10 does not overlap with the second via 23, and there is a gap between the projection of the first sub-routing 7 in the first routing portion 10 and the projection of the second via 23, and the first sub-routing 7 is not connected to the second sub-routing 8 through the second via 23.

[0123] When the second sub-scan line 5-2 adopts Figure 1 In the design concept of the structure shown, on the first side fd of the first routing portion 10, the first sub-routing 7 and the second sub-routing 8 in the first routing portion 10 are electrically connected through the first via 22. On the second side sd of the first routing portion 10, the first sub-routing 7 and the second sub-routing 8 in the first routing portion 10 are electrically connected through the second via 23. Therefore, there are mask patterns of vias on both the first side fd and the second side sd.

[0124] When the second sub-scan line 5-2 adopts Fig.25 and Fig. 27 In the design scheme, although the first sub-routing 7 and the second sub-routing 8 are not connected on the second side sd of the first routing portion 10, the second via 23 is still retained on the second side sd. In this way, it is not necessary to readjust the mask pattern of the via and replace the mask plate, saving process costs. Moreover, retaining the second via 23 on the second side sd can also make the overall distribution of the via more uniform and the layout design better.

[0125] Furthermore, if Figure 29~Figure 32 As shown, Fig.29This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.30 for Fig.29 A cross-sectional view along the F1-F2 direction, Fig.31 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.32 for Fig.31 A cross-sectional view along the G1-G2 direction shows that the display panel includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2 and is located on a side of the first wiring portion 10 in the second sub-scan line 5-2 away from the light-transmitting hole 2.

[0126] The first shift register 12 is electrically connected to the first routing portion 10 via a first connection line 15 . The first connection line 15 includes a first sub-connection line 29 .

[0127] See also Fig.29 and Fig.30 , at the second side sd of the first routing portion 10, the second via 23 is connected to the first sub-routing 7, the first sub-connecting wire 29 is located in the second metal layer Mc, and the first sub-wire is connected to the second via 23. Alternatively, see Fig.31 and Fig.32 , at the second side sd of the first routing portion 10 , the second via 23 is connected to the second sub-routing 8 , the first sub-connecting wire 29 is located in the first metal layer MG, and the first sub-wire is connected to the second via 23 .

[0128] In this setting, the second via 23 is reused as a connecting via between the first shift register 12 and the second sub-scan line 5-2, which can not only realize the rational use of the second via 23, but also prevent metal from other wirings from being deposited in the second via 23 and causing a short circuit with the second sub-scan line 5-2.

[0129] Or, combined Fig.19 ,like Figure 33~Figure 36 As shown, Fig.33 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.34 for Fig.33 A cross-sectional view along the H1-H2 direction, Fig.35 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.36 for Fig.35 In a cross-sectional view along the direction I1 - I2 , the display area AA includes a plurality of circuit rows 19 arranged along a first direction x, and the circuit row 19 includes a plurality of pixel circuits 4 arranged along a second direction y.

[0130] The display panel also includes a first shift register 12, which includes a plurality of cascaded first shift units 20, wherein one first shift unit 20 is electrically connected to the second sub-scan lines 5-2 corresponding to m circuit rows 19, m≥2, and the m second sub-scan lines 5-2 are connected via a second connecting line 30.

[0131] Among them, see Fig.33 and Fig.34 , at the second side sd of the first routing portion 10, the second via 23 is connected to the second sub-routing 8, the second connecting wire 30 is located in the first metal layer MG, and the second connecting wire 30 is connected to the second via 23. Alternatively, see Fig.35 and Fig.36 , on the second side sd of the first routing portion 10 , the second via 23 is connected to the first sub-routing 7 , the second connecting line 30 is located in the second metal layer Mc, and the second connecting line 30 is connected to the second via 23 .

[0132] When a first shift unit 20 is electrically connected to m second sub-scan lines 5-2, the m second sub-scan lines 5-2 are connected together through the second connecting line 30. The above-mentioned setting method reuses the second via 23 as a connecting via between the second sub-scan line 5-2 and the second connecting line 30. This can not only realize the reasonable use of the second via 23, but also prevent the metal of other routings from being deposited in the second via 23 and causing a short circuit with the second sub-scan line 5-2.

[0133] In one possible implementation, see again Figure 3 and Figure 4 In the second sub-scan line 5-2, the routing section 6 further includes a second routing section 31. In the second routing section 31, the first sub-routing 7 and the second sub-routing 8 penetrate the sub-area 3 along the second direction y, and the first sub-routing 7 and the second sub-routing 8 are connected at both ends.

[0134] If all the routing portions 6 in the second sub-scan line 5-2 are designed as the first routing portions 10, the overall load of the second sub-scan line 5-2 may be too large, which in turn increases the load difference between the second sub-scan line 5-1 and the first sub-scan line 5-1. In the embodiment of the present invention, by designing some of the routing portions 6 in the second sub-scan line 5-2 as the first routing portions 10 and some of the routing portions 6 as the second routing portions 31, the load of the second sub-scan line 5-2 can be increased within a reasonable range, so as to better weaken the load difference between the second sub-scan line 5-2 and the first sub-scan line 5-1.

[0135] Furthermore, if Fig.37 and Fig.38 As shown, Fig.37 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.38This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. The display panel further includes a first shift register 12. The first shift register 12 is electrically connected to the second sub-scan line 5-2.

[0136] The first shift register 12 is located at a side of the first wiring portion 10 in the second sub-scan line 5 - 2 away from the second wiring portion 31 , and is connected to the first wiring portion 10 .

[0137] The first shift register 12 performs unilateral driving on the second sub-scanning line 5-2. Since the first sub-routing 7 and the second sub-routing 8 in the first routing section 10 are only connected on one side, the overall load will be larger. By connecting the first shift register 12 to the first routing section 10, the signal voltage drop difference on the routing section 6 on both sides of the light-transmitting hole 2 can be weakened, thereby weakening the display difference of the sub-areas 3 on both sides of the light-transmitting hole 2.

[0138] Or, if Fig.39 and Fig.40 As shown, Fig.39 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.40 This is another structural diagram of the display panel provided by an embodiment of the present invention, in which the first shift register 12 can also be located on the side of the second wiring portion 31 in the second sub-scan line 5-2 away from the first wiring portion 10, and connected to the second wiring portion 31. In this case, the signal output by the first shift register 12 first flows through the second wiring portion 31, and then flows through the first wiring portion 10 via the first winding 9.

[0139] In a feasible implementation manner, the first winding 9 is connected to the first sub-route 7 or the second sub-route 8, and the first winding 9 is arranged in the same layer as the first sub-route 7 or the second sub-route 8 connected thereto. Figure 3 , the first winding 9 is connected to the second sub-wire 8 and is arranged on the same layer as the second sub-wire 8, or, see Figure 4 The first winding 9 is connected to the first sub-routing 7 and is arranged on the same layer as the first sub-routing 7.

[0140] The first winding 9 is on the same layer as the first sub-routing 7 or the second sub-routing 8 connected thereto, and there is no need to punch holes to connect the first winding 9 and the routing portion 6, so wiring is simpler.

[0141] In a possible implementation, Fig.41 As shown, Fig.41 This is another structural schematic diagram of the second sub-scan line 5-2 provided in an embodiment of the present invention, in which the first winding 9 is arranged in a different layer from at least one of the first sub-routing 7 and the second sub-routing 8. Exemplarily, the first winding 9 can be located in the third metal layer SD, or the first winding can also be located in the fourth metal layer M1 or the fifth metal layer M0.

[0142] In the above structure, other metal layers can be selected to lay out the first winding 9 according to the wiring conditions in the area where the first winding 9 is located, and the wiring position of the first winding 9 will be more flexible.

[0143] In addition, it should be noted that the first winding 9 in the embodiment of the present invention can be as follows: Figure 3 As shown, the light transmission hole 2 is arranged in the second non-display area NAA2, or as Fig.42 As shown, Fig.42 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. At least a portion of the first winding 9 may also be disposed around the light-transmitting hole 2 in the first display area AA1.

[0144] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.43 As shown, Fig.43 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig.43 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0145] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A display area, comprising a first display area and a second display area arranged along a first direction, wherein the second display area comprises light-transmitting holes and sub-areas arranged along the second direction, and opposite sides of the light-transmitting holes comprise the sub-areas, and the first direction intersects the second direction; the display area comprises a pixel circuit; a first scan line, at least partially located in the display area and electrically connected to the pixel circuit, the first scan line comprising at least one routing portion, the routing portion comprising a first sub-routing and a second sub-routing that are electrically connected, and in a direction perpendicular to the plane where the substrate is located, the first sub-routing and the second sub-routing in the same routing portion at least partially overlap; The first scan line includes a first sub-scan line and a second sub-scan line, the first sub-scan line is at least partially located in the first display area, and the second sub-scan line is at least partially located in the second display area; The first sub-scan line includes one routing portion, the first sub-routing line and the second sub-routing line in the same routing portion penetrate the first display area along the second direction, and the first sub-routing line and the second sub-routing line are connected at both ends; The second sub-scan line includes at least two routing portions, and the second sub-scan line also includes a first winding surrounding the light-transmitting hole. In the same second sub-scan line, one routing portion corresponds to one sub-area, and the two routing portions on both sides of the light-transmitting hole are connected through the first winding; and the routing portion in at least one of the second sub-scan lines includes a first routing portion, and the first routing portion includes a first side and a second side opposite to each other in the second direction, and the first sub-routing and the second sub-routing in the first routing portion are connected on the first side and not connected on the second side.

2. The display panel according to claim 1, characterized in that: The first side is a side of the first wiring portion close to the light-transmitting hole.

3. The display panel according to claim 1, characterized in that: The first side is a side of the first wiring portion away from the light-transmitting hole.

4. The display panel according to claim 1, characterized in that: The pixel circuit comprises a first transistor, an active layer of the first transistor comprises an oxide semiconductor material, and a gate of the first transistor is electrically connected to the first scan line; The gate of the first transistor includes a top gate and a bottom gate, the top gate is located in the first metal layer, and the bottom gate is located in the second metal layer; the first metal layer is located on a side of the active layer away from the substrate, and the second metal layer is located on a side of the active layer close to the substrate; In the first scan line, the first sub-routing is located in the first metal layer and is partially reused as the top gate, and the second sub-routing is located in the second metal layer and is partially reused as the bottom gate.

5. The display panel according to claim 4, characterized in that: The first side is a side of the first wiring portion close to the light-transmitting hole; The display panel also includes a first shift register, which is electrically connected to the second sub-scan line. The first shift register is located on a side of the first sub-routing portion of the second sub-scan line to which it is connected, away from the light-transmitting hole, and in the first routing portion, the second sub-routing is connected to the first shift register through the first sub-routing.

6. The display panel according to claim 4, characterized in that: The first side is a side of the first wiring portion close to the light-transmitting hole; The display panel also includes a first shift register, which is electrically connected to the second sub-scan line. The first shift register is located on a side of the first sub-routing portion of the second sub-scan line to which it is connected, away from the light-transmitting hole, and in the first routing portion, the first sub-routing is connected to the first shift register through the second sub-routing.

7. The display panel according to claim 4, characterized in that: The line width of the second sub-routing is greater than the line width of the first sub-routing.

8. The display panel according to claim 4, characterized in that: The pixel circuit includes a driving transistor; The first transistor includes a threshold compensation transistor, the threshold compensation transistor is electrically connected between the second electrode of the driving transistor and the gate of the driving transistor, and the first scan line includes a threshold compensation scan line electrically connected to the threshold compensation transistor; And / or, the first transistor includes a gate reset transistor, the gate reset transistor is electrically connected between the first reset line and the gate of the driving transistor, and the first scan line includes a reset scan line electrically connected to the gate reset transistor.

9. The display panel according to claim 1, characterized in that: The display area includes a plurality of circuit rows arranged along the first direction, and the circuit rows include a plurality of pixel circuits arranged along the second direction; The display panel also includes a first shift register, which includes a plurality of cascaded first shift units, wherein one first shift unit is electrically connected to the second sub-scan lines corresponding to m circuit rows, m≥2, and m routing portions located on the same side of the light-transmitting hole among the m second sub-scan lines are connected to the same first winding.

10. The display panel according to claim 9, characterized in that: The m second sub-scanning lines all include the first routing portion.

11. The display panel according to claim 10, characterized in that: The first routing portions in the m second sub-scan lines overlap along the first direction.

12. The display panel according to claim 1, characterized in that: The first routing portion is connected to the first via hole and the second via hole respectively; On the first side of the first routing portion, the first sub-routing and the second sub-routing are connected through the first via, and on the second side of the first routing portion, one of the first sub-routing and the second sub-routing is connected to the second via and the other is not connected to the second via.

13. The display panel according to claim 12, characterized in that: The first sub-line is located in a first metal layer, the second sub-line is located in the second metal layer, and the first metal layer is located on a side of the second metal layer away from the substrate; The display panel comprises a first connection portion and a second connection portion, wherein the first connection portion and the second connection portion are located in a third metal layer, and the third metal layer is located on a side of the first metal layer away from the substrate; Wherein, the first via hole and the second via hole each include a first sub-via hole and a second sub-via hole, the first sub-via hole penetrates the insulating layer between the third metal layer and the first metal layer, and the second sub-via hole penetrates the insulating layer between the third metal layer and the second metal layer; On the first side of the first routing portion, the first connecting portion is electrically connected to the first sub-routing portion through the first sub-via in the first via, and the first connecting portion is also electrically connected to the second sub-routing portion through the second sub-via in the first via; On the second side of the first routing portion, the second connecting portion is electrically connected to the first sub-routing portion through the first sub-via in the second via, the second connecting portion is also connected to the second sub-via in the second via, and there is a gap between the second sub-routing portion and the second sub-via in the second via in a direction perpendicular to the plane where the substrate is located; Alternatively, on the second side of the first routing portion, the second connecting portion is electrically connected to the second sub-routing through the second sub-via in the second via, and the second connecting portion is also connected to the first sub-via in the second via, and in a direction perpendicular to the plane of the substrate, there is a gap between the first sub-routing and the first sub-via in the second via.

14. The display panel according to claim 12, characterized in that: The first sub-line is located in a first metal layer, the second sub-line is located in the second metal layer, and the first metal layer is located on a side of the second metal layer away from the substrate; Wherein, the first via hole and the second via hole both penetrate the insulating layer between the first metal layer and the second metal layer; On the second side of the first routing portion, the first sub-routing is connected to the second via hole, and there is a gap between the second sub-routing and the second via hole in a direction perpendicular to the plane where the substrate is located; Alternatively, on the second side of the first routing portion, the second sub-routing is connected to the second via hole, and in a direction perpendicular to the plane where the substrate is located, there is a gap between the first sub-routing and the second via hole.

15. The display panel according to claim 14, characterized in that: The display panel comprises a first shift register, the first shift register is electrically connected to the second sub-scan line, and the first shift register is located on a side of the first wiring portion of the second sub-scan line away from the light-transmitting hole; The first shift register is electrically connected to the first wiring portion through a first connection line, and the first connection line includes a first sub-connection line; On the second side of the first routing portion, the second via is connected to the second sub-routing line, the first sub-line is located in the first metal layer, and the first sub-connecting line is connected to the second via; Alternatively, on the second side of the first routing portion, the second via is connected to the first sub-routing portion, the first sub-connecting line is located in the second metal layer, and the first sub-line is connected to the second via.

16. The display panel according to claim 14, characterized in that: The display area includes a plurality of circuit rows arranged along the first direction, and the circuit rows include a plurality of pixel circuits arranged along the second direction; The display panel further includes a first shift register, the first shift register includes a plurality of first shift units connected in cascade, wherein one first shift unit is electrically connected to the second sub-scanning lines corresponding to m circuit rows, m≥2, and the m second sub-scanning lines are connected via a second connecting line; Wherein, on the second side of the first routing portion, the second via is connected to the second sub-routing, the second connecting line is located in the first metal layer, and the second connecting line is connected to the second via; Alternatively, on the second side of the first routing portion, the second via is connected to the first sub-routing portion, the second connecting line is located in the second metal layer, and the second connecting line is connected to the second via.

17. The display panel according to claim 1, characterized in that: In the second sub-scan line, the routing portion further includes a second routing portion; In the second routing portion, the first sub-routing and the second sub-routing penetrate the sub-region along the second direction, and the first sub-routing and the second sub-routing are connected at both ends.

18. The display panel according to claim 17, characterized in that: The display panel further includes a first shift register electrically connected to the second sub-scan line. The first shift register is located on a side of the second sub-scan line where the first wiring portion is away from the second wiring portion, and is connected to the first wiring portion.

19. The display panel according to claim 17, characterized in that: The display panel further includes a first shift register electrically connected to the second sub-scan line, and the first shift register is located on a side of the second wiring portion of the second sub-scan line away from the first wiring portion, and is connected to the second wiring portion.

20. The display panel according to claim 1, characterized in that: The first winding is connected to the first sub-routing or the second sub-routing, and the first winding is arranged in the same layer as the first sub-routing or the second sub-routing connected to it.

21. The display panel according to claim 1, characterized in that: The first winding is arranged in a different layer from at least one of the first sub-routing and the second sub-routing.

22. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 21.

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