Display device

Abstract

A display device is provided. The display device includes: a substrate; a plurality of pixels including a plurality of sub-pixels; a first capping layer disposed on the substrate and including an open region; a plurality of first light emitting diodes disposed on the plurality of sub-pixels on the first capping layer; and a second light emitting diode disposed on the substrate in one or more pixels among the plurality of pixels, in which a portion of a lower side of the second light emitting diode is disposed in the opening area, and a portion of an upper side of the second light emitting diode is disposed on the first capping layer, and the area of the top surface of the second light emitting diode is larger than that of the bottom surface of the second light emitting diode. And the light emitting diode is transmitted and repaired only when defects occur, so that the processing cost is reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0152604 filed in the Korean Intellectual Property Office on November 7, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to display devices, and more particularly to display devices using light emitting diodes (LEDs). Background Art

[0004] As display devices used for displays of computers, televisions, cellular phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0005] The application range of the display device is diversified to personal digital assistants as well as monitors of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0006] In addition, in recent years, a display device including a light emitting diode has attracted attention as a next-generation display device. Since a light emitting diode is formed of an inorganic material rather than an organic material, it has excellent reliability, so that its life span is longer than that of a liquid crystal display device or an organic light emitting display device. In addition, a light emitting diode has a fast lighting speed, excellent luminous efficiency, and strong impact resistance, so that it has excellent stability and can display an image with high brightness. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a display device in which a repaired light emitting diode is delivered only when a defect occurs, thereby reducing processing costs.

[0008] Another object to be achieved by the present disclosure is to provide a display device in which a reflective layer is provided on a side surface of a repaired light emitting diode to suppress degradation of luminance.

[0009] The objects of the present disclosure are not limited to the objects mentioned above, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate; a plurality of pixels including a plurality of sub-pixels; a first covering layer disposed on the substrate and including an opening region; a plurality of first light-emitting diodes disposed on the plurality of sub-pixels on the first covering layer; and a second light-emitting diode disposed in one or more pixels among the plurality of pixels on the substrate, wherein a portion of a lower side of the second light-emitting diode is disposed in the opening region, a portion of an upper side of the second light-emitting diode is disposed on the first covering layer, and an area of ​​a top surface of the second light-emitting diode is greater than an area of ​​a bottom surface of the second light-emitting diode.

[0011] Additional details of exemplary embodiments are included in the detailed description and the accompanying drawings.

[0012] According to the present disclosure, a repaired light emitting diode is transmitted only when a defect occurs in a specific sub-pixel, so as to reduce the manufacturing cost of the display device.

[0013] According to the present disclosure, a step structure is formed on a planarization layer to easily repair a light emitting diode.

[0014] According to the present disclosure, the light emitting diode is disposed in the step structure of the planarization layer to suppress a short circuit between electrodes of the light emitting diode.

[0015] According to the present disclosure, a reflective material is disposed on a side surface of a planarization layer surrounding a light emitting layer to improve brightness.

[0016] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2 is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 3 is along Figure 2 A cross-sectional view taken along AA′;

[0021] Figure 4 is an enlarged plan view of a state before repairing a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 5 is along Figure 4 A cross-sectional view taken along BB′;

[0023] FIG. 6A to FIG. 6G is a process diagram for explaining a forming process of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 7 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure;

[0025] Figure 8 is along Figure 7 A cross-sectional view taken at CC′;

[0026] Fig. 9 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure; and

[0027] Fig.10 is along Fig. 9 Cross-sectional view taken at DD′. DETAILED DESCRIPTION

[0028] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0029] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Unless terms such as "including", "comprising", "having" and "consisting of..." used herein are used together with the term "only", these terms are generally intended to allow the addition of other components. Unless otherwise expressly stated, any reference to the singular may include the plural.

[0030] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0031] When terms such as "on", "over", "below" and "beside" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately" or "directly".

[0032] When an element or a layer is disposed “on” another element or layer, the element or layer is directly disposed on the other element or layer, or other elements or layers may be interposed therebetween.

[0033] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0034] Like reference numerals generally refer to like elements throughout the specification.

[0035] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0036] The features of the various embodiments of the present disclosure may be partially or completely adhered to or combined with each other and may interlock and operate in technically different ways, and the embodiments may be performed independently of each other or in association with each other.

[0037] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 In the present invention, for the convenience of description, among various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are shown.

[0039] Reference Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD supplying various signals to the display panel PN; and a timing controller TC controlling the gate driver GD and the data driver DD.

[0040] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 , it is shown that one gate driver GD is disposed to be spaced apart from one side of the display panel PN, but the number of the gate drivers GD and the placement thereof are not limited thereto.

[0041] The data driver DD converts the image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0042] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal input from the outside. In addition, the timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0043] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, even though not illustrated in the figure, each of the plurality of sub-pixels SP is connected to a high potential power line, a low potential power line, a reference line, and the like.

[0044] In the display panel PN, an active area AA and a non-active area NA surrounding the active area AA may be defined.

[0045] The active area AA is an area where an image is displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP configuring a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units configuring the active area AA, and n sub-pixels SP form one pixel PX. In each of the plurality of sub-pixels SP, a light-emitting diode and a thin film transistor for driving the light-emitting diode may be provided. Depending on the type of the display panel PN, the plurality of light-emitting diodes may be defined in different ways. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting diode may be a light-emitting diode (LED) or a micro light-emitting diode (micro-LED).

[0046] In the active area AA, a plurality of signal lines for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines may include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP and a plurality of scan lines for supplying a gate voltage to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low potential power line and a high potential power line may also be provided, but are not limited thereto.

[0047] The non-active area NA is an area where no image is displayed, so that the non-active area NA can be defined as an area extending from the active area AA. In the non-active area NA, a link line, a pad electrode, or a driving IC, such as a gate driver IC or a data driver IC, which transmits a signal to the sub-pixel SP of the active area AA can be set. The non-active area NA can be located on the rear surface of the display panel PN, that is, on the surface where the sub-pixel SP is not set or can be omitted, and is not limited to what is shown in the figure.

[0048] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-active area NA in the form of a gate within a panel (GIP), or may be installed between a plurality of sub-pixels SP in the active area AA in the form of a gate within an active area (GIA). For example, the data driver DD and the timing controller TC are formed in a separate flexible film and a printed circuit board, and may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to a pad electrode formed in the non-active area NA of the display panel PN. If the gate driver GD is installed in the form of a GIP, and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode of the non-active area NA, it is necessary to ensure an area of ​​the non-active area NA for setting the gate driver GD and the pad electrode. By doing so, the border is increased.

[0049] In contrast, when the gate driver GD is installed in the active area AA in a GIA manner and the side lines SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN are formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero frame having substantially no frame can be achieved.

[0050] Figure 2 is a schematic enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 2 In FIG. 1 , only a plurality of sub-pixels SP, a plurality of reflective electrodes RE, a plurality of first light emitting diodes ED1 , a plurality of second light emitting diodes ED2 , a first area A1 , a second area A2 , and a second connection electrode CE2 are shown.

[0051] First, refer to Figure 2, the display panel PN includes a plurality of pixels PX, which are formed by a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting element ED and a pixel circuit to emit light independently. One pixel PX may include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel, but is not limited thereto.

[0052] Each of the plurality of sub-pixels SP may include a first area A1 and a second area A2. In the first area A1 and the second area A2, a plurality of light emitting diodes ED including a plurality of first light emitting diodes ED1 and a plurality of second light emitting diodes ED2 may be disposed.

[0053] In the first area A1 of the plurality of sub-pixels SP, a plurality of first light emitting diodes ED1 among the plurality of light emitting diodes ED are disposed.

[0054] The plurality of first light emitting diodes ED1 are light emitting diodes transferred to the substrate when the display device is initially manufactured. That is, regardless of whether the plurality of first light emitting diodes ED1 are defective, the plurality of first light emitting diodes ED1 are disposed in each of the plurality of sub-pixels SP. Therefore, the first light emitting diodes ED1 may be referred to as main light emitting diodes.

[0055] The plurality of first LEDs ED1 include a first red LED EDR1, a first green LED EDG1, and a first blue LED EDB1. The first red LED EDR1 is disposed in the first sub-pixel SP1, the first green LED EDG1 is disposed in the second sub-pixel SP2, and the first blue LED EDB1 may be disposed in the third sub-pixel SP3.

[0056] In the second area A2 of the plurality of sub-pixels SP, a plurality of second light emitting diodes ED2 among the plurality of light emitting diodes ED are disposed.

[0057] The plurality of second light-emitting diodes ED2 are normal light-emitting diodes, and the first light-emitting diode ED1 provided in the same sub-pixel as the second light-emitting diode ED2 may be a defective light-emitting diode. For example, the plurality of second light-emitting diodes ED2 are light-emitting diodes that are transferred to the substrate when a defective light-emitting diode appears among the plurality of first light-emitting diodes ED1, or are light-emitting diodes that are transferred to the substrate when the first light-emitting diode ED1 is not illuminated due to an electrical connection failure with the first light-emitting diode ED1 even though the first light-emitting diode ED1 is not defective. Therefore, the plurality of second light-emitting diodes ED2 may be referred to as repaired light-emitting diodes. Figure 2 In the embodiment, it is assumed that all of the plurality of first light emitting diodes ED1 are not lit due to the defect reason described above, so that the plurality of second light emitting diodes ED2 are transmitted to all of the plurality of sub-pixels SP.

[0058] The plurality of second LEDs ED2 include a second red LED EDR2, a second green LED EDG2, and a second blue LED EDB2. The second red LED EDR2 is disposed in the first sub-pixel SP1, the second green LED EDG2 is disposed in the second sub-pixel SP2, and the second blue LED EDB2 may be disposed in the third sub-pixel SP3.

[0059] Therefore, if Figure 2 As shown, in the first sub-pixel SP1, a first red light emitting diode EDR1 and a second red light emitting diode EDR2 are provided. In the second sub-pixel SP2, a first green light emitting diode EDG1 and a second green light emitting diode EDG2 are provided. In the third sub-pixel SP3, a first blue light emitting diode EDB1 and a second blue light emitting diode EDB2 may be provided.

[0060] At this time, as described above, Figure 2 , it is shown that all of the plurality of first light emitting diodes ED1 are defective, so that one second light emitting diode ED2 is provided in each of the plurality of sub-pixels SP. However, this is not limited thereto, and among the plurality of sub-pixels SP, the second light emitting diode ED2 may be provided only in some of the sub-pixels SP in which the first light emitting diode ED1 is defective. For example, when among the plurality of first light emitting diodes ED1, only the first blue light emitting diode EDB1 is defective so that it is not illuminated, the second light emitting diode ED2 may be provided only in the third sub-pixel SP3 among the plurality of sub-pixels SP. In this case, one pixel PX is configured by the first sub-pixel SP1 in which the first red light emitting diode EDR1 is provided, the second sub-pixel SP2 in which the first green light emitting diode EDG1 is provided, and the third sub-pixel SP3 in which the first blue light emitting diode EDB1 and the second blue light emitting diode EDB2 are provided.

[0061] Meanwhile, the second light emitting diode ED2 may have an inverted structure of the first light emitting diode ED1. That is, the first light emitting diode ED1 and the second light emitting diode ED2 are formed with the same configuration, but in cross section, the lamination order of the second light emitting diode ED2 may be opposite to that of the first light emitting diode ED1.

[0062] At the same time, even if Figure 2Although not shown, a driving transistor may also be provided in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the driving transistor may include a first driving transistor provided in the first sub-pixel SP1, a second driving transistor provided in the second sub-pixel SP2, and a third driving transistor provided in the third sub-pixel SP3.

[0063] At this time, when both the first light emitting diode ED1 and the second light emitting diode ED2 are disposed in one sub-pixel SP, the first light emitting diode ED1 and the second light emitting diode ED2 may be connected to the same driving transistor. Therefore, among the plurality of light emitting diodes ED, the light emitting diode ED disposed in the same sub-pixel SP may be driven by the same driving transistor.

[0064] In the following, we will refer to Figure 3 The first light emitting diode ED1 and the second light emitting diode ED2 are described in more detail.

[0065] Figure 3 is along Figure 2 The cross-sectional view taken along AA′. Figure 3 In each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to the exemplary embodiment of the present disclosure, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarizing layer 115, an adhesive layer AD, a first covering layer 117, a second covering layer 118, a protective layer OL, a driving transistor DT, a light emitting diode ED, a plurality of reflective electrodes RE, a plurality of connecting electrodes CE, a first conductive pattern PE1, a second conductive pattern PE2, a power line VSS, a light shielding layer LS, and an auxiliary electrode LE are provided.

[0066] First, the substrate 110 is a component for supporting various components included in the display device 100, and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be configured to include a polymer or plastic, or may be formed of a material having flexibility.

[0067] A light shielding layer LS is disposed in each of the plurality of sub-pixels SP on the substrate 110. The light shielding layer LS blocks light incident on an active layer ACT of a driving transistor DT to be described below from below the substrate 110. Light incident on the active layer ACT of the driving transistor DT is blocked by the light shielding layer LS to minimize leakage current.

[0068] A buffer layer 111 is provided on the substrate 110 and the light shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0069] A driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0070] The active layer ACT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0071] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer ACT from the gate electrode GE and may be configured of a single layer or double layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0072] A gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0073] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the gate electrode GE. Contact holes connected to the active layer ACT through the source electrode SE and the drain electrode DE thereof are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting components below the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and may be configured of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0074] A source electrode SE and a drain electrode DE are disposed on the second interlayer insulating layer 114 and are electrically connected to the active layer ACT. The source electrode SE and the drain electrode DE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0075] Meanwhile, in the present specification, the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are described, that is, multiple insulating layers are disposed between the gate electrode GE and the source electrode SE and the drain electrode DE. However, only one insulating layer may be disposed between the gate electrode GE and the source electrode SE and the drain electrode DE, but is not limited thereto.

[0076] In addition, as shown in the figure, when a plurality of insulating layers such as the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are provided between the gate electrode GE and the source electrode SE and the drain electrode DE, an electrode may be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode may form a capacitor having an additional configuration provided below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0077] An auxiliary electrode LE is provided on the gate insulating layer 112. The auxiliary electrode LE is an electrode that connects the light shielding layer LS under the buffer layer 111 to any one of the source electrode SE and the drain electrode DE on the second interlayer insulating layer 114. For example, the light shielding layer LS is electrically connected to any one of the source electrode SE or the drain electrode DE through the auxiliary electrode LE so as not to operate as a floating gate. Therefore, the fluctuation of the threshold voltage of the driving transistor DT caused by the floating light shielding layer LS can be minimized. Even though in the drawings, the light shielding layer LS is connected to the drain electrode DE, the light shielding layer LS may also be connected to the source electrode SE, but is not limited thereto.

[0078] A power line VSS is provided on the second interlayer insulating layer 114. The power line VSS is electrically connected to the light emitting element ED together with the driving transistor DT so that the light emitting element ED can emit light. The power line VSS may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0079] A first planarization layer 115 is disposed on the driving transistor DT and the power line VSS. The first planarization layer 115 may planarize an upper portion of the substrate 110 on which the driving transistor DT is disposed. The first planarization layer 115 may be configured by a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0080] A plurality of reflective electrodes RE spaced apart from each other are disposed on the first planarization layer 115. The plurality of reflective electrodes RE electrically connect the light emitting diode ED to the power line VSS and the driving transistor DT, and serve as a reflector that reflects light emitted from the light emitting diode ED to an upper portion of the light emitting diode ED. The plurality of reflective electrodes RE are formed of a conductive material having excellent reflective properties to reflect light emitted from the light emitting diode ED toward an upper portion of the light emitting diode ED.

[0081] Considering light reflection efficiency and resistance, the plurality of reflective electrodes RE may include various conductive layers. For example, the plurality of reflective electrodes RE may use silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, but is not limited thereto.

[0082] Reference Figure 2 , the plurality of reflective electrodes RE include a first reflective electrode RE1, a second reflective electrode RE2, a third reflective electrode RE3, and a fourth reflective electrode RE4 that are spaced apart from each other.

[0083] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 among the plurality of reflective electrodes RE may be formed to have a shape corresponding to each of the plurality of sub-pixels SP. For example, the first reflective electrode RE1 is disposed in a region corresponding to the first sub-pixel SP1, and the second reflective electrode RE2 is disposed in a region corresponding to the second sub-pixel SP2. In addition, the third reflective electrode RE3 may be disposed in a region corresponding to the third sub-pixel SP3.

[0084] The first reflective electrode RE1 is disposed to overlap the first and second red light emitting diodes EDR1 and EDR2 of the first sub-pixel SP1. The first reflective electrode RE1 may reflect light emitted from the first and second red light emitting diodes EDR1 and EDR2 above the first reflective electrode RE1.

[0085] The second reflective electrode RE2 is disposed to overlap the first and second green light emitting diodes EDG1 and EDG2 of the second sub-pixel SP2. The second reflective electrode RE2 may reflect light emitted from the first and second green light emitting diodes EDG1 and EDG2 above the second reflective electrode RE2.

[0086] The third reflective electrode RE3 is disposed to overlap the first and second blue light emitting diodes EDB1 and EDB2 of the third sub-pixel SP3. The third reflective electrode RE3 may reflect light emitted from the first and second blue light emitting diodes EDB1 and EDB2 above the third reflective electrode RE3.

[0087] Meanwhile, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may electrically connect the driving transistor DT and the plurality of light emitting diodes ED. The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 are connected to the source electrode SE or the drain electrode DE of the driving transistor DT through the contact hole CH2 formed in the first planarization layer 115, and may also be electrically connected to the plurality of light emitting diodes ED. For example, Figure 3As shown, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 are connected to the drain electrode DE of the driving transistor DT, but are not limited thereto.

[0088] First, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be electrically connected to the second electrodes 125 and the second semiconductor layer 123 of the plurality of first light emitting diodes ED1 through the fourth contact hole CH4 formed in the first area A1. Figure 3 The region not overlapping with the plurality of first light emitting diodes ED1 is shown, but is not limited thereto.

[0089] In addition, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be electrically connected to the second electrodes 135 and the second semiconductor layer 133 of the plurality of second light emitting diodes ED2 in the second area A2. Figure 3 As shown, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be electrically connected to the second electrode 135 of the plurality of second light emitting diodes ED2 and the second semiconductor layer 133 in the region overlapping with the plurality of second light emitting diodes ED2. For example, in the second region A2, the top surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be exposed through the adhesive layer AD. The second electrode 135 in the plurality of second light emitting diodes ED2 may be electrically connected to the reflective electrode RE disposed below the plurality of second light emitting diodes ED2.

[0090] Next, a fourth reflective electrode RE4 among the plurality of reflective electrodes RE is disposed in a region adjacent to the plurality of sub-pixels SP to reflect light emitted from the plurality of sub-pixels SP above the fourth reflective electrode RE4. For example, the fourth reflective electrode RE4 may be disposed adjacent to the third sub-pixel SP3, but is not limited thereto. Figure 2 In the embodiment, the fourth reflective electrode RE4 is disposed not to overlap with the plurality of light emitting diodes ED, but is not limited thereto.

[0091] The fourth reflective electrode RE4 electrically connects the power line VSS and the plurality of light emitting diodes ED. The fourth reflective electrode RE4 may be connected to the power line VSS through a first contact hole CH1 formed in the first planarization layer 115. In addition, the fourth reflective electrode RE4 is electrically connected to the first electrodes 124 and the first semiconductor layer 121 of the plurality of first light emitting diodes ED1 and the first electrodes 134 and the first semiconductor layer 131 of the plurality of second light emitting diodes ED2 through a first connection electrode CE1 to be described below.

[0092] In the second area A2, the second conductive pattern PE2 is disposed on the plurality of reflective electrodes RE. For example, among the first, second, and third reflective electrodes RE1, RE2, and RE3 among the plurality of reflective electrodes RE, the second conductive pattern PE2 may be disposed on the reflective electrode RE on which the plurality of second light emitting diodes ED2 are disposed.

[0093] The second conductive pattern PE2 is disposed on the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 exposed by the first cover layer 117 and the adhesive layer AD. Therefore, the second conductive pattern PE2 can be electrically connected to the top surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 disposed thereunder. At the same time, the second conductive pattern PE2 extends from the top surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 to cover the side surface of the first cover layer 117 surrounding the opening area of ​​the first cover layer 117.

[0094] The second conductive pattern PE2 may be disposed in the second area A2 of the plurality of sub-pixels SP. Therefore, the second conductive pattern PE2 may be disposed to overlap with the plurality of second light emitting diodes ED2 among the plurality of light emitting diodes ED. At this time, the bottom surface of the second conductive pattern PE2 contacts the reflective electrode RE, and the top surface of the second conductive pattern PE2 may contact the second electrode 135 of the plurality of second light emitting diodes ED2. Therefore, the second conductive pattern PE2 is connected to the second electrode 135 of the plurality of second light emitting diodes ED2 and the second semiconductor layer 133 to electrically connect the plurality of second light emitting diodes ED2 to the driving transistor DT.

[0095] The second conductive pattern PE2 may be formed of a conductive material. In addition, the second conductive pattern PE2 may be formed of a reflective material. For example, the second conductive pattern PE2 is formed of silver (Ag) or a silver (Ag) alloy, but is not limited thereto. In addition, the second conductive pattern PE2 may be formed of any one of silver (Ag) paste, aluminum (Al) paste, gold (Au) paste, and copper (Cu) paste, and silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof is used, but is not limited thereto.

[0096] An adhesive layer AD is disposed on the plurality of reflective electrodes RE. The adhesive layer AD is disposed in the first area A1 of the plurality of sub-pixels SP. Therefore, the adhesive layer AD can fix the plurality of first light emitting diodes ED1 among the plurality of light emitting diodes ED to the substrate 110.

[0097] In contrast, the adhesive layer AD is not disposed in the region overlapping with the plurality of second light emitting diodes ED2. For example, in the second region A2, the adhesive layer AD exposes the top surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. Figure 3 , it is shown that the adhesive layer AD is not provided in the entire second area A2, but it is not limited thereto. In addition, the adhesive layer AD may not be provided only in the area overlapping the second conductive pattern PE2 and the plurality of second light emitting diodes ED2.

[0098] The adhesive layer AD may planarize the upper portions of the plurality of reflective electrodes RE. For example, the adhesive layer AD covers the regions between the plurality of reflective electrodes RE spaced apart from each other to planarize the upper portions of the plurality of reflective electrodes RE, but is not limited thereto.

[0099] The adhesive layer AD may be selected from any one of an adhesive polymer, an epoxy resist, a UV resin, a polyimide, an acrylate, a polyurethane, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0100] Meanwhile, in the adhesive layer AD, a third contact hole CH3 enabling the first connection electrode CE1 to be connected to the fourth reflective electrode RE4 and a fourth contact hole CH4 enabling the second connection electrode CE2 to be connected to the first, second and third reflective electrodes RE1, RE2 and RE3 are formed.

[0101] On the adhesive layer AD or the plurality of reflective electrodes RE, a plurality of light emitting electrodes ED are provided in each of the plurality of sub-pixels SP. The plurality of light emitting diodes ED are elements that emit light by current, and may include light emitting diodes ED that emit red light, green light, and blue light, and various colors of light including white light are realized by their combination. For example, the plurality of light emitting diodes ED may be light emitting diodes (LEDs) or micro LEDs, but are not limited thereto.

[0102] Reference Figure 2 and Figure 3 A first light emitting diode ED1 is disposed on the adhesive layer AD. The first light emitting diode ED1 is disposed in the first area A1 of the plurality of sub-pixels SP.

[0103] Reference Figure 3 Each of the first light emitting diodes ED1 includes a first semiconductor layer 121 , a light emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 , and an encapsulation layer 126 .

[0104] A first semiconductor layer 121 of the first light emitting diode ED1 is disposed on the adhesive layer AD, and a second semiconductor layer 123 of the first light emitting diode ED1 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers doped with n-type impurities and p-type impurities into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In addition, the p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0105] The width of the second semiconductor layer 123 may be smaller than that of the first semiconductor layer 121. Therefore, the second semiconductor layer 123 of the first light emitting diode ED1 may be disposed to protrude upward from the top surface of the first semiconductor layer 121.

[0106] The light emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The light emitting layer 122 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0107] The width of the light emitting layer 122 may be smaller than the width of the first semiconductor layer 121. Therefore, the light emitting layer 122 of the first light emitting diode ED1 may be disposed to protrude upward from the top surface of the first semiconductor layer 121.

[0108] The first electrodes 124 of two or more first light emitting diodes ED1 are disposed on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the power line VSS to the first semiconductor layer 121. The first electrode 124 may be in contact with the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. For example, the first electrode 124 may be disposed adjacent to both ends of the top surface of the first semiconductor layer 121 having a circular planar shape. The planar shape of the first electrode 124 may be circular and / or elliptical, but is not limited thereto. The first electrode 124 may be configured of a conductive material, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0109] A second electrode 125 of the first light emitting diode ED1 is disposed on the second semiconductor layer 123. The second electrode 125 may be in contact with the second semiconductor layer 123. The planar shape of the second electrode 125 may be circular and / or elliptical, but is not limited thereto. The second electrode 125 is an electrode that electrically connects the driving transistor DT to the second semiconductor layer 123. The second electrode 125 may be configured of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0110] Next, an encapsulation layer 126 is provided to surround the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation layer 126 is formed of an insulating material to protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. In the encapsulation layer 126, a contact hole is formed to expose the first electrode 124 and the second electrode 125 to electrically connect the first connection electrode CE1 and the second connection layer CE2 to the first electrode 124 and the second electrode 125.

[0111] Reference Figure 2 and Figure 3 , a plurality of second light emitting diodes ED2 are disposed on the plurality of reflective electrodes RE. The plurality of second light emitting diodes ED2 are disposed in at least one or more sub-pixels SP among the plurality of sub-pixels SP. For example, the plurality of second light emitting diodes ED2 may be disposed on at least one or more reflective electrodes RE among the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3.

[0112] Refer to Figure 2 and Figure 3 The second light emitting diode ED2 includes a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode 134 , a second electrode 135 and an encapsulation layer 136 .

[0113] A second semiconductor layer 133 of the second light emitting diode ED2 is disposed on the plurality of reflective electrodes RE and the second conductive pattern PE2, and a first semiconductor layer 131 of the second light emitting diode ED2 is disposed on the second semiconductor layer 133. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with n-type impurities and p-type impurities into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In addition, the p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0114] Meanwhile, the width of the second semiconductor layer 133 may be smaller than that of the first semiconductor layer 131. Therefore, the second semiconductor layer 133 of the second light emitting diode ED2 may be disposed to protrude downward from the bottom surface of the first semiconductor layer 131.

[0115] A light emitting layer 132 of the second light emitting diode ED2 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 is supplied with holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133 to emit light. The light emitting layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), etc., but is not limited thereto.

[0116] Meanwhile, the width of the light emitting layer 132 may be smaller than that of the first semiconductor layer 131. Therefore, the light emitting layer 132 of the second light emitting diode ED2 may be disposed to protrude downward from the bottom surface of the first semiconductor layer 131.

[0117] The first electrodes 134 of two or more second light emitting diodes ED2 are disposed below the first semiconductor layer 131. The first electrode 134 is an electrode that electrically connects the power line VSS to the first semiconductor layer 131. The first electrode 134 may be in contact with the first semiconductor layer 131 exposed from the light emitting layer 132 and the second semiconductor layer 133. For example, the first electrode 134 may be disposed adjacent to both ends of the bottom surface of the first semiconductor layer 131 having a circular planar shape. The planar shape of the first electrode 134 may be circular and / or elliptical, but is not limited thereto. The first electrode 134 may be configured of a conductive material, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0118] A second electrode 135 of the second light emitting diode ED2 is disposed below the second semiconductor layer 133. The second electrode 135 may be in contact with the second semiconductor layer 133. The planar shape of the second electrode 135 may be circular and / or elliptical, but is not limited thereto. The second electrode 135 is an electrode that electrically connects the driving transistor DT to the second semiconductor layer 133. The second electrode 135 may be configured of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0119] Next, an encapsulation layer 136 surrounding the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135 is provided. The encapsulation layer 136 is formed of an insulating material to protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. In the encapsulation layer 136, contact holes are formed to expose the first electrode 134 and the second electrode 135 to electrically connect the first conductive pattern PE1 and the second conductive pattern PE2 to the first electrode 134 and the second electrode 135. Meanwhile, the first red light emitting diode EDR1, the first green light emitting diode EDG1, and the first blue light emitting diode EDB1 have different shapes. In addition, the second red light emitting diode EDR2, the second green light emitting diode EDG2, and the second blue light emitting diode EDB2 have different shapes. Each of the plurality of first light emitting diodes ED1 includes the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, the second electrode 125, and the encapsulation layer 126, but the shapes of some configurations may be different from each other. In addition, each of the second light emitting diodes ED2 includes a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode 134 , a second electrode 135 , and an encapsulation layer 136 , but shapes of some configurations may be different from each other.

[0120] For example, the planar shape of the first semiconductor layer 121 of the first red light emitting diode EDR1 and the planar shape of the first semiconductor layer 131 of the second red light emitting diode EDR2 may both be circular. The planar shape of the first semiconductor layer 121 of the first green light emitting diode EDG1 and the planar shape of the first semiconductor layer 131 of the second green light emitting diode EDG2 may both be elliptical. The planar shape of the first semiconductor layer 121 of the first blue light emitting diode EDB1 and the planar shape of the first semiconductor layer 131 of the second blue light emitting diode EDB2 may both be elliptical. For example, the ratio of the major axis to the minor axis of the first blue light emitting diode EDB1 is different from the ratio of the major axis to the minor axis of the first green light emitting diode EDG1. In addition, the ratio of the major axis to the minor axis of the second blue light emitting diode EDB2 is different from the ratio of the major axis to the minor axis of the second green light emitting diode EDG2, but is not limited thereto.

[0121] In addition, the first red light emitting diode EDR1 and the second red light emitting diode EDR2 are formed with the same configuration, but the lamination order of the second red light emitting diode EDR2 is opposite to that of the first red light emitting diode EDR1. The first green light emitting diode EDG1 and the second green light emitting diode EDG2 are formed with the same configuration, but the lamination order of the second green light emitting diode EDG2 is opposite to that of the first green light emitting diode EDG1. The first blue light emitting diode EDB1 and the second blue light emitting diode EDB2 are formed with the same configuration, but the lamination order of the second blue light emitting diode EDB2 is opposite to that of the first blue light emitting diode EDB1.

[0122] A first cover layer 117 is disposed on the adhesive layer AD and the plurality of reflective electrodes RE. The first cover layer 117 covers the top surface of the adhesive layer AD and the top surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 exposed from the adhesive layer AD, and flattens the upper portions of the adhesive layer AD and the plurality of reflective electrodes RE. The first cover layer 117 may be configured by a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0123] In the first area A1, the first cover layer 117 may be provided to surround the side surfaces of the plurality of first light emitting diodes ED1. For example, the first cover layer 117 may be provided to cover the lower side surface of the first semiconductor layer 121 extending from the bottom surface of the first semiconductor layer 121 of the plurality of first light emitting diodes ED1 on the adhesive layer AD. Therefore, the first cover layer 117 overlaps a portion of the side surfaces of the plurality of first light emitting diodes ED1 to fix and protect the plurality of first light emitting diodes ED1.

[0124] Specifically, in the first region A1, the first cover layer 117 may surround at least a portion of a side surface of the first semiconductor layer 121 disposed under the first electrodes 124 of the plurality of first light emitting diodes ED1. Therefore, the thickness of the first cover layer 117 may be less than the thickness of the first semiconductor layer 121. For example, the top surface of the first cover layer 117 may be disposed under the light emitting layer 122.

[0125] In the second area A2, the first cover layer 117 may be provided to surround at least a portion of the side surface of the plurality of second light emitting diodes ED2. For example, the first cover layer 117 may include an opening area surrounding a portion of the plurality of second light emitting diodes ED2. Figure 3 In the opening region of the first cover layer 117, a portion of the plurality of second light emitting diodes ED2 may be disposed, and another portion of the plurality of second light emitting diodes ED2 may be disposed on the first cover layer 117. For example, in the opening region, the second electrode 135 of the plurality of second light emitting diodes ED2 protruding downward from the first semiconductor layer 131 of the plurality of second light emitting diodes ED2, the second semiconductor layer 133, and the light emitting layer 132 may be disposed. Therefore, the first cover layer 117 may surround the side surface of the second semiconductor layer 133 and the side surface of the light emitting layer 132 extending from the top surface of the second semiconductor layer 133. Meanwhile, when the first semiconductor layer 131 is provided with a stepped structure and the first semiconductor layer 131 protrudes downward from the first electrode 134 in a region overlapping with the light emitting layer 132, the first cover layer 117 may surround the side surface of the first semiconductor layer 131 disposed below the first electrode 134.

[0126] Meanwhile, the width of the opening region of the first cover layer 117 is smaller than the width of the first semiconductor layer 131 of the plurality of second light emitting diodes ED2, and is larger than the widths of the second semiconductor layer 133 and the light emitting layer 132 of the plurality of second light emitting diodes ED2. Therefore, in the opening region, the side surfaces of the second semiconductor layer 133 and the light emitting layer 132 of the plurality of second light emitting diodes ED2 may be disposed to be spaced apart from the side surface of the first cover layer 117.

[0127] Meanwhile, the second electrodes 135 of the plurality of second light emitting diodes ED2 may be electrically connected to the second conductive pattern PE2 in the opening region of the first cover layer 117. That is, the second electrodes 135 of the plurality of second light emitting diodes ED2 may contact the second conductive pattern PE2 disposed therebelow. In addition, the first connection electrode CE1 and the first conductive pattern PE1 are disposed on the first cover layer 117.

[0128] The first connection electrode CE1 is an electrode provided in each of the plurality of sub-pixels SP to electrically connect the light emitting diode ED to the power line VSS. The first connection electrode CE1 may be connected to the fourth reflective electrode RE4 through the third contact hole CH3 formed in the first cover layer 117 and the adhesive layer AD. Therefore, the first connection electrode CE1 may be electrically connected to the power line VSS through the fourth reflective electrode RE4. In addition, the first connection electrode CE1 may be electrically connected to the first electrode 124 of each of the plurality of first light emitting diodes ED1 in the first area A1 of the plurality of sub-pixels SP. In addition, the first connection electrode CE1 may be electrically connected to the first electrode 134 of each of the plurality of second light emitting diodes ED2 in the second area A2 of the plurality of sub-pixels SP.

[0129] Meanwhile, one first link electrode CE1 is disposed in all of the plurality of sub-pixels SP so that the first link electrodes CE1 disposed in the plurality of sub-pixels SP are connected to each other, but is not limited thereto.

[0130] First, the first connection electrode CE1 is disposed on the first electrodes 124 of the plurality of first light emitting diodes ED1 among the plurality of light emitting diodes ED in the first area A1 to directly contact the first electrodes 124 of the plurality of first light emitting diodes ED1. Therefore, the first connection electrode CE1 can electrically connect the power line VSS to the first electrodes 124 of the plurality of first light emitting diodes ED1 and the first semiconductor layer 121.

[0131] Furthermore, when the first cover layer 117 is disposed under the first electrodes 124 of the plurality of first light emitting diodes ED1 , the first connection electrode CE1 may be disposed to surround a portion of a side surface of the plurality of first light emitting diodes ED1 exposed between the first electrodes 124 of the plurality of first light emitting diodes ED1 and the first cover layer 117 .

[0132] Reference Figure 3 The first connection electrode CE1 is disposed under the first electrodes 134 of the plurality of second light emitting diodes ED2 among the plurality of light emitting diodes ED in the second area A2 to be electrically connected to the first electrodes 134 of the plurality of second light emitting diodes ED2.

[0133] Meanwhile, the first link electrode CE1 is connected to the first electrodes 134 of the plurality of second light emitting diodes ED2 through the first conductive pattern PE1 disposed on the first link electrode CE1.

[0134] The first conductive pattern PE1 is disposed between the first connection electrode CE1 in the second area A2 and the first electrodes 134 of the plurality of second light emitting diodes ED2. The first conductive pattern PE1 is disposed to overlap with the first electrodes 134 of the plurality of second light emitting diodes ED2, and, for example, the first conductive pattern PE1 may be disposed to surround the opening region of the first cover layer 117. Therefore, the bottom surface of the first conductive pattern PE1 may contact the first connection electrode CE1 in a region adjacent to the opening region of the first cover layer 117. In addition, the top surface of the first conductive pattern PE1 may contact the first electrodes 134 of the plurality of second light emitting diodes ED2. Therefore, the first conductive pattern PE1 electrically connects the first electrodes 134 of the plurality of second light emitting diodes ED2 with the first connection electrode CE1 in a region adjacent to the opening region, and may be electrically connected to the power line VSS through the first connection electrode CE1 and the fourth reflective electrode RE4.

[0135] The first conductive pattern PE1 may be formed of a conductive material. In addition, the first conductive pattern PE1 may be formed of a material having reflectivity. For example, the first conductive pattern PE1 is formed of silver (Ag) or a silver (Ag) alloy, but is not limited thereto. In addition, the first conductive pattern PE1 may be formed of any one of silver (Ag) paste, aluminum (Al) paste, gold (Au) paste, and copper (Cu) paste, and silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof is used, but is not limited thereto.

[0136] In addition, the second conductive pattern PE2 and the first conductive pattern PE1 may be formed of the same material, but are not limited thereto.

[0137] A second cover layer 118 is disposed on the first connection electrode CE1 and the plurality of light emitting diodes ED. The second cover layer 118 may planarize the upper portion of the substrate 110 on which the plurality of light emitting diodes ED are disposed. The first cover layer 117 and the second cover layer 118 may be configured by a single layer or a double layer and may be formed of, for example, a photoresist or an acrylic-based organic material, but are not limited thereto.

[0138] The second cover layer 118 is disposed over the first cover layer 117 to surround a portion of side surfaces of the plurality of first light emitting diodes ED1 and a portion of side surfaces of the plurality of second light emitting diodes ED2 .

[0139] First, the second cover layer 118 covers the side surfaces of the plurality of first light emitting diodes ED1 in the first area A1 to fix the plurality of first light emitting diodes ED1 to the substrate 110 together with the adhesive layer AD. The top surface of the second cover layer 118 is set to be at least higher than the light emitting layer 122 of the plurality of first light emitting diodes ED1 and equal to or lower than the top surface of the second semiconductor layer 123 of the plurality of first light emitting diodes ED1. For example, the top surface of the second cover layer 118 corresponding to the plurality of first light emitting diodes ED1 may be set between the top surface of the light emitting layer 122 and the top surface of the second semiconductor layer 123 of the plurality of first light emitting diodes ED1. Alternatively, the top surface of the second cover layer 118 corresponding to the plurality of first light emitting diodes ED1 may be set on the same plane as the top surface of the second semiconductor layer 123. Therefore, the second cover layer 118 may surround the side surfaces of the light emitting layer 122 and the second semiconductor layer 123 of the plurality of first light emitting diodes ED1 in the first area A1.

[0140] In the first area A1, the second cover layer 118 may be disposed to surround at least a portion of the side surface of the plurality of second light emitting diodes ED2. For example, the second cover layer 118 may include an opening area corresponding to the second area A2. At this time, the width of the opening area of ​​the second cover layer 118 may be greater than the width of the opening area of ​​the first cover layer 117 and the width of the first semiconductor layer 131 of the plurality of second light emitting diodes ED2. Therefore, in the second area A2, the second cover layer 118 may surround the first semiconductor layer 131 of the plurality of second light emitting diodes ED2 disposed above the first cover layer 117. At the same time, in the second area A2, the side surface of the second cover layer 118 may be disposed to be spaced apart from the side surface of the first semiconductor layer 131 of the plurality of second light emitting diodes ED2, but is not limited thereto.

[0141] A second connection electrode CE2 is disposed on the second cover layer 118. The second connection electrode CE2 is an electrode for electrically connecting a plurality of first light emitting diodes ED1 among a plurality of light emitting diodes ED and the driving transistor DT. The second connection electrode CE2 is connected to the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 through the second cover layer 118, the first cover layer 117, and the fourth contact hole CH4 formed in the adhesive layer AD. Therefore, the second connection electrode CE2 is electrically connected to any one of the source electrode SE and the drain electrode DE of the driving transistor DT through the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The second connection electrode CE2 may be disposed separately in each of the plurality of sub-pixels SP. The second connection electrode CE2 connects the driving transistor DT and the plurality of first light emitting diodes ED1 through the plurality of reflective electrodes RE disposed in the plurality of sub-pixels SP, but is not limited thereto.

[0142] The second connection electrode CE2 may be disposed only in the first region A1 of the plurality of sub-pixels SP. In addition, the second connection electrode CE2 may be connected to the second electrode 125 of each of the plurality of first light emitting diodes ED exposed by the second cover layer 118 in the first region A1. Therefore, the second connection electrode CE2 may electrically connect the driving transistor DT to the second electrodes 125 of the plurality of light emitting diodes ED and the second semiconductor layer 123.

[0143] Meanwhile, the second connection electrode CE2 may be disposed so as not to overlap with the plurality of second light emitting diodes ED2 disposed in the second area A2. Figure 3 2 shows that the second connection electrode CE2 is not provided in the entire surface of the second area A2, but the second connection electrode CE2 may not be provided only in an area overlapping with the plurality of second light emitting diodes ED2.

[0144] A bank BB is provided on the second connection electrode CE2 and the second cover layer 118. The bank BB may cover the top surface of the second cover layer 118 exposed from the second connection electrode CE2. In addition, the bank BB is provided to be spaced apart from the plurality of light emitting diodes ED at a predetermined interval and at least partially overlap the plurality of reflective electrodes RE. For example, the bank BB may cover the second cover layer 118 and a portion of the second connection electrode CE2 formed in the contact hole of the second cover layer 118.

[0145] The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and may be formed of, for example, a black resin, but is not limited thereto.

[0146] The dam BB may include an opening area corresponding to the second area A2. The opening area of ​​the dam BB is arranged to overlap with the opening area of ​​the second cover layer 118, and the width of the opening area of ​​the dam BB may be greater than the width of the opening area of ​​the first cover layer 117 and the width of the first semiconductor layer 131 of the plurality of second light emitting diodes ED2. Therefore, the dam BB may surround the first semiconductor layer 131 of the plurality of second light emitting diodes ED2 in the second area A2. In addition, in the second area A2, the side surface of the dam BB may be arranged on the same plane as the side surface of the second cover layer 118, but is not limited thereto.

[0147] A second planarization layer 119 is disposed on the first and second connection electrodes CE1 and CE2 and the bank BB. The second planarization layer 119 is a layer for protecting components below the second planarization layer 119 and may be configured of a single layer or double layer of transparent epoxy, silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0148] The second planarization layer 119 may be disposed to overlap at least a portion of the plurality of light emitting diodes ED. For example, the second planarization layer 119 is disposed in the first area A1 to overlap only the plurality of first light emitting diodes ED1 among the plurality of light emitting diodes ED.

[0149] Meanwhile, the second planarization layer 119 may include an opening region corresponding to the second area A2. The opening region of the second planarization layer 119 is disposed to overlap with the opening region of the second cover layer 118 and the opening region of the dam BB. The width of the opening region of the second planarization layer 119 may be greater than the width of the opening region of the first cover layer 117 and the width of the first semiconductor layer 131 of the plurality of second light emitting diodes ED2. Therefore, in the opening region of the second planarization layer 119, the side surface of the second planarization layer 119 may be disposed to be spaced apart from the side surface of the plurality of second light emitting diodes ED2, but is not limited thereto.

[0150] Meanwhile, in the second area A2, a protective layer OL surrounding the plurality of second light emitting diodes ED2 may be provided. The protective layer OL fills the opening area of ​​the first cover layer 117, the opening area of ​​the second cover layer 118, the opening area of ​​the dam BB, and the opening area of ​​the second planarization layer 119, and surrounds the side surfaces and top surfaces of the plurality of second light emitting diodes ED2. Therefore, the protective layer OL may fix and protect the plurality of second light emitting diodes ED2.

[0151] The protection layer OL may be formed of a transparent material having a refractive index similar to that of the second planarization layer 119 and may be formed of a UV curable material. For example, the protection layer OL may be formed of photoresist or an acrylic-based organic material or a transparent epoxy resin having a transmittance of 99%, but is not limited thereto.

[0152] Figure 4 is an enlarged plan view of a state before repairing a display device according to an exemplary embodiment of the present disclosure. Figure 5 is along Figure 4 Cross-sectional view taken along BB′.

[0153] Reference Figure 4 Each sub-pixel SP includes a plurality of first light emitting diodes ED1 disposed in the first area A1. The pixel PX is configured by a first sub-pixel SP1 in which a first red light emitting diode EDR1 is disposed, a second sub-pixel SP2 in which a first green light emitting diode EDG1 is disposed, and a third sub-pixel SP3 in which a first blue light emitting diode EDB1 is disposed.

[0154] In the second area A2 of the sub-pixel SP, top surfaces of the first reflective electrode RE1 , the second reflective electrode RE2 , and the third reflective electrode RE3 are exposed through the adhesive layer AD.

[0155] A first cover layer 117 is disposed on the adhesive layer AD and the plurality of reflective electrodes RE. The first cover layer 117 covers the entire second area A2 and covers top surfaces of the first, second, and third reflective electrodes RE1, RE2, and RE3 exposed through the adhesive layer AD.

[0156] The first connection electrode CE1 is disposed on the first cover layer 117 , and the second cover layer 118 , the bank BB, and the second planarization layer 119 are sequentially disposed on the first connection electrode CE1 .

[0157] Thereafter, a lighting test for the plurality of first light emitting diodes ED1 disposed in the first area A1 of the plurality of sub-pixels SP may be performed.

[0158] In the following, reference will be made to 6A to 6F Describe the repair process.

[0159] FIG. 6A to FIG. 6G is a process diagram for explaining a forming process of a display device according to an exemplary embodiment of the present disclosure.

[0160] Reference Fig. 6A In the second area A2 of the plurality of sub-pixels SP, the first cover layer 117 covers the top surface of the reflective electrode RE, and the first connection electrode CE1 , the second cover layer 118 , the bank BB and the second planarization layer 119 are sequentially disposed on the first cover layer 117 .

[0161] Thereafter, the plurality of sub-pixels SP disposed in the first area A1 may be processed.

[0162] Illumination test of the first light emitting diode ED1.

[0163] Next, the defective sub-pixel SP can be repaired. Figure 6B , in the second area A2 of the defective sub-pixel SP, the second cover layer 118, the bank BB, and the second planarization layer 119 disposed on the first connection electrode CE1 are removed. For example, the second cover layer 118, the bank BB, and the second planarization layer 119 disposed in the second area A2 are removed by laser processing, and a portion of the top surface of the first connection electrode CE1 disposed under the second cover layer 118 may be exposed. At this time, the laser processing may be performed on a first width W1 that is greater than a width of the first semiconductor layer 131 of the plurality of second light emitting diodes ED2 to be disposed in the second area A2, and the top surface of the first connection electrode CE1 corresponding to the first width W1 is exposed.

[0164] Next, refer to Figure 6C, the exposed portion of the first connection electrode CE1 and a portion of the first cover layer 117 disposed under the first connection electrode CE1 are removed. For example, the first connection electrode CE1 disposed in the second area A2 and a portion of the first cover layer 117 are removed by laser processing. Therefore, a portion of the top surface of the reflective electrode RE disposed under the first cover layer 117 may be exposed. At this time, the laser processing may be performed on a second width W2 that is smaller than the width of the first semiconductor layer 131 of the plurality of second light emitting diodes ED2 to be disposed in the second area A2 and greater than the width of the second semiconductor layer 133 of the plurality of second light emitting diodes ED2 and the width of the light emitting layer 132. The top surface of the reflective electrode RE corresponding to the second width W2 is exposed. Therefore, a step region is formed between the first cover layer 117 and the second cover layer 118, the dam BB, and the second planarization layer 119, and the top surface of the first connection electrode CE1 disposed on the first cover layer 117 is exposed in the step region.

[0165] Next, refer to Fig.6D , liquid metal ink Ink is applied on the exposed reflective electrode RE to correspond to the second width W2. The liquid metal ink Ink is arranged to cover the top surface of the exposed reflective electrode RE and the top surface of the first connection electrode CE1. The liquid metal ink Ink may be a solution in which metal nanoparticles are dispersed. The liquid metal ink Ink may be one of metal organic ion ink, metal nanoparticle ink, and metal nanoparticle paste. When the liquid metal ink Ink is a silver paste, the silver (Ag) nanoparticles may be uniformly dispersed in an organic solvent.

[0166] Next, refer to Fig. 6E , a second light emitting diode ED2 as a repair light emitting diode is disposed on the liquid metal ink Ink in the step region. At this time, the second light emitting diode ED2 is a light emitting diode ED configured to emit light having the same color as the first light emitting diode ED1 disposed in the defective sub-pixel, and has a structure laminated in the reverse order of the first light emitting diode ED1.

[0167] The second semiconductor layer 133 of the second light emitting diode ED2 has a smaller area than the first semiconductor layer 131, and is disposed below the first semiconductor layer 131. Therefore, the second semiconductor layer 133 of the second light emitting diode ED2 is disposed in the opening region of the first cover layer 117, and the first semiconductor layer 131 of the second light emitting diode ED2 is disposed in the first cover layer 117 surrounding the opening region. At this time, the second electrode 135 of the second light emitting diode ED2 contacts the liquid metal ink Ink disposed on the reflective electrode RE, and the first electrode 134 of the second light emitting diode ED2 contacts the liquid metal ink Ink disposed on the first connection electrode CE1.

[0168] Next, a sintering process is performed on the liquid metal ink Ink. During the sintering process, the solvent included in the liquid metal ink Ink is volatilized. Therefore, after the sintering process, the first conductive pattern PE1 disposed on the first connection electrode CE1 and the second conductive pattern PE2 disposed on the reflective electrode RE are formed. Fig. 6F As shown, the first conductive pattern PE1 electrically connects the first electrode 134 of the second light emitting diode ED2 and the first connection electrode CE1, and the second conductive pattern PE2 electrically connects the second electrode 135 of the second light emitting diode ED2 and the reflective electrode RE.

[0169] Next, refer to Figure 6G , a protective layer OL is applied on the second light emitting diode ED2. The protective layer OL penetrates between the side surface of the second light emitting diode ED2 and the side surface of the first cover layer 117, the side surface of the second cover layer 118, the side surface of the bank BB, and the side surface of the second planarization layer 119 to surround the side surface of the second light emitting diode ED2. The protective layer OL is formed of a UV curable material. Therefore, UV treatment is performed on the protective layer OL to fix and protect the second light emitting diode ED2.

[0170] Generally, among the multiple sub-pixels arranged on the substrate, defective sub-pixels that do not emit light normally may be generated. For example, there may be defective sub-pixels, in which the light-emitting diode itself is defective, and the electrical connection between the light-emitting diode and the transistor and the power line is defective. At this time, the defective sub-pixel is not lit, or even if the defective sub-pixel emits very weak light, it is difficult to use the defective sub-pixel as a normal sub-pixel. Therefore, in each of the multiple sub-pixels, two light-emitting diodes emitting the same color are arranged to be used. For example, when the multiple sub-pixels are configured by red sub-pixels, green sub-pixels and blue sub-pixels, two red light-emitting diodes, two green light-emitting diodes and two blue light-emitting diodes are arranged on the substrate. Therefore, when any one of the two light-emitting diodes is defective, another normal light-emitting diode emitting light of the same color as the defective light-emitting diode is driven instead of the defective light-emitting diode. Therefore, since it is always necessary to place light-emitting diodes twice as many as basic light-emitting diodes in the display device, the manufacturing cost of the display device increases. Furthermore, the number of light emitting diodes provided on the display panel increases twice, so that processing cost and process may be additionally required to perform a lighting test on all the light emitting diodes.

[0171] In the display device 100 according to the exemplary embodiment of the present disclosure, after the illumination test, the second light emitting diode ED2 emitting light having the same color as the first light emitting diode ED1 is transmitted only to the sub-pixel SP where the defective first light emitting diode ED1 occurs. Therefore, repair is not performed on the sub-pixel SP provided with the normal first light emitting diode ED1, and only when a defect occurs, the second light emitting diode ED2 as the repair light emitting element is transmitted, so that the number of light emitting diodes ED provided on the display device 100 can be reduced. Therefore, the processing cost and the processing process for performing the illumination test on the light emitting diode ED can be reduced. Therefore, the manufacturing cost of the display device 100 can be saved.

[0172] In addition, in the display device 100 according to the exemplary embodiment of the present disclosure, laser processing is performed after the illumination test to locally perform repair. During the repair process, in the second area A2 of the sub-pixel SP requested for repair, the second cover layer 118, the bank BB, and the second planarization layer 119 are opened to expose the first connection electrode CE1, and a partial area of ​​the first cover layer 117 is opened to expose the reflective electrode RE. Next, liquid metal ink Ink is applied on the first connection electrode CE1 and the reflective electrode RE to perform repair using only the liquid metal ink Ink without using a separate repair line.

[0173] Furthermore, in the display device 100 according to the exemplary embodiment of the present disclosure, a stepped region corresponding to the shape of the second light emitting diode ED2 is formed in the first cover layer 117, the second cover layer 118, the bank BB, and the second planarization layer 119. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the second light emitting diode ED2 can be stably fixed to the second area A2 during the repair process.

[0174] In addition, in the display device 100 according to the exemplary embodiment of the present disclosure, the first conductive pattern PE1 and the second conductive pattern PE2 are formed in the stepped region to suppress a short circuit between the first conductive pattern PE1 and the second conductive pattern PE2. That is, the first conductive pattern PE1 is disposed on the first connection electrode CE1 and the first cover layer 117 disposed on the second conductive pattern PE2 to suppress a short circuit between the first conductive pattern PE1 and the second conductive pattern PE2.

[0175] In addition, in the display device 100 according to the exemplary embodiment of the present disclosure, the first conductive pattern PE1 and the second conductive pattern PE2 disposed in the step region are in contact with the first electrode 134 and the second electrode 135 of the second light-emitting diode ED2, and the fixing strength of the second light-emitting diode ED2 is improved. For example, when the first conductive pattern PE1 and the second conductive pattern PE2 are formed by sintering the liquid metal ink Ink, the adhesive force between the second light-emitting diode ED2 and the reflective electrode RE and the first connection electrode CE1 is improved by the previous sintering of the liquid metal ink Ink. Therefore, in a state where the second light-emitting diode ED2 is stably fixed, the liquid metal ink Ink is sintered, so that the electrical connection of the second light-emitting diode ED2 with the reflective electrode RE and the first connection electrode CE1 becomes stable. In addition, the fixing strength of the second light-emitting diode ED2 with the reflective electrode RE and the first connection electrode CE1 can be improved.

[0176] In addition, in the display device 100 according to the exemplary embodiment of the present disclosure, the second conductive pattern PE2 extends from the reflective electrode RE to cover the side surface of the first cover layer 117 surrounding the opening area. Therefore, the second conductive pattern PE2 serves as a lateral surface reflector. When the light emitting layer 132 of the plurality of second light emitting diodes ED2 is disposed in the opening area of ​​the first cover layer 117, light emitted from the plurality of second light emitting diodes ED2 is reflected from the second conductive pattern PE2 to travel upward. Therefore, the problem of reduced light emitting efficiency of the display device 100 can be suppressed, and the brightness can be improved.

[0177] Figure 7 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 8 is along Figure 7 The cross-sectional view taken at C-C'. Figure 7 and Figure 8 In the display device 700, only the first covering layer 717, the first conductive pattern PE1 and the first connecting electrode CE1 are connected to Figures 1 to 6G Those of the display device 100 are different, and other configurations are substantially the same, so a redundant description will be omitted.

[0178] Reference Figure 7 , a first cover layer 717 is disposed on the plurality of reflective electrodes RE. The first cover layer 717 may cover top surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 exposed by the adhesive layer AD.

[0179] The first capping layer 717 includes a plurality of concave patterns CCP. For example, the first capping layer 717 may include one or more concave patterns CCP overlapping the first electrode 134 of the second light emitting diode ED2.

[0180] A first connection electrode CE1 is disposed on the first cover layer 717. The first connection electrode CE1 is disposed to overlap with the first electrode 134 of the second light emitting diode ED2, and as shown in FIG. Figure 7 and Figure 8 As shown, it may be disposed on one or more concave patterns CCP. At this time, the first connection electrode CE1 may cover the concave pattern CCP of the first cover layer 717 and be disposed to be bent along the surface of the concave pattern CCP.

[0181] The first conductive pattern PE1 is disposed on the first connection electrode CE1. The first conductive pattern PE1 is disposed between the first connection electrode CE1 and the first electrodes 134 of the plurality of second light emitting diodes ED2 in the second area A2. At this time, the first conductive pattern PE1 may cover the first connection electrode CE1 and fill one or more concave patterns CCP in which the first connection electrode CE1 is disposed. Figure 8 FIG. 4 shows that the first conductive pattern PE1 flattens the surface of the bent first link electrode CE1 , but is not limited thereto.

[0182] In the display device 700 according to another exemplary embodiment of the present disclosure, after the illumination test, the second light emitting diode ED2 emitting light having the same color as the first light emitting diode ED1 is transmitted only to the sub-pixel SP where the defective first light emitting diode ED1 occurs. Therefore, the processing cost and process for performing the illumination test on the light emitting diode ED can be reduced. Therefore, the manufacturing cost of the display device 700 can be saved.

[0183] In addition, in the display device 700 according to another exemplary embodiment of the present disclosure, laser processing is performed after the illumination test to expose the first connection electrode CE1 and the reflective electrode RE. Thereafter, liquid metal ink Ink is applied on the exposed first connection electrode CE1 and the reflective electrode RE to perform repair without a separate repair line.

[0184] In addition, in a display device 700 according to another exemplary embodiment of the present disclosure, a second light-emitting diode ED2 is disposed in a stepped region of the first and second cover layers 717 and 118, the dam BB, and the second planarization layer 119 to stably fix the second light-emitting diode ED2 in the second region A2.

[0185] Furthermore, in the display device 700 according to another exemplary embodiment of the present disclosure, the first conductive pattern PE1 and the second conductive pattern PE2 are formed in the step region to suppress a short circuit between the first conductive pattern PE1 and the second conductive pattern PE2 .

[0186] Furthermore, in the display device 700 according to another exemplary embodiment of the present disclosure, the first and second conductive patterns PE1 and PE2 disposed in the step region are formed by sintering liquid metal ink Ink to improve the fixing strength of the second light emitting diode ED2 .

[0187] Furthermore, in the display device 700 according to another exemplary embodiment of the present disclosure, the second conductive pattern PE2 covers the side surface of the first cover layer 717 to function as a lateral surface reflector, thereby suppressing a reduction in light emitting efficiency and improving brightness.

[0188] In addition, in the display device 700 according to another exemplary embodiment of the present disclosure, the first covering layer 717 includes one or more concave patterns CCP overlapping the first electrode 134 of the second light emitting diode ED2. Therefore, the first connection electrode CE1 and the first conductive pattern PE1 cover the concave pattern CCP disposed in a curved shape, and the surface areas of the first connection electrode CE1 and the first conductive pattern PE1 disposed in the second area A2 can be improved. Therefore, even if the first conductive pattern PE1 is formed of a silver paste having a relatively high resistivity, the surface area of ​​the first conductive pattern PE1 is increased to reduce resistance, and an increase in the driving voltage of the second light emitting diode ED2 can be suppressed.

[0189] In addition, in the display device 700 according to another exemplary embodiment of the present disclosure, the first conductive pattern PE1 covers the concave pattern CCP provided in a curved shape to increase the contact area between the first conductive pattern PE1 and the first cover layer 717. Therefore, the surface tension of the first conductive pattern PE1 can be improved, and the problem that the first conductive pattern PE1 is electrically connected to the second conductive pattern PE2 on the step region can be suppressed. Therefore, in the display device 700 according to another exemplary embodiment of the present disclosure, the short circuit problem between the first conductive pattern PE1 and the second conductive pattern PE2 can be suppressed.

[0190] Fig. 9 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. Fig.10 is along Fig. 9 Cross-sectional view taken along line D-D'. Fig. 9 and Fig.10 The display device 900 and Figures 1 to 6G The only difference between the display devices 100 is that an insulating pattern IP is added, and other configurations are substantially the same, so a redundant description will be omitted.

[0191] Reference Fig. 9 and Fig.10, an insulating pattern IP is provided between the first conductive pattern PE1 and the second conductive pattern PE2. The insulating pattern IP separates the first conductive pattern PE1 from the second conductive pattern PE2 to suppress a short circuit between the first conductive pattern PE1 and the second conductive pattern PE2. Fig.10 As shown, the insulating pattern IP is disposed on the first connection electrode CE1 and is disposed closer to the opening region than the first conductive pattern PE1. In one or more examples, the insulating pattern IP is disposed closer to the opening region than the first conductive pattern PE1. Fig. 9 and Fig.10 The location of the insulating pattern IP is merely illustrative, but not limited thereto.

[0192] Despite Fig.10 FIG. 4 shows that the top surface of the insulating pattern IP contacts the surface of the second light emitting diode ED, but is not limited thereto. Fig.10 2 and 3 show that one surface of the insulating pattern IP is in contact with one surface of the first conductive pattern PE1, but is not limited thereto.

[0193] The insulating pattern IP may be formed of an insulating material. For example, the insulating pattern IP may be formed of a photoresist or an acrylic-based organic material, but is not limited thereto. In addition, the insulating pattern IP may be formed of a hydrophobic material. Therefore, when the first conductive pattern PE1 is formed of liquid metal ink, the liquid metal ink is suppressed from overflowing the insulating pattern IP, and the electrical connection problem of the first conductive pattern PE1 and the second conductive pattern PE2 may be suppressed.

[0194] In addition, the cross-sectional shape of the insulating pattern IP may be a trapezoidal shape. Therefore, the side surface of the insulating pattern IP may be inclined with respect to the top surface of the first connection electrode CE1 and form a relatively large contact angle with the first conductive pattern PE1.

[0195] In the display device 900 according to still another exemplary embodiment of the present disclosure, after the illumination test, the second light emitting diode ED2 emitting light having the same color as the first light emitting diode ED1 is transmitted only to the sub-pixel SP where the defective first light emitting diode ED1 occurs. Therefore, the processing cost and process for performing the illumination test on the light emitting diode ED can be reduced. Therefore, the manufacturing cost of the display device 900 can be saved.

[0196] In addition, in the display device 900 according to another exemplary embodiment of the present disclosure, laser processing is performed after the illumination test to expose the first connection electrode CE1 and the reflective electrode RE. Thereafter, liquid metal ink Ink is applied on the exposed first connection electrode CE1 and the reflective electrode RE to perform repair without a separate repair line.

[0197] In addition, in a display device 900 according to another exemplary embodiment of the present disclosure, a second light emitting diode ED2 is disposed in a stepped region of the first and second cover layers 117 and 118, the dam BB, and the second planarization layer 119 to stably fix the second light emitting diode ED2 in the second region A2.

[0198] Furthermore, in the display device 900 according to still another exemplary embodiment of the present disclosure, the first conductive pattern PE1 and the second conductive pattern PE2 are formed in the step region to suppress a short circuit between the first conductive pattern PE1 and the second conductive pattern PE2 .

[0199] In addition, in the display device 900 according to still another exemplary embodiment of the present disclosure, the first and second conductive patterns PE1 and PE2 disposed in the step region are formed by sintering liquid metal ink Ink. Therefore, the fixing strength of the second light emitting diode ED2 may be improved.

[0200] Furthermore, in the display device 900 according to still another exemplary embodiment of the present disclosure, the second conductive pattern PE2 covers the side surface of the first cover layer 117 to function as a lateral surface reflector, thereby suppressing a reduction in light emitting efficiency and improving brightness.

[0201] Therefore, in a display device 900 according to another exemplary embodiment of the present disclosure, an insulating pattern IP is provided between the first conductive pattern PE1 and the second conductive pattern PE2. Therefore, the insulating pattern IP can suppress the first conductive pattern PE1 from overflowing to connect to the second conductive pattern PE2. For example, when the first conductive pattern PE1 is formed of liquid metal ink Ink, the liquid metal ink Ink may overflow the opening area. Therefore, there is a problem of electrical connection between the first conductive pattern PE1 and the second conductive pattern PE2. Therefore, in a display device 900 according to another exemplary embodiment of the present disclosure, the insulating pattern IP is provided on the first connection electrode CE1 to separate the first conductive pattern PE1 from the second conductive pattern PE2 and suppress the short circuit of the first conductive pattern PE1 and the second conductive pattern PE2.

[0202] Exemplary embodiments of the present disclosure may also be described as follows:

[0203] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate; a plurality of pixels including a plurality of sub-pixels; a first covering layer disposed on the substrate and including an opening area; a plurality of first light-emitting diodes disposed on the plurality of sub-pixels on the first covering layer; and a second light-emitting diode disposed in one or more pixels among the plurality of pixels on the substrate, wherein a portion of a lower side of the second light-emitting diode is disposed in the opening area, a portion of an upper side of the second light-emitting diode is disposed on the first covering layer, and an area of ​​a top surface of the second light-emitting diode is greater than an area of ​​a bottom surface of the second light-emitting diode.

[0204] Each of the plurality of first light-emitting diodes and second light-emitting diodes may include: a first semiconductor layer; a second semiconductor layer whose width is smaller than that of the first semiconductor layer; a light-emitting layer whose width may be smaller than that of the first semiconductor layer and is disposed between the first semiconductor layer and the second semiconductor layer; a first electrode which may be in contact with the first semiconductor layer; and a second electrode which may be in contact with the second semiconductor layer, and a lamination order of the plurality of first light-emitting diodes may be opposite to that of the second light-emitting diodes.

[0205] The width of the opening region may be smaller than the width of the first semiconductor layer of the second light emitting diode, and larger than the width of the second semiconductor layer of the second light emitting diode.

[0206] The opening region may surround the second semiconductor layer and the light emitting layer of the second light emitting diode, and the first cover layer may surround portions of the first semiconductor layer of the plurality of first light emitting diodes.

[0207] The display device may further include: a reflective electrode, which may be disposed under the first covering layer and overlap with the plurality of first light-emitting diodes and second light-emitting diodes, wherein the opening area may expose an area of ​​the reflective electrode that may be disposed under the second light-emitting diodes, the second electrode of the second light-emitting diode may be electrically connected to the reflective electrode, and the plurality of first light-emitting diodes may be connected to the plurality of reflective electrodes through contact holes of the first covering layer that do not overlap with the plurality of first light-emitting diodes.

[0208] The display device may also include: a plurality of transistors arranged on the substrate; a plurality of power lines arranged on the substrate; and a first connecting electrode, which may be arranged on the first covering layer and electrically connected to one of the plurality of transistors and the plurality of power lines, wherein the first electrodes of the plurality of first light-emitting diodes and the first electrodes of the second light-emitting diodes may be electrically connected to the first connecting electrode.

[0209] The display device may further include: a first conductive pattern which may electrically connect the first electrode of the second light emitting diode and the first connection electrode.

[0210] The first cover layer may include one or more concave patterns overlapping the first electrode of the second light emitting diode.

[0211] The first connection electrode may be disposed on the one or more concave patterns, and the first conductive pattern fills the one or more concave patterns on which the first connection electrode may be disposed.

[0212] The display device may further include: an insulating pattern which may be disposed on the first connection electrode to be closer to the opening region than the first conductive pattern.

[0213] The display device may further include: a reflective electrode that may overlap with the plurality of first light-emitting diodes and second light-emitting diodes; and a second conductive pattern that may electrically connect the second electrode of the second light-emitting diode and the reflective electrode in the opening region, wherein the second conductive pattern may extend from a top surface of the reflective electrode to cover a side surface of the first covering layer surrounding the opening region.

[0214] The display device may further include: a second covering layer which may be disposed on the first covering layer to surround portions of side surfaces of the plurality of first light emitting diodes and portions of side surfaces of the second light emitting diodes; and a protective layer which may be filled between the side surfaces of the second light emitting diodes and the second covering layer.

[0215] The protective layer may include a UV curable material.

[0216] The second light emitting diode may be a normal light emitting diode, and a first light emitting diode disposed in the same sub-pixel as the second light emitting diode among the plurality of first light emitting diodes may be a defective light emitting diode.

[0217] The display device may further include: a reflective electrode disposed on the substrate; and an adhesive layer, which may be disposed on the substrate and in contact with the bottom surfaces of the plurality of first light-emitting diodes, wherein the planar shape of the bottom surfaces of the first light-emitting diodes may be circular or elliptical, and wherein the first light-emitting diode may be one of the plurality of first light-emitting diodes.

[0218] According to one or more aspects of the present disclosure, a display device is provided. The display device includes: a substrate; a plurality of pixels including a plurality of sub-pixels; a plurality of first light-emitting diodes disposed on the substrate, wherein each of the plurality of first light-emitting diodes is disposed in a corresponding one of the plurality of sub-pixels; and a second light-emitting diode disposed on the substrate, wherein the second light-emitting diode is disposed in one or more pixels among the plurality of pixels, wherein: a top layer of each of the plurality of first light-emitting diodes includes a conductive electrode, and a top layer of the second light-emitting diode includes a semiconductor layer and does not include a conductive electrode.

[0219] The second light emitting diode may have a side surface extending outwardly from a lower portion of the side surface to an upper portion of the side surface.

[0220] Each of the plurality of first light emitting diodes may have a second side surface extending inwardly from a lower portion of the second side surface to an upper portion of the second side surface.

[0221] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in a variety of different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent ranges should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: substrate; a plurality of pixels, comprising a plurality of sub-pixels; a first covering layer disposed on the substrate and comprising an opening area; a plurality of first light emitting diodes, which are arranged on the plurality of sub-pixels on the first covering layer; as well as a second light emitting diode, which is disposed in one or more pixels among the plurality of pixels on the substrate, Part of the lower side of the second light-emitting diode is arranged in the opening area, and part of the upper side of the second light-emitting diode is arranged on the first covering layer, and the area of ​​the top surface of the second light-emitting diode is larger than the area of ​​the bottom surface of the second light-emitting diode.

2. The display device according to claim 1, wherein: Each of the plurality of first light emitting diodes and the second light emitting diode comprises: a first semiconductor layer; A second semiconductor layer, whose width is smaller than that of the first semiconductor layer; a light emitting layer, the width of which is smaller than the width of the first semiconductor layer, and disposed between the first semiconductor layer and the second semiconductor layer; a first electrode in contact with the first semiconductor layer; and a second electrode in contact with the second semiconductor layer; and The lamination order of the plurality of first light emitting diodes is opposite to the lamination order of the second light emitting diodes.

3. The display device according to claim 2, wherein: The width of the opening region is smaller than the width of the first semiconductor layer of the second light emitting diode, and is larger than the width of the second semiconductor layer of the second light emitting diode.

4. The display device according to claim 2, wherein: The opening region surrounds the second semiconductor layer and the light emitting layer of the second light emitting diode, and the first cover layer surrounds a portion of the first semiconductor layer of the plurality of first light emitting diodes.

5. The display device according to claim 2, further comprising: a reflective electrode disposed below the first cover layer and overlapping the plurality of first light emitting diodes and the second light emitting diode, The opening area exposes the reflective electrode area disposed below the second light-emitting diode, and the second electrode of the second light-emitting diode is electrically connected to the reflective electrode. The reflective electrode includes a plurality of reflective electrodes, each of the plurality of first light-emitting diodes is connected to a corresponding one of the plurality of reflective electrodes through a contact hole of the first covering layer, and the contact hole does not overlap with a corresponding one of the plurality of first light-emitting diodes.

6. The display device according to claim 2, further comprising: a plurality of transistors disposed on the substrate; a plurality of power lines disposed on the substrate; as well as a first connection electrode disposed on the first cover layer and electrically connected to one of the plurality of transistors and the plurality of power lines, The first electrodes of the plurality of first light-emitting diodes and the first electrode of the second light-emitting diode are electrically connected to the first connection electrode.

7. The display device according to claim 6, further comprising: A first conductive pattern electrically connects the first electrode of the second light emitting diode and the first connecting electrode.

8. The display device according to claim 7, wherein: The first cover layer includes one or more concave patterns overlapping the first electrode of the second light emitting diode.

9. The display device according to claim 8, wherein: The first connection electrode is disposed on the one or more concave patterns, and the first conductive pattern fills the one or more concave patterns on which the first connection electrode is disposed.

10. The display device according to claim 7, further comprising: An insulating pattern is disposed on the first connecting electrode to be adjacent to the opening region, wherein the insulating pattern is closer to the opening region than the first conductive pattern.

11. The display device according to claim 6, further comprising: a reflective electrode overlapping the plurality of first light emitting diodes and the second light emitting diode; as well as a second conductive pattern electrically connecting the second electrode of the second light emitting diode and the reflective electrode in the opening region, The second conductive pattern extends from a top surface of the reflective electrode to cover a side surface of the first covering layer surrounding the opening area.

12. The display device according to claim 6, further comprising: a second covering layer disposed on the first covering layer to surround a portion of a side surface of the plurality of first light emitting diodes and a portion of a side surface of the second light emitting diode; as well as A protection layer fills a space between a side surface of the second light emitting diode and the second covering layer.

13. The display device according to claim 12, wherein: The protective layer includes an ultraviolet curable material.

14. The display device according to claim 1, wherein: The second light emitting diode is a normal light emitting diode, wherein the first light emitting diode disposed in the same sub-pixel as the second light emitting diode is a defective light emitting diode, wherein the first light emitting diode is one of the plurality of first light emitting diodes, and The same sub-pixel is one of the multiple sub-pixels.

15. The display device according to claim 1, further comprising: A reflective electrode, which is disposed on the substrate; as well as an adhesive layer disposed on the substrate and in contact with bottom surfaces of the plurality of first light emitting diodes, wherein the planar shape of the bottom surface of the first light emitting diode is circular or elliptical, and The first light emitting diode is one of the plurality of first light emitting diodes.

16. A display device, comprising: substrate; a plurality of pixels including a plurality of sub-pixels; a plurality of first light emitting diodes disposed on the substrate, wherein each of the plurality of first light emitting diodes is disposed in a corresponding one of the plurality of sub-pixels; and a second light emitting diode disposed on the substrate, wherein the second light emitting diode is disposed in one or more pixels among the plurality of pixels, in: A top layer of each of the plurality of first light emitting diodes comprises a conductive electrode; and The top layer of the second light emitting diode includes a semiconductor layer and does not include a conductive electrode.

17. The display device according to claim 16, wherein: The second light emitting diode has the side surface extending outward from a lower portion of the side surface to an upper portion of the side surface.

18. The display device according to claim 17, wherein: Each of the plurality of first light emitting diodes has the second side surface extending inwardly from a lower portion of the second side surface to an upper portion of the second side surface.

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