Display device

Abstract

A display device includes an open area formed in a display area including a plurality of pixels and a plurality of lines connected to the plurality of pixels, and a non-display area surrounding the open area, the non-display area including a connecting member connected to at least one of the plurality of lines of the display area, and a connection member disposed in a different layer from the connected wire, and electrically connected to the wire through a via electrode.

Description

[0001] This application is a divisional application of an application with a filing date of December 18, 2020, application number 202011500985.6, and invention name “Display Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0176438, filed on Dec. 27, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0004] The present disclosure relates to a display device. Background Art

[0005] The display device is applied not only to televisions or monitors but also to personal portable electronic devices such as mobile phones and personal digital assistants (PDAs) in various ways, and such a display device is equipped with a camera to implement a camera function and a video call function.

[0006] Display devices tend to be manufactured to have a light and thin shape and also have a wide display area. Therefore, it is necessary to form a bezel area (which is a non-display area other than the display area) as small as possible.

[0007] Recently, a structure has been disclosed in which an opening area through which light enters a front camera is disposed inside a display area. Therefore, a frame area disposed around the opening area must be made as small as possible. Summary of the invention

[0008] Therefore, the present disclosure is to provide a display device in which a bezel area surrounding an opening area is reduced.

[0009] The present disclosure also provides a display device having a high degree of design freedom by reducing parasitic capacitance generated between lines in a bezel region surrounding an opening region.

[0010] The problem to be solved in the present disclosure is not limited thereto, and includes the following technical solutions, and also includes purposes or effects that can be understood from the present disclosure.

[0011] According to one aspect of the present disclosure, a display device is provided, which includes an opening area formed in a display area and a non-display area surrounding the opening area, wherein the display area includes a plurality of pixels and a plurality of lines connected to the plurality of pixels, and the non-display area includes a connecting member connected to at least one of the plurality of lines in the display area, and the connecting member is arranged in a different layer from the connected line and is electrically connected to the line through a via electrode.

[0012] The connection member may be disposed in a lower layer than the connected wires.

[0013] The connection member may be disposed in a higher layer than the connected wires.

[0014] The pixel may include a transistor, which may include: a beam shielding member arranged on a substrate; a semiconductor pattern arranged on the beam shielding member; and a gate electrode arranged on the semiconductor pattern, wherein the line connected to the connecting member among the multiple lines may be a gate line or an emission line, and the connecting member may be arranged in the same layer as the beam shielding member.

[0015] The transistor may also include: a first insulating layer arranged between the beam shielding member and the semiconductor pattern; and a second insulating layer arranged between the semiconductor pattern and the gate electrode, and the via electrode may pass through the first insulating layer and the second insulating layer in the non-display area to electrically connect the gate line or the emission line to the connecting member.

[0016] The connecting member may be electrically insulated from the beam shielding member, and the connecting member may have the same composition and thickness as the beam shielding member.

[0017] The gate electrode in the display area may be electrically connected to the beam shielding member through the first insulating layer and the second insulating layer.

[0018] Multiple lines in the non-display area can overlap vertically.

[0019] The line electrically connected to the connection member may be a transmission line.

[0020] The pixel may include a transistor, which may include: a beam shielding member arranged on a substrate; a semiconductor pattern arranged on the beam shielding member; a gate electrode arranged on the semiconductor pattern; a source electrode and a drain electrode arranged on the gate electrode; and a pixel electrode arranged on the gate electrode, wherein a line among the multiple lines connected to the connecting member may be a gate line or an emission line, and the connecting member may be arranged in the same layer as the pixel electrode.

[0021] The via electrode may pass through the insulating layer between the gate electrode and the pixel electrode in the non-display area to electrically connect the gate line or the emission line to the connection member.

[0022] The connection member may be electrically insulated from the pixel electrode, and the connection member may have the same composition and thickness as the pixel electrode.

[0023] According to another aspect of the present disclosure, a display device is provided, comprising: a substrate having an opening area formed in a display area and a non-display area surrounding the opening area; a gate line extending through the display area and the non-display area; and an emission line arranged in a different layer from the gate line in the non-display area, wherein the emission line is arranged at a position where a parasitic capacitance between the emission line and the gate line in the non-display area is minimized.

[0024] The emission line may be disposed in a layer in which a parasitic capacitance between the emission line and the gate line in the non-display area is minimized.

[0025] The emission lines may be disposed in the same layer as the gate lines in the display area.

[0026] The display device may further include a via electrode configured to connect the emission lines disposed in different layers in the display region and the non-display region.

[0027] A width at which the emission line and the gate line overlap in the non-display area may be greater than or equal to 50% of a width of the emission line.

[0028] The insulating layer between the emission line and the gate line in the non-display area may have or greater thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above-mentioned features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary aspects of the present disclosure with reference to the accompanying drawings, in which:

[0030] Figure 1 is a conceptual diagram of a display device according to one aspect of the present disclosure;

[0031] Figure 2 is a diagram showing the operation of the display device;

[0032] Figure 3 yes Figure 1 An enlarged view of part A;

[0033] Figure 4 is along Figure 3 A cross-sectional view taken along the line A-A';

[0034] Figure 5 is a cross-sectional view of a transistor provided in a pixel;

[0035] Figure 6 is a diagram showing the arrangement of lines in a non-display area;

[0036] Figure 7 is a diagram showing parasitic capacitance formed between lines in a non-display area;

[0037] Figure 8 is a diagram showing a structure in which a gate line of a display area extends to a non-display area;

[0038] Fig. 9 is a diagram showing a structure of a connection member in which an emission line of a display area is electrically connected to a non-display area;

[0039] Fig.10 is a waveform diagram of a pixel driving signal;

[0040] Fig.11 is a diagram showing an arrangement of lines in a non-display area according to another aspect of the present disclosure;

[0041] Fig.12 is a diagram showing a structure in which a gate line of a display area extends to a non-display area; and

[0042] Fig.13 is a diagram showing a structure in which an emission line of a display area is electrically connected to a connection member of a non-display area. DETAILED DESCRIPTION

[0043] The following aspects may be modified or combined with each other, and the scope of the present disclosure is not limited to the aspects.

[0044] Unless otherwise stated or contradictory, details described in a particular aspect may be understood as descriptions associated with other aspects even if the details are not described in the other aspects.

[0045] For example, when features of element A are described in a particular aspect and features of element B are described in another aspect, unless otherwise specified or contradictory, the aspect in which element A and element B are combined with each other should be understood to fall within the scope of the present disclosure, even if such an embodiment is not explicitly described.

[0046] In the description of various aspects, when an element is referred to as being above or below another element, the two elements may be in direct contact with each other, or one or more other elements may be disposed between the two elements. In addition, the term "above or below" as used herein may represent not only an upward direction relative to an element, but also a downward direction relative to an element.

[0047] The switching elements in the gate drive circuit of the present disclosure may be implemented as transistors in an n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) structure. It should be noted that although n-type transistors are shown in the following aspects, the present disclosure is not limited thereto.

[0048] A transistor is a three-electrode element including a gate, a source, and a drain. The source is the electrode through which carriers are supplied to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode through which carriers leave the transistor. That is, the flow of carriers in a MOSFET is from the source to the drain.

[0049] In the case of an n-type MOSFET (NMOS), the carriers are electrons. Therefore, the source voltage is lower than the drain voltage, so that electrons can flow from the source to the drain.

[0050] In an n-type MOSFET, because electrons flow from the source to the drain, the current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), the carriers are holes. Therefore, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. Since the holes in the p-type MOSFET flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. Therefore, in the following aspects, the present disclosure is not limited by the source and drain of the transistor.

[0051] In one aspect of the present disclosure, transistors constituting a pixel are all implemented as p-type, but the technical spirit of the present disclosure is not limited thereto and can be applied even when the transistors are implemented as n-type.

[0052] Figure 1 is a conceptual diagram of a display device according to one aspect of the present disclosure, Figure 2 is a diagram showing the operation of the display device, Figure 3 yes Figure 1 A magnified view of part A, and Figure 4 is along Figure 3 A cross-sectional view taken along line A-A'.

[0053] refer to Figure 1 , a display device according to an aspect may include a display area DA, a non-display area NDA1 disposed at the outermost side, an opening area H1 formed in the display area DA, and a non-display area NDA2 surrounding the opening area H1.

[0054] The opening area H1 may be an area through which light enters the front camera. However, the present disclosure is not limited thereto, and the opening area H1 may be an area in which various electronic devices function. The shape and number of the opening area H1 may be variously modified as needed.

[0055] refer to Figure 2According to one aspect of the present disclosure, a display device may include: a display panel 100 in which pixels PXL are formed; a data driving unit 12 for driving data lines DL1 to DLm; a gate driving unit 13 for driving gate lines GL1 to GL[n]; and a timing controller 11 for controlling driving timings of the data driving unit 12 and the gate driving unit 13.

[0056] A plurality of pixels PXL may be arranged in a matrix form in the display panel 100. The pixels PXL disposed in the nth horizontal line may be connected to the nth gate line GL[n]. The nth gate line GL[n] may include the nth scan line SL[n] and the (n-1)th scan line SL[n-1]. The pixels PXL arranged in each column line may be connected to one data line DL.

[0057] The pixel PXL may be commonly supplied with high potential and low potential driving voltages ELVDD and ELVSS and an initialization voltage Vini from a power generation unit (not shown). The initialization voltage may be selected within a voltage range sufficiently lower than an operating voltage of an organic light emitting device (OLED) to prevent unnecessary light emission of the OLED during an initial period and a sampling period.

[0058] The transistor TFT constituting the pixel PXL may be implemented as a transistor including an oxide semiconductor layer. Considering electron mobility, process variation, etc., the oxide semiconductor layer is advantageous for increasing the size of the display panel 100. The oxide semiconductor layer may be formed of an oxide semiconductor, including but not limited to indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), and the like. In addition, the present disclosure is not limited thereto, and the semiconductor layer of the transistor may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor, and the like.

[0059] The timing controller 11 may rearrange the digital video data RGB input from the outside according to the resolution of the display panel 100, and supply the rearranged digital video data to the data driving unit 12. In addition, the timing controller 11 may generate a data control signal DDC for controlling the operation timing of the data driving unit 12 and a gate control signal GDC for controlling the operation timing of the gate driving unit 13 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE.

[0060] The data driving unit 12 may convert the digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC.

[0061] The gate driving unit 13 may generate a scan signal and an emission signal (light emitting control signal) based on the gate control signal GDC. The gate driving unit 13 may include a scan driving unit and an emission driving unit. Hereinafter, it is defined that the scan signal is supplied through the gate line and the emission signal is supplied through the emission line.

[0062] The scan driving unit may generate first to nth scan signals SCAN1 to SCAN[n], and the emission driving unit may generate first to nth light emission control signals EM1 to EM[n]. The gate driving unit 13 may be directly formed on the non-display area of ​​the display panel 100 according to a gate in panel (GIP).

[0063] refer to Figure 3 , a plurality of lines may be disposed in the non-display area NDA2 surrounding the opening area H1. For example, a plurality of data lines SD1, a plurality of gate lines, and a plurality of emission lines EM may be disposed in the non-display area NDA2. The plurality of data lines, the plurality of gate lines, and the plurality of emission lines may be formed with a bend along the opening area H1 in the non-display area NDA2.

[0064] In the drawings, for ease of description, the data line SD1 and the emission line EM are shown as not overlapping. However, in the following description, a plurality of lines may be arranged to vertically overlap each other. Therefore, the size of the non-display area NDA2 may be reduced.

[0065] refer to Figure 4 , a display device according to an aspect may include a display panel 100, a touch panel 200, a black matrix 300 disposed in a non-display area, and a window 400. An opening area H1 may be vertically formed in the display panel 100, and a camera module 500 may be disposed under the display panel 100.

[0066] The non-display area NDA2 surrounding the opening area H1 may have different layers in which the plurality of lines SL are disposed. The plurality of lines SL may include a plurality of first data lines, a plurality of second data lines, a plurality of gate lines, and a plurality of emission lines. Therefore, the size of the non-display area NDA2 may be minimized by vertically arranging the first data lines, the second data lines, the gate lines, and the emission lines in an overlapping manner. For example, the size of the non-display area NDA2 may be reduced to about one third compared to conventional techniques.

[0067] As reference Figure 3 As described above, the plurality of data lines, the plurality of gate lines, and the plurality of emission lines may be formed with bends along the opening area H1. Figure 3 In the cross section taken along line AA′ of FIG. 8 , a plurality of data lines, a plurality of gate lines, and a plurality of emission lines of the non-display area NDA2 may extend in the same direction.

[0068] Therefore, the display area DA may be disposed outside the non-display area NDA2. The display area DA may include a plurality of pixels defined by data lines and gate lines.

[0069] Figure 5 is a cross-sectional view of a transistor provided in a pixel.

[0070] refer to Figure 5 , the base substrate 111 may include a polyimide layer (not shown) and a buffer layer (not shown). The buffer layer may be silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof. The base substrate 111 may include an opening area formed in the display area and a non-display area surrounding the opening area.

[0071] The beam shielding member BSM may be disposed on the base substrate 111. The polyimide-based insulating film forms mobile charges, thereby affecting a semiconductor layer of a transistor and reducing a driving current.

[0072] The beam shielding member BSM may be used to prevent the amount of current of the semiconductor layer 122 from being reduced due to the flow of charges in the polyimide layer. As shown in the figure, the beam shielding member BSM may be in a floating state or may be connected to the gate electrode GE. Although the present specification shows an aspect in which the beam shielding member BSM is connected to the gate electrode GE, the present disclosure is not limited thereto, and the beam shielding member BSM may be connected to the drain electrode DE. Moreover, the beam shielding member BSM may be connected to another constant voltage source having a constant voltage level.

[0073] The first insulating layer 112 may be disposed on the beam shielding member BSM. The first insulating layer 112 may be used to protect a thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the beam shielding member BSM. The first insulating layer 112 may be silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof, but the present disclosure is not limited thereto.

[0074] The semiconductor layer 122 may be disposed on the first insulating layer 112. The semiconductor layer 122 may be made of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polysilicon. Here, polysilicon has a high mobility (more than 100 cm 2 / Vs), low energy consumption and excellent reliability, and thus can be applied to a multiplexer (MUX) and / or a gate driver of a driver device, or can be applied to a driving TFT in a pixel. At the same time, the oxide semiconductor has a low off-current, and thus is suitable for a switching TFT with a short on-time and a long off-time. Moreover, due to the low off-current, the pixel has a long voltage holding period, and therefore, the oxide semiconductor is suitable for a display device requiring low-speed driving and / or low power consumption.

[0075] The second insulating layer 113 may be disposed on the semiconductor layer 122. The second insulating layer 113 may be a gate insulating film. The second insulating layer 113 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0076] The gate electrode GE may be disposed on the second insulating layer 113 over a certain region of the semiconductor layer 122 , ie, at a position corresponding to a channel when impurities are injected.

[0077] The gate electrode GE may be formed of one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. Moreover, the gate electrode GE may be formed of one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the gate electrode GE may be a double layer of molybdenum and aluminum-neodymium or a double layer of molybdenum and aluminum.

[0078] A third insulating layer 114 for insulating the gate electrode GE may be disposed on the gate electrode GE. The third insulating layer 114 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

[0079] The capacitor metal layer TM1 may be disposed on the third insulating layer 114. The capacitor metal layer TM1 may face the gate electrode GE with the third insulating layer 114 therebetween, and the capacitor metal layer TM1 may form a storage capacitor.

[0080] The fourth insulating layer 115 may be disposed on the capacitor metal layer TM1. The fourth insulating layer 115 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer thereof.

[0081] The drain electrode DE and the source electrode SE may be disposed on the fourth insulating layer 115. The source electrode SE may be connected to the semiconductor layer 122 through a contact hole, and the drain electrode DE may be connected to the semiconductor layer 122 through a contact hole.

[0082] The source electrode SE and the drain electrode DE may include a single layer or multiple layers. When the source electrode SE and the drain electrode DE include a single layer, the source electrode SE and the drain electrode DE may be formed of one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0083] The semiconductor layer 122 , the gate electrode GE, the drain electrode DE, and the source electrode SE may constitute a driving transistor.

[0084] A fifth insulating layer 116 may be disposed on the source electrode SE and the drain electrode DE. The fifth insulating layer 116 may protect the driving transistor and the transistor disposed in the display area, and may reduce a height difference in the display area DA. A second drain electrode 125 may be disposed on the fifth insulating layer 116, and then a sixth insulating layer 117 may be disposed on the second drain electrode 125.

[0085] The pixel electrode 126 of the organic light emitting diode 127 may be disposed on the sixth insulating layer 117. The pixel electrode 126 may be connected to the second drain electrode 125 of the driving transistor DT through a via hole. The pixel electrode 126 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO), but the present disclosure is not limited thereto.

[0086] A bank layer 118 that divides a pixel may be disposed on the pixel electrode 126. The bank layer 118 may be made of an organic material such as polyimide, benzocyclobutene series resin, and acrylate. A common electrode 128 may be disposed above the bank layer 118.

[0087] Figure 6 is a diagram showing the arrangement of lines in a non-display area, Figure 7 is a diagram showing parasitic capacitance formed between lines in a non-display area, Figure 8 is a diagram showing a structure in which a gate line of a display area extends to a non-display area, Fig. 9 is a diagram showing a structure in which an emission line of a display area is electrically connected to a connection member of a non-display area, and Fig.10 It is a waveform diagram of the pixel driving signal.

[0088] refer to Figure 6 , the first emission line 121a may be disposed on the base substrate 111 in the non-display area NDA2, the gate line 123a may be disposed on the second insulating layer 113, the first data line 124a may be disposed on the fourth insulating layer 115, and the second data line 125a may be disposed on the fifth insulating layer 116.

[0089] According to one aspect, the size of the non-display area NDA2 can be reduced by placing the gate line 123a for supplying a scan signal and the first emission line 121a for supplying an emission signal in different layers. In this case, the size of the non-display area NDA2 can be minimized by vertically overlapping the first data line 124a, the second data line 125a, the gate line 123a, and the first emission line 121a.

[0090] The overlap may include not only the complete vertical overlap of the first data line 124a, the second data line 125a, the gate line 123a, and the first emission line 121a, but also their partial overlap. For example, the width S1 of the vertical overlap of the gate line 123a and the first emission line 121a (in the y-axis direction) may be greater than 50% of the width of the first emission line 121a. When the width S1 of the overlap of the gate line 123a and the first emission line 121a is less than 50% of the width of the first emission line 121a, the parasitic capacitance may not be significantly reduced, and the size of the non-display area may increase. Here, the width may be the width in the direction perpendicular to the length direction of the line (the x-axis direction).

[0091] The first insulating layer 112 is an active buffer layer and has approximately The second insulating layer 113 is a gate insulating layer and has a thickness of about Therefore, with a thickness of approximately An insulating layer with a thickness of 500 Å is formed between the gate line 123a and the first emission line 121a, and thus parasitic capacitance may be reduced.

[0092] According to one aspect, the first emission line 121a may be disposed at the bottom in the non-display area NDA2. In the non-display area NDA2, the first emission line 121a may be a dummy pattern of a beam shielding member. That is, when the beam shielding member is formed in the display area, a dummy pattern may be formed in the non-display area NDA2, and the dummy pattern may be electrically connected to the emission line of the display area. Therefore, the first emission line 121a of the non-display area NDA2 may have the same material and thickness as the beam shielding member of the display area.

[0093] refer to Figure 7 , when the first emitting line 121a is disposed above the third insulating layer 114 on which the capacitor metal layer is disposed, the thickness of the third insulating layer 114 is And thus the parasitic capacitance PC is relatively increased. Therefore, the load may be increased, which may cause a dim type defective pixel.

[0094] On the other hand, reference Figure 6 , a relatively thick insulating layer is between the gate line 123a and the first emission line 121a, and thus the parasitic capacitance can be relatively small. For example, when the insulating layer between the gate line 123a and the first emission line 121a has a capacitance of about When the thickness is 1000 Å or greater, the resistor-capacitor (RC) delay can be reduced by relatively reducing the parasitic capacitance.

[0095] According to one aspect, the position of the first emission line 121a can be adjusted in the non-display area NDA2 so that the parasitic capacitance between the gate line 123a and the first emission line 121a is minimized. For example, in the non-display area NDA2, the first emission line 121a can be set in a layer where the parasitic capacitance between the gate line 123a and the first emission line 121a is minimized. In this case, by comprehensively considering the parasitic capacitance between the gate line 123a and the first emission line 121a, and the parasitic capacitance between the first gate line 123a and the data lines 124a and 125a, the first emission line 121a can be set at an optimal position. .

[0096] refer to Figure 8 , the gate line 123a of the non-display area NDA2 may be disposed in the same layer as the gate line 123 of the display area DA. Fig. 9 As shown, the first emission line 121a of the non-display area NDA2 and the emission line 121 of the display area DA may be arranged in different layers. As described above, the emission line 121 of the display area DA may be electrically connected to the first emission line 121a, which is a dummy pattern of the beam shielding member. Therefore, the first emission line 121a of the non-display area NDA2 may be a connecting member connecting the emission line 121 of the display area DA. In one aspect, the connecting member of the non-display area NDA2 has the same reference numeral as the first emission line of the non-display area NDA2 because the connecting member may be used as an emission line.

[0097] The via electrode VE may pass through the first and second insulating layers 112 and 113 of the non-display area NDA2 to electrically connect the emission line 121 of the display area DA to the first emission line 121a. The via electrode VE may be formed by extending the emission line 121 of the display area DA to the non-display area NDA2.

[0098] The first emission line 121a of the non-display area NDA2 may be disposed in the same layer as the emission line 121 of the display area DA, while the gate line 123a of the non-display area NDA2 and the gate line 123 of the display area DA are disposed in different layers.

[0099] refer to Fig.10 , the parasitic capacitance between the gate line 123a and the first emission line 121a can be reduced to about one third, and the resistance of the gate line 123a can be maintained. Therefore, the scan load can be reduced, which allows a fast response.

[0100] On the other hand, the resistance of the first transmission line 121a can be increased by about three times, while the parasitic capacitance is reduced to about one third. Therefore, compared with the conventional technology, the RC delay can have a similar level. However, since the transmission signal is turned off during the sampling period and has a holding period HT of 1H, there is enough margin for the rise time Tr and the fall time Tf. Therefore, there is no problem in operation.

[0101] Fig.11 is a diagram showing an arrangement of lines in a non-display area according to another aspect of the present disclosure, Fig.12 is a diagram showing a structure in which a gate line of a display area extends to a non-display area, and Fig.13 is a diagram showing a structure in which an emission line of a display area is electrically connected to a connection member of a non-display area.

[0102] refer to Fig.11 In the non-display area NDA2, the second emission line 126a may be disposed on the sixth insulating layer 117, the gate line 123a may be disposed on the second insulating layer 113, the first data line 124a may be disposed on the fourth insulating layer 115, and the second data line 125a may be disposed on the fifth insulating layer 116.

[0103] According to one aspect, the size of the frame area can be reduced by placing the gate line 123a for supplying the scan signal and the second emission line 126a for supplying the emission signal in different layers. In this case, the size of the non-display area NDA2 can be minimized by vertically overlapping the first data line 124a, the second data line 125a, the gate line 123a and the second emission line 126a.

[0104] In this case, the overlap may include not only a complete vertical overlap of the first data line 124a, the second data line 125a, the gate line 123a, and the second emission line 126a, but also a partial overlap thereof.

[0105] Since the gate line 123a is disposed on the second insulating layer 113 and the second emission line 126a is disposed on the sixth insulating layer 117, parasitic capacitance may not be formed between the gate line 123a and the second emission line 126a. In addition, since the sixth insulating layer 117, which is thicker and has a thickness of about 2 μm, is disposed between the second emission line 126a and the second data line 125a, the parasitic capacitance may be very small.

[0106] According to one aspect, the second emission line 126a may be disposed at the top in the non-display area NDA2. In the non-display area NDA2, the second emission line 126a may be a dummy pattern of a pixel electrode. That is, when a pixel electrode is formed in the display area, a dummy pattern may be formed in the non-display area NDA2, and the dummy pattern may be electrically connected to the emission line 121 of the display area DA. Therefore, the second emission line 126a of the non-display area NDA2 may have the same material and thickness as the pixel electrode of the display area.

[0107] refer to Fig.12 , the gate line 123a of the non-display area NDA2 may be disposed in the same layer as the gate line 123 in the display area DA. Fig.13 As shown, the second emission line 126a of the non-display area NDA2 and the emission line 121 of the display area DA can be set in different layers. As described above, the emission line 121 in the display area DA can be electrically connected to the second emission line 126a, and the connection member is a dummy pattern of the pixel electrode. Therefore, the second emission line 126a of the non-display area NDA2 can be a connection member connecting the emission line 121 of the display area DA.

[0108] In the non-display area NDA2, the via electrode VE may include a first via electrode VE1 passing through the third insulating layer 114 and the fourth insulating layer 115 and a second via electrode VE2 connected to the first via VE1 through the fifth insulating layer 116. However, the present disclosure is not limited thereto, and one via electrode may pass through the third to fifth insulating layers 114, 115, and 116.

[0109] The second emission line 126a of the non-display area NDA2 may be disposed in the same layer as the emission line 121 of the display area DA, while the gate line 123a of the non-display area NDA2 and the gate line 123 of the display area DA are disposed in different layers and connected to each other.

[0110] According to one aspect, the size of the bezel area surrounding the opening area can be reduced.

[0111] In addition, parasitic capacitance generated between lines arranged in the frame area can be reduced. Therefore, image quality defects in the form of dimming can be prevented.

[0112] Furthermore, the degree of design freedom can be increased when designing the line.

[0113] Furthermore, since the dummy pattern is used, a conventional process can be applied without change.

[0114] Various advantageous advantages and effects of the present disclosure are not limited to the above description and will be easily understood when various aspects of the present disclosure are described in detail.

[0115] Although the present disclosure has been described with reference to exemplary aspects, these are merely examples and do not limit the present disclosure. It will be appreciated by those skilled in the art that various modifications and applications may be made therein without departing from the basic characteristics of the various aspects. For example, the elements described in detail in the above various aspects may be modified. In addition, the differences associated with such modifications and applications should be interpreted as being included within the scope of the present disclosure defined by the appended claims.

Claims

1. A display device, comprising: a display panel including a substrate, a beam shielding member disposed on the substrate, and a transistor including an oxide semiconductor disposed on the beam shielding member; a touch panel on the display panel; as well as The black matrix on the touch panel, Wherein, the display panel includes a display area and a non-display area, Wherein, the non-display area of ​​the display panel includes: a first gate electrode, a first insulating layer insulating the first gate electrode, a second insulating layer on the first insulating layer, a first data line overlapping at least a portion of the first gate electrode, and A second data line overlaps at least a portion of the first data line.

2. The display device according to claim 1, wherein: The transistor includes a second gate electrode electrically connected to the first gate electrode, a source electrode, and a drain electrode, and Wherein, each of the source electrode and the drain electrode includes a plurality of layers.

3. The display device according to claim 2, wherein: The second gate electrode is made of the same material as the first gate electrode.

4. The display device according to claim 2, wherein: The display region includes a third gate electrode, wherein the first insulating layer is disposed on the second gate electrode and the third gate electrode.

5. The display device according to claim 4, wherein: The transistor includes a capacitor metal layer disposed to overlap at least a portion of the second gate electrode on the first insulating layer. 6 . The display device according to claim 1 , further comprising a window disposed on the black matrix, and a camera module disposed under the window.

7. The display device according to claim 1, wherein: The non-display area surrounds an opening area provided in the display area.

8. The display device according to claim 1, wherein: The non-display area includes an emission line overlapping the first gate electrode, the first data line, and the second data line.

9. The display device according to claim 1, wherein: The display area includes a plurality of pixels and a plurality of lines connected to the plurality of pixels. wherein the non-display area includes a connection member connected to at least one of the plurality of lines of the display area, and The connection member is disposed in a layer different from the at least one line among the plurality of lines in the display area and is electrically connected to the at least one line among the plurality of lines through a via electrode.

10. The display device according to claim 9, wherein: The connection member is disposed in a layer lower than a line among the plurality of lines connected to the connection member.

11. The display device according to claim 9, wherein: The connection member is disposed in a layer higher than a line among the plurality of lines connected to the connection member.

12. The display device according to claim 9, wherein: The line connected to the connection member among the plurality of lines is the first gate electrode or an emitter line.

13. The display device according to claim 9, wherein: The connecting member is provided in the same layer as the beam shielding member. 14 . The display device according to claim 12 , further comprising a via electrode passing through the first insulating layer and the second insulating layer in the non-display area to electrically connect the first gate electrode or the emission line to the connection member.

15. The display device according to claim 14, wherein: The connecting member is electrically insulated from the beam shielding member, and Wherein, the connecting member has the same composition and thickness as the beam shielding member.

16. The display device according to claim 9, wherein: The connection member is provided in the same layer as a pixel electrode of the transistor.

17. The display device according to claim 16, wherein: The connection member is electrically insulated from the pixel electrode, and Wherein, the connection member has the same composition and thickness as the pixel electrode.

18. The display device according to claim 8, wherein: In the non-display area, an insulating layer disposed between the emission line and the gate line has or greater thickness.

19. The display device according to claim 6, wherein: The display panel and the black matrix include an opening area formed at a position corresponding to the camera module.

20. The display device according to claim 19, wherein: The first gate electrode, the first data line, and the second data line surround the opening area.

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