Shift register unit, display panel, display device, and driving method

Abstract

The shift register unit, the display panel, the display device and the driving method provided by the embodiments of the present disclosure comprise: a shift register configured to output a cascade signal through a cascade output end; and an output circuit electrically connected with the shift register, the output circuit being configured to control a driving output end to output a gate scanning signal according to a signal of an output control signal end and a signal of a reference signal end.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to shift register units, display panels, display devices, and driving methods. Background Technology

[0002] With the rapid development of display technology, display panels are showing a trend towards high integration and low cost. Among them, Gate Driver on Array (GOA) technology integrates the drive control circuitry onto the array substrate of the display panel to form a scanning drive for the display panel. Currently, the drive control circuitry typically consists of multiple cascaded shift register units. Summary of the Invention

[0003] The shift register unit provided in some embodiments of this disclosure includes:

[0004] The shift register is configured to output cascaded signals through the cascaded output terminal;

[0005] An output circuit, electrically connected to the shift register, is configured to control the output terminal to output a gate scan signal based on the signal at the first voltage signal terminal and the signal at the reference signal terminal.

[0006] The shift register includes: a first control sub-circuit;

[0007] The first control sub-circuit is electrically connected to the first node, the second node, the second voltage signal terminal, and the first clock signal terminal in the shift register; the first control circuit is configured to control the voltage of the second node according to the voltage of the first node and the signal of the first clock signal terminal.

[0008] In some possible implementations provided in this disclosure, the shift register includes:

[0009] The input sub-circuit is configured to provide the signal from the input signal terminal to the first node in response to a signal from the second clock signal terminal.

[0010] In some possible implementations provided in this disclosure, the input sub-circuit includes: a first transistor;

[0011] The first terminal of the first transistor is electrically connected to the input signal terminal, the second terminal of the first transistor is electrically connected to the first node, and the third terminal of the first transistor is electrically connected to the second clock signal terminal.

[0012] In some possible implementations provided in this disclosure, the first control sub-circuit includes: a second transistor, a third transistor, a fourth transistor, and a first capacitor;

[0013] The first terminal of the second transistor is electrically connected to the first clock signal terminal, the second terminal of the second transistor is electrically connected to the second node, and the third terminal of the second transistor is electrically connected to the third node.

[0014] The first terminal of the third transistor is electrically connected to the second voltage signal terminal, the second terminal of the third transistor is electrically connected to the third node, and the third terminal of the third transistor is electrically connected to the first node.

[0015] The first terminal of the fourth transistor is electrically connected to the second voltage signal terminal, the second terminal of the fourth transistor is electrically connected to the second node, and the third terminal of the fourth transistor is electrically connected to the first node.

[0016] The first electrode of the first capacitor is electrically connected to the first clock signal terminal, and the second electrode of the first capacitor is electrically connected to the third node.

[0017] In some possible implementations provided in this disclosure, the shift register includes:

[0018] The second control sub-circuit is electrically connected to the first node, the second node, the second voltage signal terminal, and the first clock signal terminal; the second control sub-circuit is configured to transmit a signal from the second voltage signal terminal to the first node based on the voltage of the second node and the signal from the first clock signal terminal.

[0019] In some possible implementations provided in this disclosure, the second control sub-circuit includes: a fifth transistor and a sixth transistor;

[0020] The first terminal of the fifth transistor is electrically connected to the second voltage signal terminal, the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor, and the third terminal of the fifth transistor is electrically connected to the second node.

[0021] The second terminal of the sixth transistor is electrically connected to the first node, and the third terminal of the sixth transistor is electrically connected to the first clock signal terminal.

[0022] In some possible implementations provided in this disclosure, the shift register includes:

[0023] A potential stabilizing sub-circuit is electrically connected to the first node, the fourth node, and the first voltage signal terminal. The potential stabilizing sub-circuit is configured to transmit the voltage from the first node to the fourth node according to the signal from the first voltage signal terminal.

[0024] In some possible implementations provided in this disclosure, the potential stabilizing sub-circuit includes: a seventh transistor;

[0025] The first terminal of the seventh transistor is electrically connected to the first node, the second terminal of the seventh transistor is electrically connected to the fourth node, and the third terminal of the seventh transistor is electrically connected to the first voltage signal terminal.

[0026] In some possible implementations provided in this disclosure, the shift register includes:

[0027] A cascaded sub-circuit is electrically connected to the second node, the fourth node, the first clock signal terminal, and the second voltage signal terminal. The cascaded sub-circuit is configured to output the cascaded signal at the cascaded output terminal in response to the voltages of the second node and the fourth node.

[0028] In some possible implementations provided in this disclosure, the cascaded sub-circuit includes: an eighth transistor, a ninth transistor, and a second capacitor;

[0029] The first terminal of the eighth transistor is electrically connected to the first clock signal terminal, the second terminal of the eighth transistor is electrically connected to the cascaded output terminal, and the third terminal of the eighth transistor is electrically connected to the fourth node.

[0030] The first terminal of the ninth transistor is electrically connected to the second voltage signal terminal, the second terminal of the ninth transistor is electrically connected to the cascaded output terminal, and the third terminal of the ninth transistor is electrically connected to the second node.

[0031] The first electrode of the second capacitor is electrically connected to the fourth node, and the second electrode of the second capacitor is electrically connected to the cascaded output terminal.

[0032] In some possible implementations provided in this disclosure, the cascaded sub-circuit includes: a third capacitor;

[0033] The first electrode of the third capacitor is electrically connected to the second voltage signal terminal, and the second electrode of the third capacitor is electrically connected to the cascaded output terminal.

[0034] In some possible implementations provided in this disclosure, the shift register includes:

[0035] A pull-down sub-circuit, electrically connected to a third voltage signal terminal and the first node, is configured to transmit a signal from the third voltage signal terminal to the first node.

[0036] In some possible implementations provided in this disclosure, the amplitude of the voltage signal at the third voltage signal terminal is greater than the amplitude of the voltage signal at the first voltage signal terminal.

[0037] In some possible implementations provided in this disclosure, the pull-down sub-circuit includes: a twelfth transistor;

[0038] The first terminal of the twelfth transistor is electrically connected to the third voltage signal terminal, the second terminal of the twelfth transistor is electrically connected to the first node, and the third terminal of the twelfth transistor is electrically connected to the fourth node.

[0039] In some possible implementations provided in this disclosure, the pull-down sub-circuit includes: a twelfth transistor;

[0040] The first terminal of the twelfth transistor is electrically connected to the third voltage signal terminal, the second terminal of the twelfth transistor is electrically connected to the first node, and the third terminal of the twelfth transistor is electrically connected to the first node.

[0041] In some possible implementations provided in this disclosure, the output circuit includes: a tenth transistor and an eleventh transistor;

[0042] The first terminal of the tenth transistor is electrically connected to the reference signal terminal, the second terminal of the tenth transistor is electrically connected to the drive output terminal, and the third terminal of the tenth transistor is electrically connected to the first node.

[0043] The first terminal of the eleventh transistor is electrically connected to the first voltage signal terminal, the second terminal of the eleventh transistor is electrically connected to the drive output terminal, and the third terminal of the eleventh transistor is electrically connected to the second node.

[0044] In some possible implementations provided in this disclosure, the output circuit includes: a tenth transistor, an eleventh transistor, and a thirteenth transistor;

[0045] The first terminal of the tenth transistor is electrically connected to the reference signal terminal, the second terminal of the tenth transistor is electrically connected to the drive output terminal, and the third terminal of the tenth transistor is electrically connected to the second terminal of the thirteenth transistor.

[0046] The first terminal of the eleventh transistor is electrically connected to the first voltage signal terminal, the second terminal of the eleventh transistor is electrically connected to the drive output terminal, and the third terminal of the eleventh transistor is electrically connected to the second node.

[0047] The first terminal of the thirteenth transistor is electrically connected to the first node, and the third terminal of the thirteenth transistor is electrically connected to the first voltage signal terminal.

[0048] In some possible implementations provided in this disclosure, the output circuit further includes: a fourth capacitor;

[0049] The first electrode of the fourth capacitor is electrically connected to the first voltage signal terminal, and the second electrode of the fourth capacitor is electrically connected to the second node.

[0050] In some possible implementations provided in this disclosure, the signal at the reference signal terminal and the signal at the first clock signal terminal are inverted signals.

[0051] In some possible implementations provided in this disclosure, the signals at the first clock signal terminal and the signals at the second clock signal terminal are not simultaneously valid level signals.

[0052] The display panel provided in some embodiments of this disclosure includes:

[0053] The substrate includes the display area and the non-display area;

[0054] The display area includes:

[0055] Multiple sub-pixels;

[0056] Multiple scan lines, wherein one row of sub-pixels in the plurality of sub-pixels is electrically connected to at least one of the multiple scan lines;

[0057] The non-display area includes:

[0058] The gate drive circuit includes a plurality of shift register units as described above, wherein the drive output terminal of each of the plurality of shift register units is electrically connected to at least one of the plurality of scan lines.

[0059] In some possible implementations provided in this disclosure, the system further includes: an input signal line electrically connected to the gate driving circuit and disposed in the non-display area, a first voltage signal line, a first clock signal line, and a second clock signal line located away from the display area;

[0060] The input signal line, the first voltage signal line away from the display area, the first clock signal line, and the second clock signal line extend along a first direction, and the gate line extends along a second direction, with the first direction intersecting the second direction.

[0061] In some possible embodiments provided in this disclosure, the orthogonal projections of the input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line away from the display area onto the substrate are arranged sequentially along the direction close to the display area and are located on the side of the shift register unit away from the display area.

[0062] In some possible implementations provided in this disclosure, the input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line located away from the display area are arranged on the same layer.

[0063] In some possible embodiments provided in this disclosure, the input signal line, the first voltage signal line away from the display area, the first clock signal line, and the second clock signal line are arranged sequentially on the substrate along the direction close to the display area, and are located on the side of the shift register unit away from the display area.

[0064] In some possible implementations provided in this disclosure, the input signal line and the first voltage signal line away from the display area are arranged on the same layer, the first clock signal line and the second clock signal line are arranged on the same layer, and the input signal line, the first voltage signal line away from the display area, the first clock signal line, and the second clock signal line are arranged on different layers.

[0065] In some possible implementations provided in this disclosure, a second voltage signal line electrically connected to the gate driving circuit and disposed in the non-display area is further included, the second voltage signal line extending along a first direction.

[0066] In some possible implementations provided in this disclosure, the second voltage signal line is disposed on the side of the first voltage signal line that is far from the display area and close to the display area.

[0067] In some possible implementations provided in this disclosure, a third voltage signal line electrically connected to the gate driving circuit and disposed in the non-display area is further included, the third voltage signal line extending along a first direction.

[0068] In some possible implementations provided in this disclosure, the third voltage signal line is disposed on the side of the second voltage signal line closer to the display area.

[0069] In some possible implementations provided in this disclosure, a third clock signal line, a fourth clock signal line, and a first voltage signal line near the display area are electrically connected to the gate driving circuit and disposed in the non-display area, wherein the third clock signal line, the fourth clock signal line, and the first voltage signal line near the display area extend along a first direction.

[0070] In some possible implementations provided in this disclosure, either the third clock signal line or the fourth clock signal line is disposed on the side of the third voltage signal line closer to the display area;

[0071] The first voltage signal line near the display area is located on the side of either the third clock signal line or the fourth clock signal line closest to the display area.

[0072] In some possible implementations provided in this disclosure, the reference signal terminal of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the reference signal terminal of the (i+1)-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

[0073] In some possible implementations provided in this disclosure, the first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line.

[0074] The signal lines connected to the first clock signal terminals of adjacent shift register units are different, and the signal lines connected to the second clock signal terminals of adjacent shift register units are different.

[0075] In some possible implementations provided in this disclosure, the width of any one of the input signal line, the first voltage signal line, the second voltage signal line, and the third voltage signal line along the second direction is less than the width of any one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line along the second direction.

[0076] In some possible implementations provided in this disclosure, the shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor, and a first capacitor;

[0077] At least a portion of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the first capacitor is located between the first voltage signal line and the second voltage signal line.

[0078] In some possible implementations provided in this disclosure, the shift register unit includes: a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a twelfth transistor, and a second capacitor;

[0079] At least a portion of any one of the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the twelfth transistor, and the second capacitor is located between the second voltage signal line and the third voltage signal line.

[0080] In some possible embodiments provided in this disclosure, the active layer of the twelfth transistor extends along a first direction, at least a portion of either the first or second electrode of the twelfth transistor extends along a second direction, and the third electrode of the twelfth transistor extends along a second direction.

[0081] In some possible implementations provided in this disclosure, the shift register unit includes: a tenth transistor, an eleventh transistor, and a third capacitor;

[0082] At least a portion of any one of the tenth transistor, the eleventh transistor, and the third capacitor is located on the side of the first voltage signal line near the display area.

[0083] The orthographic projection of the first voltage signal line near the display area on the substrate overlaps with the orthographic projection of the third capacitor on the substrate.

[0084] In some possible implementations provided in this disclosure, the channel width of the active layer of the tenth transistor is greater than the channel width of the active layer of the eighth transistor.

[0085] In some possible implementations provided in this disclosure, the channel width of the active layer of the tenth transistor is not less than 90 micrometers.

[0086] In some possible implementations provided in this disclosure, the channel width of the active layer of the eighth transistor is no greater than 50 micrometers.

[0087] In some possible implementations provided in this disclosure, the channel width of the active layer of the eleventh transistor is greater than the channel width of the active layer of the ninth transistor.

[0088] In some possible implementations provided in this disclosure, the channel width of the active layer of the eleventh transistor is not less than 90 micrometers.

[0089] In some possible implementations provided in this disclosure, the channel width of the active layer of the ninth transistor is no greater than 50 micrometers.

[0090] The display device provided in some embodiments of this disclosure includes the display panel described above.

[0091] Some embodiments of this disclosure provide driving methods, including:

[0092] The input sub-circuit, under the signal control of the second clock signal terminal, provides the input signal terminal signal to the first node;

[0093] The first control sub-circuit controls the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal;

[0094] The second control sub-circuit, under the control of the voltage of the second node and the signal of the first clock signal terminal, provides the signal of the second voltage signal terminal to the first node;

[0095] The potential stabilizing sub-circuit, under the signal control of the first voltage signal terminal, provides the voltage of the first node to the fourth node;

[0096] The cascaded sub-circuit, under the control of the voltages of the second node and the fourth node, provides a signal from the second voltage signal terminal or the first clock signal terminal to the cascaded output terminal;

[0097] The output circuit, under the control of the voltages of the first node and the second node, provides a signal from the reference signal terminal or the first voltage signal terminal to the drive output terminal.

[0098] In some possible implementations provided in this disclosure, the shift register unit further includes: a pull-down sub-circuit;

[0099] The method further includes: the pull-down sub-circuit providing a signal from the third voltage signal terminal to the first node under the control of the voltage of the first node or the fourth node.

[0100] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0101] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0102] Figure 1 Some structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;

[0103] Figure 2 Other structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;

[0104] Figure 3 One of the equivalent circuit diagrams of the shift register unit provided in the embodiments of this disclosure;

[0105] Figure 4 Further structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;

[0106] Figure 5 A second equivalent circuit diagram of a shift register unit provided in an embodiment of this disclosure;

[0107] Figure 6The third equivalent circuit diagram of the shift register unit provided in the embodiments of this disclosure;

[0108] Figure 7 Fourth equivalent circuit diagram of the shift register unit provided in the embodiments of this disclosure;

[0109] Figure 8 Fifth equivalent circuit diagram of the shift register unit provided in the embodiments of this disclosure;

[0110] Figure 9 Sixth equivalent circuit diagram of the shift register unit provided in the embodiments of this disclosure;

[0111] Figure 10 for Figure 3 , Figures 5 to 9 The provided signal timing simulation diagram for the shift register unit;

[0112] Figure 11 A comparison diagram of the signals at the drive output terminals of different shift register units;

[0113] Figure 12 This is a schematic diagram of the structure of a display device;

[0114] Figure 13 This is a schematic diagram of a planar structure of a display substrate;

[0115] Figure 14 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0116] Figure 15 for Figure 14 The corresponding timing diagram of the pixel driving circuit;

[0117] Figure 16 This is a schematic diagram of a cascaded gate drive circuit for a display device;

[0118] Figure 17 A schematic diagram of the layout structure of a shift register unit provided in an embodiment of this disclosure;

[0119] Figure 18 for Figure 17 A schematic diagram of the structure after the semiconductor layer pattern has been formed;

[0120] Figure 19 for Figure 17 A schematic diagram of the structure of the first conductive layer pattern;

[0121] Figure 20 for Figure 17 A schematic diagram of the structure after the first conductive layer pattern has been formed;

[0122] Figure 21 for Figure 17A schematic diagram of the structure of the second conductive layer pattern;

[0123] Figure 22 for Figure 17 A schematic diagram of the structure after the second conductive layer pattern has been formed;

[0124] Figure 23 for Figure 17 A schematic diagram of the structure of the third insulating layer pattern;

[0125] Figure 24 for Figure 17 A schematic diagram of the structure after the third insulating layer pattern has been formed;

[0126] Figure 25 for Figure 17 A schematic diagram of the structure of the third conductive layer pattern;

[0127] Figure 26 for Figure 17 A schematic diagram of the structure after the third conductive layer pattern has been formed;

[0128] Figure 27 for Figure 17 A schematic diagram of the structure of the fourth insulating layer pattern;

[0129] Figure 28 for Figure 17 A schematic diagram of the structure after the fourth insulating layer pattern is formed;

[0130] Figure 29 for Figure 17 A schematic diagram of the structure of the fourth conductive layer pattern;

[0131] Figure 30 for Figure 17 A schematic diagram of the structure after the fourth conductive layer pattern is formed;

[0132] Figure 31 A schematic diagram of the layout structure of another shift register unit provided in an embodiment of this disclosure;

[0133] Figure 32 for Figure 31 A schematic diagram of the structure of the first conductive layer pattern;

[0134] Figure 33 for Figure 31 A schematic diagram of the structure after the first conductive layer pattern has been formed;

[0135] Figure 34 for Figure 31 A schematic diagram of the structure of the second conductive layer pattern;

[0136] Figure 35 for Figure 31 A schematic diagram of the structure after the second conductive layer pattern has been formed;

[0137] Figure 36 for Figure 31 A schematic diagram of the structure of the third insulating layer pattern;

[0138] Figure 37 for Figure 31 A schematic diagram of the structure after the third insulating layer pattern has been formed;

[0139] Figure 38 for Figure 31 A schematic diagram of the structure of the third conductive layer pattern;

[0140] Figure 39 for Figure 31 A schematic diagram of the structure after the third conductive layer pattern has been formed;

[0141] Figure 40 for Figure 31 A schematic diagram of the structure of the fourth insulating layer pattern;

[0142] Figure 41 for Figure 31 A schematic diagram of the structure after the fourth insulating layer pattern is formed;

[0143] Figure 42 for Figure 31 A schematic diagram of the structure of the fourth conductive layer pattern;

[0144] Figure 43 for Figure 31 A schematic diagram of the structure after the fourth conductive layer pattern is formed. Detailed Implementation

[0145] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0146] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “electrical connection” or “connected” are not limited to physical or mechanical electrical connections, but can include electrical connections, whether direct or indirect.

[0147] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0148] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0149] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0150] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0151] The display substrate includes a pixel driving circuit, a light-emitting element, and a gate driving circuit. The gate driving circuit provides a third-pole signal to the pixel driving circuit, enabling it to drive the light-emitting element to emit light. The display substrate uses Low Temperature Poly-Silicon (LTPS) technology, which boasts advantages such as high resolution, high response speed, high brightness, and high aperture ratio. Despite its market popularity, LTPS technology also has some drawbacks, such as high production costs and high power consumption. Therefore, Low Temperature Polycrystalline Oxide (LTPO) technology emerged. Compared to LTPS technology, where the pixel driving circuit includes LTPS transistors, LTPO technology uses both LTPS transistors and metal-oxide transistors (MOTs). MOTs have lower leakage current, resulting in faster pixel response. The addition of an oxide layer to the display substrate further reduces the energy required to excite the pixels, thus lowering power consumption during screen display. The development of LTPO technology requires the gate driving circuit to provide a third-pole signal that meets the required voltage potential.

[0152] This disclosure provides a shift register unit, such as... Figure 1 As shown, it includes:

[0153] Shift register 100 is configured to output a cascaded signal through cascaded output terminal OUT1;

[0154] The output circuit 200 is electrically connected to the shift register 100. The output circuit 200 is configured to control the output terminal OUT2 to output a gate scan signal based on the signal of the reference signal terminal VREF and the signal of the first voltage signal terminal U1.

[0155] In some embodiments of this disclosure, such as Figure 2 As shown, shift register 100 includes:

[0156] The input sub-circuit 110 is configured to provide the signal from the input signal terminal IN to the first node N1 according to the signal from the second clock signal terminal CK2;

[0157] The first control sub-circuit 120 is electrically connected to the first clock signal terminal CK1, the second voltage signal terminal U2, the first node N1 and the second node N2, respectively, and is configured to control the voltage of the second node N2 according to the voltage of the first node N1 and the signal of the first clock signal terminal CK1.

[0158] The second control sub-circuit 130 is configured to transmit a signal from the second voltage signal terminal U2 to the first node N1 based on the voltage of the second node N2 and the signal of the first clock signal terminal CK1.

[0159] The potential stabilizing sub-circuit 140 is configured to transmit the voltage from the first node N1 to the fourth node N4 according to the signal from the first voltage signal terminal U1.

[0160] The cascaded sub-circuit 150 is configured to control the cascaded output terminal OUT1 to output a cascaded signal based on the voltages of the second node N2 and the fourth node N4.

[0161] In some embodiments of this disclosure, such as Figure 3 As shown, the input sub-circuit 110 includes: a first transistor T1; wherein, the first terminal of the first transistor T1 is electrically connected to the input signal terminal IN, the second terminal of the first transistor T1 is electrically connected to the first node N1, and the third terminal of the first transistor T1 is electrically connected to the second clock signal terminal CK2.

[0162] In some embodiments of this disclosure, such as Figure 3 As shown, the first control sub-circuit 120 includes: a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1;

[0163] The first terminal of the second transistor T2 is electrically connected to the first clock signal terminal CK1, the second terminal of the second transistor T2 is electrically connected to the second node N2, and the third terminal of the second transistor T2 is electrically connected to the third node N3; the first terminal of the third transistor T3 is electrically connected to the second voltage signal terminal U2, the second terminal of the third transistor T3 is electrically connected to the third node N3, and the third terminal of the third transistor T3 is electrically connected to the first node N1; the first terminal of the fourth transistor T4 is electrically connected to the second voltage signal terminal U2, the second terminal of the fourth transistor T4 is electrically connected to the second node N2, and the third terminal of the fourth transistor T4 is electrically connected to the first node N1; the first electrode of the first capacitor C1 is electrically connected to the third node N3, and the second electrode of the first capacitor C1 is electrically connected to the first clock signal terminal CK1.

[0164] In some embodiments of this disclosure, the first capacitor C1 can couple the signal from the first clock signal terminal to the third node N3.

[0165] In some embodiments of this disclosure, such as Figure 3 As shown, the second control sub-circuit 130 includes: a fifth transistor T5 and a sixth transistor T6;

[0166] The first terminal of the fifth transistor T5 is electrically connected to the second voltage signal terminal U2, the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the sixth transistor T6, and the third terminal of the fifth transistor T5 is electrically connected to the second node N2; the second terminal of the sixth transistor T6 is electrically connected to the first node N1, and the third terminal of the sixth transistor T6 is electrically connected to the first clock signal terminal CK1.

[0167] In some embodiments of this disclosure, such as Figure 3 As shown, the potential stabilizing sub-circuit 140 includes: a seventh transistor T7; wherein, the first terminal of the seventh transistor T7 is electrically connected to the first node N1, the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4, and the third terminal of the seventh transistor T7 is electrically connected to the first voltage signal terminal U1.

[0168] In some embodiments of this disclosure, such as Figure 3 As shown, the cascaded sub-circuit 150 includes: an eighth transistor T8, a ninth transistor T9, and a second capacitor C2;

[0169] The first terminal of the eighth transistor T8 is electrically connected to the first clock signal terminal CK1, the second terminal of the eighth transistor T8 is electrically connected to the cascaded output terminal OUT1, and the third terminal of the eighth transistor T8 is electrically connected to the fourth node N1; the first terminal of the ninth transistor T9 is electrically connected to the second voltage signal terminal U2, the second terminal of the ninth transistor T9 is electrically connected to the cascaded output terminal OUT1, and the third terminal of the ninth transistor T9 is electrically connected to the second node N2; the first electrode of the second capacitor C2 is electrically connected to the fourth node N4, and the second electrode of the second capacitor C2 is electrically connected to the cascaded output terminal OUT1.

[0170] In some embodiments of this disclosure, the second capacitor C2 can maintain the voltage difference between the fourth node N4 and the cascaded output terminal OUT1 signal.

[0171] In some embodiments of this disclosure, such as Figure 3 As shown, the output circuit 200 includes: a tenth transistor T10 and an eleventh transistor T11;

[0172] The first terminal of the tenth transistor T10 is electrically connected to the reference signal terminal VREF, the second terminal of the tenth transistor T10 is electrically connected to the drive output terminal OUT2, and the third terminal of the tenth transistor T10 is electrically connected to the first node N1; the first terminal of the eleventh transistor T11 is electrically connected to the first voltage signal terminal U1, the second terminal of the eleventh transistor T11 is electrically connected to the drive output terminal OUT2, and the third terminal of the eleventh transistor T11 is electrically connected to the second node N2.

[0173] In some embodiments of this disclosure, such as Figure 4As shown, the shift register 100 further includes a pull-down sub-circuit 160 configured to transmit a signal from the third voltage signal terminal U3 to the first node N1. The amplitude of the voltage signal at the third voltage signal terminal U3 is greater than the amplitude of the voltage signal at the first voltage signal terminal U1. That is, the absolute value of the voltage value at the third voltage signal terminal U3 is greater than the absolute value of the voltage value at the first voltage signal terminal U1.

[0174] In some embodiments of this disclosure, such as Figure 5 As shown, the pull-down sub-circuit 160 includes: a twelfth transistor T12; wherein, the first terminal of the twelfth transistor T12 is electrically connected to the third voltage signal terminal U3, the second terminal of the twelfth transistor T12 is electrically connected to the first node N1, and the third terminal of the twelfth transistor T12 is electrically connected to the fourth node N4.

[0175] In some embodiments of this disclosure, such as Figure 6 As shown, the pull-down sub-circuit 160 includes: a twelfth transistor T12; wherein, the first terminal of the twelfth transistor T12 is electrically connected to the third voltage signal terminal U3, the second terminal of the twelfth transistor T12 is electrically connected to the first node N1, and the third terminal of the twelfth transistor T12 is electrically connected to the first node N1.

[0176] The shift register unit provided in this disclosure can pull down the signal of the first node N1 to a lower voltage level by setting the pull-down sub-circuit 160, so that some transistors in the shift register unit can be fully turned on, thereby enabling the output signal voltage of the shift register unit to reach a predetermined voltage, improving the driving capability of the shift register unit, ensuring the conduction capability of the transistors in the pixel driving circuit, and thus improving the performance of the pixel driving circuit and the display effect of the display substrate.

[0177] In some embodiments of this disclosure, such as Figure 7 As shown, the cascaded sub-circuit 150 also includes a third capacitor C3; wherein, the first electrode of the third capacitor C3 is electrically connected to the second voltage signal terminal U2, and the second electrode of the third capacitor C3 is electrically connected to the cascaded output terminal OUT1.

[0178] In this disclosure, since the signal output by the cascaded output terminal OUT1 is a cascaded signal, meaning the signal line connected to OUT1 does not flow through the display area where the pixel driving circuit is located, the load on the signal line connected to OUT1 is relatively small. This makes it susceptible to the parasitic capacitance of some transistors in the output circuit, resulting in signal fluctuations at OUT1. This disclosure addresses this by adding a third capacitor C3, which stabilizes the signal output by OUT1 and improves the performance of the shift register unit.

[0179] In some embodiments of this disclosure, such as Figure 8 As shown, the output circuit 200 may further include: a fourth capacitor C4; wherein the first electrode of the fourth capacitor C4 is electrically connected to the second node N2, and the second electrode of the fourth capacitor C4 is electrically connected to the first voltage signal terminal U1.

[0180] In some embodiments of this disclosure, the fourth capacitor C4 can ensure the stability of the signal of the second node N2.

[0181] In some embodiments of this disclosure, such as Figure 9 As shown, the output circuit 200 further includes: a thirteenth transistor T13; wherein, the first terminal of the thirteenth transistor T13 is electrically connected to the first node N1, the second terminal of the thirteenth transistor T13 is electrically connected to the third terminal of the tenth transistor T10, and the third terminal of the thirteenth transistor T13 is electrically connected to the first voltage signal terminal U1.

[0182] In some embodiments of this disclosure, the thirteenth transistor T13 is a continuously conducting transistor, which can ensure the stability of the signal at the third terminal of the tenth transistor T10, avoid large deviations in the output signal of the shift register unit, and ensure the stability of the output signal of the shift register unit.

[0183] In some embodiments of this disclosure, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0184] In some embodiments of this disclosure, the first transistor T1 to the thirteenth transistor T13 may all be P-type transistors.

[0185] In some embodiments of this disclosure, the first voltage signal terminal U1 and the third voltage signal terminal U3 continuously provide low-level signals, and the second voltage signal terminal U2 continuously provides high-level signals.

[0186] In some embodiments of this disclosure, the amplitude of the voltage signal at the third voltage signal terminal U3 is greater than the amplitude of the voltage signal at the first voltage signal terminal U1.

[0187] In some embodiments of this disclosure, the signal of any one of the reference signal terminal VREF, the first clock signal terminal CK1, and the second clock signal terminal CK2 can be a periodic pulse signal.

[0188] In some embodiments of this disclosure, the signal of any one of the reference signal terminal VREF, the first clock signal terminal CK1, and the second clock signal terminal CK2 can be a clock signal.

[0189] In some embodiments of this disclosure, the signal at the reference signal terminal VREF and the signal at the first clock signal terminal CK1 are inverted signals, or they may not be inverted signals. When the signal at the reference signal terminal VREF and the signal at the first clock signal terminal CK1 are inverted signals, and the signal at the first clock signal terminal CK1 is an invalid signal when the signal at the reference signal terminal VREF is an active level signal; and when the signal at the reference signal terminal VREF is an invalid level signal, the signal at the first clock signal terminal CK1 is an active level signal.

[0190] In some embodiments of this disclosure, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are not simultaneously valid signals. For example, when the signal at the first clock signal terminal CK1 is valid, the signal at the second clock signal terminal CK2 is invalid; conversely, when the signal at the second clock signal terminal CK2 is valid, the signal at the first clock signal terminal CK1 is invalid.

[0191] In some embodiments of this disclosure, the signals of the cascade output terminal OUT1 and the drive output terminal OUT2 can be single pulse signals, and the signals of the cascade output terminal OUT1 and the drive output terminal OUT2 can be inverse signals of each other. That is, when the signal of the cascade output terminal OUT1 is a high-level signal, the signal of the drive output terminal OUT2 is a low-level signal; when the signal of the cascade output terminal OUT1 is a low-level signal, the signal of the drive output terminal OUT2 is a high-level signal.

[0192] In some embodiments of this disclosure, the cascade output terminal OUT1 is configured to output a cascade signal, which can be a low-level signal, and the drive output terminal OUT2 is configured to output a gate scan signal, which can be a high-level signal.

[0193] Figure 10 for Figure 3 , Figures 5 to 9 The provided signal timing simulation diagram for the shift register unit. Figure 10 This explanation assumes that all transistors in the shift register unit are P-type transistors. Understandably, at this time, the first voltage signal terminal U1 provides a first low-level signal VGL1, the second voltage signal terminal U2 provides a high-level signal VGH, and the third voltage signal terminal U3 provides a second low-level signal VGL2. Furthermore, the second low-level signal VGL2 provided by the third voltage signal terminal U3 is lower than the first low-level signal VGL1 provided by the first voltage signal terminal U1.

[0194] In some embodiments of this disclosure, for Figure 3 , Figures 5 to 9 The provided shift register unit is continuously turned on because the third terminal of the seventh transistor T7 is electrically connected to the first power supply terminal V1.

[0195] Combination Figure 5 and Figure 10 As shown, Figure 5 The operation of the provided control shift register unit includes the following stages:

[0196] In the first stage t1, i.e., the input stage, the input signal terminal IN, the reference signal terminal VREF, and the second clock signal terminal CK2 provide low-level signals, while the first clock signal terminal CK1 provides a high-level signal. At this time, the first transistor T1 is turned on, and the low-level signal provided by the input signal terminal IN is written to the first node N1. Since the first voltage signal terminal U1 continuously provides a low-level signal VGL1, the seventh transistor T7 is continuously turned on. At this time, the low-level signal of the first node N1 is written to the fourth node N4 via the seventh transistor T7, the eighth transistor T8 is turned on, and the high-level signal provided by the first clock signal terminal CK1 is written to the cascaded output terminal OUT1. The low-level signal of the first node N1 is written to the third terminal of the tenth transistor T10 via the thirteenth transistor T13, turning on the tenth transistor T10, and the low-level signal provided by the reference signal terminal VREF is written to the drive output terminal OUT2. Simultaneously, the twelfth transistor T12 is turned on, and the second low-level signal VGL2 provided by the third voltage signal terminal U3 is written to the first node N1, maintaining the signal at the first node N1 as a low-level signal. The third transistor T3 and the fourth transistor T4 are turned on, and the high-level signal VGH provided by the second voltage signal terminal U2 is written to the second node N2 and the third node N3 respectively. At this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are all turned off. The first clock signal terminal CK1 provides a high-level signal, and the sixth transistor T6 is turned off. The first capacitor C1 can couple the high-level signal provided by the first clock signal terminal CK1 to the third node N3, and the second capacitor C2 can maintain the voltage difference between the fourth node N4 and the cascaded output terminal OUT1. At this time, the cascaded output terminal OUT1 outputs the high-level signal provided by the first clock signal terminal CK1, driving the output terminal OUT2 to output the low-level signal provided by the reference signal terminal VREF.

[0197] In the second stage t2, i.e., the output stage, the first clock signal terminal CK1 provides a low-level signal, while the input signal terminal IN, the reference signal terminal VREF, and the second clock signal terminal CK2 provide high-level signals. At this time, the first transistor T1 is off, the second capacitor C2 can discharge, and the voltage of the first node N1 remains low. Since the first voltage signal terminal U1 continuously provides a low-level signal VGL1, the seventh transistor T7 remains on. At this time, the low-level signal of the first node N1 is written to the fourth node N4 via the seventh transistor T7, the eighth transistor T8 is turned on, and the low-level signal provided by the first clock signal terminal CK1 is written to the cascaded output terminal OUT1. The low-level signal of the first node N1 is written to the third terminal of the tenth transistor T10, the tenth transistor T10 is turned on, and the high-level signal provided by the reference signal terminal VREF is written to the drive output terminal OUT2. At the same time, the twelfth transistor T12 is turned on, and the second low-level signal VGL2 provided by the third voltage signal terminal U3 is written to the first node N1, and the voltage of the first node N1 is further pulled down, so that the eighth transistor T8 and the tenth transistor T10 are fully turned on. The third transistor T3 and the fourth transistor T4 are turned on, and the high-level signal VGH provided by the second voltage signal terminal U2 is written to the second node N2 and the third node N3 respectively. At this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are all turned off. The third transistor T3 is turned on, and the high-level signal VGH provided by the second voltage signal terminal U2 is written to the third node N3. At this time, the first clock signal terminal CK1 is still coupled to the third node N3 through the first capacitor C1, but the voltage of the third node N3 is still controlled by the second voltage signal terminal U2. In the output stage, the cascaded output terminal OUT1 outputs the low-level signal provided by the first clock signal terminal CK1, driving the output terminal OUT2 to output the high-level signal provided by the reference signal terminal VREF.

[0198] In the third stage t3, the input signal terminal IN and the first clock signal terminal CK1 provide a high-level signal, while the reference signal terminal VREF provides a low-level signal. The second clock signal terminal CK2 initially maintains a high-level signal before transitioning to a low-level signal. During the period when the second clock signal terminal CK2 maintains a high-level signal, the first transistor T1 is off, and the first node N1 is in a floating state. The voltage of the first node N1 is low at this time, and the low-level signal is written to the fourth node N4 via the continuously conducting seventh transistor T7. The eighth transistor T8 and the tenth transistor T10 are turned on, and the high-level signal provided by the first clock signal terminal CK1 is written to the cascaded output terminal OUT1. The low-level signal provided by the reference signal terminal VREF is written to the drive output terminal OUT2. The third transistor T3 and the fourth transistor T4 are turned on, and the high-level VGH signal provided by the second voltage signal terminal U2 is written to the second node N2 and the third node N3, respectively. At this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are all off. The first clock signal terminal CK1 provides a high-level signal, and the sixth transistor T6 is off. Therefore, during the period when the second clock signal terminal CK2 remains high, the cascaded output terminal OUT1 outputs the high-level signal provided by the first clock signal terminal CK1, driving the output terminal OUT2 to output the low-level signal provided by the reference signal terminal VREF. When the second clock signal terminal CK2 transitions to a low-level signal, the first transistor T1 is turned on, and the high-level signal provided by the input signal terminal IN is written to the first node N1. At this time, the third transistor T3 and the fourth transistor T4 are turned off, and the high-level signal of the first node N1 is written to the fourth node N4 via the continuously conducting seventh transistor T7. The eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 are turned off. Since the first clock signal terminal CK1 transitions from a low-level signal to a high-level signal, and due to the coupling effect of the first capacitor C1, the voltage of the third node N3 remains a high-level signal, and the second transistor T2 is turned off. The second node N2 is in a floating state, and the voltage of the second node N2 is high at this time. The fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are turned off. Therefore, during the stage when the second clock signal terminal CK2 transitions to a low level signal, both the cascade output terminal OUT1 and the drive output terminal OUT2 are in a floating state. At this time, the cascade output terminal OUT1 outputs a high level signal, and the drive output terminal OUT2 outputs a low level signal.

[0199] In the fourth stage t4, the input signal terminal IN, the reference signal terminal VREF, and the second clock signal terminal CK2 provide high-level signals, while the first clock signal terminal CK1 provides a low-level signal. At this time, the first transistor T1 is off, the first node N1 is in a floating state, and the voltage of the first node N1 is high. The third transistor T3 and the fourth transistor T4 are off. The high-level signal of the first node N1 is written to the fourth node N4 through the continuously conducting seventh transistor T7, while the eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 are off. As the first clock signal terminal CK1 transitions from high to low, and due to the coupling effect of the first capacitor C1, the voltage of the third node N3 is low, and the second transistor T2 is on. The low-level signal provided by the first clock signal terminal CK1 is written to the second node N2 through the second transistor T2, while the fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are on. At this time, the sixth transistor T6 is also on. The high-level signal VGH provided by the second voltage signal terminal U2 is written to the first node N1 via the fifth transistor T5 and the sixth transistor T6, and then to the cascaded output terminal OUT1 via the ninth transistor T9. The low-level signal VGL1 provided by the first voltage signal terminal U1 is written to the drive output terminal OUT2 via the eleventh transistor T11. During this stage, the cascaded output terminal OUT1 outputs the high-level signal provided by the second voltage signal terminal U2, and the drive output terminal OUT2 outputs the low-level signal provided by the first voltage signal terminal U1.

[0200] The operation of the shift register unit includes multiple third stages t3 and fourth stages t4, with the third stage t3 and the fourth stage t4 working alternately.

[0201] Figure 3 The provided shift register unit and Figure 5 The difference in the provided shift register units is that... Figure 5 The provided shift register unit includes a twelfth transistor T12. Figure 3 The provided shift register unit does not contain a twelfth transistor, T12. In addition, Figure 3 The working process of the provided shift register unit and Figure 5 The provided shift register unit operates in the same way.

[0202] The arrangement of the twelfth transistor T12 in this disclosure allows the first node N1 to be pulled down to the signal of the third voltage signal terminal U3, which has a lower voltage value, thereby increasing the conduction level of the eighth transistor T8 and the tenth transistor T10, so that the eighth transistor T8 and the tenth transistor T10 can be fully turned on.

[0203] Figure 6 The provided shift register unit and Figure 5The difference in the provided shift register unit lies in the node connected to the third terminal of the twelfth transistor T12. Figure 5 The following explanation uses the connection between the third terminal of the twelfth transistor T12 and the fourth node N4 as an example. Figure 6 The third terminal of the twelfth transistor T12 is connected to the first node N1. Since the signals at the first node N1 and the fourth node N4 are simultaneously high-level signals or simultaneously low-level signals, i.e. Figure 5 and Figure 6 The twelfth transistor T12 in the provided shift register unit can be simultaneously turned on or simultaneously turned off. Therefore, Figure 5 The working process of the provided shift register unit and Figure 6 The provided shift register unit operates in the same way.

[0204] Figure 7 The provided shift register unit and Figure 5 The difference in the provided shift register units is that... Figure 7 The provided shift register unit also includes a third capacitor C3. The third capacitor C3 is used to maintain the stability of the cascaded output OUT1 signal, and at the same time, it will not have any other impact on the operation of the shift register unit. Therefore, Figure 5 The working process of the provided shift register unit and Figure 7 The provided shift register unit operates in the same way.

[0205] Figure 8 The provided shift register unit and Figure 5 The difference in the provided shift register units is that... Figure 8 The provided shift register unit also includes a fourth capacitor C4, which is used to maintain the stability of the voltage at the second node N2 without affecting the operation of the shift register unit. Therefore, Figure 8 The working process of the provided shift register unit and Figure 7 The provided shift register unit operates in the same way.

[0206] Figure 9 The provided shift register unit and Figure 8 The difference in the provided shift register units is that... Figure 9 The provided shift register unit also includes a thirteenth transistor T13. Since the third terminal of the thirteenth transistor T13 is electrically connected to the first voltage signal terminal U1, the thirteenth transistor T13 is continuously turned on. Therefore, the thirteenth transistor T13 can be considered equivalent to a wire and will not affect the operation of other transistors in the shift register unit. Figure 9 The working process of the provided shift register unit and Figure 5The provided shift register unit operates in the same way.

[0207] It is understood that, in some embodiments of this disclosure, the shift register unit may include: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; or it may include: a first capacitor C1 and a second capacitor C2; or it may include: a first capacitor C1, a second capacitor C2, and a third capacitor C3; or it may include: a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. Those skilled in the art can configure it according to actual needs.

[0208] Figure 11 OUT2-0 refers to the information provided in this application. Figure 3 The signal output from the drive output terminal of the shift register unit provided in this application, OUT2-M refers to the signal provided in this application. Figures 5 to 9 The signal output from the drive output terminal of any shift register unit. For example... Figure 11 As shown, in other operating phases besides the output phase, the voltage value of the OUT2-M signal is lower than the voltage value of the OUT2-0 signal, and in the output phase, the rising edge duration of the OUT2-M signal is less than the rising edge duration of the OUT2-0 signal. That is, the shift register unit provided in some embodiments of this disclosure can pull down the voltage value of the signal output by the drive output terminal, thereby improving the performance of the shift register unit.

[0209] This disclosure also provides a method for driving a shift register unit, configured to drive the shift register unit. The method for driving the shift register unit may include the following steps:

[0210] Step 100: Under the signal control of the second clock signal terminal, the input sub-circuit provides the input signal terminal signal to the first node.

[0211] Step 200: The first control sub-circuit controls the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal.

[0212] Step 300: The second control sub-circuit, under the control of the voltage of the second node and the signal of the first clock signal terminal, provides the signal of the second voltage signal terminal to the first node.

[0213] Step 400: Under the signal control of the first voltage signal terminal, the potential stabilizing sub-circuit provides the voltage of the first node to the fourth node.

[0214] Step 500: Under the control of the voltages of the second and fourth nodes, the cascaded sub-circuit provides a signal from the second voltage signal terminal or the first clock signal terminal to the cascaded output terminal.

[0215] Step 600: Under the control of the voltages of the first node and the second node, the output circuit provides a signal from the reference signal terminal or the first voltage signal terminal to the drive output terminal.

[0216] The shift register unit is the shift register unit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0217] In some embodiments of this disclosure, the shift register unit may further include a pull-down sub-circuit; the driving method of the shift register unit may further include: the pull-down sub-circuit providing a signal from the third voltage signal terminal to the first node under the control of the voltage of the first node or the fourth node.

[0218] This disclosure also provides a display device. Figure 12 This is a schematic diagram of the structure of a display device. Figure 12 As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a display substrate. The display substrate includes pixels arranged in an array. The timing controller is connected to the data signal driver, the scan signal driver, and the light emission signal driver. The data signal driver is connected to multiple data signal lines (D1 to Dn), the scan signal driver is connected to multiple scan signal lines (S1 to Sm), and the light emission signal driver is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels P. ij i and j can be natural numbers, and there is at least one sub-pixel P. ijThe system may include circuit units and light-emitting devices connected to the circuit units. The circuit units may include pixel driving circuits, which may be electrically connected to scan signal lines, light-emitting signal lines, and data signal lines, respectively. In some embodiments of this disclosure, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver, and clock signals, transmit stop signals, etc., of specifications suitable for the light-emitting signal driver to the light-emitting signal driver to the light-emitting signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may use a clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan signal driver may receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, a scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register unit and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. An LED signal driver can generate transmit signals to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, an LED signal driver can sequentially provide transmit signals with off-level pulses to LED signal lines E1 to Eo. For example, the LED signal driver can be configured as a shift register unit and can generate transmit signals by sequentially transmitting transmit stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0219] In some embodiments of this disclosure, the display device can be a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display device. This display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light-emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0220] Figure 13 This is a schematic diagram of a planar structure of a display substrate. Figure 13 As shown, the display substrate may include multiple pixel units P arranged in a matrix. Each pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and at least one third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are electrically connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and to control the pixel driving circuit to output a corresponding current. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are electrically connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0221] In some embodiments of this disclosure, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In some embodiments of this disclosure, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not impose any limitations on this arrangement.

[0222] In some embodiments of this disclosure, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement. Figure 13 This explanation uses a horizontal, side-by-side arrangement as an example.

[0223] In some embodiments of this disclosure, a pixel unit may further include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0224] In some embodiments of this disclosure, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0225] In some embodiments of this disclosure, the organic light-emitting layer may include a stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In some embodiments of this disclosure, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole block layers of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0226] In some embodiments of this disclosure, the display substrate is an LTPO display substrate.

[0227] Figure 14 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In some embodiments of this disclosure, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 14 As shown, the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7) and one capacitor C.

[0228] like Figure 14As shown, the first terminal of the first transistor M1 is electrically connected to the first initial signal line INIT1, the second terminal of the first transistor M1 is electrically connected to the first node Q1, and the third terminal of the first transistor M1 is electrically connected to the reset signal line Reset; the first terminal of the second transistor M2 is electrically connected to the first node Q1, the second terminal of the second transistor M2 is electrically connected to the third node Q3, and the third terminal of the second transistor M2 is electrically connected to the second scan signal line Gate2; the first terminal of the third transistor M3 is electrically connected to the second node Q2, the second terminal of the third transistor M3 is electrically connected to the third node Q3, and the third terminal of the third transistor M3 is electrically connected to the first node Q1; the first terminal of the fourth transistor M4 is electrically connected to the data signal line Data, the second terminal of the fourth transistor M4 is electrically connected to the second node Q2, and the third terminal of the fourth transistor M4 is electrically connected to the data signal line Data. The first terminal of the fifth transistor M5 is electrically connected to the first scan signal line Gate1; the first terminal of the fifth transistor M5 is electrically connected to the high-level power supply line VDD, the second terminal of the fifth transistor M5 is electrically connected to the second node Q2, and the third terminal of the fifth transistor M5 is electrically connected to the light-emitting signal line EM; the first terminal of the sixth transistor M6 is electrically connected to the third node Q3, the second terminal of the sixth transistor M6 is electrically connected to the fourth node Q4, and the third terminal of the sixth transistor M6 is electrically connected to the light-emitting signal line EM; the first terminal of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, the second terminal of the seventh transistor M7 is electrically connected to the fourth node Q4, and the third terminal of the seventh transistor M7 is electrically connected to the first scan signal line Gate1; the first plate of capacitor C is electrically connected to the first node Q1, and the second plate of capacitor C is electrically connected to the high-level power supply line VDD.

[0229] In some embodiments of this disclosure, the first transistor M1 to the seventh transistor M7 in the pixel driving circuit can be a low-temperature polysilicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or both. The active layer of the LTPS is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form an LTPO display substrate allows for the utilization of both advantages, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0230] In some embodiments of this disclosure, the first transistor M1 and the second transistor M2 are of the opposite transistor type to the third transistor M3 through the seventh transistor M7. For example, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 through the seventh transistor M7 may be P-type transistors.

[0231] In some embodiments of this disclosure, the first transistor M1 and the second transistor M2 may be oxide transistors, and the third transistor M3 to the seventh transistor M7 may be low-temperature polycrystalline silicon transistors.

[0232] In some embodiments of this disclosure, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal; the voltage value of the signal of the first initial signal line INIT1 can be -3V.

[0233] In some embodiments of this disclosure, the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal; the voltage value of the signal of the second initial signal line INIT2 can be 0V.

[0234] In some embodiments of this disclosure, the light-emitting device L can be electrically connected to the fourth node Q4 and the low-level power line VSS, respectively.

[0235] In some embodiments of this disclosure, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0236] Figure 15 for Figure 14 The corresponding timing diagram of the pixel driving circuit. The following is a summary... Figure 14 The operation of the example pixel driving circuit during the display stage illustrates an exemplary embodiment of this disclosure. Figure 15 This explanation uses the example of first transistor M1 and second transistor M2 being N-type transistors, and third transistor M3 through seventh transistor M7 being P-type transistors. Figure 26 The pixel driving circuit in B includes transistors M1 to M7, a capacitor C, and eight signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, reset signal line Reset, first initial signal line INIT1, second initial signal line INIT2, light emission signal line EM, and high-level power supply line VDD).

[0237] Combination Figure 14 and Figure 15 The operation of the pixel driving circuit can include:

[0238] The first stage, P1, is called the initialization stage. The Reset signal line is high, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node Q1 through the turned-on first transistor M1 to initialize (i.e. reset) the first node Q1, clear its internal pre-stored voltage, and complete the initialization.

[0239] The second stage, P2, is called the data writing stage or threshold compensation stage. The first scan signal line, Gate1, is at a low level, the second scan signal line, Gate2, is at a high level, and the data signal line, Data, outputs the data voltage. During this stage, since the first node, Q1, is at a low level, the third transistor, M3, is turned on. The first scan signal line Gate1 is at a low level, turning on the fourth transistor M4 and the seventh transistor M7. The second scan signal line Gate2 is at a high level, turning on the second transistor M2. The data voltage output from the data signal line Data is supplied to the first node N1 via the turned-on fourth transistor M4, the second node Q2, the turned-on third transistor M3, the third node Q3, and the turned-on second transistor M2. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor M3 is charged into capacitor C until the voltage of the first node Q1 is Vd-|Vth|, where Vd is the data voltage output from the data signal line Data and Vth is the threshold voltage of the third transistor M3. The seventh transistor M7 is turned on, and the signal from the second initial signal line INIT2 is written to the fourth node Q4 via the turned-on seventh transistor M7. This initializes (i.e., resets) the first electrode of the light-emitting device L, clearing its internal pre-stored voltage and completing the initialization.

[0240] The third stage, P3, is called the light-emitting stage. The signal on the light-emitting signal line EM is a low-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output by the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the light-emitting device L to emit light.

[0241] During the pixel driving circuit operation, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its third and first terminals. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor M3 is:

[0242] I = K (Vgs-Vth) 2 =K [(Vdd-Vd+|Vth|)-Vth] 2 =K (Vdd-Vd) 2

[0243] Where, I is the driving current flowing through the third transistor M3, which is also the driving current for driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the third and first electrodes of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0244] The display substrate provided by the embodiments of the present disclosure may include: a substrate substrate, and sub-pixels, gate lines, and a gate driving circuit provided on the substrate substrate. The substrate substrate is provided with a display area and a non-display area. The gate driving circuit is located in the non-display area, and the sub-pixels and gate lines are located in the display area. The gate lines are electrically connected to the sub-pixels and the gate driving circuit respectively.

[0245] In some embodiments of the present disclosure, the sub-pixel includes: a pixel driving circuit and a light-emitting device. When the pixel driving circuit is Figure 14 the provided pixel driving circuit, the gate line may include: at least one of a reset signal line, a first scan signal line, a second scan signal line, and a light-emitting signal line.

[0246] Figure 16 is a cascade schematic diagram of the gate driving circuit. As Figure 16 shown, the cascade output terminal OUT1 of the i-th stage shift register unit GOA(i) is connected to the signal input terminal IN of the i+1-th stage shift register unit GOA(i+1), 1≤i<N, and N is the total number of stages of the shift register unit.

[0247] In some embodiments of the present disclosure, as Figure 16 shown, the clock signal is respectively input into the second clock signal terminal CK2 and the first clock signal terminal CK1 of multiple shift register units through the first clock signal line CLK1 and the second clock signal line CLK2.

[0248] In some embodiments of the present disclosure, as Figure 16 shown, the clock signal is respectively input into the reference signal terminal VREF of multiple shift register units through the third clock signal line CLK3 and the fourth clock signal line CLK4.

[0249] In some embodiments of the present disclosure, as Figure 16 shown, the driving output terminal OUT2 of the shift register unit may be electrically connected to the gate line.

[0250] In some embodiments of the present disclosure, as Figure 16As shown, the second clock signal terminal CK2 of the i-th stage shift register unit is electrically connected to one of the first clock signal lines CLK1 and CLK2, and the first clock signal terminal CK1 of the i-th stage shift register unit is electrically connected to the other of the first clock signal lines CLK1 and CLK2. The signal lines connected to the second clock signal terminals of adjacent shift register units are different, and the signal lines connected to the first clock signal terminals of adjacent shift register units are different. For example, the second clock signal terminal CK2 of the odd-level shift register unit can be electrically connected to the first clock signal line CLK1, and the first clock signal terminal CK1 of the odd-level shift register unit can be electrically connected to the second clock signal line CLK2. The second clock signal terminal CK2 of the even-level shift register unit can be electrically connected to the second clock signal line CLK2, and the first clock signal terminal CK1 of the even-level shift register unit can be electrically connected to the first clock signal line CLK1. Alternatively, the second clock signal terminal CK2 of the odd-level shift register unit can be electrically connected to the second clock signal line CLK2, and the first clock signal terminal CK1 of the odd-level shift register unit can be electrically connected to the first clock signal line CLK1. The second clock signal terminal CK2 of the even-level shift register unit can be electrically connected to the first clock signal line CLK1, and the first clock signal terminal CK1 of the even-level shift register unit can be electrically connected to the second clock signal line CLK2. Figure 16 The following example illustrates the connection between the second clock signal terminal CK2 of the odd-numbered shift register unit and the first clock signal line CLK1, the first clock signal terminal CK1 of the odd-numbered shift register unit and the second clock signal line CLK2, the second clock signal terminal CK2 of the even-numbered shift register unit and the second clock signal line CLK2, and the first clock signal terminal CK1 of the even-numbered shift register unit and the first clock signal line CLK1.

[0251] In some embodiments of this disclosure, such as Figure 16 As shown, the reference signal terminal VREF of the i-th stage shift register unit is electrically connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4, and the reference signal terminal VREF of the (i+1)-th stage shift register unit is electrically connected to the other of the third clock signal line CLK3 and the fourth clock signal line CLK4. For example, the reference signal terminal VREF of the odd-numbered stage shift register unit is electrically connected to the third clock signal line CLK3, and the reference signal terminal VREF of the even-numbered stage shift register unit is electrically connected to the fourth clock signal line CLK4; alternatively, the reference signal terminal VREF of the odd-numbered stage shift register unit is electrically connected to the fourth clock signal line CLK4, and the reference signal terminal VREF of the even-numbered stage shift register unit is electrically connected to the third clock signal line CLK3. Figure 16The following explanation uses the example of the reference signal terminal VREF of the odd-numbered shift register unit being electrically connected to the third clock signal line CLK3, and the reference signal terminal VREF of the even-numbered shift register unit being electrically connected to the fourth clock signal line CLK4.

[0252] In some embodiments of this disclosure, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and conductive foil. The flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0253] In some embodiments of this disclosure, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In some embodiments of this disclosure, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the preparation of the substrate.

[0254] In some embodiments of this disclosure, Figure 17 This is a schematic diagram of the display substrate. Figure 17 Therefore Figure 8 The provided shift register unit will be used as an example for explanation. Figures 16 to 17As shown, the display substrate may further include: an input signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first voltage signal line VGL1, a second voltage signal line VGH, and a third voltage signal line VGL2 disposed on the substrate and located in the non-display area. The number of first voltage signal lines VGL1 is at least one.

[0255] In some embodiments of this disclosure, the input signal terminal IN of the first-stage shift register unit GOA (1) is electrically connected to the input signal line STV, the first voltage signal terminal U1 of the i-th stage shift register unit is electrically connected to the first voltage signal line VGL1, the second voltage signal terminal U2 of the i-th stage shift register unit is electrically connected to the second voltage signal line VGH, and the third voltage signal terminal U3 of the i-th stage shift register unit is electrically connected to the third voltage signal line VGL2.

[0256] In some embodiments of this disclosure, any one of the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1, the second voltage signal line VGH, and the third voltage signal line VGL2 extends along the first direction D1, and the gate line extends along the second direction D2, with the first direction D1 intersecting the second direction D2.

[0257] In some embodiments of this disclosure, such as Figure 17 As shown, the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, and the first voltage signal line VGL1 are arranged sequentially along the direction close to the display area, and are located on the side of the shift register unit away from the display area.

[0258] In some embodiments of this disclosure, such as Figure 17 As shown, the shift register unit includes multiple transistors, and the second voltage signal line VGH is located on the side of the first voltage signal line VGL1 near the display area, and is located between the multiple transistors of the shift register unit.

[0259] In some embodiments of this disclosure, such as Figure 17 As shown, the third voltage signal line VGL2 is located on the side of the second voltage signal line VGH closer to the display area, and its orthographic projection on the substrate overlaps with the orthographic projection of the shift register unit on the substrate.

[0260] In some embodiments of this disclosure, such as Figure 17As shown, the shift register unit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. At least a portion of any one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the first capacitor C1 is located between the first voltage signal line VGL1 and the second voltage signal line VGH.

[0261] In some embodiments of this disclosure, such as Figure 17 As shown, the shift register unit includes: a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a twelfth transistor T12, and a second capacitor C2. At least a portion of any one of the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the second capacitor C2 is located on the side of the second voltage signal line VGH closest to the display area.

[0262] In some embodiments of this disclosure, such as Figure 17 As shown, the orthographic projection of the third voltage signal line VGL2 on the substrate overlaps with the orthographic projections of the eighth transistor T8, the ninth transistor T9, and the second capacitor C2 on the substrate.

[0263] In some embodiments of this disclosure, such as Figure 17 As shown, the display substrate may further include a third clock signal line CLK3 and a fourth clock signal line CLK4 disposed on the substrate and located in the non-display area, wherein either the third clock signal line CLK3 or the fourth clock signal line CLK4 extends along the first direction D1.

[0264] In some embodiments of this disclosure, such as Figure 17 As shown, there are two first voltage signal lines VGL1. The first voltage signal line VGL1 closer to the display area is located on the side of either the third clock signal line CLK3 or the fourth clock signal line CLK4 that is closer to the display area. The first voltage signal line VGL1 farther from the display area is located on the side of either the first clock signal line CLK1 or the second clock signal line CLK2 that is closer to the display area, and is located on the side of the second voltage signal line VGH that is farther from the display area.

[0265] In some embodiments of this disclosure, such as Figure 17 As shown, the shift register unit also includes: a tenth transistor T10, an eleventh transistor T11, and a fourth capacitor C4. At least a portion of any one of the tenth transistor T10, the eleventh transistor T11, and the fourth capacitor C4 is located on the side of the first voltage signal line VGL1 closest to the display area.

[0266] In some embodiments of this disclosure, such as Figure 17 As shown, the orthographic projection of the first voltage signal line VGL1 near the display area on the substrate overlaps with the orthographic projection of the fourth capacitor C4 on the substrate.

[0267] In some embodiments of this disclosure, such as Figure 17 As shown, the active layer T121 of the twelfth transistor T12 extends along the first direction D1, either the first electrode or the second electrode of the twelfth transistor T12 extends along the second direction D2, and the third electrode T82 of the twelfth transistor T12 extends at least partially along the second direction D2.

[0268] In some embodiments of this disclosure, such as Figure 17 As shown, the width of any one of the two first voltage signal lines VGL1, the second voltage signal line VGH, and the third voltage signal line VGL2 along the second direction D2 is less than the width of any one of the first clock signal lines CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 along the second direction D2.

[0269] In some embodiments of this disclosure, since the clock signal line is an AC signal, the wider width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 along the second direction D2 can effectively reduce the load on the signal line.

[0270] In some embodiments of this disclosure, the channel width of the active layer of the tenth transistor T10 is greater than the channel width of the active layer of the eighth transistor T8.

[0271] In some embodiments of this disclosure, the channel width of the active layer of the tenth transistor T10 is not less than 90 micrometers. Exemplarily, the channel width of the active layer of the tenth transistor T10 may be approximately 100 micrometers.

[0272] In some embodiments of this disclosure, the channel length of the active layer of the tenth transistor T10 can be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the tenth transistor T10 can be approximately 100 / 3.5.

[0273] In some embodiments of this disclosure, the channel width of the active layer of the eighth transistor T8 is no greater than 50 micrometers. Exemplarily, the channel width of the active layer of the eighth transistor T8 can be approximately 25 micrometers.

[0274] In some embodiments of this disclosure, the channel length of the active layer of the eighth transistor T8 can be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the eighth transistor T8 can be approximately 25 / 3.5.

[0275] In some embodiments of this disclosure, the channel width of the active layer of the eleventh transistor T11 is greater than the channel width of the active layer of the fifth transistor.

[0276] In some embodiments of this disclosure, the channel width of the active layer of the eleventh transistor T11 is not less than 90 micrometers. Exemplarily, the channel width of the active layer of the eleventh transistor T11 can be approximately 100 micrometers.

[0277] In some embodiments of this disclosure, the channel length of the active layer of the eleventh transistor T11 can be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the eleventh transistor T11 can be approximately 100 / 3.5.

[0278] In some embodiments of this disclosure, the channel width of the active layer of the ninth transistor T9 is no greater than 50 micrometers. Exemplarily, the channel width of the active layer of the ninth transistor T9 can be approximately 25 micrometers.

[0279] In some embodiments of this disclosure, the channel length of the active layer of the ninth transistor T9 can be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the ninth transistor T9 can be approximately 25 / 3.5.

[0280] In some embodiments of this disclosure, the display substrate may further include: a driving structure layer disposed on the substrate; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; the shift register unit includes: a plurality of transistors and a plurality of capacitors, any one of the capacitors including: a first electrode and a second electrode;

[0281] The semiconductor layer includes at least: an active layer of multiple transistors located in at least one shift register unit;

[0282] The first conductive layer includes at least: the third electrode of a plurality of transistors located in at least one shift register unit and the first electrode of a plurality of capacitors;

[0283] The second conductive layer includes at least: the second plates of a plurality of capacitors located in at least one shift register unit;

[0284] The third conductive layer includes at least: an initial signal line, a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, a third clock signal line, a fourth clock signal line, and the first and second terminals of a plurality of transistors located in at least one shift register unit;

[0285] The fourth conductive layer includes at least the third power line.

[0286] In some embodiments of this disclosure, the driving structure layer may further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a planarization layer, wherein the first insulating layer is located between the semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, the fourth insulating layer is located between the third conductive layer and the fourth conductive layer, the fifth insulating layer is located on the side of the fourth conductive layer away from the substrate, and the planarization layer is located on the side of the fifth insulating layer away from the substrate.

[0287] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0288] The first step is to form a semiconductor pattern on a substrate, including: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer pattern. For example... Figure 18 As shown, Figure 18 for Figure 17 A schematic diagram after the semiconductor layer pattern has been formed.

[0289] In some embodiments of this disclosure, such as Figure 18 As shown, the semiconductor layer may include: the active layer T1a of the first transistor to the active layer T12a of the twelfth transistor located in at least one shift register unit.

[0290] In some embodiments of this disclosure, such as Figure 18 As shown, the active layer T1a of the first transistor and the active layer T7a of the seventh transistor are integrally formed; the active layer T2a of the second transistor and the active layer T4a of the fourth transistor are integrally formed; the active layer T5a of the fifth transistor and the active layer T6a of the sixth transistor are integrally formed; and the active layer T10a of the tenth transistor and the active layer T11a of the eleventh transistor are integrally formed. The active layers T3a of the third transistor, T8a of the eighth transistor, T9a of the ninth transistor, and T12a of the twelfth transistor can be individually configured.

[0291] In some embodiments of this disclosure, such as Figure 18 As shown, the active layer T1a of the first transistor (also the active layer T7a of the seventh transistor) is located on the side away from the display area. The active layer T2a of the second transistor (also the active layer T4a of the fourth transistor) is located on the side of the active layer T1a of the first transistor closer to the display area. The active layer T3a of the third transistor is located on the side of the active layer T1a of the first transistor closer to the display area, and the active layer T3a of the third transistor is located on the side of the active layer T2a of the second transistor (also the active layer T4a of the fourth transistor) of the current stage shift register unit closer to the next stage shift register unit. The active layer T5a of the fifth transistor (also the active layer T6a of the sixth transistor) and the active layer T12a of the twelfth transistor are arranged along the first direction D1, and are located on the side of the active layer T2a of the second transistor (also the active layer T4a of the fourth transistor) closer to the display area. The active layers T9a of the ninth transistor and T8a of the eighth transistor are arranged along the first direction D1 and are located on the side of the active layer T5a of the fifth transistor (which is also the active layer T6a of the sixth transistor) closer to the display area. Specifically, the active layer T9a of the ninth transistor in this stage shift register unit is located on the side of the active layer T8a of the eighth transistor in this stage shift register unit closer to the previous stage shift register unit. The active layer T10a of the tenth transistor (which is also the active layer T11a of the eleventh transistor) is located on the side of the active layer T8a of the eighth transistor closer to the display area.

[0292] In some embodiments of this disclosure, such as Figure 18 As shown, the active layers T1a of the first transistor (also the active layer T7a of the seventh crystal), T5a of the fifth transistor (also the active layer T6a of the sixth crystal), T12a of the twelfth transistor, T8a of the eighth transistor, T9a of the ninth transistor, and T10a of the tenth transistor (also the active layer T11a of the eleventh crystal) are all strip-shaped and extend along the first direction D1. The active layers T2a of the second transistor (also the active layer T4a of the fourth crystal) and T3a of the third transistor are strip-shaped and extend along the second direction D2.

[0293] In some embodiments of this disclosure, such as Figure 18 As shown, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The first and second regions are conductive after the subsequent formation of the first conductive layer, and are therefore also referred to as conductive regions. In some embodiments of this disclosure, the second region T1a-2 of the active layer T1a of the first transistor can simultaneously serve as the first region T7a-1 of the active layer T7a of the seventh transistor; the second region T2a-2 of the active layer T2a of the second transistor can simultaneously serve as the second region T4a-2 of the active layer T4a of the fourth transistor; the second region T5a-2 of the active layer T5a of the fifth transistor can simultaneously serve as the first region T6a-1 of the active layer T6a of the sixth transistor; and the second region T10a-2 of the active layer T10a of the tenth transistor can simultaneously serve as the second region T11a-2 of the active layer T11a of the eleventh transistor. The first region T1a-1 of the active layer T1a of the first transistor, the first region T2a-1 of the active layer T2a of the second transistor, the first region T3a-1 of the active layer T3a of the third transistor, the second region T3a-2 of the active layer T3a of the third transistor, the first region T4a-1 of the active layer T4a of the fourth transistor, the first region T5a-1 of the active layer T5a of the fifth transistor, the second region T6a-2 of the active layer T6a of the sixth transistor, the second region T7a-2 of the active layer T7a of the seventh transistor, the first region T8a-1 of the active layer T8a of the eighth transistor, the second region T8a-2 of the active layer T8a of the eighth transistor, the first region T9a-1 of the active layer T9a of the ninth transistor, the second region T9a-2 of the active layer T9a of the ninth transistor, the first region T10a-1 of the active layer T10a of the tenth transistor, and the first region T11a-1 of the active layer T11a of the eleventh transistor can be set individually.

[0294] The second step, forming a first conductive pattern, includes: depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; and patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive pattern disposed on the first insulating layer pattern, such as... Figure 19 and Figure 20 As shown, Figure 19 for Figure 17 A schematic diagram of the first conductive layer pattern in the image. Figure 20 for Figure 17 A schematic diagram showing the formation of the first conductive layer pattern. In some embodiments of this disclosure, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0295] In some embodiments of this disclosure, such as Figure 19 and Figure 20As shown, the first conductive layer pattern may include: the third electrode T1b of the first transistor to the third electrode T12b of the twelfth transistor located in at least one level shift register unit, the first electrode C1-1 of the first capacitor, the first electrode C2-1 of the second capacitor, the first electrode C4-1 of the fourth capacitor, and the first connection portion L1.

[0296] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the third terminal T2b of the second transistor and the first plate C1-1 of the first capacitor are integrally formed. The third terminals T3b of the third transistor, T4b of the fourth transistor, and T10b of the tenth transistor are integrally formed. The third terminals T5b of the fifth transistor, T9b of the ninth transistor, T11b of the eleventh transistor, and the first plate C4-1 of the fourth capacitor are integrally formed. The third terminals T8b of the eighth transistor, T12b of the twelfth transistor, and the first plate C2-1 of the second capacitor are integrally formed. The third terminals T1b of the first transistor, T6b of the sixth transistor, T7b of the seventh transistor, and the first connection portion L1 can be individually provided.

[0297] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the third electrode T1b of the first transistor includes: a first third electrode portion T1b-1 and a second third electrode portion T1b-2. The first third electrode portion T1b-1 of the first transistor is in the form of a " The first transistor is in the shape of a "". The second and third electrode portions T1b-2 of the first transistor extend along the second direction D2, and the first and third electrode portions T1b-1 of the first transistor are connected to the middle portions of the second and third electrode portions T1b-2 of the first transistor.

[0298] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the first plate C1-1 of the first capacitor can be square in shape, and the third electrode T2b of the second transistor can be strip-shaped and extend along the first direction D1. The third electrode T2b of the second transistor is located on the side of the first plate C1-1 of the first capacitor closer to the previous stage shift register unit.

[0299] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the shape of the first plate C2-1 of the second capacitor can be “ The shape of the third electrode T8b of the eighth transistor and the third electrode T12b of the twelfth transistor can be strip-shaped and extend along the second direction D2. The end of the third electrode T8b of the eighth transistor is connected to the middle of the first plate C2-1 of the second capacitor extending along the first direction D1. The third electrode T12b of the twelfth transistor is located on the side of the third electrode T8b of the eighth transistor away from the display area.

[0300] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the first plate C4-1 of the fourth capacitor can be square in shape and extends along the first direction D1. The third electrode T11b of the eleventh transistor includes: multiple first branch segments T11b-1, which extend along the second direction D2 and are arranged along the first direction D1. The third electrode T9b of the ninth transistor is located on the side of the first plate C4-1 of the fourth capacitor away from the display area, and the third electrode T5b of the fifth transistor is located on the side of the third electrode T9b of the ninth transistor away from the display area. Figure 19 and Figure 20 This explanation will be based on the example of the eleventh transistor's third terminal T11b containing two first branch segments T11b-1.

[0301] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the third terminal T10b of the tenth transistor includes a first connection segment T10b-1 and multiple second branch segments T10b-2. The first connection segment T10b-1 extends along a first direction D1, and the multiple second branch segments T10b-2 extend along a second direction D2, and the multiple second branch segments T10b-2 are arranged along the first direction D1. The first connection segment T10b-1 is equivalent to the "back of a comb," and the multiple second branch segments T10b-2 are equivalent to the "teeth of a comb." Figure 19 and Figure 20 The following explanation uses the example of the third terminal T10b of the tenth transistor containing four second branch segments T10b-2. The third terminals T3b of the third transistor and T4b of the fourth transistor are located on the side of the third terminal T10b of the tenth transistor away from the display area, and the third terminal T3b of the third transistor is located on the side of the third terminal T4b of the fourth transistor closer to the next-stage shift register unit. The third terminals T3b of the third transistor and T4b of the fourth transistor extend at least partially along the first direction D1.

[0302] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the third electrode T6b of the sixth transistor, the third electrode T7b of the seventh transistor, and the first connection L1 can be strip-shaped and extend at least partially along the second direction D2.

[0303] In some embodiments of this disclosure, such as Figure 19 and Figure 20 As shown, the first third electrode portion T1b-1 and the second third electrode portion T1b-2 of the third electrode T1b of the first transistor are respectively disposed across the active layer T1a of the first transistor; the third electrode T2b of the second transistor is disposed across the active layer T2a of the second transistor; the third electrode T3b of the third transistor is disposed across the active layer T3a of the third transistor; the third electrode T4b of the fourth transistor is disposed across the active layer T4a of the fourth transistor; the third electrode T5b of the fifth transistor is disposed across the active layer T5a of the fifth transistor; and the third electrode T6b of the sixth transistor is disposed across the active layer T6a of the sixth transistor. The third electrode T7b of the seventh transistor is located on the active layer T6a of the transistor; the third electrode T8b of the eighth transistor is located on the active layer T8a of the eighth transistor; the third electrode T9b of the ninth transistor is located on the active layer T9a of the ninth transistor; multiple second branch segments T10b-2 of the third electrode T10b of the tenth transistor are located on the active layer T10a of the tenth transistor; multiple first branch segments T11b-1 of the third electrode T11b of the eleventh transistor are located on the active layer T11a of the eleventh transistor. That is, the extension direction of the third electrode of at least one transistor intersects (is perpendicular to) the extension direction of the active layer.

[0304] In some embodiments of this disclosure, the process further includes a conductor-enhancing process. The conductor-enhancing process involves, after forming the first conductive layer, using the semiconductor layer corresponding to the third electrode shielding region of multiple transistors (i.e., the region where the semiconductor layer and the third electrode overlap) as the channel region of the transistor. The semiconductor layer not shielded by the first conductive layer is processed into a conductor-enhancing layer, forming the electrode connection portion of the transistor.

[0305] The third step, forming a second conductive layer pattern, includes: depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; and patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer pattern. Figure 21 and Figure 22 As shown, Figure 21 for Figure 17 A schematic diagram of the second conductive layer pattern. Figure 22 for Figure 17 A schematic diagram showing the formation of the second conductive layer pattern. In some embodiments of this disclosure, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0306] In some embodiments of this disclosure, such as Figure 21 and Figure 22As shown, the second conductive layer pattern may include: a second plate C1-2 of a first capacitor located in at least one level of shift register unit, a second plate C2-2 of a second capacitor, a second plate C4-2 of a fourth capacitor, a second connecting portion L2, a third connecting portion L3, a fourth connecting portion L4, a fifth connecting portion L5, and a sixth connecting portion L6.

[0307] In some embodiments of this disclosure, such as Figure 21 and Figure 22 As shown, the second electrode C1-2, the third connecting part L3, the fourth connecting part L4, and the fifth connecting part L5 of the first capacitor can be integrally formed. The second electrode C2-2 of the second capacitor, the second electrode C4-2 of the fourth capacitor, the second connecting part L2, and the sixth connecting part L6 can be set separately.

[0308] In some embodiments of this disclosure, such as Figure 21 and Figure 22 As shown, the second plate C1-2 of the first capacitor can be square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate C1-1 of the first capacitor on the substrate.

[0309] In some embodiments of this disclosure, such as Figure 21 and Figure 22 As shown, the shape of the second plate C2-2 of the second capacitor can be “ The shape is " ", and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the first plate C2-1 of the second capacitor on the substrate.

[0310] In some embodiments of this disclosure, such as Figure 21 and Figure 22 As shown, the second plate C4-2 of the fourth capacitor can be square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate C4-1 of the fourth capacitor on the substrate.

[0311] In some embodiments of this disclosure, such as Figure 21 and Figure 22 As shown, the second connecting portion L2, the fourth connecting portion L4, and the fifth connecting portion L5 can be strip-shaped and extend at least partially along the second direction D2. The third connecting portion L3 and the sixth connecting portion L6 can be strip-shaped and extend at least partially along the first direction D1.

[0312] The fourth step, forming the third insulating layer pattern, includes: depositing a third insulating film on the substrate with the aforementioned pattern, and patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the aforementioned structure. The third insulating layer has multiple via patterns, such as... Figure 23 and Figure 24 As shown, Figure 23 for Figure 17 A schematic diagram of the first via pattern in the image. Figure 24 for Figure 17 A schematic diagram after the third insulating layer pattern has been formed.

[0313] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the multiple via patterns may include: the first via V1 to the thirty-seventh via V37.

[0314] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the third electrode of the first transistor onto the substrate. The second insulating layer beneath the first via V1 is etched away, exposing the surface of the third electrode of the first transistor. The first via V1 is configured to electrically connect one of the first clock signal line and the second clock signal line formed in subsequent processes to the third electrode of the first transistor.

[0315] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the first region of the active layer of the first transistor onto the substrate. The first and second insulating layers below the second via V2 are etched away, exposing the surface of the first region of the active layer of the first transistor. The second via V2 is configured to electrically connect the first electrode of the first transistor, which is subsequently formed, to the first region of the active layer of the first transistor through the via.

[0316] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the third via V3 on the substrate lies within the range of the orthographic projection of the second connection portion L2 on the substrate, and the third via V3 exposes the surface of the second connection portion L2. The third via V3 is configured to electrically connect the first terminal of the first transistor of the local shift register unit formed in subsequent processes to the second connection portion L2.

[0317] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the fourth via V4 on the substrate lies within the range of the orthographic projection of the second connection portion L2 on the substrate, and the fourth via V4 exposes the surface of the second connection portion L2. The fourth via V4 is configured to allow the second terminal (also the second terminal of the ninth transistor) of the previous stage shift register unit formed in a subsequent process to be electrically connected to the second connection portion L2 through the via.

[0318] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the second region of the active layer of the first transistor onto the substrate. The first and second insulating layers below the fifth via V5 are etched away, exposing the surface of the second region of the active layer of the first transistor. The fifth via V5 is configured to electrically connect the second terminal of the first transistor (which is also the first terminal of the seventh transistor) formed in subsequent processes to the second region of the active layer of the first transistor through this via.

[0319] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthogonal projection of the sixth via V6 onto the substrate lies within the orthogonal projection of the third electrode of the seventh transistor onto the substrate. The second insulating layer beneath the sixth via V6 is etched away, exposing the surface of the third electrode of the seventh transistor. The sixth via V6 is configured to electrically connect the first voltage signal line formed in subsequent processes to the third electrode of the seventh transistor.

[0320] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the second region of the active layer of the seventh transistor onto the substrate. The first and second insulating layers beneath the seventh via V7 are etched away, exposing the surface of the second region of the active layer of the seventh transistor. The seventh via V7 is configured to electrically connect the second terminal of the seventh transistor, formed in subsequent processes, to the second region of the active layer of the seventh transistor through this via.

[0321] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the eighth via V8 on the substrate lies within the range of the orthographic projection of the fifth connection portion L5 on the substrate, and the eighth via V8 exposes the surface of the fifth connection portion L5. The eighth via V8 is configured to electrically connect one of the first clock signal lines and the second clock signal line formed in subsequent processes to the second plate of the first capacitor.

[0322] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the ninth via V9 on the substrate lies within the range of the orthographic projection of the third connection portion L3 on the substrate, and the ninth via V9 exposes the surface of the third connection portion L3. The ninth via V9 is configured to electrically connect the first electrode of the second transistor formed in subsequent processes to the second plate of the first capacitor.

[0323] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the first region of the active layer of the second transistor onto the substrate. The first and second insulating layers below the tenth via V10 are etched away, exposing the surface of the first region of the active layer of the second transistor. The tenth via V10 is configured to electrically connect the first electrode of the second transistor, which is subsequently formed, to the first region of the active layer of the second transistor through the via.

[0324] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the eleventh via V11 onto the substrate lies within the orthographic projection of the second region of the active layer of the second transistor onto the substrate. The first and second insulating layers below the eleventh via V11 are etched away, exposing the surface of the second region of the active layer of the second transistor. The eleventh via V11 is configured to electrically connect the second terminal of the second transistor (which is also the second terminal of the fourth transistor) formed in subsequent processes to the second region of the active layer of the second transistor through this via.

[0325] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the twelfth via V12 onto the substrate lies within the orthographic projection of the third electrode of the second transistor onto the substrate. The second insulating layer beneath the twelfth via V12 is etched away, exposing the surface of the third electrode of the second transistor. The twelfth via V12 is configured to electrically connect the second electrode of the third transistor formed in subsequent processes to the third electrode of the second transistor (which is also the first plate of the first capacitor).

[0326] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the thirteenth via V13 onto the substrate lies within the orthographic projection of the second region of the active layer of the third transistor onto the substrate. The first and second insulating layers below the thirteenth via V13 are etched away, exposing the surface of the second region of the active layer of the third transistor. The thirteenth via V13 is configured to electrically connect the second terminal of the third transistor, which is subsequently formed, to the second region of the active layer of the third transistor through this via.

[0327] In some embodiments of this disclosure, such as Figure 23 and Figure 24As shown, the orthographic projection of the fourteenth via V14 onto the substrate lies within the orthographic projection of the first region of the active layer of the third transistor onto the substrate. The first and second insulating layers below the fourteenth via V14 are etched away, exposing the surface of the first region of the active layer of the third transistor. The fourteenth via V14 is configured to electrically connect the first electrode of the third transistor, which is subsequently formed, to the first region of the active layer of the third transistor through this via.

[0328] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthogonal projection of the fifteenth via V15 onto the substrate lies within the orthogonal projection of the third electrode of the third transistor onto the substrate. The second insulating layer beneath the fifteenth via V15 is etched away, exposing the surface of the third electrode of the third transistor. The fifteenth via V15 is configured to electrically connect the first electrode of the seventh transistor, which is subsequently formed, to the third electrode of the third transistor (which is also the third electrode of the fourth transistor) through this via.

[0329] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthogonal projection of the sixteenth via V16 onto the substrate lies within the orthogonal projection of the third electrode of the third transistor onto the substrate. The second insulating layer beneath the sixteenth via V16 is etched away, exposing the surface of the third electrode of the third transistor. The sixteenth via V16 is configured to electrically connect the second electrode of the sixth transistor (which is also the third electrode of the fourth transistor) through this via. Simultaneously, the sixteenth via V16 is also configured to electrically connect the second electrode of the twelfth transistor (which is also the third electrode of the fourth transistor) through this via.

[0330] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the seventeenth via V17 onto the substrate lies within the orthographic projection of the second region of the active layer of the sixth transistor onto the substrate. The first and second insulating layers beneath the seventeenth via V17 are etched away, exposing the surface of the second region of the active layer of the sixth transistor. The seventeenth via V17 is configured to electrically connect the second terminal of the sixth transistor, formed in subsequent processes, to the second region of the active layer of the sixth transistor through this via.

[0331] In some embodiments of this disclosure, such as Figure 23 and Figure 24As shown, the orthographic projection of the eighteenth via V18 onto the substrate lies within the orthographic projection of the third electrode of the sixth transistor onto the substrate. The second insulating layer beneath the eighteenth via V18 is etched away, exposing the surface of the third electrode of the sixth transistor. The eighteenth via V18 is configured to electrically connect the first electrode of the eighth transistor, which is subsequently formed, to the third electrode of the sixth transistor.

[0332] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the nineteenth via V19 onto the substrate lies within the orthographic projection of the first region of the active layer of the fifth transistor onto the substrate. The first and second insulating layers beneath the nineteenth via V19 are etched away, exposing the surface of the first region of the active layer of the fifth transistor. The nineteenth via V19 is configured to electrically connect the first electrode of the fifth transistor, which is subsequently formed, to the first region of the active layer of the fifth transistor through this via.

[0333] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the twentieth via V20 onto the substrate lies within the orthographic projection of the second region of the active layer of the eighth transistor onto the substrate. The first and second insulating layers beneath the twentieth via V20 are etched away, exposing the surface of the second region of the active layer of the eighth transistor. The twentieth via V20 is configured to electrically connect the second terminal of the eighth transistor, formed in subsequent processes, to the second region of the active layer of the eighth transistor through this via.

[0334] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the twenty-first via V21 onto the substrate lies within the orthographic projection of the first region of the active layer of the eighth transistor onto the substrate. The first and second insulating layers below the twenty-first via V21 are etched away, exposing the surface of the first region of the active layer of the eighth transistor. The twenty-first via V21 is configured to electrically connect the first terminal of the eighth transistor, which is subsequently formed, to the first region of the active layer of the eighth transistor through this via.

[0335] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 22nd via V22 on the substrate lies within the range of the orthographic projection of the fourth connection portion L4 on the substrate, and the 22nd via V22 exposes the surface of the fourth connection portion L4. The 22nd via V22 is configured to allow the first electrode of the eighth transistor formed in a subsequent process to be electrically connected to the second electrode of the first capacitor through the via.

[0336] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 23rd via V23 onto the substrate lies within the orthographic projection of the third electrode of the 12th transistor onto the substrate. The second insulating layer beneath the 23rd via V23 is etched away, exposing the surface of the third electrode of the 12th transistor. The 23rd via V23 is configured to electrically connect the second electrode of the 7th transistor, which is subsequently formed, to the third electrode of the 12th transistor through this via.

[0337] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 24th via V24 onto the substrate lies within the orthographic projection of the first region of the active layer of the ninth transistor onto the substrate. The first and second insulating layers beneath the 24th via V24 are etched away, exposing the surface of the first region of the active layer of the ninth transistor. The 24th via V24 is configured to electrically connect the first electrode of the ninth transistor, which is subsequently formed, to the first region of the active layer of the ninth transistor through this via.

[0338] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 25th via V25 onto the substrate lies within the orthographic projection of the second region of the active layer of the ninth transistor onto the substrate. The first and second insulating layers beneath the 25th via V25 are etched away, exposing the surface of the second region of the active layer of the ninth transistor. The 25th via V25 is configured to electrically connect the second terminal of the ninth transistor, which is subsequently formed, to the second region of the active layer of the ninth transistor through this via.

[0339] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 26th via V26 on the substrate lies within the orthographic projection of the second plate of the second capacitor on the substrate, and the 26th via V26 exposes the surface of the second plate of the second capacitor. The 26th via V26 is configured to electrically connect the second electrode of the eighth transistor (which is also the second electrode of the ninth transistor) formed in a subsequent process to the second plate of the second capacitor.

[0340] In some embodiments of this disclosure, such as Figure 23 and Figure 24As shown, the orthographic projection of the 27th via V27 onto the substrate lies within the orthographic projection of the second region of the active layer of the 12th transistor onto the substrate. The first and second insulating layers beneath the 27th via V27 are etched away, exposing the surface of the second region of the active layer of the 12th transistor. The 27th via V27 is configured to electrically connect the second terminal of the active layer of the 12th transistor, formed in subsequent processes, to the second region of the active layer of the 12th transistor through this via.

[0341] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 28th via V28 onto the substrate lies within the orthographic projection of the first region of the active layer of the 12th transistor onto the substrate. The first and second insulating layers below the 28th via V28 are etched away, exposing the surface of the first region of the active layer of the 12th transistor. The 28th via V28 is configured to electrically connect the first terminal of the 12th transistor, which is subsequently formed, to the first region of the active layer of the 12th transistor through the via.

[0342] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 29th via V29 onto the substrate lies within the orthographic projection of the third electrode of the fifth transistor onto the substrate. The second insulating layer beneath the 29th via V29 is etched away, exposing the surface of the third electrode of the fifth transistor. The 29th via V29 is configured to allow the second electrode of the second transistor (which is also the second electrode of the fourth transistor) formed in subsequent processes to be electrically connected to the third electrode of the fifth transistor through this via.

[0343] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 30th via V30 onto the substrate lies within the orthographic projection of the first region of the active layer of the 11th transistor onto the substrate. The first and second insulating layers below the 30th via V30 are etched away, exposing the surface of the first region of the active layer of the 11th transistor. The 30th via V30 is configured to electrically connect the first electrode of the 11th transistor, which is subsequently formed, to the first region of the active layer of the 11th transistor through this via.

[0344] In some embodiments of this disclosure, such as Figure 23 and Figure 24As shown, the orthographic projection of the thirty-first via V31 onto the substrate lies within the orthographic projection of the second region of the active layer of the eleventh transistor onto the substrate. The first and second insulating layers below the thirty-first via V31 are etched away, exposing the surface of the second region of the active layer of the eleventh transistor. The thirty-first via V31 is configured to electrically connect the second terminal of the eleventh transistor (which is also the second terminal of the tenth transistor) formed in subsequent processes to the second region of the active layer of the eleventh transistor (which is also the second region of the active layer of the tenth transistor) through this via.

[0345] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 32nd via V32 onto the substrate lies within the orthographic projection of the first region of the active layer of the 10th transistor onto the substrate. The first and second insulating layers below the 32nd via V32 are etched away, exposing the surface of the first region of the active layer of the 10th transistor. The 32nd via V32 is configured to electrically connect the first terminal of the 10th transistor, which is subsequently formed, to the first region of the active layer of the 10th transistor through this via.

[0346] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the thirty-third via V33 on the substrate lies within the orthographic projection of the first connection portion L1 on the substrate. The second insulating layer beneath the thirty-third via V33 is etched away, exposing the surface of the first connection portion L1. The thirty-third via V33 is configured to electrically connect one of the third clock signal line and the fourth clock signal line formed in subsequent processes to the first connection portion L1.

[0347] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the thirty-fourth via V34 onto the substrate lies within the orthographic projection of the first connection portion L1 onto the substrate. The second insulating layer beneath the thirty-fourth via V34 is etched away, exposing the surface of the first connection portion L1. The thirty-fourth via V34 is configured to electrically connect the first electrode of the tenth transistor formed in subsequent processes to the first connection portion L1.

[0348] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the thirty-fifth via V35 on the substrate lies within the range of the orthographic projection of the sixth connection portion L6 on the substrate, and the thirty-fifth via V35 exposes the surface of the sixth connection portion L6. The thirty-fifth via V35 is configured to electrically connect the second terminal of the tenth transistor (which is also the second terminal of the eleventh transistor) formed in subsequent processes to the sixth connection portion L6.

[0349] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the thirty-sixth via V36 on the substrate lies within the orthographic projection of the second plate of the fourth capacitor on the substrate, and the thirty-sixth via V36 exposes the surface of the second plate of the fourth capacitor. The thirty-sixth via V36 is configured to electrically connect the first voltage signal line formed by subsequent processes to the second plate of the fourth capacitor.

[0350] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the orthographic projection of the 37th via V37 onto the substrate lies within the orthographic projection of the first region of the active layer of the fourth transistor onto the substrate. The first and second insulating layers below the 37th via V37 are etched away, exposing the surface of the first region of the fourth transistor. The 37th via V37 is configured to electrically connect the first electrode of the fourth transistor, which is subsequently formed, to the first region of the active layer of the fourth transistor through this via.

[0351] The fifth step, forming the third conductive pattern, includes: depositing a third conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive thin film using a patterning process to form the third conductive layer pattern, such as... Figure 25 and Figure 26 As shown, Figure 25 for Figure 17 A schematic diagram of the third conductive layer pattern in the image. Figure 29 for Figure 17 A schematic diagram showing the formation of the third conductive pattern. In some embodiments of this disclosure, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0352] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the third conductive layer pattern may include: an input signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, two first voltage signal lines VGL1, a second voltage signal line VGH, a third clock signal line CLK3, a fourth clock signal line CLK4, and the first pole T1c-1 and the second pole T1c-2 of the first transistor to the first pole T12c-1 and the second pole T12c-2 of the twelfth transistor located in the shift register unit of this stage.

[0353] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line away from the display area are arranged on the same layer.

[0354] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the second terminal T1c-2 of the first transistor and the first terminal T7c-1 of the seventh transistor are integrally molded; the second terminal T2c-2 of the second transistor and the second terminal T4c-2 of the fourth transistor are integrally molded; the second voltage signal line VGH, the first terminal T5c-1 of the fifth transistor and the first terminal T9c-1 of the ninth transistor are integrally molded; the second terminal T6c-2 of the sixth transistor and the second terminal T12c-2 of the twelfth transistor are integrally molded; the second terminal T8c-2 of the eighth transistor and the second terminal T9c-2 of the ninth transistor are integrally molded; the first terminal T10c-1 of the tenth transistor and the first terminal T11c-1 of the eleventh transistor are integrally molded; the first voltage signal line VGL1 near the display area and the second terminal T11c-2 of the eleventh transistor are integrally molded. The first terminal T1c-1 of the first transistor, the first terminal T2c-1 of the second transistor, the second terminal T3c-2 of the third transistor, the second terminal T7c-2 of the seventh transistor, the first terminal T8c-1 of the eighth transistor, the first terminal T12c-1 of the twelfth transistor, and the second terminal T10c-2 of the tenth transistor can be set individually.

[0355] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1 (away from the display area), the second voltage signal line VGH, the third clock signal line CLK3, the fourth clock signal line CLK4, and the first voltage signal line VGL1 (closest to the display area) are arranged sequentially along the side closest to the display area. Any one of the following—the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1 (away from the display area), the second voltage signal line VGH, the third clock signal line CLK3, the fourth clock signal line CLK4, and the first voltage signal line VGL1 (closest to the display area)—extends along the first direction D1.

[0356] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the first electrode T1c-1 of the first transistor can be strip-shaped and extends along the second direction D2. The first electrode T1c-1 of the first transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The first electrode T1c-1 of the first transistor is electrically connected to the first region T1a-1 of the active layer of the first transistor through the second via V2, and is electrically connected to the second connection portion L2 located in the shift register unit of this stage through the third via V3.

[0357] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the second terminal T1c-2 of the first transistor (which is also the first terminal T7c-1 of the seventh transistor) can be strip-shaped and extends along the second direction D2. The second terminal T1c-2 of the first transistor (which is also the first terminal T7c-1 of the seventh transistor) is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The second terminal T1c-2 of the first transistor (which is also the first terminal T7c-1 of the seventh transistor) is electrically connected to the second region T1a-2 of the active layer of the first transistor (which is also the first region T7a-1 of the active layer of the seventh transistor) through the fifth via V5, and is electrically connected to the third terminal T3b of the third transistor (which is also the third terminal T4b of the fourth transistor) through the fifteenth via V15.

[0358] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the first electrode T2c-1 of the second transistor can be strip-shaped and extends along the first direction D1. The first electrode T2c-1 of the second transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The first electrode T2c-1 of the second transistor is electrically connected to the first region T2a-1 of the active layer of the second transistor through the tenth via V10, and is electrically connected to the second plate C1-2 of the first capacitor through the ninth via V9.

[0359] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the second terminal T2c-2 of the second transistor (which is also the second terminal T4c-2 of the fourth transistor) can be strip-shaped and extends along the first direction D1. The second terminal T2c-2 of the second transistor (which is also the second terminal T4c-2 of the fourth transistor) is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The second terminal T2c-2 of the second transistor (which is also the second terminal T4c-2 of the fourth transistor) is electrically connected to the second region T2a-2 of the active layer of the second transistor (which is also the second region T4a-2 of the active layer of the fourth transistor) through the eleventh via V11, and is electrically connected to the third terminal T5b of the fifth transistor through the twenty-ninth via V29.

[0360] In some embodiments of this disclosure, such as Figure 25 and Figure 26As shown, the second electrode T3c-2 of the third transistor can be strip-shaped and extends along the second direction D2. The second electrode T3c-2 of the third transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The second electrode T3c-2 of the third transistor is electrically connected to the second region T3a-2 of the active layer of the third transistor through the thirteenth via V13, and is electrically connected to the third electrode T2b of the second transistor (which is also the first plate C1-1 of the first capacitor) through the twelfth via V12.

[0361] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the second electrode T7c-2 of the seventh transistor can be strip-shaped and extends along the second direction D2. The second electrode T7c-2 of the seventh transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The second electrode T7c-2 of the seventh transistor is electrically connected to the second region T7a-2 of the active layer of the seventh transistor through the seventh via V7, and is electrically connected to the third electrode T12b of the twelfth transistor through the twenty-third via V23.

[0362] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the first terminal T5c-1 of the fifth transistor (which is also the first terminal T9c-1 of the ninth transistor) can be strip-shaped and extends along the second direction D2. The first terminal T5c-1 of the fifth transistor (which is also the first terminal T9c-1 of the ninth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The first terminal T5c-1 of the fifth transistor is electrically connected to the first terminal T5a-1 of the active layer of the fifth transistor through the nineteenth via V19, and the first terminal T9c-1 of the ninth transistor is electrically connected to the first terminal T9a-1 of the active layer of the ninth transistor through the twenty-fourth via V24.

[0363] In some embodiments of this disclosure, such as Figure 25 and Figure 26As shown, the second terminal T6c-2 of the sixth transistor (also the second terminal T12c-2 of the twelfth transistor) can be strip-shaped and extends along the first direction D1. The second terminal T6c-2 of the sixth transistor (also the second terminal T12c-2 of the twelfth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The second terminal T6c-2 of the sixth transistor is electrically connected to the second terminal T6a-2 of the active layer of the sixth transistor through the seventeenth via V17, and is electrically connected to the third terminal T3b of the third transistor (also the third terminal T4b of the fourth transistor) through the sixteenth via V16. The second terminal T12c-2 of the twelfth transistor is electrically connected to the second terminal T12a-2 of the active layer of the twelfth transistor through the twenty-seventh via V27.

[0364] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the shape of the first terminal T12c-1 of the twelfth transistor can be “ The 12th transistor is shaped like the letter "T". The first terminal T12c-1 of the 12th transistor is located between the second voltage signal line VGH and the third clock signal line CLK3. The first terminal T12c-1 of the 12th transistor is electrically connected to the first terminal T12a-1 of the active layer of the 12th transistor through the 28th via V28.

[0365] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the shape of the first electrode T8c-1 of the eighth transistor can be “ The first terminal T8c-1 of the eighth transistor is located between the second voltage signal line VGH and the third clock signal line CLK3. The first terminal T8c-1 of the eighth transistor is electrically connected to the first region T8a-1 of the active layer of the eighth transistor through the twenty-first via V21, electrically connected to the fourth connection part L4 through the twenty-second via V22, and electrically connected to the third terminal T6b of the sixth transistor through the eighteenth via V18.

[0366] In some embodiments of this disclosure, such as Figure 25 and Figure 26As shown, the second terminal T8c-2 of the eighth transistor (which is also the second terminal T9c-2 of the ninth transistor) can be shaped like an "F". The second terminal T8c-2 of the eighth transistor (which is also the second terminal T9c-2 of the ninth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The second terminal T8c-2 of the eighth transistor can be electrically connected to the second region T8a-2 of the active layer of the eighth transistor through the twentieth via V20. The second terminal T9c-2 of the ninth transistor can be electrically connected to the second region T9a-2 of the active layer of the ninth transistor through the twenty-fifth via V25. Furthermore, the second terminal T8c-2 of the eighth transistor (which is also the second terminal T9c-2 of the ninth transistor) is electrically connected to the second plate C2-2 of the second capacitor through the twenty-sixth via V26.

[0367] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the second electrode T11c-2 of the eleventh transistor can be strip-shaped and extends along the second direction D2. The second electrode T11c-2 of the eleventh transistor is located on the side of the first voltage signal line VGL1 near the display area. The second electrode T11c-2 of the eleventh transistor can be electrically connected to the second region T11a-2 of the active layer of the eleventh transistor through the thirty-first via V31.

[0368] In some embodiments of this disclosure, such as Figure 25 and Figure 26 As shown, the second terminal T10c-2 of the tenth transistor can be shaped like an "F". The second terminal T10c-2 of the tenth transistor is located on the side of the first voltage signal line VGL1 closest to the display area. The second terminal T10c-2 of the tenth transistor can be electrically connected to the second region T10-2 of the active layer of the tenth transistor through the thirty-second via V32.

[0369] In some embodiments of this disclosure, such as Figure 25 and Figure 26As shown, the first terminal T10c-1 of the tenth transistor (also the first terminal T11c-1 of the eleventh transistor) can be comb-shaped, with its "tooth" located on the side of the "back of the comb" away from the display area. The first terminal T10c-1 (also the first terminal T11c-1 of the eleventh transistor) is located on the side of the first voltage signal line VGL1 closest to the display area. The first terminal T10c-1 of the tenth transistor is electrically connected to the first region T10a-1 of the active layer of the tenth transistor through the thirty-second via V32, and the first terminal T11c-1 of the eleventh transistor is electrically connected to the first region T11a-1 of the active layer of the eleventh transistor through the thirty-ninth via V30. The first terminal T10c-1 (also the first terminal T11c-1 of the eleventh transistor) of the tenth transistor is electrically connected to the sixth connection portion L6 through the thirty-fifth via V35.

[0370] In some embodiments of this disclosure, such as Figure 26 As shown, the orthographic projection of the first voltage signal line VGL1 near the display area on the substrate overlaps with the orthographic projection of the fourth capacitor on the substrate.

[0371] The sixth step, forming a fourth insulating layer pattern, includes: depositing a fourth insulating film on a substrate with the aforementioned pattern, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the aforementioned structure. The fourth insulating layer contains via patterns. Figure 27 and Figure 28 Show, Figure 27 Figure 17 A schematic diagram of the second via pattern in the diagram. Figure 28 Figure 17 A schematic diagram after the fourth insulating layer pattern is formed.

[0372] In some embodiments of this disclosure, such as Figure 27 and Figure 28 As shown, the via pattern may include: the thirty-eighth via V38.

[0373] In some embodiments of this disclosure, such as Figure 27 and Figure 28 As shown, the orthographic projection of the thirty-eighth via V38 onto the substrate lies within the orthographic projection of the first electrode T12c-1 of the twelfth transistor onto the substrate, and the thirty-eighth via V38 exposes the surface of the first electrode T12c-1 of the twelfth transistor. The thirty-eighth via V38 is configured to allow the third voltage signal line VGL2, which is subsequently formed, to be electrically connected to the first electrode T12c-1 of the twelfth transistor through this via.

[0374] The seventh step, forming the fourth conductive layer pattern, includes: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form the fourth conductive layer pattern. For example... Figure 29 and Figure 30 As shown, Figure 29 for Figure 17 A schematic diagram of the fourth conductive layer pattern. Figure 30 for Figure 17 A schematic diagram showing the formation of the fourth conductive layer pattern. In some embodiments of this disclosure, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0375] In some embodiments of this disclosure, such as Figure 29 and Figure 30 As shown, the fourth conductive layer pattern may include: a third voltage signal line VGL2.

[0376] In some embodiments of this disclosure, such as Figure 29 and Figure 30 As shown, the third voltage signal line VGL2 can be a line shape and extends along the first direction D1. The orthographic projection of the third voltage signal line VGL2 on the substrate is located between the second voltage signal line VGH and the third clock signal line CLK3, and its orthographic projection on the substrate overlaps with the orthographic projections of the eighth transistor, the ninth transistor, and the second capacitor on the substrate.

[0377] In some embodiments of this disclosure, such as Figure 29 and Figure 30 As shown, the third voltage signal line VGL2 is electrically connected to the first terminal T12c-1 of the twelfth transistor through the thirty-eighth via V38.

[0378] The eighth step, forming a planarization layer pattern, includes: depositing a fifth insulating film on a substrate on which the aforementioned pattern has been formed, coating a planarization film, and patterning the fifth insulating film and the planarization film through a patterning process to form a fifth insulating layer pattern and a planarization layer pattern covering the aforementioned pattern.

[0379] At this point, the driving structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple shift register units, and the driving structure layer may be disposed on the substrate. The driving structure layer may include, sequentially disposed on the substrate, a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a planarization layer.

[0380] In some embodiments of this disclosure, such as Figure 31As shown, the first clock signal line CLK1 and the second clock signal line CLK2 can be disposed on the same layer as the third voltage signal line VGL2. In this case, the input signal lines, the first voltage signal line away from the display area, and the first and second clock signal lines are disposed on different layers. In some embodiments of this disclosure, the driving structure layer disposed on the substrate includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a planarization layer, sequentially stacked on the substrate. The following is an exemplary description through the fabrication process of the display substrate.

[0381] The first step is to form a semiconductor layer pattern on the substrate. This process is similar to the aforementioned preparation process and will not be described in detail here.

[0382] The second step, forming the first conductive layer, includes: depositing a first insulating film and a first conductive film on a substrate having the aforementioned pattern formed; and patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive pattern disposed on the first insulating layer pattern, such as... Figure 32 and Figure 33 As shown, Figure 32 for Figure 31 A schematic diagram of the first conductive layer pattern in the image. Figure 33 for Figure 31 A schematic diagram showing the formation of the first conductive layer pattern. In some embodiments of this disclosure, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0383] In some embodiments of this disclosure, such as Figure 32 and Figure 33 As shown, the third electrode T1b' of the first transistor includes: a first third electrode portion T1b'-1 and a second third electrode portion T1b'-2. The third electrode T1b' of the first transistor is shaped like a "ㄈ". Both the first third electrode portion T1b'-1 and the second third electrode portion T1b'-2 of the first transistor extend along the second direction D2. The end of the first third electrode portion T1b'-1 of the first transistor is connected to the end of the second third electrode portion T1b'-2 of the first transistor.

[0384] In some embodiments of this disclosure, the preparation process of the first conductive layer is similar to the aforementioned preparation process, and will not be repeated here.

[0385] The third step, forming a second conductive layer pattern, includes: depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; and patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer pattern. Figure 21 and Figure 22 As shown, Figure 21 for Figure 17 A schematic diagram of the second conductive layer pattern. Figure 22 for Figure 17 A schematic diagram showing the formation of the second conductive layer pattern. In some embodiments of this disclosure, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0386] In some embodiments of this disclosure, such as Figure 34 and Figure 35 As shown, the second conductive layer pattern may include: a second plate C1-2 of a first capacitor located in at least one level of shift register unit, a second plate C2-2 of a second capacitor, a second plate C4-2 of a fourth capacitor, a second connecting portion L2, a third connecting portion L3, a fourth connecting portion L4, and a sixth connecting portion L6.

[0387] In some embodiments of this disclosure, the preparation process of the second conductive layer is similar to the aforementioned preparation process, and will not be repeated here.

[0388] The fourth step, forming the third insulating layer pattern, includes: depositing a third insulating film on the substrate with the aforementioned pattern, and patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the aforementioned structure. The third insulating layer has multiple via patterns, such as... Figure 36 and Figure 37 As shown, Figure 36 for Figure 31 A schematic diagram of the via pattern in the third insulating layer. Figure 37 for Figure 31 A schematic diagram after the third insulating layer pattern has been formed.

[0389] In some embodiments of this disclosure, such as Figure 23 and Figure 24 As shown, the multiple via patterns may include: the second via V2 to the seventh via V7, and the ninth via V9 to the thirty-seventh via V37.

[0390] In some embodiments of this disclosure, the preparation process of the third insulating layer is similar to the aforementioned preparation process, and will not be repeated here.

[0391] The fifth step, forming the third conductive layer pattern, includes: depositing a third conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive thin film using a patterning process to form the third conductive layer pattern, such as... Figure 38 and Figure 39 As shown, Figure 38 for Figure 31 A schematic diagram of the third conductive layer pattern in the image. Figure 39 for Figure 31A schematic diagram showing the formation of the third conductive pattern. In some embodiments of this disclosure, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0392] In some embodiments of this disclosure, such as Figure 38 and Figure 39 As shown, the third conductive layer pattern may include: an input signal line STV, two first voltage signal lines VGL1, a second voltage signal line VGH, a third clock signal line CLK3, a fourth clock signal line CLK4, a seventh connection L7, an eighth connection L8, and the first pole T1c-1 and the second pole T1c-2 of the first transistor to the first pole T12c-1 and the second pole T12c-2 of the twelfth transistor located in the shift register unit of this stage.

[0393] In some embodiments of this disclosure, the preparation process of the third conductive layer is similar to the aforementioned preparation process, and will not be repeated here.

[0394] The sixth step, forming a fourth insulating layer pattern, includes: depositing a fourth insulating film on a substrate with the aforementioned pattern, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the aforementioned structure. The fourth insulating layer contains via patterns. Figure 40 and Figure 41 As shown, Figure 40 for Figure 31 A schematic diagram of the second via pattern in the diagram. Figure 42 Figure 31 A schematic diagram after the fourth insulating layer pattern is formed.

[0395] In some embodiments of this disclosure, such as Figure 40 and Figure 41 As shown, the via pattern may include: the first via V1', the eighth via V8', and the thirty-eighth via V38.

[0396] In some embodiments of this disclosure, such as Figure 40 and Figure 41 As shown, the orthographic projection of the first via V1' onto the substrate lies within the orthographic projection of the third electrode of the first transistor onto the substrate. The second insulating layer, the third insulating layer, and the third conductive layer beneath the first via V1' are etched away, exposing the surface of the third electrode of the first transistor. The first via V1' is configured to electrically connect one of the first clock signal line and the second clock signal line formed in subsequent processes to the third electrode of the first transistor.

[0397] In some embodiments of this disclosure, such as Figure 40 and Figure 41As shown, the orthographic projection of the eighth via V8' onto the substrate lies within the orthographic projection of the second electrode of the first capacitor onto the substrate. The third insulating layer and the third conductive layer below the eighth via V8' are etched away, exposing the surface of the second electrode of the first capacitor. The eighth via V8' is configured to electrically connect another of the first clock signal line and the second clock signal line formed in subsequent processes to the second electrode of the first capacitor.

[0398] In some embodiments of this disclosure, the preparation process of the fourth insulating layer is similar to the aforementioned preparation process, and will not be repeated here.

[0399] The seventh step, forming the fourth conductive layer pattern, includes: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form the fourth conductive layer pattern. For example... Figure 42 and Figure 43 As shown, Figure 42 for Figure 31 A schematic diagram of the fourth conductive layer pattern. Figure 42 for Figure 31 A schematic diagram showing the formation of the fourth conductive layer pattern. In some embodiments of this disclosure, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0400] In some embodiments of this disclosure, such as Figure 42 and Figure 43 As shown, the fourth conductive layer pattern may include: a first clock signal line CLK1, a second clock signal line CLK2, and a third voltage signal line VGL2.

[0401] In some embodiments of this disclosure, such as Figure 42 and Figure 43 As shown, the first clock signal line CLK1 can be a line shape and extends along the first direction D1. The orthographic projection of the first clock signal line CLK1 on the substrate is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are far from the display area, and the orthographic projection of the first clock signal line CLK1 on the substrate overlaps with the orthographic projections of the first transistor, the seventh transistor, and the first capacitor on the substrate.

[0402] In some embodiments of this disclosure, such as Figure 42 and Figure 43 As shown, the first clock signal line CLK1 is electrically connected to the third terminal T1b of the first transistor through the first via V1'.

[0403] In some embodiments of this disclosure, such as Figure 42 and Figure 43As shown, the second clock signal line CLK2 can be a line shape and extends along the first direction D1. The orthogonal projection of the second clock signal line CLK2 on the substrate is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are far from the display area, and the orthogonal projection of the second clock signal line CLK2 on the substrate overlaps with the orthogonal projections of the second transistor and the first capacitor on the substrate.

[0404] In some embodiments of this disclosure, such as Figure 42 and Figure 43 As shown, the second clock signal line CLK2 is electrically connected to the second plate C2-2 of the first capacitor through the eighth via V8'.

[0405] In some embodiments of this disclosure, such as Figure 42 and Figure 43 As shown, the third voltage signal line VGL2 can be a line shape and extends along the first direction D1. The orthographic projection of the third voltage signal line VGL2 on the substrate is located between the second voltage signal line VGH and the third clock signal line CLK3, and the orthographic projection on the substrate overlaps with the orthographic projection of the second capacitor on the substrate.

[0406] In some embodiments of this disclosure, such as Figure 42 and Figure 43 As shown, the third voltage signal line VGL2 is electrically connected to the first terminal T12c-1 of the twelfth transistor through the thirty-eighth via V38.

[0407] The eighth step is to form a planarization layer pattern. This process is similar to the preparation process described above and will not be repeated here.

[0408] In some embodiments of this disclosure, the first clock signal line CLK1, the second clock signal line CLK2, and the third voltage signal line VGL2 are arranged on the same layer, which can reduce the size of the shift register unit along the first direction by about 25 micrometers, effectively reducing the size of the shift register unit, and further reducing the bezel length of the non-display area, which is beneficial for narrow bezel design.

[0409] In some embodiments of this disclosure, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or it may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0410] In some embodiments of this disclosure, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0411] In some embodiments of this disclosure, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0412] In some embodiments of this disclosure, the planarization layer may be made of organic materials, such as resin.

[0413] In some embodiments of this disclosure, after the driving structure layer is prepared, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer may include the following operations.

[0414] On the substrate with the aforementioned pattern, an anodic conductive film is deposited, and a patterning process is used to pattern the anodic conductive film to form an anodic conductive layer pattern disposed on a planarization layer. On the substrate with the aforementioned pattern, a pixel definition film is deposited, and a patterning process is used to pattern the pixel definition film to form a pixel definition layer pattern that exposes the anodic conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated, and a patterning process is used to pattern the organic light-emitting material to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited, and a patterning process is used to pattern the cathode conductive film to form a cathode conductive layer.

[0415] At this point, the light-emitting structure layer has been successfully fabricated on the substrate.

[0416] In some embodiments of this disclosure, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0417] In some embodiments of this disclosure, the anode conductive layer includes at least a plurality of anode patterns.

[0418] In some embodiments of this disclosure, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it may adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0419] In some embodiments of this disclosure, the organic structural layer may include at least: an organic light-emitting layer of a light-emitting device.

[0420] In some embodiments of this disclosure, the cathode conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0421] In some embodiments of this disclosure, the cathode layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or conductive alloy materials such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0422] The display substrate described in this embodiment can be used in display products of any resolution.

[0423] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0424] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0425] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A shift register unit, comprising: The shift register is configured to output cascaded signals through the cascaded output terminal; An output circuit, electrically connected to the shift register, is configured to control the output terminal to output a gate scan signal based on the signal at the first voltage signal terminal and the signal at the reference signal terminal. The shift register includes: a first control sub-circuit; The first control sub-circuit is electrically connected to the first node, the second node, the second voltage signal terminal, and the first clock signal terminal in the shift register; the first control sub-circuit is configured to control the voltage of the second node according to the voltage of the first node and the signal of the first clock signal terminal. The shift register further includes: a potential stabilizing sub-circuit; The potential stabilizing sub-circuit is electrically connected to the first node, the fourth node, and the first voltage signal terminal. The potential stabilizing sub-circuit is configured to transmit the voltage from the first node to the fourth node according to the signal from the first voltage signal terminal. The shift register further includes: a pull-down sub-circuit; The pull-down sub-circuit, electrically connected to the third voltage signal terminal and the first node, is configured to transmit a signal from the third voltage signal terminal to the first node.

2. The shift register unit as described in claim 1, wherein, The shift register further includes: an input sub-circuit; The input sub-circuit is configured to provide the input signal terminal to the first node according to the signal at the second clock signal terminal.

3. The shift register unit as described in claim 2, wherein, The input sub-circuit includes: a first transistor; The first terminal of the first transistor is electrically connected to the input signal terminal, the second terminal of the first transistor is electrically connected to the first node, and the third terminal of the first transistor is electrically connected to the second clock signal terminal.

4. The shift register unit as described in claim 1, wherein, The first control sub-circuit includes: a second transistor, a third transistor, a fourth transistor, and a first capacitor; The first terminal of the second transistor is electrically connected to the first clock signal terminal, the second terminal of the second transistor is electrically connected to the second node, and the third terminal of the second transistor is electrically connected to the third node. The first terminal of the third transistor is electrically connected to the second voltage signal terminal, the second terminal of the third transistor is electrically connected to the third node, and the third terminal of the third transistor is electrically connected to the first node. The first terminal of the fourth transistor is electrically connected to the second voltage signal terminal, the second terminal of the fourth transistor is electrically connected to the second node, and the third terminal of the fourth transistor is electrically connected to the first node. The first electrode of the first capacitor is electrically connected to the first clock signal terminal, and the second electrode of the first capacitor is electrically connected to the third node.

5. The shift register unit as described in claim 1, wherein, The shift register further includes: a second control sub-circuit; The second control sub-circuit is electrically connected to the first node, the second node, the second voltage signal terminal, and the first clock signal terminal; the second control sub-circuit is configured to transmit a signal from the second voltage signal terminal to the first node based on the voltage of the second node and the signal from the first clock signal terminal.

6. The shift register unit as described in claim 5, wherein, The second control sub-circuit includes: a fifth transistor and a sixth transistor; The first terminal of the fifth transistor is electrically connected to the second voltage signal terminal, the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor, and the third terminal of the fifth transistor is electrically connected to the second node. The second terminal of the sixth transistor is electrically connected to the first node, and the third terminal of the sixth transistor is electrically connected to the first clock signal terminal.

7. The shift register unit as described in claim 1, wherein, The potential stabilizing sub-circuit includes: a seventh transistor; The first terminal of the seventh transistor is electrically connected to the first node, the second terminal of the seventh transistor is electrically connected to the fourth node, and the third terminal of the seventh transistor is electrically connected to the first voltage signal terminal.

8. The shift register unit as claimed in claim 1, wherein, The shift register further includes: cascaded sub-circuit; The cascaded sub-circuit is electrically connected to the second node, the fourth node, the first clock signal terminal, and the second voltage signal terminal. The cascaded sub-circuit is configured to output the cascaded signal at the cascaded output terminal based on the voltages of the second node and the fourth node.

9. The shift register unit as described in claim 8, wherein, The cascaded sub-circuit includes: an eighth transistor, a ninth transistor, and a second capacitor; The first terminal of the eighth transistor is electrically connected to the first clock signal terminal, the second terminal of the eighth transistor is electrically connected to the cascaded output terminal, and the third terminal of the eighth transistor is electrically connected to the fourth node. The first terminal of the ninth transistor is electrically connected to the second voltage signal terminal, the second terminal of the ninth transistor is electrically connected to the cascaded output terminal, and the third terminal of the ninth transistor is electrically connected to the second node. The first electrode of the second capacitor is electrically connected to the fourth node, and the second electrode of the second capacitor is electrically connected to the cascaded output terminal.

10. The shift register unit as claimed in claim 9, wherein, The cascaded sub-circuit includes: a third capacitor; The first electrode of the third capacitor is electrically connected to the second voltage signal terminal, and the second electrode of the third capacitor is electrically connected to the cascaded output terminal.

11. The shift register unit as claimed in claim 1, wherein, The amplitude of the voltage signal at the third voltage signal terminal is greater than the amplitude of the voltage signal at the first voltage signal terminal.

12. The shift register unit as claimed in claim 11, wherein, The pull-down sub-circuit includes: a twelfth transistor; The first terminal of the twelfth transistor is electrically connected to the third voltage signal terminal, the second terminal of the twelfth transistor is electrically connected to the first node, and the third terminal of the twelfth transistor is electrically connected to the fourth node.

13. The shift register unit as claimed in claim 11, wherein, The pull-down sub-circuit includes: a twelfth transistor; The first terminal of the twelfth transistor is electrically connected to the third voltage signal terminal, the second terminal of the twelfth transistor is electrically connected to the first node, and the third terminal of the twelfth transistor is electrically connected to the first node.

14. The shift register unit as claimed in claim 1, wherein, The output circuit includes: a tenth transistor and an eleventh transistor; The first terminal of the tenth transistor is electrically connected to the reference signal terminal, the second terminal of the tenth transistor is electrically connected to the drive output terminal, and the third terminal of the tenth transistor is electrically connected to the first node. The first terminal of the eleventh transistor is electrically connected to the first voltage signal terminal, the second terminal of the eleventh transistor is electrically connected to the drive output terminal, and the third terminal of the eleventh transistor is electrically connected to the second node.

15. The shift register unit as claimed in claim 1, wherein, The output circuit includes: a tenth transistor, an eleventh transistor, and a thirteenth transistor; The first terminal of the tenth transistor is electrically connected to the reference signal terminal, the second terminal of the tenth transistor is electrically connected to the drive output terminal, and the third terminal of the tenth transistor is electrically connected to the second terminal of the thirteenth transistor. The first terminal of the eleventh transistor is electrically connected to the first voltage signal terminal, the second terminal of the eleventh transistor is electrically connected to the drive output terminal, and the third terminal of the eleventh transistor is electrically connected to the second node. The first terminal of the thirteenth transistor is electrically connected to the first node, and the third terminal of the thirteenth transistor is electrically connected to the first voltage signal terminal.

16. The shift register unit as claimed in claim 14 or 15, wherein, The output circuit also includes: a fourth capacitor; The first electrode of the fourth capacitor is electrically connected to the first voltage signal terminal, and the second electrode of the fourth capacitor is electrically connected to the second node.

17. The shift register unit according to claim 1, wherein, The signal at the reference signal terminal and the signal at the first clock signal terminal are inverse signals.

18. The shift register unit according to claim 2, wherein, The signals at the first clock signal terminal and the signals at the second clock signal terminal are not simultaneously valid level signals.

19. A display panel, comprising: The substrate includes the display area and the non-display area; The display area includes: Multiple sub-pixels; Multiple scan lines, wherein one row of sub-pixels in the plurality of sub-pixels is electrically connected to at least one of the multiple scan lines; The non-display area includes: The gate drive circuit includes a plurality of shift register units as described in any one of claims 1-18, wherein the drive output terminal of each of the plurality of shift register units is electrically connected to at least one of the plurality of scan lines.

20. The display panel as claimed in claim 19, wherein, It also includes: an input signal line electrically connected to the gate driving circuit and disposed in the non-display area, a first voltage signal line, a first clock signal line and a second clock signal line away from the display area; The input signal line, the first voltage signal line away from the display area, the first clock signal line, and the second clock signal line extend along a first direction, and the gate line extends along a second direction, with the first direction intersecting the second direction.

21. The display panel as claimed in claim 20, wherein, The input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line away from the display area are arranged sequentially on the substrate along the direction close to the display area, and are located on the side of the shift register unit away from the display area.

22. The display panel as claimed in claim 21, wherein, The input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line located away from the display area are arranged on the same layer.

23. The display panel as claimed in claim 20, wherein, The input signal line, the first voltage signal line away from the display area, the first clock signal line, and the second clock signal line are arranged sequentially on the substrate along the direction close to the display area, and are located on the side of the shift register unit away from the display area.

24. The display panel as claimed in claim 23, wherein, The input signal line and the first voltage signal line away from the display area are arranged on the same layer, the first clock signal line and the second clock signal line are arranged on the same layer, and the input signal line, the first voltage signal line away from the display area, the first clock signal line, and the second clock signal line are arranged on different layers.

25. The display panel as claimed in claim 20, wherein, Also includes: A second voltage signal line is electrically connected to the gate driving circuit and disposed in the non-display area, the second voltage signal line extending along a first direction.

26. The display panel as claimed in claim 25, wherein, The second voltage signal line is located on the side of the first voltage signal line that is far from the display area and close to the display area.

27. The display panel as claimed in claim 25, wherein, It also includes a third voltage signal line electrically connected to the gate driving circuit and disposed in the non-display area, the third voltage signal line extending along a first direction.

28. The display panel as claimed in claim 27, wherein, The third voltage signal line is located on the side of the second voltage signal line closest to the display area.

29. The display panel as claimed in claim 27, wherein, It also includes: a third clock signal line, a fourth clock signal line, and a first voltage signal line near the display area, which are electrically connected to the gate driving circuit and disposed in the non-display area, wherein the third clock signal line, the fourth clock signal line, and the first voltage signal line near the display area extend along a first direction.

30. The display panel as claimed in claim 29, wherein, Either the third clock signal line or the fourth clock signal line is disposed on the side of the third voltage signal line closest to the display area; The first voltage signal line near the display area is located on the side of either the third clock signal line or the fourth clock signal line closest to the display area.

31. The display panel according to claim 29, wherein, The reference signal terminal of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the reference signal terminal of the (i+1)-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

32. The display panel according to claim 20, wherein, The first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line. The signal lines connected to the first clock signal terminals of adjacent shift register units are different, and the signal lines connected to the second clock signal terminals of adjacent shift register units are different.

33. The display panel according to claim 29, wherein, The width of any one of the input signal line, the first voltage signal line, the second voltage signal line, and the third voltage signal line along the second direction is less than the width of any one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line along the second direction.

34. The display panel as claimed in claim 29, wherein, The shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor, and a first capacitor; At least a portion of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the first capacitor is located between the first voltage signal line and the second voltage signal line.

35. The display panel as claimed in claim 29, wherein, The shift register unit includes: a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a twelfth transistor, and a second capacitor; At least a portion of any one of the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the twelfth transistor, and the second capacitor is located between the second voltage signal line and the third voltage signal line.

36. The display panel as claimed in claim 35, wherein, The active layer of the twelfth transistor extends along a first direction, at least a portion of either the first or second electrode of the twelfth transistor extends along a second direction, and the third electrode of the twelfth transistor extends along a second direction.

37. The display panel as claimed in claim 35, wherein, The shift register unit includes: a tenth transistor, an eleventh transistor, and a third capacitor; At least a portion of any one of the tenth transistor, the eleventh transistor, and the third capacitor is located on the side of the first voltage signal line near the display area. The orthographic projection of the first voltage signal line near the display area on the substrate overlaps with the orthographic projection of the third capacitor on the substrate.

38. The display panel according to claim 37, wherein, The channel width of the active layer of the tenth transistor is greater than the channel width of the active layer of the eighth transistor.

39. The display panel according to claim 38, wherein, The channel width of the active layer of the tenth transistor is not less than 90 micrometers.

40. The display panel according to claim 38, wherein, The channel width of the active layer of the eighth transistor is no greater than 50 micrometers.

41. The display panel according to claim 37, wherein, The channel width of the active layer of the eleventh transistor is greater than the channel width of the active layer of the ninth transistor.

42. The display panel according to claim 41, wherein, The channel width of the active layer of the eleventh transistor is not less than 90 micrometers.

43. The display panel according to claim 41, wherein, The channel width of the active layer of the ninth transistor is no greater than 50 micrometers.

44. A display device, comprising: The display panel as described in any one of claims 19-43.

45. A method for driving a shift register, comprising: The input sub-circuit, under the signal control of the second clock signal terminal, provides the input signal terminal signal to the first node; The first control sub-circuit controls the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal; The second control sub-circuit, under the control of the voltage of the second node and the signal of the first clock signal terminal, provides the signal of the second voltage signal terminal to the first node; The potential stabilizing sub-circuit, under the signal control of the first voltage signal terminal, provides the voltage of the first node to the fourth node; The cascaded sub-circuit, under the control of the voltages of the second node and the fourth node, provides a signal from the second voltage signal terminal or the first clock signal terminal to the cascaded output terminal; The output circuit, under the control of the voltages of the first node and the second node, provides a signal from the reference signal terminal or the first voltage signal terminal to the drive output terminal; The shift register unit further includes: a pull-down sub-circuit; The method further includes: the pull-down sub-circuit providing a signal from the third voltage signal terminal to the first node under the control of the voltage of the first node or the fourth node.

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