Shifting register unit, driving control circuit, display device and driving method

Abstract

Provided are a shift register unit, a driving control circuit, a display device and a driving method wherein the shift register unit comprises: an input circuit (10) coupled to a signal input end (IP), a first clock signal end (CK) and a first node (N1) and configured to provide a signal of the signal input end (IP) to the first node (N1) in response to a signal of the first clock signal end (CK); a first stabilization circuit (20) configured to provide a signal of a stabilization control signal terminal (SC) to the first node (N1) in response to a signal of a switching control signal terminal (CTL); the conduction control circuit (30) is coupled with the first node (N1) and the second node (N2) and is configured to respond to a signal of a first reference signal end (VGL) and conduct the first node (N1) and the second node (N2); and the output circuit (40) is coupled with the second node (N2), a second clock signal end (CB) and the signal output end (OT), and is configured to respond to a signal of the second node (N2), provide a signal of the second clock signal end (CB) to the signal output end (OT) and enable the signal output end (OT) to output a driving signal.

Description

Shift register unit, drive control circuit, display device and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a drive control circuit, a display device, and a driving method. Background Art

[0002] In recent years, the development of displays has shown a trend towards high integration and low cost. One of the most important technologies is the mass production of Gate Driver on Array (GOA) technology. Using GOA technology, the drive control circuit is integrated onto the array substrate of the display panel to form a scan drive for the display panel, thereby eliminating the gate driver integrated circuit component and reducing product costs in terms of both material costs and manufacturing process. The drive control circuit is typically composed of multiple cascaded shift register units. If the output of the shift register unit is unstable, it will cause display abnormalities.

[0003] Summary of the Invention

[0004] The present disclosure provides a shift register unit, a drive control circuit, a display device, and a drive method. The specific solutions are as follows:

[0005] The shift register unit provided by the embodiment of the present disclosure includes:

[0006] an input circuit coupled to the signal input terminal, the first clock signal terminal, and the first node, and configured to provide the signal of the signal input terminal to the first node in response to the signal of the first clock signal terminal;

[0007] a first stabilization circuit coupled to the first node, a switch control signal terminal, and a stabilization control signal terminal, and configured to provide a signal from the stabilization control signal terminal to the first node in response to a signal from the switch control signal terminal;

[0008] a conduction control circuit coupled to the first node and the second node, and configured to conduct the first node and the second node in response to a signal at a first reference signal terminal;

[0009] The output circuit is coupled to the second node, the second clock signal terminal and the signal output terminal, and is configured to provide the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node, so that the signal output terminal outputs a driving signal.

[0010] Optionally, in an embodiment of the present disclosure, the first stabilization circuit includes a first transistor, a first electrode of the first transistor is coupled to the first node, a second electrode of the first transistor is coupled to the stabilization control signal terminal, and a gate of the first transistor is coupled to the switch control signal terminal.

[0011] Optionally, in an embodiment of the present disclosure, a second stabilization circuit is also included, which includes a first capacitor and a second transistor; the gate of the second transistor and the first electrode of the first capacitor are both coupled to a third node, the first electrode of the second transistor is coupled to the second clock signal end, and the second electrode of the second transistor is coupled to the second electrode of the first capacitor.

[0012] Optionally, in an embodiment of the present disclosure, the switch control signal terminal is coupled to the second electrode of the first capacitor.

[0013] Optionally, in an embodiment of the present disclosure, the switch control signal terminal and the second clock signal terminal are the same signal terminal.

[0014] Optionally, in an embodiment of the present disclosure, the stabilization control signal terminal and the signal output terminal are the same signal terminal.

[0015] Optionally, in an embodiment of the present disclosure, the stabilization control signal terminal and the second reference signal terminal are the same signal terminal.

[0016] Optionally, in an embodiment of the present disclosure, the input circuit includes a third transistor; the gate of the third transistor is coupled to the first clock signal terminal, the first electrode of the third transistor is coupled to the signal input terminal, and the second electrode of the third transistor is coupled to the first node.

[0017] Optionally, in an embodiment of the present disclosure, the conduction control circuit includes a fourth transistor; the gate of the fourth transistor is coupled to the first reference signal terminal, the first electrode of the fourth transistor is coupled to the first node, and the second electrode of the fourth transistor is coupled to the second node.

[0018] Optionally, in the embodiment of the present disclosure, the output circuit includes a second capacitor and a fifth transistor;

[0019] The first electrode of the second capacitor and the gate of the fifth transistor are both coupled to the second node;

[0020] A first electrode of the fifth transistor is coupled to the second clock signal terminal, and a second electrode of the fifth transistor and a second electrode of the second capacitor are both coupled to the signal output terminal.

[0021] Optionally, in the embodiment of the present disclosure, the shift register unit further includes:

[0022] a first control circuit coupled to a third node and configured to provide a signal from the first reference signal terminal to the third node in response to a signal from the first clock signal terminal, and to provide a signal from the first clock signal terminal to the third node in response to a signal from the first node;

[0023] The second control circuit is coupled to the signal output terminal and configured to provide a signal from a second reference signal terminal to the signal output terminal in response to a signal from the third node.

[0024] Optionally, in an embodiment of the present disclosure, the first control circuit includes a sixth transistor and a seventh transistor;

[0025] The gate of the sixth transistor is coupled to the first clock signal terminal, the first electrode of the sixth transistor is coupled to the first reference signal terminal, and the second electrode of the sixth transistor is coupled to the third node;

[0026] A gate of the seventh transistor is coupled to the first node, a first electrode of the seventh transistor is coupled to the first clock signal terminal, and a second electrode of the seventh transistor is coupled to the third node.

[0027] Optionally, in the embodiment of the present disclosure, the second control circuit includes an eighth transistor and a third capacitor;

[0028] The gate of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the signal output terminal, and the second electrode of the eighth transistor is coupled to the second reference signal terminal;

[0029] A first electrode of the third capacitor is coupled to the second reference signal terminal, and a second electrode of the third capacitor is coupled to the third node.

[0030] Accordingly, the drive control circuit provided by the embodiment of the present disclosure includes:

[0031] A plurality of the above shift register units are cascaded;

[0032] The signal input terminal of the first stage shift register unit is coupled to the frame trigger signal terminal;

[0033] In every two adjacent stages of shift register units, the signal input end of the next stage shift register unit is coupled to the signal output end of the previous stage shift register unit.

[0034] Accordingly, the display device provided by the embodiment of the present disclosure includes:

[0035] Drive control circuit as described above.

[0036] Accordingly, the driving method of the shift register unit provided in the embodiment of the present disclosure includes:

[0037] In the first stage, the input circuit provides the signal of the signal input terminal to the first node in response to the signal of the first clock signal terminal; the conduction control circuit connects the first node and the second node in response to the signal of the first reference signal terminal; and the output circuit provides the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node;

[0038] In the second stage, the output circuit provides the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node, so that the signal output terminal outputs the driving signal;

[0039] In the third stage, the input circuit responds to the signal of the first clock signal terminal and provides the signal of the signal input terminal to the first node; the first stabilization circuit responds to the signal of the switch control signal terminal and provides the signal of the stabilization control signal terminal to the first node.

[0040] Optionally, in the embodiment of the present disclosure, after the third stage, the driving method further includes:

[0041] In the fourth stage, the first stabilization circuit responds to the signal of the switch control signal terminal to provide the signal of the stabilization control signal terminal to the first node, and responds to the signal of the third node to provide the signal of the second clock signal terminal to the third node; the conduction control circuit responds to the signal of the first reference signal terminal to conduct the first node and the second node.

[0042] Optionally, in the embodiment of the present disclosure, the driving method further includes:

[0043] In the first phase, the first control circuit provides the signal of the first reference signal terminal to the third node in response to the signal of the first clock signal terminal, and provides the signal of the first clock signal terminal to the third node in response to the signal of the first node; the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node;

[0044] In the second phase, the first control circuit provides the signal of the first clock signal terminal to the third node in response to the signal of the first node;

[0045] In the third phase, the first control circuit provides the signal of the first reference signal terminal to the third node in response to the signal of the first clock signal terminal; the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node;

[0046] In the fourth phase, the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic structural diagram of a shift register unit in the related art;

[0048] FIG2 is a schematic diagram of voltage simulation waveforms of various nodes of the shift register unit shown in FIG1 in a working state;

[0049] FIG3 is a schematic diagram of some structures of a shift register unit provided by an embodiment of the present disclosure;

[0050] FIG4 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0051] FIG5 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0052] FIG6 is another signal timing diagram provided by an embodiment of the present disclosure;

[0053] FIG7 is a schematic diagram of some further structures of the shift register unit provided by the embodiment of the present disclosure;

[0054] FIG8 is a schematic diagram of some structures of a drive control circuit provided by an embodiment of the present disclosure;

[0055] FIG9 is a flow chart of a driving method of a shift register unit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0057] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0058] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0059] In the related art, as shown in Figures 1 and 2, Figure 1 is a schematic diagram of the structure of the shift register unit in Gate GOA, which includes transistors M1 to M8 and capacitors C01 and C02. Figure 2 is a schematic diagram of the simulated waveforms of the voltages at various nodes of the shift register unit shown in Figure 1 when in operation. During the period when Gout remains at a high level, the n2 node is only pulled down by VGL when GCK is set low. Once the voltage of the n2 node is coupled and jumps, it is easy to cause voltage instability when GCK is at a high level, thereby affecting the stability of the Gout output.

[0060] In view of this, an embodiment of the present disclosure provides a shift register unit, as shown in FIG3 , the shift register unit includes:

[0061] The input circuit 10 is coupled to the signal input terminal IP, the first clock signal terminal CK and the first node N1, and is configured to provide the signal of the signal input terminal IP to the first node N1 in response to the signal of the first clock signal terminal CK;

[0062] A first stabilization circuit 20 is coupled to the first node N1, the switch control signal terminal CTL, and the stabilization control signal terminal SC, and is configured to provide the signal of the stabilization control signal terminal SC to the first node N1 in response to the signal of the switch control signal terminal CTL;

[0063] In a specific implementation process, the switch control signal terminal CTL may include an interface of a signal line or a node in a circuit.

[0064] The conduction control circuit 30 is coupled to the first node N1 and the second node N2 and is configured to conduct the first node N1 and the second node N2 in response to a signal of the first reference signal terminal VGL;

[0065] The output circuit 40 is coupled to the second node N2, the second clock signal terminal CB and the signal output terminal OT, and is configured to provide the signal of the second clock signal terminal CB to the signal output terminal OT in response to the signal of the second node N2, so that the signal output terminal OT outputs a driving signal.

[0066] In the disclosed embodiment, the input circuit 10, the first stabilization circuit 20, the conduction control circuit 30, and the output circuit 40 cooperate with each other to enable the signal output terminal OT to output a driving signal, thereby achieving a driving process for the coupled signal. Furthermore, by providing the first stabilization circuit 20, the signal of the stabilization control signal terminal SC can be provided to the first node N1 during the third phase, thereby causing the output circuit 40 to be cut off as much as possible, maintaining a stable level of the signal at the first node N1, thereby improving the stability of the signal output by the signal output terminal OT and ensuring the driving performance of the shift register unit.

[0067] In the embodiment of the present disclosure, as shown in Figure 3, the first stabilization circuit 20 includes a first transistor T1, a first electrode of the first transistor T1 is coupled to the first node N1, a second electrode of the first transistor T1 is coupled to the stabilization control signal terminal SC, and a gate of the first transistor T1 is coupled to the switch control signal terminal CTL.

[0068] In a specific implementation, the first transistor T1 can be turned on under the control of the active level of the switch control signal transmitted by the switch control signal terminal CTL, and can be turned off under the control of the inactive level of the switch control signal. Exemplarily, if the first transistor T1 is configured as a P-type transistor, the active level of the switch control signal is a low level, and the inactive level of the switch control signal is a high level. Exemplarily, if the first transistor T1 is configured as an N-type transistor, the active level of the switch control signal is a high level, and the inactive level of the switch control signal is a low level.

[0069] In an embodiment of the present disclosure, as shown in Figure 3, the shift register unit further includes a second stabilization circuit 21, which includes a first capacitor C1 and a second transistor T2; the gate of the second transistor T2 and the first electrode of the first capacitor C1 are both coupled to the third node N3, the first electrode of the second transistor T2 is coupled to the second clock signal terminal CB, and the second electrode of the second transistor T2 is coupled to the second electrode of the first capacitor C1.

[0070] In a specific implementation, the gate of the second transistor T2 and the first electrode of the first capacitor C1 are both coupled to the third node N3. In this way, the second transistor T2 can be turned on under the control of the active level of the signal transmitted by the third node N3 and turned off under the control of the inactive level of the signal transmitted by the third node N3. Exemplarily, the second transistor T2 is configured as an N-type transistor, the active level of the signal transmitted by the third node N3 is a high level, and the inactive level of the signal transmitted by the third node N3 is a low level. Exemplarily, the second transistor T2 is configured as a P-type transistor, the active level of the signal transmitted by the third node N3 is a low level, and the inactive level of the signal transmitted by the third node N3 is a high level.

[0071] In the embodiment of the present disclosure, as shown in FIG3 , the switch control signal terminal CTL is coupled to the second electrode of the first capacitor C1 .

[0072] Exemplarily, the switch control signal terminal CTL and the second electrode of the first capacitor C1 are both coupled to the fourth node N4 in FIG. 3 .

[0073] In an embodiment of the present disclosure, as shown in FIG3 , the stabilization control signal terminal SC and the second reference signal terminal VGH are the same signal terminal.

[0074] For example, the stable control signal terminal SC and the second reference signal terminal VGH may be coupled together, which can reduce the number of signal lines and reduce wiring difficulty.

[0075] In the embodiment of the present disclosure, as shown in Figure 3, the input circuit 10 includes a third transistor T3; the gate of the third transistor T3 is coupled to the first clock signal terminal CK, the first electrode of the third transistor T3 is coupled to the signal input terminal IP, and the second electrode of the third transistor T3 is coupled to the first node N1.

[0076] In a specific implementation, the third transistor T3 can be turned on under the control of the active level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off under the control of the inactive level of the first clock signal transmitted by the first clock signal terminal CK. Exemplarily, the third transistor T3 is configured as an N-type transistor, the active level of the first clock signal is a high level, and the inactive level of the first clock signal is a low level. Exemplarily, the third transistor T3 is configured as a P-type transistor, the active level of the first clock signal is a low level, and the inactive level of the first clock signal is a high level.

[0077] In the embodiment of the present disclosure, as shown in Figure 3, the conduction control circuit 30 includes a fourth transistor T4; the gate of the fourth transistor T4 is coupled to the first reference signal terminal VGL, the first electrode of the fourth transistor T4 is coupled to the first node N1, and the second electrode of the fourth transistor T4 is coupled to the second node N2.

[0078] In a specific implementation, the fourth transistor T4 can be turned on under the control of the active level of the first reference signal transmitted by the first reference signal terminal VGL, and can be turned off under the control of the inactive level of the first reference signal transmitted by the first reference signal terminal VGL. Exemplarily, the fourth transistor T4 is configured as an N-type transistor, the active level of the first reference signal is a high level, and the inactive level of the first reference signal is a low level. Exemplarily, the third transistor T3 is configured as a P-type transistor, the active level of the first reference signal is a low level, and the inactive level of the first reference signal is a high level.

[0079] In the embodiment of the present disclosure, as shown in FIG3 , the output circuit 40 includes a second capacitor C2 and a fifth transistor T5 ;

[0080] The first electrode of the second capacitor C2 and the gate of the fifth transistor T5 are both coupled to the second node N2;

[0081] A first electrode of the fifth transistor T5 is coupled to the second clock signal terminal CB, and a second electrode of the fifth transistor T5 and a second electrode of the second capacitor C2 are both coupled to the signal output terminal OT.

[0082] In a specific implementation, the fifth transistor T5 can be turned on under the control of the active level of the signal transmitted by the second node N2, and can be turned off under the control of the inactive level of the signal transmitted by the second node N2. Exemplarily, the fifth transistor T5 is configured as an N-type transistor, the active level of the signal transmitted by the second node N2 is a high level, and the inactive level of the signal transmitted by the second node N2 is a low level. Exemplarily, the fifth transistor T5 is configured as a P-type transistor, the active level of the signal transmitted by the second node N2 is a low level, and the inactive level of the signal transmitted by the second node N2 is a high level.

[0083] In an embodiment of the present disclosure, as shown in FIG3 , the shift register unit further includes:

[0084] A first control circuit 50 is coupled to the third node N3 and is configured to provide the signal of the first reference signal terminal VGL to the third node N3 in response to the signal of the first clock signal terminal CK, and to provide the signal of the first clock signal terminal CK to the third node N3 in response to the signal of the first node N1;

[0085] The second control circuit 60 is coupled to the signal output terminal OT, and is configured to provide the signal of the second reference signal terminal VGH to the signal output terminal OT in response to the signal of the third node N3.

[0086] In the embodiment of the present disclosure, as shown in FIG3 , the first control circuit 50 includes a sixth transistor T6 and a seventh transistor T7;

[0087] The gate of the sixth transistor T6 is coupled to the first clock signal terminal CK, the first electrode of the sixth transistor T6 is coupled to the first reference signal terminal VGL, and the second electrode of the sixth transistor T6 is coupled to the third node N3;

[0088] A gate of the seventh transistor T7 is coupled to the first node N1 , a first electrode of the seventh transistor T7 is coupled to the first clock signal terminal CK, and a second electrode of the seventh transistor T7 is coupled to the third node N3 .

[0089] In a specific implementation, the sixth transistor T6 can be turned on under the control of the active level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off under the control of the inactive level of the first clock signal. Exemplarily, the sixth transistor T6 is configured as an N-type transistor, the active level of the first clock signal is a high level, and the inactive level of the first clock signal is a low level. Exemplarily, the sixth transistor T6 is configured as a P-type transistor, the active level of the first clock signal is a low level, and the inactive level of the first clock signal is a high level.

[0090] In a specific implementation, the seventh transistor T7 can be turned on under the control of the active level of the signal transmitted by the first node N1, and can be turned off under the control of the inactive level of the signal transmitted by the first node N1. Exemplarily, the seventh transistor T7 is configured as an N-type transistor, the active level of the signal transmitted by the first node N1 is a high level, and the inactive level of the signal transmitted by the first node N1 is a low level. Exemplarily, the seventh transistor T7 is configured as a P-type transistor, the active level of the signal transmitted by the first node N1 is a low level, and the inactive level of the signal transmitted by the first node N1 is a high level.

[0091] In the embodiment of the present disclosure, as shown in FIG3 , the second control circuit 60 includes an eighth transistor T8 and a third capacitor C3 ;

[0092] The gate of the eighth transistor T8 is coupled to the third node N3, the first electrode of the eighth transistor T8 is coupled to the signal output terminal OT, and the second electrode of the eighth transistor T8 is coupled to the second reference signal terminal VGH;

[0093] A first electrode of the third capacitor C3 is coupled to the second reference signal terminal VGH, and a second electrode of the third capacitor C3 is coupled to the third node N3.

[0094] In a specific implementation, the eighth transistor T8 can be turned on under the control of the active level of the signal transmitted by the third node N3, and can be turned off under the control of the inactive level of the signal transmitted by the third node N3. Exemplarily, the eighth transistor T8 is configured as an N-type transistor, the active level of the signal transmitted by the third node N3 is a high level, and the inactive level of the signal transmitted by the third node N3 is a low level. Exemplarily, the eighth transistor T8 is configured as a P-type transistor, the active level of the signal transmitted by the third node N3 is a low level, and the inactive level of the signal transmitted by the third node N3 is a high level.

[0095] In the specific implementation process, according to the flow direction of the signal, the first electrode of the above-mentioned transistor can be used as its source, and the second electrode can be used as its drain; or, the first electrode can be used as its drain, and the second electrode can be used as its source, without making a specific distinction here.

[0096] It should be noted that the transistors mentioned in the embodiments of the present disclosure may be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSs), which are not limited here.

[0097] In the embodiment of the present disclosure, the above-mentioned transistors can all be set as P-type transistors, and the first reference signal terminal VGL can be configured to load a constant first reference voltage, and the first reference voltage is generally a negative value, such as -9V. And, the second reference signal terminal VGH can load a constant second reference voltage, and the second reference voltage can generally be a positive value, such as 7V. In actual applications, the specific values ​​of the above-mentioned voltages can be designed and determined according to the actual application environment, and are not limited here. Of course, the above-mentioned transistors can all be set as N-type transistors, and are not limited here.

[0098] The following describes the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure, taking the shift register unit shown in Figure 3 as an example and combining it with the signal timing diagram shown in Figure 4. In the following description, "1" represents a high-level signal, "0" represents a low-level signal, ip represents the input signal of the signal input terminal IP, ck represents the first clock signal of the first clock signal terminal CK, cb represents the second clock signal of the second clock signal terminal CB, and ot represents the output signal of the signal output terminal OT. It should be noted that 1 and 0 are logic levels, which are only for better explanation of the specific working process of the embodiment of the present disclosure, rather than the voltage applied to the gate of each transistor during specific implementation.

[0099] Specifically, an example is provided in which the voltage value of the first reference signal outputted from the first reference signal terminal VGL is a negative voltage, the voltage value of the second reference signal outputted from the second reference signal terminal VGH is a positive voltage, and all transistors are P-type transistors. Four stages, namely the first stage f1, the second stage f2, the third stage f3, and the fourth stage f4, are selected from the signal timing diagram shown in FIG4 . It should be noted that the signal timing diagram shown in FIG4 only represents the operating process of a certain shift register unit in the current frame. The operating processes of the shift register unit in other frames are substantially the same as the operating process in the current frame, and therefore are not further described herein.

[0100] Since the gate of the fourth transistor T4 is coupled to the first reference signal terminal VGL, and the first reference signal terminal VGL inputs a low-level signal, the fourth transistor T4 is in a normally-on state. For ease of description, the state of the fourth transistor T4 at any time will not be analyzed below.

[0101] In the first stage f1, ip = 0, ck = 0, cb = 1;

[0102] Since the input signal ip provides a low level, the first clock signal ck provides a low level, and the second clock signal cb provides a high level, the third transistor T3 is turned on, the low level of the input signal ip is provided to the first node N1 and the second node N2, the fifth transistor T5 and the seventh transistor T7 are both turned on, the third node N3 is at a low level, the second transistor T2 and the eighth transistor T8 are both turned on, the fourth node N4 is at a high level, the first transistor T1 is turned off, and the sixth transistor T6 is turned on, then the signal output by the signal output terminal OT is a high level.

[0103] In the second stage f2, ip=1, ck=1, cb=0;

[0104] Since the input signal ip provides a high level, the first clock signal ck provides a high level, and the second clock signal cb provides a low level, the third transistor T3 is turned off, the second node N2 maintains a low level, the first node N1 is at a low level, the fifth transistor T5 and the seventh transistor T7 are both turned on, the high level of the first clock signal ck is provided to the third node N3, the second transistor T2 and the eighth transistor T8 are both turned off, the fourth node N4 maintains a high level, the first transistor T1 is turned off, and the sixth transistor T6 is turned off, then the signal output by the signal output terminal OT is a low level.

[0105] In the third stage f3, ip = 1, ck = 0, cb = 1;

[0106] Since the input signal ip provides a high level, the first clock signal ck provides a low level, and the second clock signal cb provides a high level, the third transistor T3 is turned on, the high level of the input signal ip is provided to the first node N1 and the second node N2, the fifth transistor T5 and the seventh transistor T7 are both turned off, the signal at the third node N3 is a low level, the second transistor T2 and the eighth transistor T8 are both turned on, the fourth node N4 maintains a high level, the first transistor T1 is turned off, and the sixth transistor T6 is turned on, then the signal output by the signal output terminal OT is a high level.

[0107] In the fourth stage f4, ip = 1, ck = 1, cb = 0;

[0108] Since the input signal ip provides a high level, the first clock signal ck provides a high level, and the second clock signal provides a low level, the third transistor T3 and the sixth transistor T6 are both turned off, the third node N3 maintains a low level, the second transistor T2 and the eighth transistor T8 are both turned on, the fourth node N4 is at a low level, the first transistor T1 is turned on, the first node N1 and the second node N2 are at a high level, the fifth transistor T5 and the seventh transistor T7 are both turned off, and the signal output by the signal output terminal OT is a high level.

[0109] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 5, which is a modification of the embodiment described above. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0110] In the embodiment of the present disclosure, as shown in Figure 5, the first stabilization circuit 20 includes a first transistor T1, a first electrode of the first transistor T1 is coupled to the first node N1, a second electrode of the first transistor T1 is coupled to the stabilization control signal terminal SC, and a gate of the first transistor T1 is coupled to the switch control signal terminal CTL.

[0111] In an embodiment of the present disclosure, as shown in Figure 5, the shift register unit further includes a second stabilization circuit 21, which includes a first capacitor C1 and a second transistor T2; the gate of the second transistor T2 and the first electrode of the first capacitor C1 are both coupled to the third node N3, the first electrode of the second transistor T2 is coupled to the second clock signal terminal CB, and the second electrode of the second transistor T2 is coupled to the second electrode of the first capacitor C1.

[0112] In an embodiment of the present disclosure, as shown in FIG5 , the switch control signal terminal CTL and the second clock signal terminal CB are the same signal terminal.

[0113] For example, the switch control signal terminal CTL and the second clock signal terminal CB may be coupled together, which can reduce the number of signal lines and reduce wiring difficulty.

[0114] In the embodiment of the present disclosure, as shown in FIG5 , the stabilization control signal terminal SC and the signal output terminal OT are the same signal terminal.

[0115] For example, the stabilization control signal terminal SC and the signal output terminal OT may be coupled together, which can reduce the number of signal lines and reduce wiring difficulty.

[0116] Based on the above embodiment, the first transistor T1 is controlled by the second clock signal of the second clock signal terminal CB to be turned on and off. The rest of the working process can refer to the description of the above embodiment and will not be repeated here.

[0117] The following describes the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure, taking the shift register unit shown in Figure 5 as an example and combining it with the signal timing diagram shown in Figure 6. In the following description, "1" represents a high-level signal, "0" represents a low-level signal, ip represents the input signal of the signal input terminal IP, ck represents the first clock signal of the first clock signal terminal CK, cb represents the second clock signal of the second clock signal terminal CB, and ot represents the output signal of the signal output terminal OT. It should be noted that 1 and 0 are logic levels, which are only for better explanation of the specific working process of the embodiment of the present disclosure, rather than the voltage applied to the gate of each transistor during specific implementation.

[0118] Specifically, an example is provided in which the voltage value of the first reference signal outputted from the first reference signal terminal VGL is a negative voltage, the voltage value of the second reference signal outputted from the second reference signal terminal VGH is a positive voltage, and all transistors are P-type transistors. Four stages, namely the first stage f1, the second stage f2, the third stage f3, and the fourth stage f4, are selected from the signal timing diagram shown in FIG6 . It should be noted that the signal timing diagram shown in FIG6 only represents the operating process of a certain shift register unit in the current frame. The operating processes of the shift register unit in other frames are substantially the same as the operating process in the current frame, and therefore are not described in detail here.

[0119] Since the gate of the fourth transistor T4 is coupled to the first reference signal terminal VGL, and the first reference signal terminal VGL inputs a low-level signal, the fourth transistor T4 is in a normally-on state. For ease of description, the state of the fourth transistor T4 at any time will not be analyzed below.

[0120] In the first stage f1, ip = 0, ck = 0, cb = 1;

[0121] Since the input signal ip provides a low level, the first clock signal ck provides a low level, and the second clock signal cb provides a high level, the third transistor T3 is turned on, the low level of the input signal ip is provided to the first node N1 and the second node N2, the fifth transistor T5 and the seventh transistor T7 are both turned on, the low level of the first reference signal is provided to the third node N3, the third node N3 is a low level, the second transistor T2 and the eighth transistor T8 are both turned on, the fourth node N4 is a high level, and the first transistor T1 is turned off, the sixth transistor T6 is turned on, and the signal output by the signal output terminal OT is a high level.

[0122] In the second stage f2, ip=1, ck=1, cb=0;

[0123] Since the input signal ip provides a high level, the first clock signal ck provides a high level, and the second clock signal cb provides a low level, the third transistor T3 is turned off, the first node N1 and the second node N2 maintain a low level, the fifth transistor T5 and the seventh transistor T7 are both turned on, the high level of the first clock signal ck is provided to the third node N3, the second transistor T2 and the eighth transistor T8 are both turned off, the fourth node N4 maintains a high level, and the first transistor T1 is turned on, the sixth transistor T6 is turned off, and the signal output by the signal output terminal OT is a low level.

[0124] In the third stage f3, ip = 1, ck = 0, cb = 1;

[0125] Since the input signal ip provides a high level, the first clock signal ck provides a low level, and the second clock signal cb provides a high level, the third transistor T3 is turned on, the high level of the input signal ip is provided to the first node N1 and the second node N2, the fifth transistor T5 and the seventh transistor T7 are both turned off, the third node N3 is at a low level, the second transistor T2 and the eighth transistor T8 are both turned on, the fourth node N4 maintains a high level, and the first transistor T1 is turned off, the sixth transistor T6 is turned on, and the signal output by the signal output terminal OT is a high level.

[0126] In the fourth stage f4, ip = 1, ck = 1, cb = 0;

[0127] Since the input signal ip provides a high level, the first clock signal ck provides a high level, and the second clock signal provides a low level, the third transistor T3 is turned off, the first node N1 and the second node N2 maintain a high level, the fifth transistor T5 and the seventh transistor T7 are both turned off, the third node N3 is a low level, the second transistor T2 and the eighth transistor T8 are both turned on, the fourth node N4 is a low level, and the first transistor T1 is turned on, and the sixth transistor T6 is turned off, then the signal output by the signal output terminal OT is a high level.

[0128] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 7, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0129] In the embodiment of the present disclosure, as shown in Figure 7, the first stabilization circuit 20 includes a first transistor T1, a first electrode of the first transistor T1 is coupled to the first node N1, a second electrode of the first transistor T1 is coupled to the stabilization control signal terminal SC, and a gate of the first transistor T1 is coupled to the switch control signal terminal CTL.

[0130] In an embodiment of the present disclosure, as shown in FIG7 , the switch control signal terminal CTL and the second clock signal terminal CB are the same signal terminal.

[0131] In the embodiment of the present disclosure, as shown in FIG7 , the stabilization control signal terminal SC and the signal output terminal OT are the same signal terminal.

[0132] Based on the above embodiment, the first transistor T1 is controlled by the second clock signal of the second clock signal terminal CB to be turned on and off. The rest of the working process can refer to the description of the above embodiment and will not be repeated here.

[0133] In the exemplary embodiment shown in FIG. 7 , compared with FIG. 3 and FIG. 5 , layout space is saved.

[0134] The above is merely an example to illustrate the specific structure of the shift register unit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuits is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0135] Based on the same disclosed concept, an embodiment of the present disclosure also provides a drive control circuit, including multiple cascaded shift register units; the signal input terminal IP of the first-level shift register unit is coupled to the frame trigger signal terminal; in each adjacent two-level shift register unit, the signal input terminal IP of the next-level shift register unit is coupled to the signal output terminal of the previous-level shift register unit.

[0136] For example, as shown in FIG8 , the drive control circuit includes a plurality of cascaded shift register units SR1, SR2, SR3, ..., SRn-2, SRn-1, and SRn; where n is a natural number. The value of n depends on the actual design requirements. The shift register unit uses the shift register unit shown in FIG3 , FIG5 , or FIG7 . Each shift register unit includes a signal input terminal IP, a signal output terminal, a first clock signal terminal, and a second clock signal terminal. Among them, each endpoint is connected to the signal marked in the timing diagram shown in Figure 4: the signal input terminal IP of the shift register unit SR1 is coupled to the frame trigger signal terminal STV, where stv represents the frame trigger signal provided by the frame trigger signal terminal STV. In each of the remaining shift register units, the signal output terminal of the previous shift register unit is coupled to the signal input terminal IP of the next shift register unit. That is, the signal output from the signal output terminal of the shift register unit SR1 can be used as the signal of the signal input terminal IP of the shift register unit SR2, and the signal output from the signal output terminal of the shift register unit SR2 can be used as the signal of the signal input terminal IP of the shift register unit SR3... The signal output from the signal output terminal of the shift register unit SRn-1 can be used as the signal of the signal input terminal IP of the shift register unit SRn, until there is no next shift register unit. The first clock signal is connected to the first clock signal, and the second clock signal terminal is connected to the second clock signal. The timing of the drive control circuit shown in Figure 8 can be inferred based on the connection relationship between the various shift register units and the timing shown in Figure 4, and will not be repeated here.

[0137] Based on the same disclosed concept, embodiments of the present disclosure further provide a display device comprising a plurality of pixel units, a plurality of signal lines, and the aforementioned drive control circuit provided in embodiments of the present disclosure. A signal output terminal of a shift register unit in the drive control circuit is coupled to at least one of the plurality of signal lines. The principles underlying the problem solved by this display device are similar to those of the aforementioned drive control circuit. Therefore, the implementation of this display device can be referenced to the implementation of the aforementioned drive control circuit, and any repetitions will not be repeated here.

[0138] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0139] In a specific implementation, the display device may include multiple pixel units, multiple gate lines, and data lines. Each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. The display device provided in the embodiments of the present disclosure may be an organic light-emitting display device or a liquid crystal display device, without limitation.

[0140] In the embodiment of the present disclosure, a plurality of gate lines are also provided with corresponding drive control circuits; one gate line is coupled to the signal output terminal of a shift register unit in the drive control circuit. For example, when the display device provided in the embodiment of the present disclosure is a liquid crystal display device, the TFT in the sub-pixel can be coupled to the gate line, and the drive control circuit can be used as a gate drive circuit, and the gate drive circuit is coupled to the gate line to provide a gate scan signal to the TFT in the sub-pixel. It should be noted that the TFT in the sub-pixel can be an N-type transistor or a P-type transistor, which is not limited here.

[0141] In some embodiments of the present disclosure, when the display device provided in the embodiments of the present disclosure is an organic light-emitting display device, the display device further includes a plurality of light-emitting control signal lines; a drive control circuit is provided for each of the plurality of light-emitting control signal lines; and one light-emitting control signal line is coupled to the signal output terminal of a shift register unit in the drive control circuit. Furthermore, a plurality of gate lines are also provided with a drive control circuit; and one gate line is coupled to the signal output terminal of a shift register unit in the drive control circuit. For example, an organic light-emitting display device generally includes a plurality of organic light-emitting diodes and a pixel circuit connected to each organic light-emitting diode. The pixel circuit generally includes a light-emitting control transistor for controlling the light emission of the organic light-emitting diode and a scan control transistor for controlling the input of a data signal.

[0142] In a specific implementation, the light-emitting control transistor can be coupled to a light-emitting control signal line, and the scan control transistor can be coupled to a gate line. The organic light-emitting display device can include the aforementioned drive control circuit provided by an embodiment of the present disclosure. The drive control circuit can function as a light-emitting drive circuit, coupled to the light-emitting control transistor, and used to provide a light-emitting control signal to the light-emitting control transistor. Alternatively, the drive control circuit can function as a gate drive circuit, coupled to a gate line, and used to provide a gate scan signal to the scan control transistor.

[0143] Of course, the organic light-emitting display device may also include two of the above-mentioned driving control circuits provided in the embodiments of the present disclosure, wherein one of the driving control circuits may serve as a light-emitting driving circuit, coupled to a light-emitting control transistor, and used to provide a light-emitting control signal to the light-emitting control transistor; and the other driving control circuit may serve as a gate driving circuit, coupled to a gate line, and used to provide a gate scanning signal to the scanning control transistor, which is not limited here.

[0144] Based on the same disclosed concept, as shown in FIG9 , an embodiment of the present disclosure provides a driving method of the above-mentioned shift register unit, including:

[0145] S101: In the first stage, the input circuit provides the signal of the signal input terminal to the first node in response to the signal of the first clock signal terminal; the conduction control circuit connects the first node and the second node in response to the signal of the first reference signal terminal; the output circuit provides the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node;

[0146] S102: In the second stage, the output circuit provides the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node, so that the signal output terminal outputs the driving signal;

[0147] S103: In the third stage, the input circuit responds to the signal of the first clock signal terminal and provides the signal of the signal input terminal to the first node; the first stabilization circuit responds to the signal of the switch control signal terminal and provides the signal of the stabilization control signal terminal to the first node.

[0148] In an embodiment of the present disclosure, as shown in FIG9 , after the third stage, the driving method further includes:

[0149] S104: In the fourth stage, the first stabilization circuit responds to the signal of the switch control signal end to provide the signal of the stabilization control signal end to the first node, and responds to the signal of the third node to provide the signal of the second clock signal end to the third node; the conduction control circuit responds to the signal of the first reference signal end to conduct the first node and the second node.

[0150] In an embodiment of the present disclosure, the driving method further includes:

[0151] In the first phase, the first control circuit provides the signal of the first reference signal terminal to the third node in response to the signal of the first clock signal terminal, and provides the signal of the first clock signal terminal to the third node in response to the signal of the first node; the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node;

[0152] In the second phase, the first control circuit provides the signal of the first clock signal terminal to the third node in response to the signal of the first node;

[0153] In the third stage, the first control circuit provides the signal of the first reference signal terminal to the third node in response to the signal of the first clock signal terminal; the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node;

[0154] In the fourth phase, the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node.

[0155] The driving principle and specific implementation of the driving method are the same as those of the shift register unit in the above embodiment. Therefore, the driving method can be implemented with reference to the specific implementation of the shift register unit in the above embodiment, which will not be repeated here.

[0156] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0157] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A shift register unit, wherein: include: an input circuit coupled to the signal input terminal, the first clock signal terminal and the first node, and configured to provide the signal of the signal input terminal to the first node in response to the signal of the first clock signal terminal; A first stabilization circuit is coupled to the first node, a switch control signal terminal and a stabilization control signal terminal, and is configured to respond to a signal at the switch control signal terminal and provide a signal at the stabilization control signal terminal to the first node; A conduction control circuit, coupled to the first node and the second node, configured to conduct the first node and the second node in response to a signal at a first reference signal terminal; The output circuit is coupled to the second node, the second clock signal terminal and the signal output terminal, and is configured to provide the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node, so that the signal output terminal outputs a driving signal.

2. The shift register unit according to claim 1, wherein: The first stabilization circuit includes a first transistor, a first electrode of the first transistor is coupled to the first node, a second electrode of the first transistor is coupled to the stabilization control signal terminal, and a gate of the first transistor is coupled to the switch control signal terminal.

3. The shift register unit according to claim 1, wherein: It also includes a second stabilization circuit, which includes a first capacitor and a second transistor; the gate of the second transistor and the first electrode of the first capacitor are both coupled to the third node, the first electrode of the second transistor is coupled to the second clock signal end, and the second electrode of the second transistor is coupled to the second electrode of the first capacitor.

4. The shift register unit according to claim 3, wherein: The switch control signal terminal is coupled to the second electrode of the first capacitor.

5. The shift register unit according to claim 2 or 3, wherein: The switch control signal terminal and the second clock signal terminal are the same signal terminal.

6. The shift register unit according to any one of claims 2 to 5, wherein: The stabilization control signal terminal and the signal output terminal are the same signal terminal.

7. The shift register unit according to any one of claims 2 to 5, wherein: The stable control signal terminal and the second reference signal terminal are the same signal terminal.

8. The shift register unit according to any one of claims 1 to 7, wherein: The input circuit includes a third transistor; a gate of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the signal input terminal, and a second electrode of the third transistor is coupled to the first node.

9. The shift register unit according to any one of claims 1 to 8, wherein: The conduction control circuit includes a fourth transistor; a gate of the fourth transistor is coupled to the first reference signal terminal, a first electrode of the fourth transistor is coupled to the first node, and a second electrode of the fourth transistor is coupled to the second node.

10. The shift register unit according to any one of claims 1 to 9, wherein: The output circuit includes a second capacitor and a fifth transistor; A first electrode of the second capacitor and a gate of the fifth transistor are both coupled to the second node; A first electrode of the fifth transistor is coupled to the second clock signal terminal, and a second electrode of the fifth transistor and a second electrode of the second capacitor are both coupled to the signal output terminal.

11. The shift register unit according to any one of claims 1 to 10, wherein: Also includes: a first control circuit coupled to a third node and configured to provide a signal at the first reference signal terminal to the third node in response to a signal at the first clock signal terminal, and to provide a signal at the first clock signal terminal to the third node in response to a signal at the first node; The second control circuit is coupled to the signal output terminal and is configured to provide a signal from a second reference signal terminal to the signal output terminal in response to a signal from the third node.

12. The shift register unit according to claim 11, wherein: The first control circuit includes a sixth transistor and a seventh transistor; The gate of the sixth transistor is coupled to the first clock signal terminal, and the A first electrode is coupled to the first reference signal terminal, and a second electrode of the sixth transistor is coupled to the third node; A gate of the seventh transistor is coupled to the first node, a first electrode of the seventh transistor is coupled to the first clock signal terminal, and a second electrode of the seventh transistor is coupled to the third node.

13. The shift register unit according to claim 11, wherein: The second control circuit includes an eighth transistor and a third capacitor; The gate of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the signal output terminal, and the second electrode of the eighth transistor is coupled to the second reference signal terminal; A first electrode of the third capacitor is coupled to the second reference signal terminal, and a second electrode of the third capacitor is coupled to the third node.

14. A drive control circuit, wherein: include: A plurality of cascaded shift register units according to any one of claims 1 to 13; The signal input terminal of the first stage shift register unit is coupled to the frame trigger signal terminal; In each of two adjacent shift register units, the signal input end of the next shift register unit is coupled to the signal output end of the previous shift register unit.

15. A display device, wherein: include: The drive control circuit as claimed in claim 14.

16. A method for driving a shift register unit according to any one of claims 1 to 13, wherein: include: In the first stage, the input circuit provides the signal of the signal input terminal to the first node in response to the signal of the first clock signal terminal; The conduction control circuit conducts the first node and the second node in response to the signal of the first reference signal terminal; the output circuit provides the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node; In the second stage, the output circuit provides the signal of the second clock signal terminal to the signal output terminal in response to the signal of the second node, so that the signal output terminal outputs the driving signal; In the third stage, the input circuit provides the signal of the signal input terminal to the first node in response to the signal of the first clock signal terminal; The first stabilization circuit provides the signal of the stabilization control signal terminal to the first node in response to the signal of the switch control signal terminal.

17. The driving method according to claim 16, wherein: After the third stage, the driving method further includes: In the fourth stage, the first stabilization circuit responds to the signal of the switch control signal terminal to provide the signal of the stabilization control signal terminal to the first node, and responds to the signal of the third node to provide the signal of the second clock signal terminal to the third node; the conduction control circuit responds to the signal of the first reference signal terminal to conduct the first node and the second node.

18. The driving method according to claim 17, wherein: Also includes: In the first stage, the first control circuit provides the signal of the first reference signal terminal to the third node in response to the signal of the first clock signal terminal, and provides the signal of the first clock signal terminal to the third node in response to the signal of the first node; the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node; In the second stage, the first control circuit provides the signal of the first clock signal terminal to the third node in response to the signal of the first node; In the third stage, the first control circuit provides the signal of the first reference signal terminal to the third node in response to the signal of the first clock signal terminal; the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node; In the fourth stage, the second control circuit provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the third node.

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