Display substrate and display device

Abstract

A display substrate and a display device, the display substrate having a display area (100) and a non-display area (200) surrounding at least one side of the display area (100), the display area (100) being provided with pixel driving circuits (PE) arranged in an array, the non-display area (200) being provided with a gate driving circuit and a gating signal line group (DL), the gating signal line group (DL) comprising: a plurality of gating signal lines, the gate driving circuit is electrically connected with the pixel driving circuit (PE) and the gating signal line group (DL) respectively; the gate drive circuit comprises gate signal lines extending in a first direction (D1), the plurality of gate signal lines are arranged in a second direction (D2), the gate drive circuit comprises a plurality of shift registers, each shift register comprises a gate sub-circuit (10), the gate sub-circuit (10) is electrically connected with a part of the gate signal lines in a gate signal line group (DL), the gate sub-circuit (10) comprises a plurality of gate transistors, the gate transistors are electrically connected with the gate signal lines in the gate signal line group (DL), and the gate transistors are electrically connected with the gate signal lines in the gate signal line group (DL). For any shift register, a plurality of gate transistors in a gate sub-circuit (10) are arranged along a first direction (D1).

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate comprising a display area and a non-display area surrounding at least one side of the display area, wherein the display area is provided with a pixel driving circuit arranged in an array, and the non-display area is provided with a gate driving circuit and a gate signal line group, wherein the gate signal line group includes: a plurality of gate signal lines, and the gate driving circuit is electrically connected to the pixel driving circuit and the gate signal line group, respectively;

[0006] The strobe signal line extends along a first direction, the plurality of strobe signal lines are arranged along a second direction, and the first direction and the second direction intersect;

[0007] The gate drive circuit includes: multiple shift registers, the shift registers include: a gating sub-circuit, the gating sub-circuit is electrically connected to some of the gating signal lines in the gating signal line group, the gating sub-circuit includes: multiple gating transistors, for any shift register, the multiple gating transistors in the gating sub-circuit are arranged along the first direction.

[0008] In an exemplary embodiment, the shift register includes: M strobe signal terminals, and the strobe signal line group includes: 2M strobe signal lines;

[0009] The mth selection signal terminal is electrically connected to the 2m-1th selection signal line or the 2mth selection signal line, the signal of the 2m-1th selection signal line and the signal of the 2mth selection signal line are inverted signals, 1≤m≤M.

[0010] In an exemplary embodiment, the non-display area includes a signal line area and a device area, the gate driver circuit is at least partially located in the device area, the signal line area includes: a first signal line area, a second signal line area, and a third signal line area sequentially arranged along the display area, and the device area includes: a first device area, a second device area, a third device area, and a fourth device area sequentially arranged along the display area;

[0011] The first signal line area is located on a side of the first device area away from the display area, and the third signal line area is located on a side of the fourth device area close to the display area;

[0012] The gating signal line group is located in the first signal line region, and the gating sub-circuit is located in the first device region.

[0013] In an exemplary embodiment, the second signal line region is located between the first signal line region and the first device region, or between the first device region and the second device region.

[0014] In an exemplary embodiment, the length of the first signal line section along the second direction is greater than the length of the second signal line section along the second direction, and the length of the third signal line section along the second direction is greater than the length of the second signal line section along the second direction.

[0015] In an exemplary embodiment, the non-display area is further provided with a clock signal line group, and the gate driving circuit is electrically connected to the clock signal line group;

[0016] The clock signal line group is located in the first signal line area and on a side of the strobe signal line group away from the display area.

[0017] In an exemplary embodiment, the clock signal line group includes: a control clock signal line group and an output clock signal line group;

[0018] The control clock signal line group includes: a plurality of control clock signal lines, the control clock signal lines extending along the first direction, and the plurality of control clock signal lines arranged along the second direction; the output clock signal line group includes: a plurality of output clock signal lines, the output clock signal lines extending along the first direction, and the plurality of output clock signal lines arranged along the second direction, wherein the line width of the output clock signal lines is greater than the line width of the control clock signal lines and the line width of the selection signal lines;

[0019] The shift register includes: a plurality of control clock terminals and a plurality of output clock terminals, wherein any one of the plurality of control clock terminals is electrically connected to one of the control clock signal lines in the control clock signal line group, and any one of the plurality of output clock terminals is electrically connected to one of the output clock signal lines in the output clock signal line group;

[0020] For any shift register, a plurality of control clock terminals are electrically connected to some signal lines in the control clock signal group, and a plurality of output clock terminals are electrically connected to some signal lines in the output clock signal line group;

[0021] The output clock signal line group is located on a side of the control clock signal line group away from the display area.

[0022] In an exemplary embodiment, the non-display area is further provided with a first high-level power line and a second high-level power line;

[0023] The shift register includes: a first high-level power supply terminal and a second high-level power supply terminal. For any shift register, the first high-level power supply terminal is electrically connected to the first high-level power line, and the second high-level power supply terminal is electrically connected to the second high-level power line.

[0024] The first high-level power line and the second high-level power line are located in the second signal line area;

[0025] A line width of any one of the first high-level power line and the second high-level power line is greater than a line width of any signal line located in the first signal line region.

[0026] In an exemplary embodiment, the non-display area is further provided with a first low-level power line and a second low-level power line;

[0027] The shift register includes: a first low-level power supply terminal and a second low-level power supply terminal. For any shift register, the first low-level power supply terminal is electrically connected to the first low-level power line, and the second low-level power supply terminal is electrically connected to the second low-level power line.

[0028] The first low-level power line and the second low-level power line are located in the third signal line area, and the first low-level power line is located on a side of the second low-level power line away from the display area;

[0029] The line width of any one of the first low level power line and the second low level power line is greater than the line width of any signal line located in the first signal line area, and the line width of the first low level power line is smaller than the line width of the second low level power line.

[0030] In an exemplary embodiment, the length of the second device region along the second direction is greater than the length of the first device region along the second direction, the length of the third device region along the second direction is greater than the length of the second device region along the second direction, and the length of the fourth device region along the second direction is greater than the length of the third device region along the second direction.

[0031] In an exemplary embodiment, the shift register further includes: an input subcircuit, a node setting subcircuit, and a pre-processing subcircuit; the plurality of control clock terminals include: a first control clock terminal to a third control clock terminal;

[0032] The node setting subcircuit is electrically connected to at least the second high-level power supply terminal, the second low-level power supply terminal, the second control clock terminal, the third control clock terminal, the first node, and the third node, and is configured to provide a signal from the second high-level power supply terminal or the second low-level power supply terminal to the first node under the control of the signals from the second control clock terminal, the third control clock terminal, and the third node;

[0033] The input sub-circuit is electrically connected to at least the third control clock terminal, the third node and the fifth node respectively, and is configured to provide the signal of the third control clock terminal to the fifth node under the control of the signals of the third node and the third control clock terminal;

[0034] The pre-processing sub-circuit is electrically connected to at least the second node, the third node, the fourth node, the first high-level power supply terminal, and the first control clock terminal, respectively, and is configured to provide a signal from the first control clock terminal or the first high-level power supply terminal to the third node and the fourth node under the control of a signal from the second node and the first control clock terminal;

[0035] The gating subcircuit is also electrically connected to the second control clock terminal and the second node respectively, and is configured to provide the signal of the second control clock terminal to the second node under the control of the signals of the plurality of gating signal terminals;

[0036] The input sub-circuit, the node setting sub-circuit and the pre-processing sub-circuit are located in the second device region and arranged along the first direction. The pre-processing sub-circuit is located between the input sub-circuit and the node setting sub-circuit.

[0037] In an exemplary embodiment, the pre-processing sub-circuit includes: a plurality of pre-processing transistors and pre-processing capacitors;

[0038] The pre-processing capacitor is located on a side of the plurality of pre-processing transistors close to the node setting sub-circuit.

[0039] In an exemplary embodiment, the shift register further comprises: a node separation subcircuit;

[0040] The node separation sub-circuit is electrically connected to the third control clock terminal, the first high-level power supply terminal, the second low-level power supply terminal, the first node, the fifth node, the sixth node, the seventh node, the eighth node, and the ninth node, respectively, and is configured to provide a signal of the fifth node to the sixth to ninth nodes respectively under the control of a signal of the third control clock terminal and the first node, or to provide a signal of the first high-level power supply terminal to the fifth node under the control of a signal of the sixth node;

[0041] The node separation sub-circuit is located in the third device region.

[0042] In an exemplary embodiment, the shift register further includes: an output subcircuit;

[0043] The output sub-circuit is electrically connected to at least a plurality of output clock terminals, a first low-level power terminal and a plurality of signal output terminals, and is configured to output signals corresponding to the output clock terminal or the first low-level power terminal to the plurality of signal output terminals;

[0044] The output sub-circuit is located in the fourth device region.

[0045] In an exemplary embodiment, the output sub-circuit further includes: a plurality of output capacitors, and the plurality of output capacitors are arranged in an array along the first direction and the second direction.

[0046] In an exemplary embodiment, the shift register further includes: a reset subcircuit and a noise reduction subcircuit, and the plurality of control clock terminals include: a first control clock terminal to a third control clock terminal;

[0047] The reset sub-circuit is electrically connected to at least the main reset signal terminal, the third node, the fourth node, the first high-level power terminal and the second low-level power terminal respectively, and is configured to provide a second low-level power terminal electrical connection to the third node, the fourth node and the first high-level power terminal under the control of the signal of the main reset signal terminal;

[0048] The noise reduction sub-circuit is electrically connected to at least the first node, the second node, the ninth node, the first control clock terminal, the second control clock terminal, and the second low-level power terminal, respectively, and is configured as a control line of the signal at the first control clock terminal, providing the signal of the second control clock terminal to the second node, and providing the signal of the second low-level power terminal to the first node under the control of the signal of the ninth node;

[0049] The reset sub-circuit and the noise reduction sub-circuit are located in the second device area, and the reset sub-circuit and the pre-processing sub-circuit are arranged along the second direction.

[0050] In an exemplary embodiment, the non-display area is further provided with a reset signal line;

[0051] The total reset signal terminal of the shift register is electrically connected to the reset signal line, and the reset signal line is located in the first signal line area.

[0052] In an exemplary embodiment, the gate driving circuit includes: a plurality of shift register groups, the shift register group including N1 shift register units, the shift register unit including N2 shift registers, N1, N2 ≥ 2;

[0053] The part of the selection signal lines connected to the multiple selection signal terminals of the shift register is called a selection signal line unit; the selection signal lines included in the selection signal line unit connected to any two shift registers located in the same shift register unit are the same, and at least one of the selection signal lines included in the selection signal line unit connected to any two shift register units located in the same shift register group is different; the selection signal lines included in the selection signal line unit connected to the n1th shift register unit located in different shift register groups are the same, 1≤n1≤N1.

[0054] In an exemplary embodiment, a portion of the control clock signal lines connected to the multiple control clock terminals of the shift register is referred to as a control clock signal line unit, and a portion of the output clock signal lines connected to the multiple output clock terminals of the shift register is referred to as an output clock signal line unit;

[0055] At least one of the control clock signal lines included in the control clock signal line unit connected to any two shift registers located in the same shift register unit is different, and at least one of the output clock signal lines included in the output clock signal line unit connected to any two shift registers located in the same shift register unit is different; the control clock signal lines included in the control clock signal line unit connected to the n2th shift register located in different shift register units are the same, and the output clock signal lines included in the output clock signal line unit connected to the n2th shift register located in different shift register units are the same, 1≤n2≤N2.

[0056] In an exemplary embodiment, the present invention comprises: a substrate and a driving structure layer disposed on the substrate, wherein the shift register comprises: a plurality of transistors;

[0057] The driving structure layer includes: a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a second conductive layer stacked on the substrate;

[0058] The semiconductor layer includes at least: an active pattern of a plurality of transistors in the shift register;

[0059] The second conductive layer at least includes: gate electrodes, a first electrode, and a second electrode of a plurality of transistors in the shift register.

[0060] In an exemplary embodiment, it also includes: a selection signal line, a control clock signal line, an output clock signal line, the first high-level power line, the second high-level power line, the first low-level power line, and the second low-level power line, wherein any signal line among the selection signal line, the control clock signal line, the output clock signal line, the first high-level power line, the second high-level power line, the first low-level power line and the second low-level power line is a single-layer structure located in the first conductive layer, or is a double-layer structure and is located in the first conductive layer and the second conductive layer.

[0061] In an exemplary embodiment, the non-display area is further provided with a first connection line and a second connection line, and the first connection line and the second connection line are located in the first conductive layer;

[0062] The first electrodes of all the gating transistors in the same gating sub-circuit are electrically connected to the first connection line, and the second electrodes of the plurality of gating transistors in the same gating sub-circuit are electrically connected to the second connection line;

[0063] Any one of the gate electrode, the first electrode, and the second electrode in any selection transistor at least partially extends along the second direction, and the first connection line and the second connection line extend along the first direction.

[0064] In an exemplary embodiment, the non-display area is further provided with a plurality of control clock connection lines and a plurality of control clock electrostatic release circuits; the plurality of control clock connection lines correspond one-to-one to the plurality of control clock signal lines, and the plurality of control clock connection lines correspond one-to-one to the plurality of control clock electrostatic release circuits;

[0065] The control clock connection lines are electrically connected to corresponding control clock signal lines and corresponding control clock electrostatic release circuits respectively.

[0066] In an exemplary embodiment, the control clock connection line includes: a first control clock connection portion extending along the second direction and a second control clock connection portion extending along the first direction;

[0067] For any control clock connection line, the first control clock connection portion is electrically connected to the corresponding control clock signal line and the second control clock connection portion, and the second control clock connection portion is electrically connected to the corresponding control clock electrostatic discharge circuit;

[0068] The first control clock connection portion is located in the second conductive layer, and the second control clock connection portion is located in the first conductive layer.

[0069] In an exemplary embodiment, the non-display area is further provided with a plurality of output clock connection lines and a plurality of output clock electrostatic discharge circuits; the plurality of output clock connection lines correspond one-to-one to the plurality of output clock signal lines, and the plurality of output clock connection lines correspond one-to-one to the plurality of output clock electrostatic discharge circuits;

[0070] The output clock connection lines are electrically connected to corresponding output clock signal lines and corresponding output clock electrostatic discharge circuits respectively.

[0071] In an exemplary embodiment, the output clock connection line includes: a first output clock connection portion extending along the second direction and a second output clock connection portion extending along the first direction;

[0072] For any output clock connection line, the first output clock connection portion is electrically connected to the corresponding output clock signal line and the second output clock connection portion, and the second output clock connection portion is electrically connected to the corresponding output clock electrostatic discharge circuit;

[0073] The first output clock connection portion is located in the second conductive layer, and the second output clock connection portion is located in the first conductive layer.

[0074] In an exemplary embodiment, the non-display area is further provided with four power connection lines and four power electrostatic discharge circuits.

[0075] The first power connection line is electrically connected to the first high-level power line and the first power electrostatic discharge circuit respectively;

[0076] The second power connection line is electrically connected to the second high-level power line and the second power electrostatic discharge circuit respectively;

[0077] The third power connection line is electrically connected to the first low-level power line and the third power electrostatic discharge circuit respectively;

[0078] The fourth power connection line is electrically connected to the second low-level power line and the fourth power electrostatic discharge circuit respectively.

[0079] In an exemplary embodiment, the power connection line includes: a first power connection portion extending along the second direction and a second power connection portion extending along the first direction;

[0080] For any power connection line, the first power connection part is electrically connected to the connected power line and the second power connection part, and the second power connection part is electrically connected to the connected power electrostatic discharge circuit;

[0081] The first power connection portion is located on the second conductive layer, and the second power connection portion is located on the first conductive layer.

[0082] In an exemplary embodiment, a distance between a first signal line away from a boundary of the display area and a second signal line close to a boundary of the display area is approximately 3400 μm to 3450 μm;

[0083] The first signal line is the signal line farthest from the border of the display area in the first signal line area, and the second signal line is the signal line closest to the border of the display area in the third signal line area.

[0084] In an exemplary embodiment, signals of at least two gate signal lines are inverted signals to each other during a partial period.

[0085] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0086] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0087] Summary of the Figures

[0088] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0089] FIG1 is a schematic structural diagram of a display device;

[0090] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0091] FIG3 is a second schematic diagram of a planar structure of a display substrate;

[0092] FIG4 is a third schematic diagram of a planar structure of a display substrate;

[0093] FIG5A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0094] FIG5B is a timing diagram of an operation of a pixel driving circuit;

[0095] FIG6 is an equivalent circuit diagram of a shift register;

[0096] FIG7 is a timing diagram of the operation of the shift register provided in FIG6 ;

[0097] FIG8 is a first structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0098] FIG9 is a second structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0099] FIG10 is a top view of the gating subcircuit;

[0100] FIG11 is a schematic diagram showing the connection of multiple shift registers;

[0101] FIG12 is a schematic diagram showing the connection of multiple shift register groups;

[0102] FIG13 is a schematic cross-sectional view showing a substrate;

[0103] FIG14 is a partial schematic diagram of a non-display area of ​​a display substrate;

[0104] FIG15 is a schematic diagram of the first conductive layer pattern in FIG10;

[0105] FIG16 is a schematic diagram of a semiconductor layer pattern in FIG10 ;

[0106] FIG17 is a schematic diagram of FIG10 after a semiconductor pattern is formed;

[0107] FIG18 is a schematic diagram of FIG10 after forming a second insulating layer pattern;

[0108] FIG19 is a schematic diagram of a second conductive layer pattern in FIG10 ;

[0109] FIG. 20 is a schematic diagram of FIG. 10 after forming a second conductive layer pattern.

[0110] Details

[0111] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0112] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0113] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0114] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0115] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0116] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0117] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0118] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0119] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0120] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0121] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0122] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0123] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0124] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a source driver circuit, a gate driver circuit, and a pixel array. The timing controller is respectively connected to the source driver circuit and the gate driver circuit, and the source driver circuit is respectively connected to a plurality of data signal lines (D1 to Dn). The gate driver circuit includes a scan driver circuit and a light-emitting driver circuit. The scan driver circuit is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver circuit is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driver circuit. The pixel driver circuit may be respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the source driver circuit to the source driver circuit, clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit to the scan driver circuit, and clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver circuit to the light-emitting driver circuit. The source driver circuit may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn. For example, the source driver circuit may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver circuit may generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver circuit may sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan drive circuit can be constructed in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal, and m can be a natural number. The light-emitting drive circuit can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting drive circuit can sequentially provide an emission signal with an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting drive circuit can be constructed in the form of a shift register and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal, and o can be a natural number.

[0125] Figure 2 is a schematic diagram of a planar structure of a display substrate (I), Figure 3 is a schematic diagram of a planar structure of a display substrate (II), and Figure 4 is a schematic diagram of a planar structure of a display substrate (III). As shown in Figures 2 to 4, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel in which they are located.

[0126] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0127] In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon, which is not limited in the present disclosure.

[0128] In an exemplary embodiment, the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0129] In other exemplary embodiments, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square, etc., which is not limited in the present disclosure.

[0130] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

[0131] Figure 5A is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 5A illustrates a pixel driving circuit having a 7T1C structure. As shown in Figure 5A, the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7) and one storage capacitor C. The pixel driving circuit may be connected to seven signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, emission signal line EM, initial signal line INIT, first power line VDD, and second power line VSS).

[0132] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor M3, the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor M2, the control electrode of the third transistor M3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor M2, the second electrode of the third transistor M3, and the first electrode of the sixth transistor M6.

[0133] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor M3 .

[0134] The control electrode of the first transistor M1 is connected to the second scan signal line Gate2, the first electrode of the first transistor M1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line Gate2, the first transistor M1 transmits an initialization voltage to the control electrode of the third transistor M3, thereby initializing the charge amount of the control electrode of the third transistor M3.

[0135] The control electrode of the second transistor M2 is connected to the first scan signal line Gate1, the first electrode of the second transistor M2 is connected to the second node N2, and the second electrode of the second transistor M2 is connected to the third node N3. When an on-level scan signal is applied to the first scan signal line Gate1, the second transistor M2 connects the control electrode of the third transistor M3 to the second electrode.

[0136] The control electrode of the third transistor M3 is connected to the second node N2, that is, the control electrode of the third transistor M3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor M3 is connected to the first node N1, and the second electrode of the third transistor M3 is connected to the third node N3. The third transistor M3 can be called a driving transistor. The third transistor M3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0137] A control electrode of the fourth transistor M4 is connected to the first scan signal line Gate1, a first electrode of the fourth transistor M4 is connected to the data signal line Data, and a second electrode of the fourth transistor M4 is connected to the first node N1. The fourth transistor M4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line Gate1, the fourth transistor M4 inputs the data voltage of the data signal line Data to the pixel driving circuit.

[0138] The control electrode of the fifth transistor M5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the first power line VDD, and the second electrode of the fifth transistor M5 is connected to the first node N1. The control electrode of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device. The fifth transistor M5 and the sixth transistor M6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line EM, the fifth transistor M5 and the sixth transistor M6 form a drive current path between the first power line VDD and the second power line VSS, thereby causing the light-emitting device to emit light.

[0139] A control electrode of the seventh transistor M7 is connected to the first scan signal line Gate1, a first electrode of the seventh transistor M7 is connected to the initialization signal line INIT, and a second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device. When an on-level scan signal is applied to the first scan signal line Gate1, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light-emitting device L, thereby initializing or releasing the charge accumulated in the first electrode of the light-emitting device L.

[0140] In an exemplary embodiment, the second electrode of the light emitting device L is connected to the second power line VSS, the second power line VSS continuously provides a low level signal, and the first power line VDD continuously provides a high level signal.

[0141] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0142] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor M1 to the seventh transistor M7 may include P-type transistors and N-type transistors.

[0143] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0144] In an exemplary embodiment, the first and second scan signal lines Gate1 and Gate2 , the emission signal line EM, and the initial signal line INIT may extend horizontally, and the second and first power lines VSS and VDD, and the data signal line Data may extend vertically.

[0145] In an exemplary embodiment, the light emitting device L may include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0146] Figure 5B is an operating timing diagram of a pixel driving circuit. The following illustrates exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in Figure 5A. The pixel driving circuit in Figure 5A includes seven transistors (first transistor M1 to seventh transistor M7), and one storage capacitor C. All seven transistors are P-type transistors.

[0147] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0148] In the first phase A1, referred to as the reset phase, the signal on the second scan signal line Gate2 is low, while the signals on the first scan signal line Gate1 and the emission signal line EM are high. The low signal on the second scan signal line Gate2 turns on the first transistor M1, and the signal on the initialization signal line INIT is supplied to the second node N2, initializing (resetting) the storage capacitor C and clearing the existing charge in the storage capacitor. The high signals on the first scan signal line Gate1 and the emission signal line EM turn off the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7. During this phase, the light-emitting device L does not emit light.

[0149] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line Gate1 is a low-level signal, the signals on the second scan signal line Gate2 and the emission signal line EM are high-level signals, and the data signal line Data outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor M3 is turned on. The low-level signal on the first scan signal line Gate1 turns on the second transistor M2, the fourth transistor M4, and the seventh transistor M7. The second transistor M2 and the fourth transistor M4 are turned on, causing the data voltage output by the data signal line Data to be supplied to the second node N2 via the first node N1, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The seventh transistor M7 is turned on, so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting device L does not emit light. The signal of the second scanning signal line Gate2 is a high-level signal, turning off the first transistor M1. The signal of the emission signal line EM is a high-level signal, turning off the fifth transistor M5 and the sixth transistor M6.

[0150] In the third phase A3, referred to as the light-emitting phase, the signal on the light-emitting signal line EM is a low-level signal, and the signals on the first scanning signal line Gate1 and the second scanning signal line Gate2 are high-level signals. The low-level signal on the light-emitting signal line EM turns on the fifth transistor M5 and the sixth transistor M6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the light-emitting device L to emit light.

[0151] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0152] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0153] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0154] With the continuous development of display technology, the market has placed higher demands on low-cost, narrow-frame, and lightweight designs for display devices. In response, Gate Driver on Array (GOA) technology has become a research hotspot for major manufacturers due to its advantages in achieving narrow-frame and lightweight designs.

[0155] GOA technology integrates the gate drive circuit onto the array substrate on which the pixel array is mounted. This allows the gate drive circuit to directly provide gate drive signals to the pixel array, eliminating the need for an additional gate drive chip and corresponding binding structure, thereby reducing costs and bezel width. The gate drive circuit is electrically connected to the first scan signal line, the second scan signal line, the reset signal line, and the light-emitting signal line.

[0156] The gate drive circuit includes multiple shift registers. Figure 6 shows an equivalent circuit diagram of a shift register. As shown in Figure 6, the shift register includes a gating subcircuit 10, a node setting subcircuit 20, a preprocessing subcircuit 30, an input subcircuit 40, a node separation subcircuit 50, an output subcircuit 60, a noise reduction subcircuit 70, and a reset subcircuit 80. The gating sub-circuit 10 is electrically connected to the first gating signal terminal D0 to the eighth gating signal terminal D7, the second control clock terminal CKB and the second node N2, respectively, and is configured to provide the signal of the second control clock terminal CKB to the second node N2 under the control of the signal of the first gating signal terminal D0 to the eighth gating signal terminal D7; the node setting sub-circuit 20 is electrically connected to at least the second high-level power supply terminal GVDD2, the second low-level power supply terminal LVGL, the second control clock terminal CKB, the third control clock terminal CKC, the first node N1 and the third node N3, respectively, and is configured to provide the second high-level power supply terminal GVDD2 to the first node N1 under the control of the signal of the second control clock terminal CKB, the third control clock terminal CKC and the third node N3. VDD2 or the signal of the second low-level power supply terminal LVGL; the input sub-circuit is electrically connected to at least the third control clock terminal CKC, the third node N3 and the fifth node N5, respectively, and is configured to provide the signal of the third control clock terminal CKC to the fifth node N3 under the control of the signal of the third node N3 and the third control clock terminal CKC; the pre-processing sub-circuit is electrically connected to at least the second node N2, the third node N3, the fourth node N4, the first high-level power supply terminal GVDD1 and the first control clock terminal CKA, respectively, and is configured to provide the signal of the first control clock terminal CKA or the first high-level power supply terminal GVDD1 to the third node N3 and the fourth node N4 under the control of the signal of the second node N2 and the first control clock terminal CKA.The node separation sub-circuit is electrically connected to the third control clock terminal CKC, the first high-level power supply terminal GVDD1, the second low-level power supply terminal LVGL, the first node N1, the fifth node N5, the sixth node N6, the seventh node N7, the eighth node N8 and the ninth node N9, respectively, and is configured to provide the signal of the fifth node N5 to the sixth node N6 to the ninth node N9 respectively under the control of the signal of the third control clock terminal CKC and the first node N1, or provide the signal of the first high-level power supply terminal GVDD2 to the fifth node N5 under the control of the signal of the sixth node N6. The output sub-circuit is at least electrically connected to the first output clock terminal CKE1 to the fourth output clock terminal CKE1. The output clock terminal CKE4, the first low-level power supply terminal VGL and the first signal output terminal OUT1 to the fourth signal output terminal OUT4 are electrically connected, and are configured to output the signal of the first output clock terminal CKE1 or the first low-level power supply terminal VGL to the first signal output terminal OUT1, output the signal of the second output clock terminal CKE2 or the first low-level power supply terminal VGL to the second signal output terminal OUT2, output the signal of the third output clock terminal CKE3 or the first low-level power supply terminal VGL to the third signal output terminal OUT3, and output the signal of the fourth output clock terminal CKE4 or the first low-level power supply terminal VGL to the fourth signal output terminal OUT4.

[0157] In an exemplary embodiment, as shown in FIG6 , the gating subcircuit 10 includes at least a second transistor T2 to a ninth transistor T9. A gate electrode of the second transistor T2 is electrically connected to the first gating signal terminal D0, a first electrode of the second transistor T2 is electrically connected to the second control clock terminal CKB, and a second electrode of the second transistor T2 is electrically connected to the second node N2. A gate electrode of the third transistor T3 is electrically connected to the second gating signal terminal D1, a first electrode of the third transistor T3 is electrically connected to the second control clock terminal CKB, and a second electrode of the third transistor T3 is electrically connected to the second node N2. A gate electrode of the fourth transistor T4 is electrically connected to the third gating signal terminal D2, a first electrode of the fourth transistor T4 is electrically connected to the second control clock terminal CKB, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. A gate electrode of the fifth transistor T5 is electrically connected to the fourth gating signal terminal D3, a first electrode of the fifth transistor T5 is electrically connected to the second control clock terminal CKB, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2. In addition, a gate electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, a first electrode of the sixth transistor T6 is electrically connected to the second control clock terminal CKB, and a second electrode of the sixth transistor T6 is electrically connected to the second node N2. A gate electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, a first electrode of the seventh transistor T7 is electrically connected to the second control clock terminal CKB, and a second electrode of the seventh transistor T7 is electrically connected to the second node N2. A gate electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, a first electrode of the eighth transistor T8 is electrically connected to the second control clock terminal CKB, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2. A gate electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, a first electrode of the ninth transistor T9 is electrically connected to the second control clock terminal CKB, and a second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0158] In an exemplary embodiment, as shown in FIG6 , the node setting subcircuit 20 includes at least a first transistor T1, a fifteenth transistor T15, and a sixteenth transistor T16. The gate electrode of the first transistor T1 is electrically connected to the second control clock terminal CKB, the first electrode of the first transistor T1 is electrically connected to the second high-level power supply terminal GVDD2, the second electrode of the first transistor T1 is electrically connected to the first node N1, the gate electrode of the fifteenth transistor T15 is electrically connected to the third node N3, the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, the second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16, the gate electrode of the sixteenth transistor T16 is electrically connected to the third control clock terminal, and the second electrode of the sixteenth transistor T16 is electrically connected to the second low-level power supply terminal LVGL.

[0159] In an exemplary embodiment, as shown in FIG6 , the pre-processing sub-circuit 30 includes at least an eleventh transistor T11 , a twelfth transistor T12 , a thirteenth transistor T13 , a tenth transistor T14 and a second capacitor C2 . Among them, a gate electrode of the eleventh transistor T11 is electrically connected to the second node N2, a first electrode of the eleventh transistor T11 is electrically connected to the first control clock terminal CKA, and a second electrode of the eleventh transistor T11 is electrically connected to the fourth node N4. A gate electrode of the twelfth transistor T12 is electrically connected to the second node N2, a first electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, and a second electrode of the twelfth transistor T12 is electrically connected to the third node N3. A gate electrode of the thirteenth transistor T13 is electrically connected to the first control clock terminal CKA, a first electrode of the thirteenth transistor T13 is electrically connected to the third node N3, and a second electrode of the thirteenth transistor T13 is electrically connected to the first high-level power supply terminal GVDD1. A gate electrode of the fourteenth transistor T14 is electrically connected to the third node N3, a first electrode of the fourteenth transistor T14 is electrically connected to the fourth node N4, and a second electrode of the fourteenth transistor T14 is electrically connected to the first high-level power supply terminal GVDD1. A first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the first high-level power supply terminal GVDD1.

[0160] In an exemplary embodiment, as shown in FIG6 , the input sub-circuit 40 includes at least a twenty-first transistor T21 and a twenty-second transistor T22. A gate electrode of the twenty-first transistor T21 is electrically connected to the third node N3, a first electrode of the twenty-first transistor T21 is electrically connected to the third control clock terminal CKC, a second electrode of the twenty-first transistor T21 is electrically connected to the first electrode of the twenty-second transistor T22, a gate electrode of the twenty-second transistor T22 is electrically connected to the third control clock terminal CKC, and a second electrode of the twenty-second transistor T22 is electrically connected to the fifth node N5.

[0161] In an exemplary embodiment, as shown in FIG6 , the node separation sub-circuit 50 includes at least: a twenty-third transistor T23 to a thirty-fifth transistor T35. The control electrode of the twenty-third transistor T23 is electrically connected to the third control clock terminal CKC, the first electrode of the twenty-third transistor T23 is electrically connected to the fifth node N5, the second electrode of the twenty-third transistor T23 is electrically connected to the sixth node N6, the control electrode of the twenty-fourth transistor T24 is electrically connected to the third control clock terminal CKC, the first electrode of the twenty-fourth transistor T24 is electrically connected to the fifth node N5, the second electrode of the twenty-fourth transistor T24 is electrically connected to the seventh node N7, the control electrode of the twenty-fifth transistor T25 is electrically connected to the third control clock terminal CKC, the first electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8. 8, a control electrode of the twenty-sixth transistor T26 is electrically connected to the third control clock terminal CKC, a first electrode of the twenty-sixth transistor T26 is electrically connected to the fifth node N5, a second electrode of the twenty-sixth transistor T26 is electrically connected to the ninth node N9, a control electrode of the twenty-seventh transistor T27 is electrically connected to the first node N1, a first electrode of the twenty-seventh transistor T27 is electrically connected to the sixth node N6, a second electrode of the twenty-seventh transistor T27 is electrically connected to the fifth node N5, a control electrode of the twenty-eighth transistor T28 is electrically connected to the first node N1, a first electrode of the twenty-eighth transistor T28 is electrically connected to the fifth node N5, and a second electrode of the twenty-eighth transistor T28 is electrically connected to the second low-level power supply terminal LVG L is electrically connected, a control electrode of the twenty-ninth transistor T29 is electrically connected to the first node N1, a first electrode of the twenty-ninth transistor T29 is electrically connected to the seventh node N7, a second electrode of the twenty-ninth transistor T29 is electrically connected to the fifth node N5, a control electrode of the thirtieth transistor T30 is electrically connected to the first node N1, a first electrode of the thirtieth transistor T30 is electrically connected to the fifth node N5, a second electrode of the thirtieth transistor T30 is electrically connected to the second low-level power supply terminal LVGL, a control electrode of the thirty-first transistor T31 is electrically connected to the first node N1, a first electrode of the thirty-first transistor T31 is electrically connected to the sixth node N6, a second electrode of the thirty-first transistor T31 is electrically connected to the eighth node N8, and a control electrode of the thirty-first transistor T31 is electrically connected to the first node N1. The control electrode of the twelfth transistor T32 is electrically connected to the first node N1, the first electrode of the thirty-second transistor T32 is electrically connected to the fifth node N5, and the second electrode of the thirty-second transistor T32 is electrically connected to the second low-level power supply terminal LVGL. The control electrode of the thirty-third transistor T33 is electrically connected to the first node N1, the first electrode of the thirty-third transistor T33 is electrically connected to the ninth node N9, and the second electrode of the thirty-third transistor T33 is electrically connected to the fifth node N5. The control electrode of the thirty-fourth transistor T34 is electrically connected to the first node N1, the first electrode of the thirty-fourth transistor T34 is electrically connected to the fifth node N5, and the second electrode of the thirty-fourth transistor T34 is electrically connected to the second low-level power supply terminal LVGL.A gate electrode of the thirty-fifth transistor T35 is electrically connected to the sixth node N6, a first electrode of the thirty-fifth transistor T35 is electrically connected to the first high-level power supply terminal GVDD1, and a second electrode of the thirty-fifth transistor T35 is electrically connected to the fifth node N5.

[0162] In an exemplary embodiment, as shown in FIG6 , the output sub-circuit 60 includes at least a 36th transistor T36, a 37th transistor T37, a 38th transistor T38, a 39th transistor T39, a 40th transistor T40, a 41st transistor T41, a 42nd transistor T42, a 43rd transistor T43, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. A gate electrode of the 36th transistor T36 is electrically connected to the ninth node N9, a first electrode of the 36th transistor T36 is electrically connected to the first output clock terminal CKE1, a second electrode of the 36th transistor T36 is electrically connected to the first output terminal OUT1, a gate electrode of the 37th transistor T37 is electrically connected to the first node N1, a first electrode of the 37th transistor T37 is electrically connected to the first output terminal OUT1, a second electrode of the 37th transistor T37 is electrically connected to the first low-level power supply terminal VGL, a gate electrode of the 38th transistor T38 is electrically connected to the eighth node N8, and a first electrode of the 38th transistor T38 is electrically connected to the second The output clock terminal CKE2 is electrically connected, the second electrode of the thirty-eighth transistor T38 is electrically connected to the second output terminal OUT2, the gate electrode of the thirty-ninth transistor T39 is electrically connected to the first node N1, the first electrode of the thirty-ninth transistor T39 is electrically connected to the second output terminal OUT2, the second electrode of the thirty-ninth transistor T39 is electrically connected to the first low-level power supply terminal VGL, the gate electrode of the fortieth transistor T40 is electrically connected to the seventh node N7, the first electrode of the fortieth transistor T40 is electrically connected to the third output clock terminal CKE3, the second electrode of the fortieth transistor T40 is electrically connected to the third output terminal OUT3, and the fortieth transistor T41 is electrically connected to the first node N1. A gate electrode of the forty-first transistor T41 is electrically connected to the first node N1, a first electrode of the forty-first transistor T41 is electrically connected to the third output terminal OUT3, a second electrode of the forty-first transistor T41 is electrically connected to the first low-level power supply terminal VGL, a gate electrode of the forty-second transistor T42 is electrically connected to the sixth node N6, a first electrode of the forty-second transistor T42 is electrically connected to the fourth output clock terminal CKE4, a second electrode of the forty-second transistor T42 is electrically connected to the fourth output terminal OUT4, a gate electrode of the forty-third transistor T43 is electrically connected to the first node N1, and a first electrode of the forty-third transistor T43 is electrically connected to the fourth output terminal OUT4 A second electrode of the forty-third transistor T43 is electrically connected to the first low-level power supply terminal VGL, a first end of the third capacitor C3 is electrically connected to the ninth node N9, a second end of the third capacitor C3 is electrically connected to the first output terminal OUT1, a first end of the fourth capacitor C4 is electrically connected to the eighth node N8, a second end of the fourth capacitor C4 is electrically connected to the second output terminal OUT2, a first end of the fifth capacitor C5 is electrically connected to the seventh node N7, a second end of the fifth capacitor C5 is electrically connected to the third output terminal OUT3, a first end of the sixth capacitor C6 is electrically connected to the sixth node N6, and a second end of the sixth capacitor C6 is electrically connected to the fourth output terminal OUT4.

[0163] In an exemplary embodiment, as shown in FIG6 , the noise reduction sub-circuit 70 includes at least a tenth transistor T10, a seventeenth transistor T17, and a first capacitor C1. The gate electrode of the tenth transistor T10 is electrically connected to the first control clock terminal CKA, the first electrode of the tenth transistor T10 is electrically connected to the second control clock terminal CKB, the second electrode of the tenth transistor T10 is electrically connected to the second node N2, the gate electrode of the seventeenth transistor T17 is electrically connected to the ninth node N9, the first electrode of the seventeenth transistor T17 is electrically connected to the first node N1, the second electrode of the seventeenth transistor T17 is electrically connected to the second low-level power supply terminal LVGL, the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the second low-level power supply terminal LVGL.

[0164] In an exemplary embodiment, as shown in FIG6 , the reset sub-circuit 80 includes at least an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20. A gate electrode of the eighteenth transistor T18 is electrically connected to the general reset signal terminal TRS, a first electrode of the eighteenth transistor T18 is electrically connected to the third node N3, a second electrode of the eighteenth transistor T18 is electrically connected to the fourth node N4, a gate electrode of the nineteenth transistor T19 is electrically connected to the general reset signal terminal TRS, a first electrode of the nineteenth transistor T19 is electrically connected to the first high-level power supply terminal GVDD1, a second electrode of the nineteenth transistor T19 is electrically connected to the first node N1, a gate electrode of the twentieth transistor T20 is electrically connected to the general reset signal terminal TRS, a first electrode of the twentieth transistor T20 is electrically connected to the fourth node N4, and a second electrode of the twentieth transistor T20 is electrically connected to the second low-level power supply terminal LVGL.

[0165] In an exemplary embodiment, all transistors in the shift register, namely the first transistor T1 to the forty-third transistor T43, may be N-type transistors. Using the same type of transistors in the shift register can simplify the process, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0166] In an exemplary embodiment, the gate driving circuit including the shift register provided in FIG. 6 may be located in a large-size display product, and the pixel driving circuit in the large-size display product may be 3T1C, which is not limited in the present disclosure.

[0167] In an exemplary embodiment, the signals of the first high-level power supply terminal GVDD1 and the second high-level power supply terminal GVDD2 are direct current signals and are high-level signals.

[0168] In an exemplary embodiment, the signals of the first low-level power supply terminal VGL and the second low-level power supply terminal LVGL are DC signals and low-level signals, and the absolute value of the voltage value of the signal of the second low-level power supply terminal LVGL is greater than the absolute value of the voltage value of the signal of the first low-level power supply terminal VGL.

[0169] In an exemplary embodiment, the signals at any of the first control clock terminal CKA through the third control clock terminal CKC and the first output clock terminal CK1 through the fourth output clock terminal CK4 are square wave signals that repeat high and low voltages. For example, the signals at any two of the first control clock terminal CKA through the third control clock terminal CKC can have the same period and can be configured as phase-shifted signals. The signals at any two of the first output clock terminal CK1 through the fourth output clock terminal CK4 can have the same period and can be configured as phase-shifted signals.

[0170] In an exemplary embodiment, a high voltage period of the signal of the first control clock terminal CKA may overlap with a portion of a low voltage period of the second control clock terminal CKB and a portion of a low level period of the third control clock terminal CKC. A high voltage period of the signal of the second control clock terminal CKB may overlap with a portion of a low voltage period of the first control clock terminal CKA and a portion of a low level period of the third control clock terminal CKC. A high voltage period of the signal of the third control clock terminal CKC may overlap with a portion of a low voltage period of the first control clock terminal CKA and a portion of a low level period of the second control clock terminal CKB.

[0171] In an exemplary embodiment, the high voltage period of the signal of the first output clock terminal CKE1 may partially overlap with the high voltage period of the second output clock terminal CKE2, the high voltage period of the signal of the second output clock terminal CKE2 may partially overlap with the high voltage period of the third output clock terminal CKE3, the high voltage period of the signal of the third output clock terminal CKE3 may partially overlap with the high voltage period of the fourth output clock terminal CKE4, and the high voltage period of the signal of the first output clock terminal CKE1 does not overlap with the high voltage period of the fourth output clock terminal CKE4.

[0172] In an exemplary embodiment, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a capacitor device made by a process. For example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the sixth capacitor C6 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0173] In an exemplary embodiment, the shift register may include multiple selection signal terminals. Figure 6 is illustrated using 8 as an example. In an exemplary embodiment, any selection signal terminal in the shift register can be connected to two selection signals, and the two selection signals are inverted signals. The two selection signals connected to different selection signal terminals are different. Only when the signals of all selection signal terminals are invalid level signals, the shift register has no output. The setting of multiple selection signal terminals can realize that at least part of the shift registers in the gate drive circuit can work independently, and there is no cascade relationship between adjacent shift registers. Among them, when the selection sub-circuit includes 8 transistors, the independent operation of 2^8=256 shift registers can be realized.

[0174] In an exemplary embodiment, the shift register may include multiple output terminals, each connected to a row of sub-pixels. The shift register shown in FIG6 includes four output terminals, i.e., connected to four rows of sub-pixels. In other words, when the gating sub-circuit includes eight transistors, 2^10=1024 rows of sub-pixels can operate independently. To increase the number of rows of independently operating sub-pixels, the number of transistors included in the gating sub-circuit or the number of output terminals can be increased. For example, the gating sub-circuit may include ten transistors, but this disclosure does not limit this.

[0175] The shift register provided by the present disclosure can ensure that multiple shift registers do not need to be cascaded, thereby allowing the shift registers to operate independently, allowing the gate drive circuit using the shift register provided in Figure 6 to randomly select a sub-pixel row. Therefore, on the one hand, using the gate drive circuit using the shift register provided in Figure 6 can partially refresh the display screen without performing row-by-row scanning, thereby greatly improving the refresh rate; for example, when only a portion of the display screen needs to be refreshed, only that portion of the display screen can be refreshed, thereby greatly improving the refresh rate.

[0176] FIG7 is an operating timing diagram of the shift register provided in FIG6. As shown in FIG7, the operating process of the shift register illustrated in FIG6 is used below to illustrate exemplary embodiments of the present disclosure. The shift register in FIG6 includes 43 transistors (first transistor T1 to forty-third transistor T43) and six capacitors C (first capacitor C1 to sixth capacitor C6). All 43 transistors are P-type transistors.

[0177] In an exemplary embodiment, the shift register's operating process may include a display phase and a non-display phase. The signal at the master reset signal terminal TRS is a high-level signal during a portion of the non-display phase and a low-level signal during the display phase. The signals at the first control clock terminal CKA to the third control clock terminal CKC and the first output clock terminal CKE1 to the fourth output clock terminal CKE4 are low-level signals, and the signals at the first selection signal terminal D0 to the eighth selection signal terminal D7 are high-level signals. According to the gating principle, the shift register will not be selected when all selection signal terminals are high-level signals.

[0178] In the non-display phase, the signal at the master reset signal terminal TRS is a high-level signal, and the signals at the first selection signal terminal D0 to the eighth selection signal terminal D7 are high-level signals. The signal at the master reset signal terminal TRS is a high-level signal, the eighteenth transistor T18 and the twentieth transistor T20 are turned on, the signals at the third node N3 and the fourth node N4 are pulled low by the second low-level power supply terminal LVGL, becoming low-level signals, the nineteenth transistor T19 is turned on, the first node N1 is pulled high by the high-level signal of the first high-level power supply GVDD1, the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are turned on, the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are turned on, the signals at the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are pulled low by the second low-level power supply terminal LVGL, becoming low-level signals, and the signals at the first output terminal OUT1 to the fourth output terminal OUT4 are pulled low by the first low-level power supply terminal VGL. The signals from the first selection signal D0 to the eighth selection signal terminal D7 are high level signals, the second transistor T2 to the ninth transistor T9 are turned on, and the signal at the second node N2 is pulled low by the second control clock terminal CKB.

[0179] In an exemplary embodiment, the operation process of the shift register in the display phase may include:

[0180] In the first phase P1, the signals from the first control clock terminal CKA and the first selection signal terminal D0 to the eighth selection signal terminal D7 are high-level signals, while the signals from the second control clock terminal CKB and the third control clock terminal CKC are low-level signals. Under the action of the first capacitor C1, the first node N1 maintains a high-level signal, the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are turned on, the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are continuously turned on, the signals from the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are continuously pulled low by the second low-level power supply terminal LVGL, and the signals from the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled low by the first low-level power supply terminal VGL. The signals from the first selection signal terminal D0 to the eighth selection signal terminal D7 are high-level signals, the second transistors T2 to the ninth transistor T9 are turned on, the signal from the second node N2 is pulled low by the second control clock terminal CKB, and the signal from the second node N2 is a low-level signal. The signal of the first control clock terminal CKA is a high-level signal, the thirteenth transistor T13 is turned on, the third node N3 is pulled high by the signal of the first high-level power supply terminal GVDD1, the signal of the third node N3 is a high-level signal, the twenty-first transistor T21 is turned on, the signal of the third control clock terminal CKC is a low-level signal, the twenty-second transistor T22 to the twenty-sixth transistor T26 are turned off, the fourteenth transistor T14 is turned on, the signal of the fourth node N4 is pulled high by the signal of the first high-level power supply terminal GVDD1, the signal of the fourth node N4 is a high-level signal. In this stage, the signal of the first node N1 is a high-level signal, the signal of the second node N2 is a low-level signal, the signal of the third node N3 is a high-level signal, the signal of the fourth node N4 is a high-level signal, and the first output terminal OUT1 to the fourth output terminal OUT4 have no output.

[0181] In the second phase P2, the signal at the second control clock terminal CKB is a high-level signal, and the signals from the first selection signal D0 to the eighth selection signal terminal D7, the second control clock terminal CKB, and the third control clock terminal CKC are low-level signals. The signal at the second control clock terminal CKB is a high-level signal, the first transistor T1 is turned on, and the signal at the first node N1 is pulled high by the high level of the second high-level power supply terminal GVDD2. The twenty-seventh transistor T27 to the thirty-fourth transistor T34 are turned on, and the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are continuously turned on. The signals at the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are continuously pulled low by the second low-level power supply terminal LVGL, becoming low-level signals. The signals at the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled low by the first low-level power supply terminal VGL. Since the signals from the first selection signal D0 to the eighth selection signal terminal D7 are low-level signals, the second transistor T2 to the ninth transistor T9 are disconnected, the high-level signal from the second control clock terminal CKB cannot be written into the second node N2, and the third node N3 and the fourth node N4 maintain the high-level signals of the previous stage. In this stage, the signal from the first node N1 is a high-level signal, the signal from the second node N2 is a low-level signal, the signal from the third node N3 is a high-level signal, and the signal from the fourth node N4 is a high-level signal, and there is no output from the first output terminal OUT1 to the fourth output terminal OUT4.

[0182] In the third phase P3 , the signal of the third control clock terminal CKC is a high level signal, and the signals of the first control clock terminal CKA, the second control clock terminal CKB, and the first selection signal terminal D0 to the eighth selection signal terminal D7 are low level signals. The second node N2 maintains a low-level signal in the previous stage, the third node N3 and the fourth node N4 maintain a high-level signal in the previous stage, the signal at the third control clock terminal CKC is a high-level signal, the fifteenth transistor T15 and the sixteenth transistor T16 are turned on, the signal at the first node N1 is pulled low by the second low-level power supply GVDD2, the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are turned on, the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are turned off, the twenty-first transistor T21 to the twenty-sixth transistor T26 are turned on, the fifth node N5 is pulled high by the high-level signal at the third control clock terminal CKC, the sixth node N6 to the ninth node N9 are pulled high by the signal at the fifth node N5, the thirty-sixth transistor T36, the thirty-eighth transistor T38, the fortieth transistor T40, and the forty-second transistor T42 are turned on, and since the signals at the first output clock terminal CKE1 to the fourth output clock terminal CKE4 are low-level signals, the signals at the first output terminal OUT1 to the fourth output terminal OUT4 are low-level signals.

[0183] In the fourth phase P4, the signals from the first output clock terminal CKE1 to the fourth output clock terminal CKE4 are high-level signals in part of the time period, and the signals from the first control clock terminal CKA to the third control clock terminal CKC and the first selection signal terminal D0 to the eighth selection signal terminal D7 are low-level signals. Under the bootstrap effect of the third capacitor C3, the ninth node N9 is raised, the thirty-sixth transistor T36 is turned on, and the high-level signal of the first output clock terminal CKE1 is written to the first output terminal OUT1. Under the bootstrap effect of the fourth capacitor C4, the eighth node N8 is raised, the thirty-eighth transistor T38 is turned on, and the high-level signal of the second output clock terminal CKE2 is written to the second output terminal OUT2. Under the bootstrap effect of C5, the seventh node N7 is raised, the 40th transistor T40 is turned on, and the high-level signal of the third output clock terminal CKE3 is written to the third output terminal OUT3. Under the bootstrap effect of the fourth capacitor C4, the sixth node N6 is raised, the 42nd transistor T42 is turned on, and the high-level signal of the fourth output clock terminal CKE4 is written to the fourth output terminal OUT4. The 35th transistor T35 is continuously turned on, and the signal of the fifth node N5 is continuously pulled high. In this stage, the signals of the first node N1 and the second node N2 are low-level signals, the signals of the third node N3 to the ninth node N9 are high-level signals, and the signals of the first output terminal OUT1 to the fourth output terminal OUT4 are high-level signals.

[0184] In the fifth phase P5, the signals at the second control clock terminal CKB and the first selection signal terminal D0 are high-level signals, while the signals at the first control clock terminal CKA, the third control clock terminal CKB, and the second selection signal terminals D1 to D7 are low-level signals. The signal at the second control clock terminal CKB is high-level, the first transistor T1 is turned on, and the signal at the first node N1 is pulled high by the high level of the second high-level power supply terminal GVDD2. The twenty-seventh transistor T27 to the thirty-fourth transistor T34 are turned on, and the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are continuously turned on. The signals at the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are continuously pulled low by the second low-level power supply terminal LVGL, becoming low-level signals. The signals at the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled low by the first low-level power supply terminal VGL. Since the signal of the first selection signal D0 is a high-level signal, the second transistor T2 is turned on, the high-level signal of the second control clock terminal CKB is written to the second node N2, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the low-level signal of the first control clock terminal CKA is written to the third node N3 and the fourth node N4. In this stage, the signals of the first node N1 and the second node N2 are high-level signals, the signals of the third node N3 and the fourth node N4 are low-level signals, and there is no output from the first output terminal OUT1 to the fourth output terminal OUT4.

[0185] The above description is based on an example in which the signals at the first selection signal terminal D0 to the eighth selection signal terminal D7 of the shift register are all low-level signals in the second stage.

[0186] For a shift register in which, in the second stage, the signal at one of the first selection signal terminal D0 to the eighth selection signal terminal D7 is a high-level signal, in the second stage, the signal at the second control clock terminal CKB is a high-level signal, the first transistor T1 is turned on, the signal at the first node N1 is pulled high by the high level of the second high-level power supply terminal GVDD2, the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are turned on, the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41 and the forty-third transistor T43 are continuously turned on, the signals at the sixth node N6, the seventh node N7, the eighth node N8 and the ninth node N9 are continuously pulled low by the second low-level power supply terminal LVGL and are low-level signals, and the signals at the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled low by the first low-level power supply terminal VGL. Since the signal of one of the first selection signal terminal D0 to the eighth selection signal terminal D7 is a high-level signal, one of the second transistor T2 to the ninth transistor T9 is turned on, the high-level signal of the second control clock terminal CKB is written to the second node N2, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the low-level signal of the first control clock terminal CKA is written to the third node N3 and the fourth node N4. In this stage, the signals of the first node N1 and the second node N2 are high-level signals, and the signals of the third node N3 and the fourth node N4 are low-level signals. There is no output from the first output terminal OUT1 to the fourth output terminal OUT4. The third stage is not executed until the signals of all the selection signal terminals are low-level signals, and the output starts.

[0187] In summary, when the signals at all the selection signal terminals in the shift register are low-level signals, the shift register starts to output, and when at least one of the signals at all the selection signal terminals in the shift register is a high-level signal, the shift register does not output.

[0188] The display device includes the gate driving circuit shown in FIG6 . Since the shift register in the gate driving circuit includes a large number of transistors, the display device cannot achieve a narrow frame.

[0189] FIG8 is a first schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, FIG9 is a second schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, and FIG10 is a top view of the gating subcircuit. As shown in FIG8 to FIG10, the display substrate provided in an embodiment of the present disclosure has a display area 100 and a non-display area 200 surrounded by at least one side of the display area 100. The display area 100 is provided with an array-arranged pixel driving circuit PE, and the non-display area 200 is provided with a gate driving circuit and a gating signal line group DL. The gating signal line group DL includes: a plurality of gating signal lines, and the gate driving circuit is electrically connected to the pixel driving circuit and the gating signal line group DL, respectively. The gating signal lines extend along a first direction D1, and the plurality of gating signal lines are arranged along a second direction D2, wherein the first direction D1 and the second direction D2 intersect.

[0190] For example, the first direction D1 may be a column direction, and the second direction D2 may be a row direction. The intersection of the first direction and the second direction means that the angle between the first direction and the second direction is approximately 70 degrees to 90 degrees. The first direction and the second direction may be located in the same plane.

[0191] Figures 8 and 9 are explained by taking sixteen selection signal lines, namely the first selection signal line DL0, the second selection signal line DLN0, the third selection signal line DL1, the fourth selection signal line DLN1, the fifth selection signal line DL2, the sixth selection signal line DLN2, the seventh selection signal line DL3, the eighth selection signal line DLN3, the ninth selection signal line DL4, the tenth selection signal line DLN4, the eleventh selection signal line DL5, the twelfth selection signal line DLN5, the thirteenth selection signal line DL6, the fourteenth selection signal line DLN6, the fifteenth selection signal line DL7 and the sixteenth selection signal line DLN7 as examples.

[0192] As shown in Figures 8 to 10, the gate drive circuit includes: multiple shift registers, each of which includes a gating subcircuit 10 electrically connected to a portion of the gating signal lines in the gating signal line group DL. The gating subcircuit may include: multiple gating transistors. For any shift register, the multiple gating transistors in the gating subcircuit are arranged along the first direction D1. Exemplarily, the multiple gating transistors are the second transistor T2 to the ninth transistor T9 in Figure 6, i.e., the second transistor T2 to the ninth transistor T9 are arranged along the first direction D1. Figures 8 and 9 only illustrate one shift register.

[0193] In an exemplary embodiment, the gate driving circuit may be located on at least one side of the display area 200 , which is not limited in the present disclosure.

[0194] A display substrate provided by an embodiment of the present disclosure includes a display area and a non-display area surrounding at least one side of the display area. The display area is provided with an array-arranged pixel driving circuit, and the non-display area is provided with a gate driving circuit and a selection signal line group. The selection signal line group includes: a plurality of selection signal lines. The gate driving circuit is electrically connected to the pixel driving circuit and the selection signal line group, respectively. The selection signal lines extend along a first direction, and the plurality of selection signal lines are arranged along a second direction. The signals of at least two selection signal lines are mutually inverted signals. The gate driving circuit includes: a plurality of shift registers. The shift registers include: a selection subcircuit. The selection subcircuit is electrically connected to some of the selection signal lines in the selection signal line group. The selection subcircuit includes: a plurality of selection transistors. For any shift register, the plurality of selection transistors in the selection subcircuit are arranged along the first direction. By arranging the plurality of selection transistors in the selection subcircuit in any shift register along the first direction, the present disclosure can reduce the length of the gate driving circuit along the second direction, thereby achieving a narrow frame of the display substrate.

[0195] In an exemplary embodiment, signals of at least two gate signal lines are inverted signals to each other during a partial period.

[0196] In an exemplary embodiment, FIG11 is a connection diagram of multiple shift registers. The shift register GOA includes: M selection signal terminals, and the selection signal line group includes: 2M selection signal lines. The mth selection signal terminal is electrically connected to the 2m-1th selection signal line or the 2mth selection signal line, and the signal of the 2m-1th selection signal line and the signal of the 2mth selection signal line are mutually inverted signals, 1≤m≤M. Taking M=8 as an example, in combination with FIG6, FIG8 and FIG9, the first selection signal terminal D0 is electrically connected to the first selection signal line DL0 or the second selection signal line DLN0, the second selection signal terminal D1 is electrically connected to the third selection signal line DL1 or the fourth selection signal line DLN1, the third selection signal terminal D2 is electrically connected to the fifth selection signal line DL2 or the sixth selection signal line DLN2, and the fourth selection signal terminal D3 is electrically connected to the seventh selection signal line DL3 or the eighth selection signal line DLN1. LN3 is electrically connected, the fifth selection signal terminal D4 is electrically connected to the ninth selection signal line DL4 or the tenth selection signal line DLN4, the sixth selection signal terminal D5 is electrically connected to the eleventh selection signal line DL5 or the twelfth selection signal line DLN5, the seventh selection signal terminal D6 is electrically connected to the thirteenth selection signal line DL6 or the fourteenth selection signal line DLN6, and the eighth selection signal terminal D7 is electrically connected to the fifteenth selection signal line DL7 or the sixteenth selection signal line DLN7.

[0197] In an exemplary embodiment, the frequencies of the signals of the first to eighth selection signal terminals D0 to D7 may sequentially decrease, that is, the pulses of the signals of the first to eighth selection signal terminals D0 to D7 may sequentially increase. Illustratively, the signal frequency of the selection signal at the first selection signal terminal D0 is the highest, the signal frequency of the selection signal at the second selection signal terminal D1 is half of the signal frequency of the selection signal at the first selection signal terminal D0, the signal frequency of the selection signal at the third selection signal terminal D2 is half of the signal frequency of the selection signal at the second selection signal terminal D1, the signal frequency of the selection signal at the fourth selection signal terminal D3 is half of the signal frequency of the selection signal at the third selection signal terminal D2, the signal frequency of the selection signal at the fifth selection signal terminal D4 is half of the signal frequency of the selection signal at the fourth selection signal terminal D3, the signal frequency of the selection signal at the sixth selection signal terminal D5 is half of the signal frequency of the selection signal at the fifth selection signal terminal D4, the signal frequency of the selection signal at the seventh selection signal terminal D6 is half of the signal frequency of the selection signal at the sixth selection signal terminal D5, and the signal frequency of the selection signal at the eighth selection signal terminal D7 is half of the signal frequency of the selection signal at the seventh selection signal terminal D6. The signal pulse width of the selection signal at the first selection signal terminal D0 is the smallest, the signal pulse width of the selection signal at the second selection signal terminal D1 is twice the signal pulse width of the selection signal at the first selection signal terminal D0, the signal pulse width of the selection signal at the third selection signal terminal D2 is twice the signal pulse width of the selection signal at the second selection signal terminal D1, the signal pulse width of the selection signal at the fourth selection signal terminal D3 is twice the signal pulse width of the selection signal at the third selection signal terminal D2, and the signal pulse width of the selection signal at the fifth selection signal terminal D4 is twice the signal pulse width of the selection signal at the fifth selection signal terminal D5. The signal pulse width of the selection signal is twice the signal pulse width of the selection signal of the fourth selection signal terminal D3, the signal pulse width of the selection signal of the sixth selection signal terminal D5 is twice the signal pulse width of the selection signal of the fifth selection signal terminal D4, the signal pulse width of the selection signal of the seventh selection signal terminal D6 is twice the signal pulse width of the selection signal of the sixth selection signal terminal D5, and the signal pulse width of the selection signal of the eighth selection signal terminal D7 is twice the signal pulse width of the selection signal of the seventh selection signal terminal D6.

[0198] In an exemplary embodiment, as shown in Figures 8 and 9, the non-display area 200 includes a signal line area and a device area, and the gate driver circuit is at least partially located in the device area. The signal line area may include: a first signal line area RS1, a second signal line area RS2, and a third signal line area RS3, which are sequentially arranged along the display area 100. The device area may include: a first device area RT1, a second device area RT2, a third device area RT3, and a fourth device area RT4, which are sequentially arranged along the display area 100. The first signal line area RS1 is located on a side of the first device area RT1 away from the display area 100, and the third signal line area RS3 is located on a side of the fourth device area RT4 closer to the display area 100.

[0199] In exemplary embodiments, as shown in FIG. 8 and FIG. 9 , the gate signal line group DL may be located in the first signal line region RS1 .

[0200] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the gating sub-circuit 10 may be located in the first device region RT1 .

[0201] In exemplary embodiments, as shown in FIG8 and FIG9 , the second signal line region RS2 may be located between the first signal line region RS1 and the first device region RT1, or may be located between the first device region RT1 and the second device region RT2. FIG8 illustrates an example in which the second signal line region RS2 may be located between the first signal line region RS1 and the first device region RT1. FIG9 illustrates an example in which the second signal line region RS2 is located between the first device region RT1 and the second device region RT2.

[0202] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the length of the first signal line section RS1 along the second direction D2 is greater than the length of the second signal line section RS2 along the second direction D2 .

[0203] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the length of the third signal line section RS3 along the second direction D2 is greater than the length of the second signal line section RS2 along the second direction D2 .

[0204] In an exemplary embodiment, as shown in Figures 8 and 9, the non-display area 200 is further provided with a clock signal line group CLK, and the gate driving circuit is electrically connected to the clock signal line group CLK. The clock signal line group CLK is located in the first signal line area RS1 and is located on the side of the gate signal line group DL away from the display area 100.

[0205] In an exemplary embodiment, as shown in Figures 8, 9, and 11, the clock signal line group CLK includes a control clock signal line group CLK2 and an output clock signal line group CLK1. The control clock signal line group CLK2 includes a plurality of control clock signal lines extending along a first direction D1 and a plurality of control clock signal lines arranged along a second direction D2. The output clock signal line group CLK1 includes a plurality of output clock signal lines extending along the first direction D1 and a plurality of output clock signal lines arranged along the second direction D2. The line width of the output clock signal lines is greater than the line width of the control clock signal lines and the line width of the strobe signal lines. Figures 8, 9, and 11 illustrate 16 output clock signal lines and 4 control clock signal lines as an example.

[0206] In an exemplary embodiment, as shown in FIG11 , a shift register includes: multiple control clock terminals and multiple output clock terminals. Any of the multiple control clock terminals is electrically connected to one of the control clock signal lines in the control clock signal line group CLK2, and any of the multiple output clock terminals is electrically connected to one of the output clock signal lines in the output clock signal line group CLK1. In any shift register, the multiple control clock terminals are electrically connected to some of the signal lines in the control clock signal group CLK2, and the multiple output clock terminals are electrically connected to some of the signal lines in the output clock signal line group CLK1. FIG11 illustrates an example of a shift register including three control clock terminals, e.g., first through third control clock terminals CKA through CKC, and four output clock terminals, e.g., first through fourth output clock terminals CKE1 through CKE4.

[0207] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the output clock signal line group CLK1 is located at a side where the clock signal line group CLK2 can be controlled to be away from the display area 100 .

[0208] In an exemplary embodiment, as shown in Figures 8 and 9, the non-display area 200 is further provided with a first high-level power line VDDL1 and a second high-level power line VDDL2. The shift register includes a first high-level power terminal and a second high-level power terminal. For any shift register, the first high-level power terminal is electrically connected to the first high-level power line VDDL1, and the second high-level power terminal is electrically connected to the second high-level power line VDDL2.

[0209] In exemplary embodiments, as shown in FIG. 8 and FIG. 9 , the first high-level power line VDDL1 and the second high-level power line VDDL2 may be located in the second signal line region RS2 .

[0210] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the line width of any one of the first high level power line VDDL1 and the second high level power line VDDL2 is greater than the line width of any signal line located in the first signal line region RS1 .

[0211] In an exemplary embodiment, as shown in Figures 8 and 9, the non-display area 200 is further provided with a first low-level power line VGL1 and a second low-level power line VGL2. The shift register includes a first low-level power terminal and a second low-level power terminal. For any shift register, the first low-level power terminal is electrically connected to the first low-level power line VGL1, and the second low-level power terminal is electrically connected to the second low-level power line VGL2.

[0212] 8 and 9 , the first and second low-level power lines VGL1 and VGL2 are located in the third signal line area RS3 , and the first and second low-level power lines VGL1 and VGL2 are located on a side away from the display area.

[0213] In an exemplary embodiment, as shown in Figures 8 and 9, the line width of any one of the first low-level power line VGL1 and the second low-level power line VGL2 is greater than the line width of any signal line located in the first signal line area RS1, and the line width of the first low-level power line VGL1 is smaller than the line width of the second low-level power line VGL2.

[0214] In an exemplary embodiment, as shown in Figures 8 and 9, the length of the second device region RT2 along the second direction D2 is greater than the length of the first device region RT1 along the second direction D2, the length of the third device region RT3 along the second direction D2 is greater than or equal to the length of the second device region RT2 along the second direction D2, and the length of the fourth device region RT4 along the second direction D2 is greater than the length of the third device region RT3 along the second direction D2.

[0215] In an exemplary embodiment, as shown in FIG6 , FIG8 and FIG9 , the shift register further includes: an input subcircuit 40 , a node setting subcircuit 20 and a preprocessing subcircuit 30 ; and the plurality of control clock terminals include: a first control clock terminal to a third control clock terminal. The node setting subcircuit 20 is electrically connected to at least the second high-level power supply terminal, the second low-level power supply terminal, the second control clock terminal, the third control clock terminal, the first node, and the third node, and is configured to provide a signal from the second high-level power supply terminal or the second low-level power supply terminal to the first node under the control of signals from the second control clock terminal, the third control clock terminal, and the third node; the input subcircuit 40 is electrically connected to at least the third control clock terminal, the third node, and the fifth node, and is configured to provide a signal from the third control clock terminal to the fifth node under the control of signals from the third node and the third control clock terminal; the preprocessing subcircuit 30 is electrically connected to at least the second node, the third node, the fourth node, the first high-level power supply terminal, and the first control clock terminal, and is configured to provide a signal from the first control clock terminal or the first high-level power supply terminal to the third node and the fourth node under the control of signals from the second node and the first control clock terminal; the gating subcircuit 10 is also electrically connected to the second control clock terminal and the second node, and is configured to provide a signal from the second control clock terminal to the second node under the control of signals from a plurality of gating signal terminals;

[0216] In an exemplary embodiment, as shown in Figures 8 and 9, the input sub-circuit 40, the node setting sub-circuit 20, and the pre-processing sub-circuit 30 may be located in the second device region RT2 and arranged along the first direction D1, with the pre-processing sub-circuit 30 located between the input sub-circuit 40 and the node setting sub-circuit 20. The input sub-circuit 40, the node setting sub-circuit 20, and the pre-processing sub-circuit 30 may be located in the second device region RT2 and arranged along the first direction D1 to reduce the length of the gate driver circuit along the second direction, thereby achieving a narrow bezel of the display substrate.

[0217] In an exemplary embodiment, the preprocessing subcircuit 30 includes a plurality of preprocessing transistors and a preprocessing capacitor. The preprocessing capacitor may include the second capacitor C2 in FIG. 6 , and the plurality of preprocessing transistors may include the eleventh transistor T11 through the fourteenth transistor T14 in FIG. The preprocessing capacitor is located on a side of the plurality of preprocessing transistors near the node configuration subcircuit 20 . The large area occupied by the preprocessing capacitor ensures its storage capacity, thereby improving the reliability of the gate drive circuit.

[0218] In an exemplary embodiment, as shown in FIG8 and FIG9 , the shift register may further include a node separation subcircuit 50. The node separation subcircuit 50 is electrically connected to the third control clock terminal, the first high-level power supply terminal, the second low-level power supply terminal, the first node, the fifth node, the sixth node, the seventh node, the eighth node, and the ninth node, respectively, and is configured to provide the signal of the fifth node to the sixth to ninth nodes respectively under the control of the signal of the third control clock terminal and the first node, or to provide the signal of the first high-level power supply terminal to the fifth node under the control of the signal of the sixth node.

[0219] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the node separation sub-circuit 50 may be located in the third device region RT3 .

[0220] In an exemplary embodiment, the shift register further includes an output subcircuit 60. The output subcircuit 60 is electrically connected to at least a plurality of output clock terminals, a first low-level power terminal, and a plurality of signal output terminals, and is configured to output signals corresponding to the output clock terminals or the first low-level power terminal to the plurality of signal output terminals.

[0221] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the output sub-circuit 60 may be located in the fourth device region RT4 .

[0222] In an exemplary embodiment, the output sub-circuit 60 further includes a plurality of output capacitors arranged in an array along a first direction D1 and a second direction D2. Arranging the plurality of output capacitors in an array along the first direction D1 and the second direction D2 can reduce the length of the gate drive circuit along the second direction D2, thereby achieving a narrow bezel on the display substrate.

[0223] In an exemplary embodiment, as shown in Figures 8 and 9, the shift register further includes a reset subcircuit 80 and a noise reduction subcircuit (not shown in the figures), and the plurality of control clock terminals include first to third control clock terminals. The reset subcircuit 80 is electrically connected to at least the master reset signal terminal, the third node, the fourth node, the first high-level power supply terminal, and the second low-level power supply terminal, respectively, and is configured to provide a second low-level power supply terminal to the third node, the fourth node, and the first high-level power supply terminal under the control of a signal from the master reset signal terminal. The noise reduction subcircuit is electrically connected to at least the first node, the second node, the ninth node, the first control clock terminal, the second control clock terminal, and the second low-level power supply terminal, respectively, and is configured to be a control line for a signal from the first control clock terminal, provide a signal from the second control clock terminal to the second node, and provide a signal from the second low-level power supply terminal to the first node under the control of a signal from the ninth node.

[0224] In an exemplary embodiment, as shown in FIG. 8 and FIG. 9 , the reset sub-circuit 80 may be located in the second device region RT2 , and the reset sub-circuit 80 and the pre-processing sub-circuit 30 are arranged along the second direction D2 .

[0225] In an exemplary embodiment, the noise reduction sub-circuit can be located in the second device region RT2, the size of the transistors in the noise reduction sub-circuit is relatively small, and the position of the noise reduction sub-circuit can be any position, for example, it can be placed between the reset sub-circuit 80 and the node separation sub-circuit 50, and arranged along the second direction D2 with the reset sub-circuit 80 and the node separation sub-circuit 50, or it can be placed between the reset sub-circuit 80 and the node setting sub-circuit 20, and arranged along the first direction D1 with the reset sub-circuit 80 and the node setting sub-circuit 20. The present disclosure does not impose any limitations on this.

[0226] In an exemplary embodiment, a reset signal line is further provided in the non-display area 200. The main reset signal terminal of the shift register is electrically connected to the reset signal line.

[0227] In an exemplary embodiment, the reset signal line may be located in the first signal line region RS1 .

[0228] In an exemplary embodiment, FIG12 is a connection diagram of a plurality of shift register groups. As shown in FIG11 and FIG12, the gate drive circuit includes: a plurality of shift register groups (hereinafter referred to as GOA groups), the shift register group includes N1 shift register units (hereinafter referred to as GOA units), and the GOA unit includes N2 shift registers GOA, N1, N2 ≥ 2. FIG11 is a GOA unit including: 4 GOAs, FIG11 shows a GOA unit, the GOA unit includes: the first shift register GOA (1) to the fourth shift register GOA (4), each GOA is connected to four rows of sub-pixels, GOA (1) is connected to the first row of sub-pixels R1 to the fourth row of sub-pixels R4, GOA (2) is connected to the fifth row of sub-pixels R5 to the eighth row of sub-pixels R8, GOA (3) is connected to the ninth row of sub-pixels R9 to the twelfth row of sub-pixels R12, and GOA (3) is connected to the thirteenth row of sub-pixels R13 to the sixteenth row of sub-pixels T16. FIG12 is an example of a gate driving circuit connected to 2160 rows of sub-pixels, and the gate driving circuit includes 17 GOA groups, such as GOA group (1) to GOA group (17).

[0229] In an exemplary embodiment, as shown in Figure 11, some of the selection signal lines connected to the multiple selection signal terminals of the shift register are called selection signal line units; the selection signal lines included in the selection signal line units connected to any two shift registers located in the same shift register unit are the same, and at least one of the selection signal lines included in the selection signal line units connected to any two shift register units located in the same shift register group is different; the selection signal lines included in the selection signal line units connected to the n1th shift register unit located in different shift register groups are the same, 1≤n1≤N1. Figure 11 is explained by taking the example that the first selection signal terminal D0 of all shift registers located in the same GOA unit is electrically connected to the first selection signal line DL0, the second selection signal terminal D1 is electrically connected to the third selection signal line DL1, the third selection signal terminal D2 is electrically connected to the fifth selection signal line DL2, the fourth selection signal terminal D3 is electrically connected to the seventh selection signal line DL3, the fifth selection signal terminal D4 is electrically connected to the ninth selection signal line DL4, the sixth selection signal terminal D5 is electrically connected to the eleventh selection signal line DL5, the seventh selection signal terminal D6 is electrically connected to the thirteenth selection signal line DL6, and the eighth selection signal terminal D7 is electrically connected to the fifteenth selection signal line DL7. The first selection signal terminal D0 of all shift registers in the GOA unit (1) in the first GOA group in FIG12 is electrically connected to the first selection signal line DL0, the second selection signal terminal D1 is electrically connected to the third selection signal line DL1, the third selection signal terminal D2 is electrically connected to the fifth selection signal line DL2, the fourth selection signal terminal D3 is electrically connected to the seventh selection signal line DL3, the fifth selection signal terminal D4 is electrically connected to the ninth selection signal line DL4, the sixth selection signal terminal D5 is electrically connected to the eleventh selection signal line DL5, the seventh selection signal terminal D6 is electrically connected to the thirteenth selection signal line DL6, the eighth selection signal terminal D7 is electrically connected to the fifteenth selection signal line DL7. For example, the first selection signal terminal D0 in the GOA unit (8) is electrically connected to the second selection signal line DLN0, the second selection signal terminal D1 is electrically connected to the fourth selection signal line DLN1, the third selection signal terminal D2 is electrically connected to the sixth selection signal line DLN2, the fourth selection signal terminal D3 is electrically connected to the seventh selection signal line DL3, the fifth selection signal terminal D4 is electrically connected to the ninth selection signal line DL4, the sixth selection signal terminal D5 is electrically connected to the eleventh selection signal line DL5, the seventh selection signal terminal D6 is electrically connected to the thirteenth selection signal line DL6, and the eighth selection signal terminal D7 is electrically connected to the fifteenth selection signal line DL7. The present disclosure does not impose any limitation on this.

[0230] In an exemplary embodiment, some of the control clock signal lines connected to the multiple control clock terminals of the shift register are called control clock signal line units, and some of the output clock signal lines connected to the multiple output clock terminals of the shift register are called output clock signal line units; at least one of the control clock signal lines included in the control clock signal line units connected to any two shift registers located in the same shift register unit is different, and at least one of the output clock signal lines included in the output clock signal line units connected to any two shift registers located in the same shift register unit is different; the control clock signal lines included in the control clock signal line units connected to the n2th shift registers located in different shift register units are the same, and the output clock signal lines included in the output clock signal line units connected to the n2th shift registers located in different shift register units are the same, and 1≤n2≤N2.In an exemplary embodiment, FIG11 shows a first control clock terminal CKA of GOA (1) electrically connected to a first control clock signal line CLKA, a second control clock terminal CKB electrically connected to a second control clock signal line CLKB, a third control clock terminal CKC electrically connected to a third control clock signal line CLKC, a first output clock terminal CKE1 electrically connected to a first output clock signal line CLKE1, a second output clock terminal CKE2 electrically connected to a second output clock signal line CLKE2, a third output clock terminal CKE3 electrically connected to a third output clock signal line CLKE3, and a fourth output clock terminal CKE4 electrically connected to a fourth output clock signal line C LKE4 is electrically connected, the first control clock terminal CKA of GOA (2) is electrically connected to the second control clock signal line CLKB, the second control clock terminal CKB is electrically connected to the third control clock signal line CLKC, the third control clock terminal CKC is electrically connected to the fourth control clock signal line CLKD, the first output clock terminal CKE1 is electrically connected to the fifth output clock signal line CLKE5, the second output clock terminal CKE2 is electrically connected to the sixth output clock signal line CLKE6, the third output clock terminal CKE3 is electrically connected to the seventh output clock signal line CLKE7, and the fourth output clock terminal CKE4 is electrically connected to the eighth output clock signal line CLKE8. , the first control clock terminal CKA of GOA (3) is electrically connected to the third control clock signal line CLKC, the second control clock terminal CKB is electrically connected to the fourth control clock signal line CLKD, the third control clock terminal CKC is electrically connected to the first control clock signal line CLKA, the first output clock terminal CKE1 is electrically connected to the ninth output clock signal line CLKE9, the second output clock terminal CKE2 is electrically connected to the tenth output clock signal line CLKE10, the third output clock terminal CKE3 is electrically connected to the eleventh output clock signal line CLKE11, and the fourth output clock terminal CKE4 is electrically connected to the twelfth output clock signal line CLKE12, G The first control clock terminal CKA of OA(4) is electrically connected to the fourth control clock signal line CLKD, the second control clock terminal CKB is electrically connected to the first control clock signal line CLKA, the third control clock terminal CKC is electrically connected to the second control clock signal line CLKB, the first output clock terminal CKE1 is electrically connected to the thirteenth output clock signal line CLKE13, the second output clock terminal CKE2 is electrically connected to the fourteenth output clock signal line CLKE14, the third output clock terminal CKE3 is electrically connected to the fifteenth output clock signal line CLKE15, and the fourth output clock terminal CKE4 is electrically connected to the sixteenth output clock signal line CLKE16.

[0231] In an exemplary embodiment, the shift register included in the shift register unit can be determined according to the number of combinations of select signals that can be connected. If a shift register has two select signal ports, the shift register is connected to two select signals. There are four select signals available for connection, two of which are mutually inverted signals, and the other two are mutually inverted signals. The four select signals can form four combinations to connect to the shift register, thereby forming four shift register groups, and each shift register in each shift register group is connected to the same select signal combination.

[0232] In an exemplary embodiment, the number of shift registers included in the shift register unit may be determined according to the number of provided clock signals.

[0233] In an exemplary embodiment, Figure 13 is a schematic cross-sectional view of a display substrate. As shown in Figure 13, the display substrate includes a base 11 and a drive structure layer disposed on the base. The shift register includes a plurality of transistors. The drive structure layer includes a first conductive layer, a first insulating layer 12, a semiconductor layer, a second insulating layer 13, and a second conductive layer stacked on the base. Figure 13 shows only one of the transistors. The transistor includes an active pattern 21, a gate electrode 22, a first electrode 23, and a second electrode 24.

[0234] In an exemplary embodiment, the semiconductor layer includes at least an active pattern of a plurality of transistors in a shift register.

[0235] In an exemplary embodiment, the second conductive layer includes at least gate electrodes, a first electrode, and a second electrode of a plurality of transistors in the shift register.

[0236] In an exemplary embodiment, the driving structure layer may further include a third insulating layer 14 and a planar layer 15 .

[0237] In an exemplary embodiment, the first conductive layer includes at least a signal line L to which the transistor is connected. The signal line L may be any one of a strobe signal line, a control clock signal line, an output clock signal line, a first high-level power line VDDL1, a second high-level power line VDDL2, a first low-level power line VGL1, and a second low-level power line VGL2.

[0238] In an exemplary embodiment, any signal line among the selection signal line, the control clock signal line, the output clock signal line, the first high-level power line VDDL1, the second high-level power line VDDL2, the first low-level power line VGL1 and the second low-level power line VGL2 has a single-layer structure located in the first conductive layer, or has a double-layer structure and is located in the first conductive layer and the second conductive layer.

[0239] In an exemplary embodiment, as shown in FIG. 10 , the non-display area is further provided with a first connection line L1 and a second connection line L2 , and the first connection line L1 and the second connection line L2 may be located in the first conductive layer.

[0240] In an exemplary embodiment, as shown in FIG10 , first electrodes of all gate transistors in the same gate sub-circuit are electrically connected to a first connection line L1 , and second electrodes of the gate transistors in the same gate sub-circuit are electrically connected to a second connection line L2 .

[0241] In an exemplary embodiment, as shown in FIG. 10 , the gate electrode, the first electrode, and the second electrode in any gate transistor at least partially extend along the second direction D2 , and the first connection line L1 and the second connection line L2 extend along the first direction D1 .

[0242] In an exemplary embodiment, Figure 14 is a partial schematic diagram of a non-display area of ​​a display substrate. As shown in Figure 14 , the non-display area 200 is further provided with a plurality of control clock connection lines and a plurality of control clock electrostatic discharge circuits. The plurality of control clock connection lines correspond one-to-one with the plurality of control clock signal lines, and the plurality of control clock connection lines correspond one-to-one with the plurality of control clock electrostatic discharge circuits. Figure 14 illustrates an example in which the plurality of control clock connection lines include first to fourth control clock connection lines AL1 to AL4, and the plurality of control clock electrostatic discharge circuits include first to fourth control clock electrostatic discharge circuits A-ESD1 to A-ESD4. The first control clock connection line AL1 corresponds to the first control clock signal line CLKA, the second control clock connection line AL2 corresponds to the second control clock signal line CLKB, the third control clock connection line AL3 corresponds to the third control clock signal line CLKC, the fourth control clock connection line AL4 corresponds to the fourth control clock signal line CLKD, the first control clock connection line AL1 corresponds to the first control clock electrostatic release circuit A-ESD1, the second control clock connection line AL2 corresponds to the second control clock electrostatic release circuit A-ESD2, the third control clock connection line AL3 corresponds to the third control clock electrostatic release circuit A-ESD3, and the fourth control clock connection line AL4 corresponds to the fourth control clock electrostatic release circuit A-ESD4.

[0243] In an exemplary embodiment, as shown in FIG14 , the control clock connection lines are electrically connected to corresponding control clock signal lines and corresponding control clock electrostatic discharge circuits. For example, the first control clock connection line AL1 is electrically connected to the first control clock signal line CLKA and the first control clock electrostatic discharge circuit A-ESD1, the second control clock connection line AL2 is electrically connected to the second control clock signal line CLKB and the second control clock electrostatic discharge circuit A-ESD2, the third control clock connection line AL3 is electrically connected to the third control clock signal line CLKC and the third control clock electrostatic discharge circuit A-ESD3, and the fourth control clock connection line AL4 is electrically connected to the fourth control clock signal line CLKD and the fourth control clock electrostatic discharge circuit A-ESD4.

[0244] In an exemplary embodiment, as shown in FIG14 , the control clock connection line includes a first control clock connection portion ALA extending along a second direction D2 and a second control clock connection portion ALB extending along a first direction D1. For any control clock connection line, the first control clock connection portion ALA is electrically connected to the corresponding control clock signal line and the second control clock connection portion ALB, respectively, and the second control clock connection portion is electrically connected to the corresponding control clock electrostatic discharge circuit. For example, the first control clock connection portion ALA of the first control clock connection line AL1 is electrically connected to the first control clock signal line CLKA and the second control clock connection portion ALB of the first control clock connection line AL1, respectively, and the second control clock connection portion ALB of the first control clock connection line AL1 is electrically connected to the first control clock electrostatic discharge circuit A-ESD1. The first clock connection portion ALA of the second clock control line AL2 is electrically connected to the second clock control signal line CLKB and the second clock connection portion ALB of the second clock control line AL2, respectively. The second clock connection portion ALB of the second clock control line AL2 is electrically connected to the second clock control electrostatic discharge circuit A-ESD2. The first clock connection portion ALA of the third clock control line AL3 is electrically connected to the third clock control signal line CLKC and the second clock connection portion ALB of the third clock control line AL3, respectively. The second clock connection portion ALB of the third clock control line AL3 is electrically connected to the third clock control electrostatic discharge circuit A-ESD3. The first clock connection portion ALA of the fourth clock control line AL4 is electrically connected to the fourth clock control signal line CLKD and the second clock connection portion ALB of the fourth clock control line AL4, respectively. The second clock connection portion ALB of the fourth clock control line AL4 is electrically connected to the fourth clock control electrostatic discharge circuit A-ESD4.

[0245] In an exemplary embodiment, as shown in FIG. 14 , the first control clock connection portion ALA is located on the second conductive layer, and the second control clock connection portion ALB is located on the first conductive layer.

[0246] In an exemplary embodiment, as shown in FIG14 , the non-display area 200 is further provided with a plurality of output clock connection lines and a plurality of output clock electrostatic discharge circuits. The plurality of output clock connection lines correspond one-to-one with the plurality of output clock signal lines, and the plurality of output clock connection lines correspond one-to-one with the plurality of output clock electrostatic discharge circuits. FIG14 illustrates an example in which the plurality of output clock connection lines include: a first output clock connection line EL1 to a sixteenth output clock connection line EL16, and the plurality of output clock electrostatic discharge circuits include: a first output clock electrostatic discharge circuit ESD1 to a sixteenth output clock electrostatic discharge circuit ESD16. The first output clock connection line EL1 corresponds to the first output clock signal line CLKE1, the second output clock connection line EL2 corresponds to the second output clock signal line CLKE2, the third output clock connection line EL3 corresponds to the third output clock signal line CLKE3, the fourth output clock connection line EL4 corresponds to the fourth output clock signal line CLKE4, and so on. The first output clock connection line EL1 corresponds to the first output clock electrostatic release circuit ESD1, the second output clock connection line EL2 corresponds to the second output clock electrostatic release circuit ESD2, the third output clock connection line EL3 corresponds to the third output clock electrostatic release circuit ESD3, the fourth output clock connection line EL4 corresponds to the fourth output clock electrostatic release circuit ESD4, and so on.

[0247] In an exemplary embodiment, as shown in FIG14 , the output clock connection lines are electrically connected to corresponding output clock signal lines and corresponding output clock electrostatic discharge circuits. The first output clock connection line EL1 is electrically connected to the first output clock signal line CLKE1 and the first output clock electrostatic discharge circuit ESD1, the second output clock connection line EL2 is electrically connected to the second output clock signal line CLKE2 and the second output clock electrostatic discharge circuit ESD2, the third output clock connection line EL3 is electrically connected to the third output clock signal line CLKE3 and the third output clock electrostatic discharge circuit ESD3, the fourth output clock connection line EL4 is electrically connected to the fourth output clock signal line CLKE4 and the fourth output clock electrostatic discharge circuit ESD4, and so on.

[0248] In an exemplary embodiment, as shown in FIG14 , the output clock connection line includes: a first output clock connection portion ELA extending along a second direction D2 and a second output clock connection portion ELB extending along a first direction D1. For any output clock connection line, the first output clock connection portion is electrically connected to the corresponding output clock signal line and the second output clock connection portion, respectively, and the second output clock connection portion is electrically connected to the corresponding output clock electrostatic discharge circuit. For example, the first output clock connection portion ELA of the first output clock connection line EL1 is electrically connected to the first output clock signal line CLKE1 and the second output clock connection portion ELB of the first output clock connection line EL1, respectively; the second output clock connection portion ELB of the first output clock connection line EL1 is electrically connected to the first output clock electrostatic discharge circuit ESD1; the first output clock connection portion ELA of the second output clock connection line EL2 is electrically connected to the second output clock signal line CLKE2 and the second output clock connection portion ELB of the second output clock connection line EL2, respectively; and the second output clock connection portion ELB of the second output clock connection line EL2 is electrically connected to the second output clock electrostatic discharge circuit ESD2. The first output clock connection part ELA of the third output clock connection line EL3 is respectively connected to the third output clock signal line CLKE3 and the second output clock connection part ELB of the third output clock connection line EL3, the second output clock connection part ELB of the third output clock connection line EL3 is electrically connected to the third output clock electrostatic release circuit ESD3, the first output clock connection part ELA of the fourth output clock connection line EL4 is respectively connected to the fourth output clock signal line CLKE4 and the second output clock connection part ELB of the fourth output clock connection line EL4, the second output clock connection part ELB of the fourth output clock connection line EL4 is electrically connected to the fourth output clock electrostatic release circuit ESD4, and so on.

[0249] In an exemplary embodiment, as shown in FIG. 14 , the first output clock connection portion ELA may be located on the second conductive layer, and the second output clock connection portion ELB may be located on the first conductive layer.

[0250] In an exemplary embodiment, as shown in FIG14 , the non-display area 200 is further provided with four power connection lines and four power electrostatic discharge circuits. The first power connection line SL1 is electrically connected to the first high-level power line VDDL1 and the first power electrostatic discharge circuit S-ESD1, respectively; the second power connection line SL2 is electrically connected to the second high-level power line VDDL2 and the second power electrostatic discharge circuit S-ESD2, respectively; the third power connection line SL3 is electrically connected to the first low-level power line VGL1 and the third power electrostatic discharge circuit S-ESD3, respectively; and the fourth power connection line SL4 is electrically connected to the second low-level power line VGL2 and the fourth power electrostatic discharge circuit S-ESD4, respectively.

[0251] In an exemplary embodiment, as shown in FIG. 14 , the power connection line includes a first power connection portion SLA extending along the second direction D2 and a second power connection portion SLB extending along the first direction D1 .

[0252] In an exemplary embodiment, as shown in FIG14 , for any power connection line, the first power connection portion SLA is electrically connected to the connected power line and the second power connection portion SLB, respectively, and the second power connection portion SLB is electrically connected to the connected power electrostatic discharge circuit. For example, the first power connection portion SLA of the first power connection line SL1 is electrically connected to the first high-level power line VDDL1 and the second power connection portion SLB of the first power connection line SL1, respectively, and the second power connection portion SLB of the first power connection line SL1 is electrically connected to the first power electrostatic discharge circuit S-ESD1. The first power connection portion SLA of the second power connection line SL2 is electrically connected to the second high-level power line VDDL2 and the second power connection portion SLB of the second power connection line SL2, respectively, and the second power connection portion SLB of the second power connection line SL2 is electrically connected to the second power electrostatic discharge circuit S-ESD2. The first power connection portion SLA of the third power connection line SL3 is electrically connected to the first low-level power line VGL1 and the second power connection portion SLB of the third power connection line SL3, respectively. The second power connection portion SLB of the third power connection line SL3 is electrically connected to the third power electrostatic discharge circuit S-ESD3. The first power connection portion SLA of the fourth power connection line SL4 is electrically connected to the second low-level power line VGL2 and the second power connection portion SLB of the fourth power connection line SL4, respectively. The second power connection portion SLB of the fourth power connection line SL4 is electrically connected to the fourth power electrostatic discharge circuit S-ESD4.

[0253] In an exemplary embodiment, as shown in FIG. 14 , the first power connection portion SLA may be located on the second conductive layer, and the second power connection portion SLB may be located on the first conductive layer.

[0254] In an exemplary embodiment, as shown in Figures 8 and 9 , a distance H between the first signal line farthest from the border of the display area and the second signal line close to the border of the display area is approximately 3400 to 3450 micrometers. The first signal line is the signal line in the first signal line region RS1 that is farthest from the border of the display area. As shown in Figures 8 and 9 , the first signal line is the first output clock signal line CLKE1. The second signal line is the signal line in the third signal line region RS3 that is closest to the border of the display area. As shown in Figures 8 and 9 , the second signal line is the second low-level power line VGL2.

[0255] Exemplarily, a distance H between the first signal line away from the boundary of the display area and the second signal line close to the boundary of the display area is approximately 3430 micrometers.

[0256] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0257] In an exemplary embodiment, the display substrate may further include a light-emitting structure layer located on a side of the driving structure layer away from the substrate. The light-emitting structure layer may include an anode pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to one of the transistors in the driving structure layer via a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. Driven by the anode and cathode, the organic light-emitting layer emits light of a corresponding color.

[0258] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0259] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer located on a side of the light-emitting structure layer away from the substrate. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of an organic material. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0260] In an exemplary embodiment, the display substrate may further include a touch structure layer located on a side of the encapsulation structure layer away from the base. The touch structure layer may include a first touch insulation layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0261] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0262] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, and patterning the first conductive film through a patterning process to form a first conductive layer pattern, as shown in FIG. 15 , which is a schematic diagram of the first conductive layer pattern in FIG. 10 .

[0263] In an exemplary embodiment, as shown in FIG. 15 , the first conductive layer pattern may include at least a second high-level power line GVDD2 , a first connection line L1 , and a second connection line L2 located at each shift register.

[0264] In an exemplary embodiment, as shown in FIG. 15 , the second high-level power line GVDD2 is located on a side of the first connection line L1 away from the display area, and the second connection line L2 is located on a side of the first connection line L1 close to the display area.

[0265] In an exemplary embodiment, as shown in FIG15 , the second high-level power line GVDD2 may be in the shape of a line with a main portion extending along the first direction D1. A via V0 is defined in the second high-level power line GVDD2. The via V0 can reduce coupling capacitance in the gate drive circuit, thereby improving the reliability of the gate drive circuit.

[0266] In an exemplary embodiment, as shown in FIG. 15 , the first connection line L1 may have a line shape in which a main portion extends along the first direction D1 .

[0267] 15 , the second connection line L2 may be in the shape of a line with a main portion extending along the first direction D1. A groove K is formed on a side of the second connection line L2 close to the first connection line L1.

[0268] In an exemplary embodiment, the first connecting line L1 and the second connecting line L2 can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the shift register, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0269] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in Figures 16 and 17 , where Figure 16 is a schematic diagram of the semiconductor layer pattern in Figure 10 , and Figure 17 is a schematic diagram of Figure 10 after the semiconductor pattern is formed.

[0270] In example embodiments, as shown in FIG. 16 and FIG. 17 , the semiconductor layer pattern may include at least active patterns ACT21 of the second transistor to ACT91 of the ninth transistor of each shift register.

[0271] In an exemplary embodiment, orthographic projections of the second to ninth transistor active patterns ACT21 to ACT91 on the substrate are located between orthographic projections of the first and second connection lines L1 and L2 on the substrate.

[0272] In an exemplary embodiment, the active patterns ACT21 of the second transistor to ACT91 of the ninth transistor are individually provided and sequentially arranged along the first direction D1.

[0273] In an exemplary embodiment, any one of the active patterns ACT21 of the second transistor to ACT91 of the ninth transistor extends in the first direction D1.

[0274] In an exemplary embodiment, the active pattern ACT81 of the eighth transistor is located within the groove of the first connection line.

[0275] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region ACT21-1 and the second region ACT21-2 of the active pattern ACT21 of the second transistor, the first region ACT31-1 and the second region ACT31-2 of the active pattern ACT31 of the third transistor, the first region ACT41-1 and the second region ACT41-2 of the active pattern ACT41 of the fourth transistor, the first region ACT51-1 and the second region ACT51-2 of the active pattern ACT51 of the fifth transistor, the first region ACT61-1 and the second region ACT61-2 of the active pattern ACT61 of the sixth transistor, the first region ACT71-1 and the second region ACT71-2 of the active pattern ACT71 of the seventh transistor, the first region ACT81-1 and the second region ACT81-2 of the active pattern ACT81 of the eighth transistor, and the first region ACT91-1 and the second region ACT91-2 of the active pattern ACT91 of the ninth transistor are separately provided.

[0276] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the semiconductor layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG18 , which is a schematic diagram of FIG10 after the second insulating layer pattern is formed.

[0277] In an exemplary embodiment, as shown in FIG. 18 , the plurality of via holes of the second insulation layer pattern includes at least a first via hole V1 to an eighteenth via hole V18 located at each shift register.

[0278] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the first insulating layer and the second insulating layer in the first via V1 are etched away to expose the surface of the first connecting line, and the first via V1 is configured to connect the first electrode of the subsequently formed second transistor to the first electrode of the ninth transistor to the first connecting line through the via.

[0279] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second connecting line, and the second via V2 is configured to connect the second electrode of the subsequently formed second transistor to the second electrode of the ninth transistor to the second connecting line through the via.

[0280] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second transistor on the substrate, the third via V3 exposes the surface of the first area of ​​the active pattern of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of ​​the active pattern of the second transistor through the via.

[0281] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor on the substrate, the fourth via V4 exposes the surface of the second area of ​​the active pattern of the second transistor, and the fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor to the second area of ​​the active pattern of the second transistor through the via.

[0282] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third transistor on the substrate, the fifth via V5 exposes the surface of the first area of ​​the active pattern of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active pattern of the third transistor through the via.

[0283] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third transistor on the substrate, the sixth via V6 exposes the surface of the second area of ​​the active pattern of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed third transistor to the second area of ​​the active pattern of the third transistor through the via.

[0284] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the seventh via V7 exposes the surface of the first area of ​​the active pattern of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0285] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth transistor on the substrate, the eighth via V8 exposes the surface of the second area of ​​the active pattern of the fourth transistor, and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor to the second area of ​​the active pattern of the fourth transistor through the via.

[0286] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the ninth via V9 exposes the surface of the first area of ​​the active pattern of the fifth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active pattern of the fifth transistor through the via.

[0287] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifth transistor on the substrate, the tenth via V10 exposes the surface of the second area of ​​the active pattern of the fifth transistor, and the tenth via V10 is configured to connect the second electrode of the subsequently formed fifth transistor to the second area of ​​the active pattern of the fifth transistor through the via.

[0288] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixth transistor on the substrate, the eleventh via V11 exposes the surface of the first area of ​​the active pattern of the sixth transistor, and the eleventh via V11 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of ​​the active pattern of the sixth transistor through the via.

[0289] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor on the substrate, the twelfth via V12 exposes the surface of the second area of ​​the active pattern of the sixth transistor, and the twelfth via V12 is configured to connect the second electrode of the subsequently formed sixth transistor to the second area of ​​the active pattern of the sixth transistor through the via.

[0290] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventh transistor on the substrate, the thirteenth via V13 exposes the surface of the first area of ​​the active pattern of the seventh transistor, and the thirteenth via V13 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of ​​the active pattern of the seventh transistor through the via.

[0291] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventh transistor on the substrate, the fourteenth via V14 exposes the surface of the second area of ​​the active pattern of the seventh transistor, and the fourteenth via V14 is configured to connect the second electrode of the subsequently formed seventh transistor to the second area of ​​the active pattern of the seventh transistor through the via.

[0292] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eighth transistor on the substrate, the fifteenth via V15 exposes the surface of the first area of ​​the active pattern of the eighth transistor, and the fifteenth via V15 is configured to connect the first electrode of the subsequently formed eighth transistor to the first area of ​​the active pattern of the eighth transistor through the via.

[0293] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighth transistor on the substrate, the sixteenth via V16 exposes the surface of the second area of ​​the active pattern of the eighth transistor, and the sixteenth via V16 is configured to connect the second electrode of the subsequently formed eighth transistor to the second area of ​​the active pattern of the eighth transistor through the via.

[0294] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the ninth transistor on the substrate, the seventeenth via V17 exposes the surface of the first area of ​​the active pattern of the ninth transistor, and the seventeenth via V17 is configured to connect the first electrode of the subsequently formed ninth transistor to the first area of ​​the active pattern of the ninth transistor through the via.

[0295] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the ninth transistor on the substrate, the eighteenth via V18 exposes the surface of the second area of ​​the active pattern of the ninth transistor, and the eighteenth via V18 is configured to connect the second electrode of the subsequently formed ninth transistor to the second area of ​​the active pattern of the ninth transistor through the via.

[0296] In an exemplary embodiment, as shown in FIG18 , a plurality of first via holes V1 are arranged along a first direction D1. A plurality of second via holes V2 are arranged along the first direction D1, and at least a portion of the second via holes V2 are arranged along the first direction D1. A portion of the second via holes V2 is arranged along the first direction D1 along with the fifteenth and sixteenth via holes V2.

[0297] In an exemplary embodiment, as shown in FIG. 18 , the third to eighteenth via holes V3 to V18 are arranged along the first direction D1 , and the number of any one of the third to eighteenth via holes V3 to V18 may be one.

[0298] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on a substrate, and patterning the second conductive film through a patterning process to form a second conductive layer pattern, as shown in Figures 19 and 20. Figure 19 is a schematic diagram of the second conductive layer pattern in Figure 10, and Figure 20 is a schematic diagram of Figure 10 after the second conductive layer pattern is formed.

[0299] In an exemplary embodiment, as shown in Figures 19 and 20, the second conductive layer pattern includes at least: the gate electrode Gate22, the first pole SD23 and the second pole S24 of the second transistor located in each shift register, the gate electrode Gate32, the first pole SD33 and the second pole SD34 of the third transistor, the gate electrode SD42, the first pole SD43 and the second pole S44 of the fourth transistor, the gate electrode SD52, the first pole SD53 and the second pole S54 of the fifth transistor, the gate electrode SD62, the first pole SD63 and the second pole S64 of the sixth transistor, the gate electrode SD72, the first pole SD73 and the second pole S74 of the seventh transistor, the gate electrode SD82, the first pole SD83 and the second pole S84 of the eighth transistor, and the gate electrode SD92, the first pole SD93 and the second pole S94 of the ninth transistor.

[0300] In an exemplary embodiment, any gate electrode from among the gate electrodes Gate22 of the second transistor to Gate82 of the eighth transistor has a stripe shape and extends along the second direction D2.

[0301] In an exemplary embodiment, the gate electrode Gate92 of the ninth transistor may have a zigzag shape and may be in a “┘” shape.

[0302] In an exemplary embodiment, the first electrode SD23 of the second transistor may be strip-shaped and at least partially extend along the second direction D2. The first electrode SD23 of the second transistor is connected to the first connection line through a first via hole and to the first region of the active pattern of the second transistor through a third via hole.

[0303] In an exemplary embodiment, the second electrode SD24 of the second transistor may have a shape of “┐.” The second electrode SD24 of the second transistor is connected to the second connection line through a second via hole and to the second region of the active pattern of the second transistor through a fourth via hole.

[0304] In an exemplary embodiment, the first electrode SD33 of the third transistor may be strip-shaped and extend at least partially along the second direction D2. The first electrode SD33 of the third transistor is connected to the first connection line through a first via hole and to the first region of the active pattern of the third transistor through a fifth via hole.

[0305] In an exemplary embodiment, the second electrode SD34 of the third transistor may have a shape of “┐.” The second electrode SD34 of the third transistor is connected to the second connection line through a second via hole and to the second region of the active pattern of the third transistor through a sixth via hole.

[0306] In an exemplary embodiment, the first electrode SD43 of the fourth transistor may be strip-shaped and extend at least partially along the second direction D2. The first electrode SD43 of the fourth transistor is connected to the first connection line through the first via hole and to the first region of the active pattern of the fourth transistor through the seventh via hole.

[0307] In an exemplary embodiment, the second electrode SD44 of the fourth transistor may be shaped like a zigzag line. The second electrode SD44 of the fourth transistor includes a first electrode connection portion SD441, a second electrode connection portion SD442, and a third electrode connection portion SD443. The first electrode connection portion SD441 and the third electrode connection portion SD443 extend along the second direction D2, while the second electrode connection portion SD442 extends along the first direction D1. The first electrode connection portion SD441 and the third electrode connection portion SD443 are located on opposite sides of the second electrode connection portion SD442. The first electrode connection portion SD441 is disposed at a right angle to the second electrode connection portion SD442, while the third electrode connection portion SD443 is disposed at a right angle to the second electrode connection portion SD442. The second electrode SD444 of the fourth transistor is connected to the second connection line via a second via hole and to the second region of the active pattern of the fourth transistor via an eighth via hole.

[0308] In an exemplary embodiment, the first electrode SD53 of the fifth transistor may be strip-shaped and extend at least partially along the second direction D2. The first electrode SD53 of the fifth transistor is connected to the first connection line through the first via hole and to the first region of the active pattern of the fifth transistor through the ninth via hole.

[0309] In an exemplary embodiment, the second electrode SD54 of the fifth transistor includes a fourth electrode connection portion SD541, a fifth electrode connection portion SD542, and a sixth electrode connection portion SD543. The fourth electrode connection portion SD541 and the sixth electrode connection portion SD543 extend along the second direction D2, and the fifth electrode connection portion SD542 extends along the first direction D1. The fourth electrode connection portion SD541 is located on a side of the fifth electrode connection portion SD542 away from the display area, and the sixth electrode connection portion SD543 is located on a side of the fifth electrode connection portion SD542 closer to the display area. The fourth electrode connection portion SD541 and the fifth electrode connection portion SD542 are arranged at right angles, and an end of the sixth electrode connection portion SD543 is connected to the middle of the fifth electrode connection portion SD542. The second electrode SD544 of the fifth transistor is connected to the second connection line via a second via hole and to the second region of the active pattern of the fifth transistor via a tenth via hole.

[0310] In an exemplary embodiment, the first electrode SD63 of the sixth transistor may be strip-shaped and extend at least partially along the second direction D2. The first electrode SD63 of the sixth transistor is connected to the first connection line through a first via hole and to the first region of the active pattern of the sixth transistor through an eleventh via hole.

[0311] In an exemplary embodiment, the second electrode SD64 of the sixth transistor may have a shape of “┐.” The second electrode SD64 of the sixth transistor is connected to the second connection line through the second via hole and to the second region of the active pattern of the sixth transistor through the twelfth via hole.

[0312] In an exemplary embodiment, the first electrode SD73 of the seventh transistor may be strip-shaped and extend at least partially along the second direction D2. The first electrode SD73 of the seventh transistor is connected to the first connection line through the first via hole and to the first region of the active pattern of the seventh transistor through the thirteenth via hole.

[0313] In an exemplary embodiment, the second electrode SD74 of the seventh transistor may be shaped like a triangle. The second electrode SD74 of the seventh transistor is connected to the second connection line through the second via hole and to the second region of the active pattern of the seventh transistor through the fourteenth via hole.

[0314] In an exemplary embodiment, the first electrode SD83 of the eighth transistor may be strip-shaped and extend at least partially along the second direction D2. The first electrode SD83 of the eighth transistor is connected to the first connection line through the first via hole and to the first region of the active pattern of the eighth transistor through the fifteenth via hole.

[0315] In an exemplary embodiment, the second electrode SD84 of the eighth transistor may be block-shaped and extend along the second direction D2. The second electrode SD84 of the eighth transistor is connected to the second connection line through the second via hole and to the second region of the active pattern of the eighth transistor through the sixteenth via hole.

[0316] In an exemplary embodiment, the first electrode SD93 of the ninth transistor may have a shape of “┘.” The first electrode SD93 of the ninth transistor is connected to the first connection line through the first via hole and to the first region of the active pattern of the ninth transistor through the seventeenth via hole.

[0317] In an exemplary embodiment, the second electrode SD94 of the ninth transistor may be block-shaped and extend along the second direction D2. The second electrode SD94 of the ninth transistor is connected to the second connection line through the second via hole and to the second region of the active pattern of the ninth transistor through the eighteenth via hole.

[0318] (5) Forming a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, coating a planar film, and patterning the third insulating film and the planar film through a patterning process to form a third insulating layer pattern and a planar layer pattern.

[0319] In exemplary embodiments, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0320] In an exemplary embodiment, the first conductive layer and the second conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0321] In exemplary embodiments, the first insulating layer, the second insulating layer, and the third insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0322] In an exemplary embodiment, the planar layer may be made of an organic material such as resin.

[0323] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0324] An anode conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the anode conductive film is patterned using a patterning process to form an anode conductive layer pattern arranged on the second flat layer. A pixel definition film is deposited on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. An organic light-emitting material is coated on the substrate on which the pixel definition layer pattern is formed, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. A cathode conductive film is deposited on the substrate on which the organic material layer pattern is formed, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0325] At this point, the light-emitting structure layer is prepared on the substrate.

[0326] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns. The plurality of anode patterns may include an anode of a first light-emitting device, an anode of a second light-emitting device, an anode of a third light-emitting device, and an anode of a fourth light-emitting device, wherein the anode of the first light-emitting device is located in a red sub-pixel emitting red light, the anode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the anode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the anode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0327] In an exemplary embodiment, the anode of the first light-emitting device and the anode of the second light-emitting device may be alternately arranged along the first direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device may be alternately arranged along the first direction. Alternatively, the anode of the first light-emitting device and the anode of the second light-emitting device may be alternately arranged along the second direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device may be alternately arranged along the second direction.

[0328] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0329] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0330] In an exemplary embodiment, the cathode conductive layer may include at least cathodes of a plurality of light emitting devices.

[0331] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0332] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0333] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0334] An embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0335] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0336] In an exemplary embodiment, the display device may be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0337] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0338] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0339] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising a display area and a non-display area surrounding at least one side of the display area, wherein the display area is provided with a pixel driving circuit arranged in an array, and the non-display area is provided with a gate driving circuit and a gate signal line group, wherein the gate signal line group comprises: A plurality of gate signal lines, wherein the gate driving circuit is electrically connected to the pixel driving circuit and the gate signal line group respectively; The strobe signal line extends along a first direction, the plurality of strobe signal lines are arranged along a second direction, and the first direction and the second direction intersect; The gate drive circuit includes: multiple shift registers, the shift registers include: a gating sub-circuit, the gating sub-circuit is electrically connected to some of the gating signal lines in the gating signal line group, the gating sub-circuit includes: multiple gating transistors, for any shift register, the multiple gating transistors in the gating sub-circuit are arranged along the first direction.

2. The display substrate according to claim 1, wherein: The shift register comprises: M strobe signal terminals, and the strobe signal line group comprises: 2M strobe signal lines; The mth selection signal terminal is electrically connected to the 2m-1th selection signal line or the 2mth selection signal line, and the signal of the 2m-1th selection signal line and the signal of the 2mth selection signal line are inverted signals to each other, 1≤m≤M.

3. The display substrate according to claim 1, wherein: The non-display area has a signal line area and a device area, the gate driving circuit is at least partially located in the device area, the signal line area includes: a first signal line area, a second signal line area and a third signal line area arranged in sequence along the display area, and the device area includes: a first device area, a second device area, a third device area and a fourth device area arranged in sequence along the display area; The first signal line area is located at a side of the first device area away from the display area, and the third signal line area is located at a side of the fourth device area close to the display area; The gating signal line group is located in the first signal line area, and the gating sub-circuit is located in the first device area.

4. The display substrate according to claim 3, wherein: The second signal line region is located between the first signal line region and the first device region, or between the first device region and the second device region.

5. The display substrate according to claim 3 or 4, wherein: The length of the first signal line area along the second direction is greater than the length of the second signal line area along the second direction, and the length of the third signal line area along the second direction is greater than the length of the second signal line area along the second direction.

6. The display substrate according to claim 3 or 4, wherein: The non-display area is also provided with a clock signal line group, and the gate driving circuit is electrically connected to the clock signal line group; The clock signal line group is located in the first signal line area and is located on a side of the strobe signal line group away from the display area.

7. The display substrate according to claim 3 or 4, wherein: The clock signal line group includes: a control clock signal line group and an output clock signal line group; The control clock signal line group includes: a plurality of control clock signal lines, the control clock signal lines extend along the first direction, and the plurality of control clock signal lines are arranged along the second direction; the output clock signal line group includes: a plurality of output clock signal lines, the output clock signal lines extend along the first direction, and the plurality of output clock signal lines are arranged along the second direction, and the line width of the output clock signal line is greater than the line width of the control clock signal line and the line width of the selection signal line; The shift register comprises: a plurality of control clock terminals and a plurality of output clock terminals, any one of the plurality of control clock terminals One of the plurality of output clock terminals is electrically connected to one of the control clock signal lines in the control clock signal line group, and any one of the plurality of output clock terminals is electrically connected to one of the output clock signal lines in the output clock signal line group; For any shift register, a plurality of control clock terminals are electrically connected to some signal lines in the control clock signal group, and a plurality of output clock terminals are electrically connected to some signal lines in the output clock signal line group; The output clock signal line group is located at a side of the control clock signal line group away from the display area.

8. The display substrate according to claim 3 or 4, wherein: The non-display area is also provided with a first high-level power line and a second high-level power line; The shift register comprises: a first high-level power supply terminal and a second high-level power supply terminal, and for any shift register, the first high-level power supply terminal is electrically connected to the first high-level power supply line, and the second high-level power supply terminal is electrically connected to the second high-level power supply line; The first high level power line and the second high level power line are located in the second signal line area; A line width of any one of the first high-level power line and the second high-level power line is greater than a line width of any signal line located in the first signal line area.

9. The display substrate according to claim 3 or 4, wherein: The non-display area is also provided with a first low-level power line and a second low-level power line; The shift register comprises: a first low-level power supply terminal and a second low-level power supply terminal, and for any shift register, the first low-level power supply terminal is electrically connected to the first low-level power supply line, and the second low-level power supply terminal is electrically connected to the second low-level power supply line; The first low-level power line and the second low-level power line are located in the third signal line area, and the first low-level power line is located on a side of the second low-level power line away from the display area; The line width of any one of the first low level power line and the second low level power line is greater than the line width of any signal line located in the first signal line area, and the line width of the first low level power line is smaller than the line width of the second low level power line.

10. The display substrate according to claim 3 or 4, wherein: The length of the second device region along the second direction is greater than the length of the first device region along the second direction, the length of the third device region along the second direction is greater than the length of the second device region along the second direction, and the length of the fourth device region along the second direction is greater than the length of the third device region along the second direction.

11. The display substrate according to claim 3 or 4, wherein: The shift register further includes: an input subcircuit, a node setting subcircuit and a preprocessing subcircuit; the multiple control clock terminals include: a first control clock terminal to a third control clock terminal; The node setting subcircuit is at least electrically connected to the second high-level power supply terminal, the second low-level power supply terminal, the second control clock terminal, the third control clock terminal, the first node and the third node respectively, and is configured to provide a signal from the second high-level power supply terminal or the second low-level power supply terminal to the first node under the control of the signal from the second control clock terminal, the third control clock terminal and the third node; The input subcircuit is at least electrically connected to the third control clock terminal, the third node and the fifth node respectively, and is configured to provide the signal of the third control clock terminal to the fifth node under the control of the signals of the third node and the third control clock terminal; The preprocessing subcircuit is at least respectively connected to the second node, the third node, the fourth node, the first high-level power supply terminal and the first control clock terminal, and is configured to provide the signal of the first control clock terminal to the fourth node and provide the signal of the fourth node to the first high-level power supply terminal under the control of the signal of the second node; The gating subcircuit is also electrically connected to the second control clock terminal and the second node respectively, and is configured to Under the control of the signal of the signal terminal, providing the signal of the second control clock terminal to the second node; The input sub-circuit, the node setting sub-circuit and the pre-processing sub-circuit are located in the second device region and arranged along the first direction, and the pre-processing sub-circuit is located between the input sub-circuit and the node setting sub-circuit.

12. The display substrate according to claim 11, wherein: The preprocessing subcircuit comprises: a plurality of preprocessing transistors and a preprocessing capacitor; The pre-processing capacitor is located at a side of the plurality of pre-processing transistors close to the node setting sub-circuit.

13. The display substrate according to claim 3 or 4, wherein: The shift register further comprises: a node separation subcircuit; The node separation subcircuit is electrically connected to the third control clock terminal, the first high-level power terminal, the second low-level power terminal, the first node, the fifth node, the sixth node, the seventh node, the eighth node and the ninth node respectively, and is configured to provide the signal of the fifth node to the sixth node to the ninth node respectively under the control of the signal of the third control clock terminal and the first node, or, under the control of the signal of the sixth node, provide the signal of the first high-level power terminal to the fifth node; The node separation subcircuit is located in the third device region.

14. The display substrate according to claim 3 or 4, wherein: The shift register further includes: an output subcircuit; The output subcircuit is at least electrically connected to a plurality of output clock terminals, a first low-level power terminal and a plurality of signal output terminals respectively, and is configured to output signals of the corresponding output clock terminals or the first low-level power terminal to the plurality of signal output terminals; The output sub-circuit is located in the fourth device region.

15. The display substrate according to claim 14, wherein: The output sub-circuit further includes: a plurality of output capacitors, which are arranged in an array along the first direction and the second direction.

16. The display substrate according to claim 3 or 4, wherein: The shift register further includes: a reset subcircuit and a noise reduction subcircuit, and the plurality of control clock terminals include: a first control clock terminal to a third control clock terminal; The reset subcircuit is at least electrically connected to the total reset signal terminal, the third node, the fourth node, the first high-level power terminal and the second low-level power terminal respectively, and is configured to provide the second low-level power terminal electrical connection to the third node, the fourth node and the first high-level power terminal under the control of the signal of the total reset signal terminal; The noise reduction subcircuit is at least electrically connected to the first node, the second node, the ninth node, the first control clock terminal, the second control clock terminal, and the second low-level power terminal, respectively, and is configured as a control line of a signal at the first control clock terminal, providing a signal at the second control clock terminal to the second node, and providing a signal at the second low-level power terminal to the first node under the control of a signal at the ninth node; The reset sub-circuit and the noise reduction sub-circuit are located in the second device area, and the reset sub-circuit and the pre-processing sub-circuit are arranged along the second direction.

17. The display substrate according to claim 16, wherein: The non-display area is also provided with a reset signal line; The total reset signal terminal of the shift register is electrically connected to the reset signal line, and the reset signal line is located in the first signal line area.

18. The display substrate according to claim 3 or 4, wherein: The gate driving circuit comprises: a plurality of shift register groups, the shift register groups comprise N1 shift register units, the shift register units comprise N2 shift registers, N1, N2≥2; The part of the selection signal lines connected to the multiple selection signal terminals of the shift register is called a selection signal line unit; the selection signal line units connected to any two shift registers in the same shift register unit include the selection signal lines. The signal lines are the same, at least one of the selection signal lines included in the selection signal line unit connected to any two shift register units located in the same shift register group is different; the selection signal lines included in the selection signal line unit connected to the n1th shift register unit located in different shift register groups are the same, 1≤n1≤N1.

19. The display substrate according to claim 18, wherein: The part of the control clock signal lines connected to the multiple control clock terminals of the shift register is called a control clock signal line unit, and the part of the output clock signal lines connected to the multiple output clock terminals of the shift register is called an output clock signal line unit; At least one of the control clock signal lines included in the control clock signal line unit connected to any two shift registers located in the same shift register unit is different, and at least one of the output clock signal lines included in the output clock signal line unit connected to any two shift registers located in the same shift register unit is different; the control clock signal lines included in the control clock signal line unit connected to the n2th shift register located in different shift register units are the same, and the output clock signal lines included in the output clock signal line unit connected to the n2th shift register located in different shift register units are the same, 1≤n2≤N2.

20. The display substrate according to claim 1, comprising: A substrate and a driving structure layer arranged on the substrate, wherein the shift register comprises: a plurality of transistors; The driving structure layer comprises: a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a second conductive layer stacked on the substrate; The semiconductor layer includes at least: an active pattern of a plurality of transistors in the shift register; The second conductive layer at least includes: gate electrodes, a first electrode, and a second electrode of a plurality of transistors in the shift register.

21. The display substrate according to claim 20, further comprising: A selection signal line, a control clock signal line, an output clock signal line, the first high level power line, the second high level power line, the first low level power line and the second low level power line, wherein any one of the selection signal line, the control clock signal line, the output clock signal line, the first high level power line, the second high level power line, the first low level power line and the second low level power line is a single-layer structure located in the first conductive layer, or is a double-layer structure and is located in the first conductive layer and the second conductive layer.

22. The display substrate according to claim 20, wherein: The non-display area is further provided with a first connecting line and a second connecting line, and the first connecting line and the second connecting line are located in the first conductive layer; The first electrodes of all the gating transistors in the same gating subcircuit are electrically connected to the first connecting line, and the second electrodes of the plurality of gating transistors in the same gating subcircuit are electrically connected to the second connecting line; The gate electrode, the first electrode and the second electrode in any one of the gate transistors at least partially extend along the second direction, and the first connection line and the second connection line extend along the first direction.

23. The display substrate according to claim 20, wherein: The non-display area is also provided with a plurality of control clock connection lines and a plurality of control clock electrostatic release circuits; the plurality of control clock connection lines correspond one-to-one to the plurality of control clock signal lines, and the plurality of control clock connection lines correspond one-to-one to the plurality of control clock electrostatic release circuits; The control clock connection lines are electrically connected to corresponding control clock signal lines and corresponding control clock electrostatic release circuits respectively.

24. The display substrate according to claim 23, wherein: The control clock connection line includes: a first control clock connection portion extending along the second direction and a second control clock connection portion extending along the first direction; For any control clock connection line, the first control clock connection part is electrically connected to the corresponding control clock signal line and the second control clock connection part respectively, and the second control clock connection part is electrically connected to the corresponding control clock electrostatic release circuit; The first control clock connection portion is located in the second conductive layer, and the second control clock connection portion is located in the first conductive layer.

25. The display substrate according to claim 20, wherein: The non-display area is also provided with a plurality of output clock connection lines and a plurality of output clock electrostatic release circuits; the plurality of output clock connection lines correspond one-to-one to the plurality of output clock signal lines, and the plurality of output clock connection lines correspond one-to-one to the plurality of output clock electrostatic release circuits; The output clock connection lines are electrically connected to corresponding output clock signal lines and corresponding output clock electrostatic discharge circuits respectively.

26. The display substrate according to claim 25, wherein: The output clock connection line comprises: a first output clock connection portion extending along the second direction and a second output clock connection portion extending along the first direction; For any output clock connection line, the first output clock connection part is electrically connected to the corresponding output clock signal line and the second output clock connection part respectively, and the second output clock connection part is electrically connected to the corresponding output clock electrostatic discharge circuit; The first output clock connection portion is located in the second conductive layer, and the second output clock connection portion is located in the first conductive layer.

27. The display substrate according to claim 20, wherein: The non-display area is also provided with four power connection lines and four power electrostatic discharge circuits. The first power connection line is electrically connected to the first high-level power line and the first power electrostatic discharge circuit respectively; The second power connection line is electrically connected to the second high-level power line and the second power electrostatic discharge circuit respectively; The third power connection line is electrically connected to the first low-level power line and the third power electrostatic discharge circuit respectively; The fourth power connection line is electrically connected to the second low-level power line and the fourth power electrostatic release circuit respectively.

28. The display substrate according to claim 27, wherein: The power connection line comprises: a first power connection portion extending along the second direction and a second power connection portion extending along the first direction; For any power connection line, the first power connection part is electrically connected to the connected power line and the second power connection part respectively, and the second power connection part is electrically connected to the connected power electrostatic discharge circuit; The first power connection portion is located on the second conductive layer, and the second power connection portion is located on the first conductive layer.

29. The display substrate according to claim 2, wherein: The distance between the first signal line far from the boundary of the display area and the second signal line close to the boundary of the display area is about 3400 micrometers to 3450 micrometers; The first signal line is a signal line in the first signal line area that is farthest from the border of the display area, and the second signal line is a signal line in the third signal line area that is closest to the border of the display area.

30. The display substrate according to claim 1, wherein: The signals of at least two strobe signal lines are mutually inverted signals in a partial period of time.

31. A display device comprising: A display substrate as claimed in any one of claims 1 to 30.

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