High-precision current detection circuit for intelligent power high-side switch chip

Abstract

The invention belongs to the field of analog integrated circuit design, and particularly relates to a high-precision current detection circuit for an intelligent power high-side switch chip, which comprises a first-stage current sampling circuit, a second-stage current sampling circuit and a current mirror circuit, the first-stage current sampling circuit is of a negative feedback loop structure composed of an output resistor Rout, a main power tube MP, a detection transistor MS, an amplifier A1 and an MOS tube M1. The second-stage current sampling circuit is composed of a resistor R0, a resistor R1, an amplifier A2 and an MOS tube M2. According to the current mirror circuit, a cascode current mirror structure is formed by an MOS tube M3, an MOS tube M4, an MOS tube M5 and an MOS tube M6. According to the circuit structure, high-precision current detection can be carried out without introducing a sampling resistor, and extra power loss is avoided.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuit design, and in particular relates to a high-precision current detection circuit for an intelligent power high-side switch chip. Background Art

[0002] Smart power switches tend to replace traditional relays in an increasing range of applications. The main advantage of integrated solutions is that the drive and protection functions can be integrated with the actual switch, making the control of power devices easier and improving the robustness of the application. A key function is to detect the load current situation. Many topologies have been implemented for measuring load current and protecting active devices by closing the switch or limiting the current. The accuracy and complexity of the circuit vary with the application requirements. Load diagnostics usually require higher sensing accuracy.

[0003] Smart high-side power chips will experience load fluctuations during normal operation, which may cause excessive output current. It is unsafe for chips and devices to work under high current for a long time, so this situation should be avoided. Traditional current detection such as Figure 1 As shown in Figure 1, (a) a sampling resistor is used for detection, and a sampling resistor R is connected between the power tube source and the output node. sense In this way, the output current signal of the power tube can be converted into a voltage signal, and the current magnitude can be determined by detecting the sampled voltage value; (b) This method uses the fact that the current of the power tube working in the linear region is positively correlated with the drain-source voltage, and detects the drain-source voltage V of the power tube. DS Determine whether there is overcurrent; (c) The detection tube current in the detection tube detection technology is small, which reduces power consumption and improves power utilization efficiency. However, the output end of the detection tube MS is connected in series with a small resistor and then connected in parallel with the power tube MP, which will cause the source potential of the two to be different, thereby affecting the detection accuracy of the circuit. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a high-precision current detection circuit for an intelligent power high-side switch chip, comprising: a first-stage current sampling circuit, a second-stage current sampling circuit and a current mirror circuit;

[0005] The first-stage current sampling circuit is composed of an output resistor Rout, a main power tube MP, a detection transistor MS, an amplifier A1 and a MOS tube M1 to form a negative feedback loop structure;

[0006] The second-stage current sampling circuit is composed of resistors R0, R1, amplifier A2 and MOS tube M2;

[0007] The current mirror circuit is composed of MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6 to form a common source and common gate current mirror structure;

[0008] The gates of the main power transistor MP and the detection transistor MS are connected to the gate drive signal, and the drains thereof are connected to the power supply voltage AVDD;

[0009] The source of the main power tube MP is connected to one end of the output resistor Rout and the positive input end of the amplifier A1;

[0010] The source of the detection transistor MS is connected to the reverse input terminal of the amplifier A1 and the drain of the NMOS tube M1;

[0011] The output end of the amplifier A1 is connected to the gate of the NMOS tube M1;

[0012] The source of the NMOS tube M1 is connected to one end of the resistor R0 of the second-stage current sampling circuit and the positive input end of the amplifier A2;

[0013] The reverse input terminal of the amplifier A2 is connected to one end of the resistor R1 and the source of the NMOS tube M2;

[0014] The output end of the amplifier A2 is connected to the gate of the NMOS tube M2;

[0015] The other ends of the resistors R0 and R1 are connected to the output resistor Rout of the first-stage current sampling circuit and to the ground end GND;

[0016] The gate and drain of the PMOS tube M3 in the current mirror circuit are connected, and are connected to the gate of the PMOS tube M6 and the drain of the PMOS tube M2 of the second-stage current sampling circuit;

[0017] The gate and drain of the PMOS tube M4 are connected, and are connected to the gate of the PMOS tube M5 and the source of the PMOS tube M3;

[0018] The sources of the PMOS tube M4 and the PMOS tube M5 are connected to the power supply voltage AVDD, and the drain of the PMOS tube M5 is connected to the source of the PMOS tube M6;

[0019] The drain of the PMOS tube M6 serves as the output end of the overall circuit to output the detection current I s .

[0020] Preferably, the amplifier A1 in the first-stage current sampling circuit and the amplifier A2 in the second-stage current sampling circuit adopt continuous auto-zero amplifiers with a Ping-Pong structure to reduce the offset voltage Vos at the amplifier input terminal and improve the accuracy of current sampling.

[0021] Furthermore, the continuous auto-zero amplifier of the Ping-Pong structure consists of two groups of main amplifiers and auxiliary amplifiers. When one group is performing signal processing, the other group is auto-zeroing its own initial offset voltage, thereby ensuring continuous current sampling during the entire current detection cycle.

[0022] Beneficial effects of the present invention:

[0023] The present invention can improve the range of large current detection by introducing a second-level current sampling circuit and a current mirror circuit;

[0024] The circuit structure of the present invention can perform high-precision current detection without introducing a sampling resistor, thereby avoiding additional power loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of a conventional current detection circuit;

[0026] Figure 2 A schematic diagram of a high-precision current detection circuit for an intelligent power high-side switch chip of the present invention;

[0027] Figure 3 It is a structural schematic diagram of a low offset amplifier of a Ping-Pong structure of the present invention;

[0028] Figure 4 A schematic diagram of an offset voltage simulation of a Ping-Pong amplifier of the present invention;

[0029] Figure 5 It is a current detection ratio diagram of the circuit of the present invention under different loads. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] A high-precision current detection circuit for intelligent power high-side switch chips, such as Figure 2 As shown, it includes: a first-stage current sampling circuit, a second-stage current sampling circuit and a current mirror circuit;

[0032] The first-stage current sampling circuit is composed of an output resistor Rout, a main power tube MP, a detection transistor MS, an amplifier A1 and a MOS tube M1 to form a negative feedback loop structure;

[0033] The second-stage current sampling circuit is composed of resistors R0, R1, amplifier A2 and MOS tube M2;

[0034] The current mirror circuit is composed of MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6 to form a common source and common gate current mirror structure;

[0035] The gates of the main power transistor MP and the detection transistor MS are connected to the gate drive signal, and the drains thereof are connected to the power supply voltage AVDD;

[0036] The source of the main power tube MP is connected to one end of the output resistor Rout and the positive input end of the amplifier A1;

[0037] The source of the detection transistor MS is connected to the reverse input terminal of the amplifier A1 and the drain of the NMOS tube M1;

[0038] The output end of the amplifier A1 is connected to the gate of the NMOS tube M1;

[0039] The source of the NMOS tube M1 is connected to one end of the resistor R0 of the second-stage current sampling circuit and the positive input end of the amplifier A2;

[0040] The reverse input terminal of the amplifier A2 is connected to one end of the resistor R1 and the source of the NMOS tube M2;

[0041] The output end of the amplifier A2 is connected to the gate of the NMOS tube M2;

[0042] The other ends of the resistors R0 and R1 are connected to the output resistor Rout of the first-stage current sampling circuit and to the ground end GND;

[0043] The gate and drain of the PMOS tube M3 in the current mirror circuit are connected, and are connected to the gate of the PMOS tube M6 and the drain of the PMOS tube M2 of the second-stage current sampling circuit;

[0044] The gate and drain of the PMOS tube M4 are connected, and are connected to the gate of the PMOS tube M5 and the source of the PMOS tube M3;

[0045] The sources of the PMOS tube M4 and the PMOS tube M5 are connected to the power supply voltage AVDD, and the drain of the PMOS tube M5 is connected to the source of the PMOS tube M6;

[0046] The drain of the PMOS tube M6 serves as the output end of the overall circuit to output the detection current I s .

[0047] Preferably, the amplifier A1 in the first-stage current sampling circuit and the amplifier A2 in the second-stage current sampling circuit adopt a continuous auto-zero amplifier with a Ping-Pong structure to reduce the offset voltage Vos at the amplifier input end and improve the accuracy of current sampling. Figure 3 As shown, VIN+ is connected to the negative input terminal of the main input terminals of amplifiers A1 and A2 and one end of switches S1 and S7 is connected, the other end of switch S7 is connected to switch S8 and the positive input terminal of the main input terminal of amplifier A2, VIN- is connected to the other end of switch S8 and one end of switch S2, the other end of switch S1 is connected to the positive input terminal of the main input terminal of amplifier A1 and the other end of switch S2, the positive input terminal of the auxiliary input terminal of amplifier A1 is connected to the upper plate of capacitor C1 and one end of switch S3, the other end of switch S3 is connected to the negative input terminal and output terminal of amplifier A3, the lower plates of C1, C2, and C3 are all connected to ground, the upper plate of C2 is connected to one end of switch S4, the other end of switch S4 is connected to the output terminal of the main amplifier A1 and one end of switch S6, and the upper plate of C3 is connected to the positive input terminal of amplifier A3 The positive input terminal of the amplifier A5 is connected to one end of the switch S5, the other end of the switch S6 is connected to the output terminal OUT, the positive input terminal of the amplifier A5 is connected to one end of the switch S12, the negative input terminal of the amplifier A5 is connected to the upper plate of the capacitor C4, the other end of the switch S5 is connected to one end of S11, the lower plate of C4 is connected to the ground, the positive input terminal of the auxiliary input terminal of the amplifier A2 is connected to the upper plate of the capacitor C5 and one end of the switch S9, the other end of the switch S9 is connected to the negative input terminal of the amplifier A4 and its output terminal, the positive input terminal of the amplifier A4 is connected to the upper plate of the capacitor C7 and the other end of the switch S11, the lower plates of the capacitors C5, C6, and C7 are connected to the ground, the negative input terminal of the auxiliary input terminal of the amplifier A2 is connected to the upper plate of the capacitor C6 and one end of the switch S10, and the other end of the switch S10 is connected to the output terminal of the amplifier A2 and the other end of the switch S12.

[0048] Furthermore, the continuous auto-zero amplifier of the Ping-Pong structure consists of two groups of main amplifiers and auxiliary amplifiers. When one group is performing signal processing, the other group is auto-zeroing its own initial offset voltage, thereby ensuring continuous current sampling during the entire current detection cycle.

[0049] Depend on Figure 2It can be seen that in the first-stage current sampling circuit, MP is the main power tube, MS is the detection transistor, and the NMOS tubes M1 and A1 together form a negative feedback loop, so that the source voltages of MS and MP are approximately equal, that is: the voltages of the three terminals of MP and MS are equal, then the ratio of the currents flowing through them is equal to their width-to-length ratio. Because the large current flowing through the load cannot be directly detected, this circuit is required to reduce the load current proportionally. The following formula is the derivation process of the current ratio, according to the current equation of the MOS tube working in the linear region:

[0050]

[0051] Among them, I out is the load current, I sense is the current flowing through the detection tube MS, k1 and k2 are process-related parameters, and is the ratio of the width to length of MP and MS, and V GS is the voltage difference between the gate and source of MP, V DS is the voltage difference between the drain and source of MP, V TH1 , V TH2 is the threshold voltage of the transistor, and ΔV1 is the offset voltage of the amplifier A1. When k1 and k2 are approximately equal, V TH1 , V TH2 When they are also approximately equal, dividing (1) by (2) yields the current ratio of MP to MS:

[0052]

[0053] Since the transistor V GS is much larger than ΔV1, and V DS For the higher-order terms, only the first-order case is considered, and equation (3) is simplified to:

[0054]

[0055] From formula (4), it can be concluded that the accuracy of the first-stage current sampling is determined by the offset voltage ΔV1 of the amplifier A1. Similarly, the amplifier A2 in the second-stage current sampling circuit is also in a negative feedback state, and it can be obtained that:

[0056] I sense *R0=I R1 *R1-ΔV2 (5)

[0057] I R1 is the current flowing through R1, and ΔV2 is the offset voltage of amplifier A2. PMOS tubes M3, M4, M5 and M6 transistors form a common source and common gate current mirror structure, mirroring the current flowing through R1 in the second-level current sampling structure, and mirroring the current flowing through R1 to IS The cascode current mirror structure can improve the accuracy of current replication and avoid I S The current replication is inaccurate due to the terminal voltage change. are the ratios of the transistor sizes of PMOS tubes M3, M4, M5, and M6, I S The output current of the terminal can be obtained by current mirroring:

[0058] I R1 *N2=I S (6)

[0059] Substituting (6) into (5), we get:

[0060]

[0061] In summary, we can know that:

[0062]

[0063] Among them, N1, N2, R1 are fixed values. It is very small and can be ignored, so the current detection ratio can be obtained by simplifying (8):

[0064]

[0065] The N1 of this design is 5370, which can reduce the influence of the detection tube on the power tube density, and through reasonable setting (R0 is relatively small, which can expand the current detection range), The ratio of so

[0066] The introduction of the second-stage current sampling circuit and the current mirror circuit can enhance the ability to detect large load currents. Because the detection current needs to be sent to the external MCU, it needs to be converted into voltage through a resistor for MCU collection. If it is directly output through the first-stage current sampling circuit, it will increase Figure 2 The source voltage of M1 in the circuit results in insufficient large current detection capability.

[0067] exist Figure 3 The continuous auto-zero amplifier of the Ping-Pong structure shown is divided into two groups of main amplifiers and auxiliary amplifiers. When one group is performing signal processing, the other group is auto-zeroing its own initial offset voltage, thereby ensuring continuous current sampling during the entire current detection cycle.

[0068] The square wave signals of the control switches S1, S5, S6, S8, S9, and S10 are consistent. When these switches are closed and the other switches are in the open state, A1 is connected to the signal path for signal processing, and A2 is disconnected from the signal path to zero its own offset voltage. When the next cycle comes, that is, the control switches S1, S5, S6, S8, S9, and S10 are turned off, and the other switches are closed, A2 is connected to the signal path for signal processing, and A1 is disconnected from the signal path. Because capacitors C5 and C6 store the offset voltage corrected in the previous stage, the input offset voltage in this stage is compensated very small. When the next cycle comes, C1 and C2 store the offset voltage in the previous stage, and the input offset voltage in this stage is also compensated, thereby ensuring that the input offset voltage is reduced throughout the current sampling cycle.

[0069] pass Figure 4 It can be seen that the average input offset voltage of the Ping-Pong structure amplifier is 24.7μV, while the offset voltage of the amplifier in the traditional CMOS structure is 10-20mV, which means that the use of this structure significantly reduces the impact of the offset voltage and improves the accuracy of current detection.

[0070] Figure 5 The current detection ratio diagram under different loads can be seen from the figure. The structure of eliminating offset voltage adopted in this patent is significantly improved than that without this structure. In particular, in this application, the load current I out When it is 998.25mA, I S The output current is 187μA, and the current detection accuracy is as high as 99.41%.

[0071] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-precision current detection circuit for an intelligent power high-side switch chip, characterized in that: include: A first-stage current sampling circuit, a second-stage current sampling circuit and a current mirror circuit; The first-stage current sampling circuit is composed of an output resistor Rout, a main power tube MP, a detection transistor MS, an amplifier A1 and a MOS tube M1 to form a negative feedback loop structure; The second-stage current sampling circuit is composed of resistors R0, R1, amplifier A2 and MOS tube M2; The current mirror circuit is composed of MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6 to form a common source and common gate current mirror structure; The gates of the main power transistor MP and the detection transistor MS are connected to the gate drive signal, and the drains thereof are connected to the power supply voltage AVDD; The source of the main power tube MP is connected to one end of the output resistor Rout and the positive input end of the amplifier A1; The source of the detection transistor MS is connected to the reverse input terminal of the amplifier A1 and the drain of the NMOS tube M1; The output end of the amplifier A1 is connected to the gate of the NMOS tube M1; The source of the NMOS tube M1 is connected to one end of the resistor R0 of the second-stage current sampling circuit and the positive input end of the amplifier A2; The reverse input terminal of the amplifier A2 is connected to one end of the resistor R1 and the source of the NMOS tube M2; The output end of the amplifier A2 is connected to the gate of the NMOS tube M2; The other ends of the resistors R0 and R1 are connected to the output resistor Rout of the first-stage current sampling circuit and to the ground end GND; The gate and drain of the PMOS tube M3 in the current mirror circuit are connected, and are connected to the gate of the PMOS tube M6 and the drain of the PMOS tube M2 of the second-stage current sampling circuit; The gate and drain of the PMOS tube M4 are connected, and are connected to the gate of the PMOS tube M5 and the source of the PMOS tube M3; The sources of the PMOS tube M4 and the PMOS tube M5 are connected to the power supply voltage AVDD, and the drain of the PMOS tube M5 is connected to the source of the PMOS tube M6; The drain of the PMOS tube M6 serves as the output end of the overall circuit to output the detection current I s .

2. The high-precision current detection circuit for an intelligent power high-side switch chip according to claim 1, characterized in that: The amplifier A1 in the first-stage current sampling circuit and the amplifier A2 in the second-stage current sampling circuit adopt continuous auto-zero amplifiers with a Ping-Pong structure to reduce the offset voltage Vos at the amplifier input terminal and improve the accuracy of current sampling.

3. The high-precision current detection circuit for an intelligent power high-side switch chip according to claim 2, characterized in that: The continuous auto-zero amplifier of the Ping-Pong structure consists of two groups of main amplifiers and auxiliary amplifiers. When one group is performing signal processing, the other group is auto-zeroing its own initial offset voltage, thereby ensuring continuous current sampling during the entire current detection cycle.

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