Data write method and memory controller

Abstract

The present application provides a data writing method and a memory controller, which are suitable for a rewritable non-volatile memory module having a plurality of storage units. The method comprises the following steps: first, obtaining original data from a host system. Then, performing a plurality of randomization operations on the original data to obtain a plurality of write data. Next, performing a randomization verification operation on each write data based on a plurality of directions of a three-dimensional circuit architecture of the rewritable non-volatile memory module to obtain a target write data in the plurality of write data, wherein the quality of the randomization of the target write data is determined to be qualified. Finally, storing the target write data to a plurality of target storage units in the plurality of storage units. Through the multiple randomization operations and verification processes, the present application effectively improves the randomness and reliability of data storage, thereby enhancing the overall performance and data security of the storage system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, and more specifically, to a data writing method for a rewritable non-volatile memory module and a memory controller using the method. Background Technology

[0002] With the rapid development of information technology, non-volatile storage devices are increasingly widely used in various electronic products. In particular, 3D NAND flash memory, with its high storage density, low cost, and excellent performance, has become the mainstream non-volatile storage technology. However, as storage density continues to increase, data reliability and interference between storage cells are becoming increasingly prominent issues.

[0003] To improve data storage reliability and reduce inter-cell interference, data randomization technology is widely used in NAND flash memory. Traditional data randomization methods typically employ a single randomization algorithm, such as a simple XOR operation or a fixed permutation table. While this method improves data distribution to some extent, its effectiveness is often unsatisfactory when faced with increasingly complex three-dimensional NAND flash memory structures.

[0004] Furthermore, existing technologies typically lack effective verification mechanisms for randomization results. Writing data directly without verifying the quality of randomization may result in uneven distribution of certain data patterns within the memory, impacting storage performance and reliability. Particularly in high-density storage scenarios, improper data distribution can lead to read and write interference, ultimately shortening the lifespan of the storage device. Summary of the Invention

[0005] The purpose of this invention is to solve the above-mentioned problems, and to perform a variety of randomization operations and effectively verify the randomization quality, so as to ensure that the data written to the memory has good random distribution characteristics, thereby improving the reliability and performance of the storage.

[0006] One or more embodiments of the present invention provide a data writing method for a rewritable non-volatile memory module having multiple storage cells. The method includes: acquiring raw data from a host system; performing multiple randomization operations on the raw data to obtain multiple write data; performing randomization verification operations on each write data based on multiple directions of a three-dimensional circuit architecture of the rewritable non-volatile memory module to obtain target write data among the multiple write data, wherein the randomization quality of the target write data is determined to be acceptable; and storing the target write data into multiple target storage cells among the multiple storage cells.

[0007] In one or more embodiments of the present invention, each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: an XOR operation, which performs an XOR operation on the original data with a predefined plurality of different random sequences; a shift operation, which performs different cyclic shifts or logical shifts on the original data; a permutation operation, which changes the order of bits in the original data according to a predefined plurality of permutation tables; a dynamic random seed operation, which generates a plurality of different random seeds based on system time, data address or other system variables, and uses the plurality of random seeds and the original data to generate the plurality of write data; and a grouping operation, which divides the original data into a plurality of sub-blocks and applies different XOR operations, shift operations, permutation operations and dynamic random seed operations to the plurality of sub-blocks.

[0008] In one or more embodiments of the present invention, the step of performing the randomization verification operation on each written data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module includes: obtaining M bit value groups corresponding to a first direction among the multiple directions of the written data, wherein the multiple bit values ​​in each bit value group correspond to multiple storage cells in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of N bit states, where N is 2X, and X is the number of bits that each storage cell can store; obtaining the proportion of N states corresponding to the N bit states for each bit value group according to the multiple bit values ​​of each bit value group; and obtaining the quality of the randomization of the written data corresponding to the first direction according to the proportion of the N states.

[0009] In one or more embodiments of the present invention, the step of performing the randomization verification operation on each written data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module further includes: obtaining a reference proportion value based on the N bit states; and obtaining the quality of the randomization of the written data corresponding to the first direction according to the N state proportions and the reference proportion value.

[0010] In one or more embodiments of the present invention, the step of performing the randomization verification operation on each written data according to the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module further includes: obtaining N deviation values ​​between the N state proportions of each bit value group and the reference proportion value; taking the largest of the M deviation values ​​corresponding to the same bit state as the maximum deviation value corresponding to the same bit state according to the M deviation values ​​of the M bit value groups, thereby obtaining N maximum deviation values ​​corresponding to the N bit states; if all N maximum deviation values ​​are not greater than a preset threshold, determining that the quality of the randomization of the written data corresponding to the first direction is qualified; if one of the N maximum deviation values ​​is greater than the preset threshold, determining that the quality of the randomization of the written data corresponding to the first direction is unqualified.

[0011] In one or more embodiments of the present invention, the plurality of directions includes the first direction, the second direction, and the third direction. Based on the plurality of directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each piece of written data further includes: obtaining P sets of bit values ​​corresponding to the second direction of the written data and N maximum deviation values ​​of the P sets of bit values ​​corresponding to the N bit states, to obtain the quality of the randomization of the written data corresponding to the second direction; obtaining Q sets of bit values ​​corresponding to the third direction of the written data and N maximum deviation values ​​of the Q sets of bit values ​​corresponding to the N bit states, to obtain the quality of the randomization of the written data corresponding to the third direction; and if the quality of the randomization of the written data corresponding to the first direction, the second direction, and the third direction is all qualified, determining that the quality of the randomization of the written data is qualified.

[0012] In one or more embodiments of the present invention, after determining that the quality of the randomization of the written data corresponding to the first direction is unqualified, the method further includes: obtaining one or more abnormal maximum deviation values ​​among the N maximum deviation values ​​that are greater than the preset threshold and one or more abnormal bit states among the N bit states corresponding to the one or more abnormal maximum deviation values; and recording the first direction and the one or more abnormal bit states corresponding to the first direction.

[0013] In one or more embodiments of the present invention, if the quality of the randomization of the plurality of written data is unqualified, the method further includes: adjusting the plurality of randomization operations according to the one or more abnormal bit states and their corresponding directions to regenerate new plurality of written data; and performing the randomization verification operation again on each new written data to attempt to obtain the target written data, and then storing the target written data in the plurality of target storage units.

[0014] One or more embodiments of the present invention provide a memory controller suitable for a storage device configured with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of memory cells; and a processor electrically connected to the memory interface control circuit. The processor is configured to: acquire raw data from the host system; perform a plurality of randomization operations on the raw data to acquire a plurality of write data; perform a randomization verification operation on each write data based on a plurality of directions of a three-dimensional circuit architecture of the rewritable non-volatile memory module to acquire target write data among the plurality of write data, wherein the randomization quality of the target write data is determined to be acceptable; and store the target write data into a plurality of target memory cells among the plurality of memory cells.

[0015] Based on the above, the data writing method and its randomized verification operation proposed in this invention have significant technical advantages in three-dimensional non-volatile memory. By performing multiple randomization operations on the written data and executing the verification process in multiple directions based on the three-dimensional circuit architecture, this method can effectively improve the uniformity of data distribution in the memory. Attached Figure Description

[0016] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0017] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention;

[0018] Figure 2 This is a flowchart illustrating a data writing method according to an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram illustrating the randomization operation according to an embodiment of the present invention;

[0020] Figure 4This is a schematic diagram of the three-dimensional circuit architecture of multiple memory cells of a rewritable non-volatile memory module according to an embodiment of the present invention.

[0021] Figure 5 This is a flowchart illustrating the randomization verification operation according to an embodiment of the present invention.

[0022] Explanation of icon numbers

[0023] 10: Host System

[0024] 20: Storage device

[0025] 211: First Processor

[0026] 110: Second Processor

[0027] 120: Host memory

[0028] 130: Data transmission interface circuit

[0029] 210: Memory controller

[0030] 212: Data Management Circuit

[0031] 213: Memory Interface Control Circuit

[0032] 214: Buffer memory

[0033] 220: Rewritable Non-volatile Memory Module

[0034] 230: Connection interface circuit

[0035] S210~S240: Flowchart of memory testing method

[0036] OD1, OD2: Raw data

[0037] WD1~WD4: Write data

[0038] A31~A34: Arrows

[0039] WL0~WL3: Word lines

[0040] BL0~BL2: Bit lines

[0041] CSTR: Unit string

[0042] SL0~SL2: Serial cable

[0043] SSL: Source Selection Line

[0044] GSL: Grounding Selection Line

[0045] CSL: Common Source Line

[0046] MCT: Storage Cell Transistor

[0047] SST: Source Select Transistor

[0048] GST: Ground Select Transistor

[0049] S510~S580: Procedure steps for randomization verification Detailed Implementation

[0050] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0051] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10. In this embodiment, the raw data is, for example, user data transmitted by the host system 10 to the storage device 20, or data that has not yet undergone randomization.

[0052] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0053] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0054] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0055] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0056] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0057] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0058] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0059] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed during the operation of the storage device 20 to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can also be executed to perform data writing operations, randomization verification operations, or randomization operations to implement the data writing method provided by this invention. The control instructions / program codes corresponding to the data writing method can also be implemented as hardware circuit units to implement the data writing method provided by this invention.

[0060] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and the present invention is not limited thereto.

[0061] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0062] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation according to a write instruction from the host system 10). Another example is reading data from one or more physical units of the rewritable non-volatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213 and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0063] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform write (also known as programming), read, or erase operations on the rewritable non-volatile memory module 220.

[0064] Furthermore, data to be written to the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0065] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the rewritable non-volatile memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0066] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, and various information or data related to randomization operations and randomization verification operations) so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214. In one embodiment, the memory controller 210 may establish one or more write mapping tables within the buffer memory 214 to indicate the target entity address for writing valid data. It should be noted that in other embodiments, the buffer memory 214 may also be configured outside the memory controller 210. Alternatively, the buffer memory 214 may be configured both inside and outside the memory controller 210.

[0067] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store user data sent by the host system 10.

[0068] In this embodiment, each memory die (chip) in the rewritable non-volatile memory module 220 has multiple planes, and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple memory groups (also called physical bytes or bytes), and each memory group corresponds to a physical address. The physical address is used to record the physical location of the data stored in the memory group. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0069] Figure 2 This is a flowchart illustrating a data writing method according to an embodiment of the present invention.

[0070] Please refer to Figure 2 In step S210, the memory controller 210 (processor 211) obtains raw data from the host system 10. Then, in step S220, the processor 211 performs multiple randomization operations on the raw data to obtain multiple write data.

[0071] In one embodiment, the processor 211 performs a randomization operation on the original data to obtain write data. The randomization operation alters the distribution pattern of the first and second bit values ​​in the original data, causing the arrangement of the first and second bit values ​​in the write data to exhibit a random distribution characteristic. The first and second bit values ​​correspond to "0" and "1" in binary data, respectively. After performing the randomization operation, the processor 211 stores the obtained corresponding write data in a buffer memory 214.

[0072] Figure 3 This is a schematic diagram illustrating a randomization operation according to an embodiment of the present invention. For example, the randomization operation of the present invention can be further illustrated by a specific example. Figure 3 As shown in the figure, this illustrates the process of randomizing the original data. In this example, consider two sets of original data, OD1 and OD2, each containing 8 bits.

[0073] OD1 consists of eight consecutive "1"s (11111111), while OD2 consists of eight consecutive "0"s (00000000). These two sets of data represent a non-random distribution under extreme conditions, where the distribution of the first bit value ("0") and the second bit value ("1") is highly concentrated. The original data is, for example, user data that the host system 10 wants to store in the storage device 20.

[0074] By performing a randomization operation, the corresponding write data WD1, WD2, WD3, and WD4 were obtained. Specifically:

[0075] After the (first) randomization operation A31, OD1 generates WD1 (01010101).

[0076] After OD1 undergoes another (second) randomization operation A32, WD2 (10101010) is generated.

[0077] After undergoing the (third) randomization operation A33, OD2 generates WD3 (10101010).

[0078] After undergoing another (fourth) randomization operation A34, OD2 generates WD4 (01010101).

[0079] The results show that regardless of whether the original data is all "1"s or all "0"s, the written data after randomization exhibits a pattern of evenly alternating "0"s and "1"s. This pattern significantly alters the original distribution of the first and second bit values ​​in the original data, resulting in a more random distribution of "0"s and "1"s in the written data.

[0080] It's important to note that while the written data in this example exhibits a regular alternating pattern, this is merely for illustrative purposes. In practical applications, randomization operations typically result in more complex and irregular bit distributions to ensure the security of data stored on the storage device.

[0081] This example clearly demonstrates how randomization effectively alters the distribution pattern of bit values ​​in the original data, thus achieving data randomization. This randomization not only improves the uniformity of data storage, preventing write interference caused by uneven bit distribution in storage units, but also enhances data security.

[0082] More specifically, in one embodiment, the process of performing multiple randomization operations on the original data may use different randomization algorithms to process the original data, wherein the different randomization algorithms include at least one of the following:

[0083] (1) XOR operation: The system (e.g., processor 211) predefines multiple sets of random sequences of different lengths and stores them in a lookup table. A random sequence of appropriate length is selected based on the size of the original data. If the length of the original data exceeds the length of the random sequence, the random sequence is used cyclically. When performing the XOR operation, each bit of the original data is XORed with the corresponding bit of the random sequence to generate the first type of data to be written.

[0084] (2) Displacement Operation: The system maintains a displacement pool containing different cyclic displacements and logical displacement values. When performing a displacement operation on the original data, a value is selected from the displacement pool to displace the entire data block. For large data blocks, they can be divided into fixed-size segments, each using a different displacement, and then recombined to generate a second type of write data.

[0085] (3) Permutation operation: The system predefines multiple permutation tables, each defining a different bit reordering method. A permutation table is selected, and the bits in the original data are rearranged according to the order defined in the table. For large data blocks, they can be divided into fixed-size blocks, each using a different permutation table, and then recombined to generate a third type of written data.

[0086] (4) Dynamic Random Seed Operation: The system collects various system variables as inputs to the random seed, including but not limited to: system time (including the local time of host system 10 or storage device 20), data address, temperature sensor reading, power supply voltage fluctuation value, operating frequency of memory controller 210, number of recent data read / write operations, unique identifier of storage device 20, process ID or thread ID of host system 10, MAC address of network interface (if available), current remaining capacity of storage device 20, uptime since last power-on, value of internal error counter of storage device 20, etc. The system can select one variable as the seed, or combine multiple variables to generate a more complex seed. For example, the system time, temperature reading, and error counter value can be combined by bit operations to generate a composite seed. This seed is used to initialize a pseudo-random number generator (such as a linear congruential generator or Mason tween algorithm) to generate a random sequence. Then, this random sequence is used to transform the original data (such as XOR operation or bitwise addition) to generate a fourth type of write data.

[0087] (5) Grouping operation: Divide the original data into multiple sub-blocks. The size of each sub-block can be fixed (e.g., 4KB) or dynamically determined (e.g., based on the data's entropy value). For each sub-block, the system selects one or more of the above four operations and applies them in combination. For example:

[0088] The first sub-block can be XORed first, and then shifted.

[0089] The second sub-block can be permuted first, and then a dynamic random seed operation can be used.

[0090] The third sub-block can perform only dynamic random seed operations.

[0091] After processing all the sub-blocks, they are recombined to form the fifth type of write data.

[0092] Through these five different randomization operations, the system generates five different types of write data. This diverse randomization strategy increases the randomness of the data, resulting in a more uniform distribution of the bit states of the final written data.

[0093] Please return Figure 2 Next, in step S230, the processor 211 performs a randomization verification operation on each write data based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module to obtain the target write data among the multiple write data, wherein the randomization quality of the target write data is determined to be qualified.

[0094] Before explaining the details of the randomization verification operation, the three-dimensional circuit architecture of the multiple memory cells of the rewritable non-volatile memory module 220 is described first. The multiple memory cells are considered to be configured at the intersection of m first reference lines corresponding to the X direction (also called the first direction), p second reference lines corresponding to the Y direction (also called the second direction), and q third reference lines corresponding to the Z direction (also called the third direction).

[0095] Figure 4 This is a schematic diagram of a three-dimensional circuit architecture of multiple memory cells in a rewritable non-volatile memory module according to an embodiment of the present invention. This structure includes multiple key components, forming a complex three-dimensional memory array. Taking a NAND-type rewritable non-volatile memory module as an example, the specific structure is as follows:

[0096] Word Lines (WL): Marked as WL0, WL1, WL2, and WL3 in the diagram, they are arranged horizontally along the x-axis. Each plane has multiple parallel word lines used to select memory cells in a specific layer. A word line can be considered as the first baseline corresponding to the x-direction (also called the first direction).

[0097] Bit lines (BL): Marked as BL0, BL1, BL2, etc. in the diagram, they are arranged vertically along the y-axis. The word lines can be regarded as the second reference line corresponding to the Y-direction (also known as the second direction).

[0098] Cell String (CSTR): A physical structure containing a series of vertically stacked memory cells, with a top SST and a bottom GST. It represents a complete vertical NAND string in a three-dimensional memory array and is the basic building block of the memory array.

[0099] String Line (SL): Marked as SL0, SL1, SL2, etc. in the diagram, these are arranged vertically along the z-axis. Each string line contains a series of vertically stacked memory cells, forming a NAND string structure. A string line can be considered as a third baseline corresponding to the Z-direction (also called the third direction). In this invention, a CSTR (Cell String) refers to a complete vertical structure containing a series of vertically stacked memory cells, a top SST, and a bottom GST. The vertically stacked memory cells within the CSTR can be called a string line.

[0100] Source Select Line (SSL): Located at the top of the NAND string, it is used to control the source select transistor (SST).

[0101] Ground Select Line (GSL): Located at the bottom of the NAND string, it is used to control the ground select transistor (GST).

[0102] Common Source Line (CSL): Located at the bottom, it provides a common source connection for all NAND strings.

[0103] Memory Cell Transistor (MCT): Marked as MCT in the diagram, it is the actual unit for storing data.

[0104] Source Select Transistor (SST): Located at the top of each NAND string, controlled by SSL.

[0105] Ground Select Transistor (GST): Located at the bottom of each NAND string, it is controlled by GSL.

[0106] In simple terms, in this three-dimensional structure, the reference points in the three directions are:

[0107] X direction: Word line (WL), first baseline;

[0108] Y direction: Position line (BL), second baseline;

[0109] Z direction: SL line; third baseline.

[0110] The intersection of these three baselines is designated as a memory cell (labeled "Cell" in the diagram). Each memory cell is located at a specific intersection of WL, BL, and SL, and can independently store and access data. This three-dimensional structure significantly improves storage density, allowing more memory cells to be accommodated within the same chip area. It should be noted that these three directions are perpendicular to each other.

[0111] In one embodiment, the processor 211 acquires multiple bit values ​​for each written data, each of which is one of a preset N bit states. In this invention, the storage units of the non-volatile storage device can be configured to store different numbers of bits of data. The number of bits that each storage unit can store can vary depending on specific application requirements and technical implementation, ranging from 1 bit to multiple bits. They are categorized into several types: SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), QLC (Quad-Level Cell), and PLC (Penta-Level Cell).

[0112] Specifically, a single storage unit can be programmed to have 2 X The memory cell has several different threshold voltage states, where X represents the number of bits that the cell can store. For example, when X = 1, the cell has two bit states and can store 1 bit of data (SLC); when X = 2, the cell has four bit states (MLC) and can store 2 bits of data; when X = 3, the cell has eight bit states and can store 3 bits of data (TLC); when X = 4, the cell has 16 bit states and can store 4 bits of data (QLC); when X = 5, the cell has 32 bit states and can store 5 bits of data (PLC), and so on. This method allows storage devices to achieve different storage densities within the same physical structure, thus striking a balance between capacity, performance, and reliability.

[0113] Taking TLC (Triple-Level Cell) flash memory as an example, each storage cell can store 3 bits of information / data, corresponding to 8 bit states (N=8), typically denoted as S0, S1, S2, S3, S4, S5, S6, and S7. The processor 211 reads the voltage level of each storage cell and converts it into the corresponding bit state. For example, the voltage level of a certain storage cell might correspond to state S3.

[0114] On the other hand, it is worth mentioning that the processor 211 can identify the specific location of the multiple storage cells used to store the multiple bit values ​​in the three-dimensional circuit architecture of the rewritable non-volatile memory module based on the multiple physical addresses used to store the multiple bit values ​​of the written data. Therefore, the processor 211 can, based on these specific locations, obtain M groups of first bit values ​​stored on M first reference lines corresponding to the first direction (e.g., M bit groups corresponding to the first direction, each including multiple first bit values), P groups of second bit values ​​stored on P second reference lines corresponding to the second direction (e.g., P bit groups corresponding to the second direction, each including multiple second bit values), and Q groups of third bit values ​​stored on Q third reference lines corresponding to the third direction (e.g., Q bit groups corresponding to the third direction, each including multiple Qth bit values). In other words, the multiple bit values ​​in the written data can be represented by M bit groups corresponding to the first direction, P bit groups corresponding to the second direction, or Q bit groups corresponding to the third direction, respectively.

[0115] It should be noted that the randomization verification operation provided by this invention can first verify one of the first to third directions, and then verify the other directions. This invention is not limited to the order in which the directions are verified. On the other hand, the first direction is not limited to the X direction, and can be the X direction, Y direction, or Z direction; and the second and third directions are directions other than the first direction.

[0116] The following examples illustrate the implementation of the randomization verification operation of the present invention.

[0117] Example 1: Based on the multiple bit values ​​of each bit value group, obtain the percentage of N states corresponding to the N bit states of each bit value group.

[0118] For example, in one embodiment, it is assumed that the storage cell is an SLC, i.e., X=1, N=2. 1 =2. Processor 211 acquires multiple bit value groups of the write data in the first direction. Assume there are 4 bit value groups (M=4) in the first direction, corresponding to 4 first baselines, each group containing 8 bits, as follows:

[0119] Group 1: "10110101" (8 bits);

[0120] The second group of bit values: "11001100" (8 bits);

[0121] The third group of bit values: "10101010" (8 bits);

[0122] Group 4: "11110000" (8 bits).

[0123] Next, the processor 211 obtains the state percentage of the N bit states for each bit value group. In this example, N=2, indicating that there are two states (S0=0 and S1=1).

[0124] For the first group of bit values:

[0125] The number of S0 states is 3, and the state ratio is 3 / 8 = 37.5%.

[0126] The number of S1 states is 5, and the state ratio is 5 / 8 = 62.5%.

[0127] For the second group of bit values:

[0128] The number of S0 states is 4, and the state percentage is 4 / 8 = 50.0%.

[0129] The number of S1 states is 4, and the state ratio is 4 / 8 = 50.0%.

[0130] For the third group of bit values:

[0131] The number of S0 states is 4, and the state percentage is 4 / 8 = 50.0%.

[0132] The number of S1 states is 4, and the state ratio is 4 / 8 = 50.0%.

[0133] For the 4th group of bit values:

[0134] The number of S0 states is 4, and the state percentage is 4 / 8 = 50.0%.

[0135] The number of S1 states is 4, and the state ratio is 4 / 8 = 50.0%.

[0136] In this way, processor 211 obtains the N state percentages for each of the M bit value groups in the first direction. These state percentage data will be used for subsequent randomization verification operations.

[0137] In this simplified embodiment, the processor 211 can preliminarily determine the randomization quality by comparing the proportions of two states. If the difference in the proportions of the two bit states is not significant, the randomization quality is considered good. For example, if the difference between the proportions of the two states is less than a preset threshold, it can be determined that the difference in the proportions of the two states is not significant, and the randomization quality is good.

[0138] In another embodiment, the present invention provides multiple methods to obtain the randomization quality of the written data in the first direction based on the proportion of N states. Specific examples are provided below to illustrate this:

[0139] (1) Comparison method based on the difference in the proportion of the maximum and minimum states in each bit value group:

[0140] Processor 211 first calculates the maximum difference in the proportion of N states in each bit value group:

[0141] The first bit group: S0 accounts for 37.5%, S1 accounts for 62.5%, and the maximum difference is |62.5% - 37.5%| = 25%.

[0142] The second bit group: S0 accounts for 50.0%, S1 accounts for 50.0%, and the maximum difference is |50.0% - 50.0%| = 0%.

[0143] The third bit group: S0 accounts for 50.0%, S1 accounts for 50.0%, and the maximum difference is |50.0% - 50.0%| = 0%.

[0144] The fourth bit group: S0 accounts for 50.0%, S1 accounts for 50.0%, and the maximum difference is |50.0% - 50.0%| = 0%.

[0145] The processor 211 can set a preset threshold, such as 20%. If the maximum difference of all bit value groups is not greater than the threshold, the randomization quality of the written data in the first direction is deemed acceptable. In this example, since the maximum difference (25%) of the first bit value group exceeds the preset threshold, the randomization quality is deemed unacceptable.

[0146] (2) State Proportion Interval Distribution Method: The processor 211 sets multiple state proportion interval ranges, for example:

[0147] First interval: 0%–25%; Second interval: 25%–50%; Third interval: 50%–75%; Fourth interval: 75%–100%.

[0148] Next, processor 211 statistically analyzes the distribution of the state percentage of each bit value group across different intervals:

[0149] The first bit value group: S0 (37.5%) falls in the second interval, and S1 (62.5%) falls in the third interval.

[0150] The second bit value group: S0 (50.0%) falls in the third interval, and S1 (50.0%) also falls in the third interval.

[0151] The third bit value group: S0 (50.0%) falls in the third interval, and S1 (50.0%) also falls in the third interval.

[0152] The fourth bit value group: S0 (50.0%) falls in the third interval, and S1 (50.0%) also falls in the third interval.

[0153] The processor 211 can be configured with judgment rules: for example, if more than a preset percentage (e.g., 75%) of the states are concentrated in the same range, then the randomization quality of the written data in the first direction is deemed unqualified. In this example, 7 out of 8 states fall in the third range, exceeding 75%, therefore the randomization quality is deemed unqualified.

[0154] These methods can be used individually or in combination to evaluate the randomization quality of the written data in the first direction. In this way, the present invention can effectively identify cases where the bit state distribution is too concentrated or uneven. Through these different statistical methods, the processor 211 can comprehensively evaluate the randomization quality of each written data.

[0155] Example 2: Introducing a benchmark percentage value.

[0156] In this embodiment, the concept of a baseline percentage is introduced and used to evaluate the quality of randomization.

[0157] The baseline percentage for a given type of memory cell is 100% divided by the total number of corresponding bit states. For example, in MLC (Multi-Level Cell), X=2, N=2 2 =4, the benchmark percentage is 100% / 4 = 25%.

[0158] Initially, processor 211 acquires multiple bit values ​​of the data to be written. Here, it is assumed that the data to be written is "1001101110100011".

[0159] Next, the processor 211 obtains the state percentage of the N bit states. In this example, N = 4, representing the four bit states: 00, 01, 10, and 11.

[0160] Next, processor 211 divides the number of states for each bit by the total number of bits to calculate:

[0161] Percentage of bit state S0(00): 3 / 8 = 37.5%

[0162] Percentage of bit state S1(01): 2 / 8 = 25%

[0163] The percentage of bit state S2(10): 2 / 8 = 25%

[0164] The percentage of bit state S3(11) is 1 / 8 = 12.5%.

[0165] Next, the processor 211 obtains the baseline percentage value. Ideally, the percentage of each of the four bit states should be equal, i.e., 100% / 4 = 25%.

[0166] The following describes the specific details of obtaining the quality of the randomization of the written data corresponding to the first direction based on the proportions of the N states and the baseline proportion value.

[0167] In one embodiment, the processor 211 acquires N deviation values ​​between the N state percentages of each bit value group and a reference percentage value. The following is an illustration using a specific example:

[0168] Assume that the written data corresponds to 4 bit value groups in the first direction (M=4), each bit value group corresponds to two bit states (N=2), and the baseline ratio is 50%.

[0169] Processor 211 calculates the N deviation values ​​of the first bit value group: deviation value of bit state S0: |37.5%-50.0%| = 12.5%; deviation value of bit state S1: |62.5%-50.0%| = 12.5%.

[0170] Processor 211 calculates the N deviation values ​​of the second bit value group: deviation value of bit state S0: |50.0% - 50.0%| = 0%; deviation value of bit state S1: |50.0% - 50.0%| = 0%.

[0171] Processor 211 calculates the N deviation values ​​of the third bit value group: deviation value of bit state S0: |50.0% - 50.0%| = 0%; deviation value of bit state S1: |50.0% - 50.0%| = 0%.

[0172] Processor 211 calculates the N deviation values ​​of the 4th bit value group: deviation value of bit state S0: |50.0% - 50.0%| = 0%; deviation value of bit state S1: |50.0% - 50.0%| = 0%.

[0173] After obtaining these deviation values, the processor 211 compares the deviation value of each bit state in the M bit value groups and finds the largest deviation value:

[0174] (1) For bit state S0: Since the deviation values ​​in the M bit value groups are {12.5%, 0%, 0%, 0%}, the maximum deviation value of S0 is 12.5%.

[0175] (2) For bit state S1: Since the deviation values ​​in the M bit value groups are {12.5%, 0%, 0%, 0%}, the maximum deviation value of bit state S1 is 12.5%.

[0176] Thus, processor 211 obtains N maximum deviation values ​​corresponding to N bit states (e.g., in this example, N=2, the two maximum deviation values ​​for bit states S0 and S1 are 12.5% ​​and 12.5%, respectively). Assuming a preset threshold of 10%, since the maximum deviation value (12.5%) of bit state S0 and bit state S1 is greater than the preset threshold, the randomization quality of the written data in the first direction is determined to be unqualified. This indicates that in the first direction, at least one bit value group has an excessively uneven distribution of bit states.

[0177] Once the quality of randomization of a written data is determined to be acceptable, the processor 211 can use this written data as the target written data.

[0178] In one embodiment, once the processor 211 acquires a target write data, it is no longer necessary to perform randomization verification operations on other write data, thereby saving system resources.

[0179] However, in another embodiment, the processor 211 may perform a randomization verification operation on all written data to find the best randomized data (e.g., the one with the smallest maximum deviation) as the target written data, thereby further improving the reliability and security of data storage of the storage device 20.

[0180] Please return Figure 2 After acquiring the target write data, in step S240, the processor 211 stores the target write data into multiple target storage cells among the multiple storage cells of the rewritable non-volatile memory module 220. More specifically, the processor 211 assigns physical addresses to the multiple target storage cells corresponding to the target write data, and updates the corresponding mapping information after the target write data is programmed into the physical addresses. Furthermore, this process may involve a wear leveling algorithm of the flash memory controller to ensure balanced usage of the storage cells and extend the lifespan of the storage device.

[0181] On the other hand, processor 211 generates and stores metadata related to the target written data, which is associated with subsequent read and restore operations. In one embodiment, the metadata includes one or more of the following:

[0182] a. Randomization Algorithm Identifier: Used to identify the randomization algorithm used when generating target data, and is used for subsequent derandomization operations.

[0183] b. Data mapping table: Records the correspondence between data blocks and physical storage unit addresses.

[0184] c. Error Correction Code (ECC): Used to detect and correct potential bit errors.

[0185] d. Timestamp: Records the time when data was written, used for data version control and recovery.

[0186] e. Data length: Records the length of the original data, used for subsequent randomization operations.

[0187] f. Checksum: Used to verify data integrity.

[0188] In one embodiment, when the storage controller 210 receives a read instruction from the host system 10, the processor 211 performs the following steps to recover the original data:

[0189] (1) Parse read instructions: The processor 211 parses the read instructions from the host system 10 and determines the logical address range of the data to be read.

[0190] (2) Address translation: The processor 211 uses a logic-to-physical mapping table to translate the logical address into the corresponding physical address.

[0191] (3) Reading Metadata: Processor 211 first reads the metadata related to the target data. This metadata is usually stored in predefined special pages or blocks and includes:

[0192] a. Randomization algorithm identifier

[0193] b. Data Mapping Table

[0194] c. Error Correction Code (ECC)

[0195] d. Data length

[0196] e. Checksum

[0197] (4) Read randomized data: According to the data mapping table in the metadata, the processor 211 reads the randomized target write data from the corresponding physical address.

[0198] (5) Error checking and correction: The processor 211 uses the read ECC information to perform error checking on the data. If a correctable error is found, it is corrected. If an uncorrectable error is found, the data block is marked as an error, and other recovery mechanisms are attempted.

[0199] (6) Data integrity verification: In one embodiment, the processor 211 also uses a stored checksum to verify the integrity of the read data. If the verification fails, a data recovery procedure may need to be initiated or an error may be reported to the host system.

[0200] (7) Determine the derandomization algorithm: After obtaining the target data written after successful decoding, the processor 211 determines the derandomization algorithm to be used based on the randomization algorithm identifier in the metadata.

[0201] (8) Perform derandomization operation: The processor 211 performs a derandomization operation on the read randomized data. This process is the reverse of the write-time randomization operation and may include:

[0202] a. Reverse displacement operation

[0203] b. The inverse operation of XOR

[0204] c. Reverse permutation operation

[0205] d. Perform the reverse operation using the same random seed.

[0206] (9) Data length adjustment: In one embodiment, the processor 21 can also trim the derandomized data according to the original data length recorded in the metadata to ensure that the recovered data length is consistent with the original data.

[0207] (10) Data transmission: After acquiring the corresponding raw data, the processor 211 transmits the recovered raw data to the host system 10 through the connection interface circuit 230 in response to the read instruction.

[0208] Through this detailed derandomization process, the storage controller 210 can accurately restore the randomized target write data stored in the storage device 20 to the corresponding original data and securely transmit it to the host system 10. This process not only ensures correct data recovery but also includes steps such as error detection, correction, and data integrity verification to improve the reliability and correctness of data reading. It should be noted that the randomization and derandomization operations can be implemented using specific randomization and derandomization circuits to execute the aforementioned randomization / derandomization algorithms. Furthermore, the randomization and derandomization circuits can also be integrated into a single circuit unit.

[0209] Figure 5 This is a flowchart illustrating the randomization verification operation according to an embodiment of the present invention.

[0210] Please refer to Figure 5 This embodiment describes a method for verifying the quality of write data randomization, applicable to rewritable non-volatile memory modules with multiple storage cells. The method is executed by the processor of the memory controller and mainly includes the following steps:

[0211] In step S510, the processor 211 acquires the 4-bit value group (M=4) corresponding to the write data in the first direction. Since each storage unit can store 1 bit (X=1), each bit value corresponds to 2 bit states (N=2). 1 =2). Assume the contents of these 4 bit value groups are:

[0212] First bit value group: "11100000";

[0213] The second bit value group: "11110001";

[0214] The third bit value group: "00011111";

[0215] The fourth bit value group: "00001111".

[0216] In step S520, processor 211 calculates the bit state percentage for each bit value group:

[0217] (1) Bit state percentage of the first bit value group:

[0218] Bit state S0 percentage: 62.5%;

[0219] Bit state S1 percentage: 37.5%.

[0220] (2) Bit state percentage of the second bit value group:

[0221] Bit state S0 percentage: 25.0%;

[0222] Bit state S1 percentage: 75.0%.

[0223] (3) Bit state percentage of the third bit value group:

[0224] Bit state S0 percentage: 37.5%;

[0225] Bit state S1 percentage: 62.5%.

[0226] (4) Bit state percentage of the fourth bit group:

[0227] Bit state S0 percentage: 75.0%;

[0228] Bit state S1 percentage: 25.0%.

[0229] Next, in step S530, the processor 211 obtains a baseline percentage value based on two bits of state. In this example, the baseline percentage value is 50% (100% / 2 = 50%).

[0230] Next, in step S540, processor 211 calculates the deviation between the state of each bit in each bit value group and the reference percentage value:

[0231] (1) Deviation value of the first bit value group:

[0232] Bit state S0 deviation: |62.5% - 50.0%| = 12.5%;

[0233] Bit state S1 deviation: |37.5% - 50.0%| = 12.5%.

[0234] (2) Deviation value of the second bit value group:

[0235] Bit state S0 deviation: |25.0% - 50.0%| = 25.0%;

[0236] Bit state S1 deviation: |75.0% - 50.0%| = 25.0%.

[0237] (3) Deviation value of the third bit group:

[0238] Bit state S0 deviation: |37.5% - 50.0%| = 12.5%;

[0239] Bit state S1 deviation: |62.5% - 50.0%| = 12.5%.

[0240] (4) Deviation value of the fourth bit group:

[0241] Bit state S0 deviation: |75.0% - 50.0%| = 25.0%;

[0242] Bit state S1 deviation value: |25.0%-50.0%|=25.0%.

[0243] Next, in step S550, processor 211 calculates the maximum deviation value of each bit state in the four bit value groups:

[0244] The four deviation values ​​of bit state S0 are {12.5%, 25.0%, 12.5%, 25.0%}: the maximum deviation value of bit state S0 is 25.0%.

[0245] The four deviation values ​​of bit state S1 are {12.5%, 25.0%, 12.5%, 25.0%}: the maximum deviation value of bit state S1 is 25.0%.

[0246] Next, in step S560, the processor 211 sets the preset threshold to 20% and determines whether the two maximum deviation values ​​are both less than the preset threshold.

[0247] In step S580, since the maximum deviation value (25.0%) of bit state S0 and bit state S1 is greater than the preset threshold (20%), the processor 211 determines that the randomization quality of the first direction corresponding to the written data is unqualified.

[0248] Using the methods described above, this invention can not only assess the overall bit state distribution but also identify severe deviations occurring in specific bit value groups. This meticulous assessment approach helps to detect data distribution problems that may lead to a decline in storage reliability early on, avoiding the shortcomings of traditional methods that only focus on overall statistics while ignoring local extreme cases.

[0249] The randomization verification operation of the present invention will be further illustrated using a complete embodiment below.

[0250] In one embodiment, the randomization verification operation is illustrated using a three-level cell (TLC) rewritable non-volatile memory module 220 as an example. In the TLC architecture, each memory cell can store 3 bits (X=3), thus there are 8 bits of state (N=2). 3 =8). Furthermore, it is further assumed that what needs to be verified now is the three bit value groups corresponding to the first direction of the written data.

[0251] Processor 211 first obtains the 8-bit state distribution of multiple memory cells corresponding to the first bit value group in the first direction of the written data:

[0252] The percentage of bit state S0 is 13.4%, the percentage of bit state S1 is 11.8%, the percentage of bit state S2 is 12.7%, the percentage of bit state S3 is 13.1%, the percentage of bit state S4 is 12.5%, the percentage of bit state S5 is 11.7%, the percentage of bit state S6 is 13.2%, and the percentage of bit state S7 is 11.6%.

[0253] Next, the processor 211 first obtains the 8-bit state distribution of multiple memory cells corresponding to the second bit value group in the first direction of the written data:

[0254] Percentage of bit state S0: 12.2%, Percentage of bit state S1: 12.4%, Percentage of bit state S2: 13.3%, Percentage of bit state S3: 12.1%, Percentage of bit state S4: 12.6%, Percentage of bit state S5: 12.0%, Percentage of bit state S6: 12.8%, Percentage of bit state S7: 12.6%.

[0255] Next, the processor 211 first obtains the 8-bit state distribution of multiple memory cells corresponding to the third bit value group in the first direction of the written data:

[0256] The percentage of bit state S0 is 10.1%, the percentage of bit state S1 is 13.8%, the percentage of bit state S2 is 11.6%, the percentage of bit state S3 is 14.1%, the percentage of bit state S4 is 12.7%, the percentage of bit state S5 is 12.2%, the percentage of bit state S6 is 13.1%, and the percentage of bit state S7 is 12.4%.

[0257] Processor 211 uses a reference ratio of 12.5% ​​to calculate the deviation of each bit state on each line. Taking bit state S0 as an example:

[0258] The deviation value of the bit state S0 corresponding to the first bit value group is: |13.4% - 12.5%| = 0.9%;

[0259] The deviation value of the second bit value group corresponding to the bit state S0 is: |12.2% - 12.5%| = 0.3%;

[0260] The deviation value of the third bit value group corresponding to bit state S0 is: |10.1%-12.5%| = 2.4%.

[0261] Next, processor 211 finds that the maximum deviation of bit state S0 across all lines is 2.4%. Assuming a preset threshold of 3%, since 2.4% is less than 3%, it indicates that the distribution of bit state S0 is acceptable.

[0262] Processor 211 performs the same calculations and judgments on other bit states (S1 to S7). If the maximum deviation value of all bit states is less than a preset threshold, the randomization verification in the first direction is successful. Then, processor 211 performs the same verification process on the second and third directions.

[0263] This method pays particular attention to the distribution of each bit state across each line, effectively avoiding the problem of traditional methods that only consider the overall average and ignore local extreme distributions. Furthermore, by verifying the distribution in three directions separately, this invention can more comprehensively evaluate the uniformity of data distribution in a three-dimensional structure, improving storage reliability.

[0264] The following example illustrates how randomized verification can be performed based on multiple directions of a three-dimensional circuit architecture.

[0265] In one embodiment, the processor 211 first verifies the first direction. Assume the written data has four bit value groups (M=4) in the first direction, each group containing eight memory cells. In this example, each memory cell is a single-level cell (SLC), therefore having two bit states (N=2). When the processor 211 calculates that the maximum deviation values ​​of bit state S0 and bit state S1 are 18% and 17% respectively, and the preset threshold is 20%, the randomization quality of the written data corresponding to the first direction is deemed acceptable.

[0266] Next, processor 211 verifies the second direction. Assuming there are 3 bit value groups (P=3) in the second direction, processor 211 calculates the state percentage for each bit value group:

[0267] First bit value group: Bit state S0 percentage: 45%; Bit state S1 percentage: 55%.

[0268] Second bit value group: Bit state S0 percentage: 52%; Bit state S1 percentage: 48%.

[0269] Third bit value group: Bit state S0 percentage: 47%; Bit state S1 percentage: 53%.

[0270] Processor 211's calculations show a 50% deviation from the baseline percentage.

[0271] The three deviation values ​​of bit state S0 are {5%, 2%, 3%}: the maximum deviation value of bit state S0 is 5%; the three deviation values ​​of bit state S1 are {5%, 2%, 3%}: the maximum deviation value of bit state S1 is 5%.

[0272] Since both maximum deviation values ​​are less than the preset threshold of 20%, the processor 211 determines that the randomization quality of the second direction is qualified.

[0273] Finally, processor 211 verifies the third direction. Assuming there are 5 bit value groups (Q=5) in the third direction, after a similar calculation process, the maximum deviation of bit state S0 is found to be 15%; the maximum deviation of bit state S1 is 16%.

[0274] These deviation values ​​are all less than the preset threshold of 20%, therefore the processor 211 determines that the randomization quality of the third direction is qualified.

[0275] Since the randomization quality of the written data in the first, second, and third directions is all qualified, the processor 211 ultimately determines that the randomization quality of the written data is qualified.

[0276] However, in another embodiment, assuming there are 5 bit value groups (Q=5) in the third direction, after a similar calculation process, the maximum deviation value of bit state S0 is 25%; the maximum deviation value of bit state S1 is 16%. Since the maximum deviation value of bit state S0 is greater than the preset threshold of 20%, the processor 211 determines that the quality of randomization in the third direction is unqualified.

[0277] This multi-directional verification method overcomes the limitations of traditional techniques that only focus on a single direction. By simultaneously verifying the data distribution in three directions, this invention can more comprehensively evaluate the degree of data randomization in a three-dimensional structure, effectively improving storage reliability.

[0278] In one embodiment, when the processor 211 determines that the randomization quality of the written data in the first direction is unqualified, it will take further measures to record the abnormal situation.

[0279] Assuming the written data corresponds to 4 bit value groups (M=4) in the first direction, each group contains 8 memory cells and is a single-level cell (SLC), so there are 2 bit states (N=2). Processor 211 has completed the calculation of the maximum deviation value for each bit state:

[0280] The four deviation values ​​of bit state S0 are {22%, 15%, 18%, 20%}: the maximum deviation value of bit state S0 is 22%; the four deviation values ​​of bit state S1 are {12%, 25%, 16%, 15%}: the maximum deviation value of bit state S1 is 25%.

[0281] When the preset threshold is set to 20%, processor 211 detects:

[0282] The maximum deviation of bit state S0 (22%) is greater than the preset threshold (20%).

[0283] The maximum deviation of bit state S1 (25%) is greater than the preset threshold (20%).

[0284] Therefore, the processor 211 obtains the two maximum deviation values ​​of the abnormality (22% and 25%), as well as the corresponding abnormal bit states (bit state S0 and bit state S1).

[0285] Next, the processor 211 records the bit states whose maximum deviation value exceeds a preset threshold and their respective directions: a first direction (e.g., the X direction); and abnormal bit states in the first direction (bit state S0 and bit state S1). In another embodiment, the processor 211 further records the corresponding maximum deviation values ​​(e.g., 22% and 25%).

[0286] This recording mechanism allows the present invention not only to identify cases of substandard randomization quality, but also to accurately pinpoint the direction of the problem and the specific bit state, which helps to subsequently improve the randomization operation in a targeted manner.

[0287] In one embodiment, when the processor 211 finds that the randomization quality of all written data is unqualified, it adjusts the randomization operation according to the recorded abnormal bit state and its corresponding direction.

[0288] Suppose that the original data was subjected to three different randomization operations, resulting in three written data entries. The randomization verification results for the first direction are as follows:

[0289] (1) The first data written (generated via randomization operation of XOR operation): the maximum deviation of bit state S0 is 25% (in the second bit value group); the maximum deviation of bit state S1 is 23% (in the third bit value group).

[0290] (2) The second data to be written (generated by randomization operation via bit shifting): the maximum deviation of bit state S0 is 22% (in the first bit group); the maximum deviation of bit state S1 is 24% (in the fourth bit group).

[0291] (3) The third written data (generated via randomization operation of permutation operation): the maximum deviation of bit state S0 is 26% (in the third bit value group); the maximum deviation of bit state S1 is 21% (in the second bit value group).

[0292] Since the randomization quality of all written data in the first direction is unqualified (the maximum deviation value exceeds the preset threshold of 20%), the processor 211 may perform the following adjustments based on the recorded abnormal bit states and their distribution in the first direction:

[0293] 1. In response to an abnormal bit state S0 in the second bit group of the first written data, the processor 211 adjusts the random sequence of the XOR operation in that region.

[0294] 2. In response to the abnormal bit state S1 of the fourth bit group in the second written data, the processor 211 increases the number of shift operations in that region.

[0295] 3. In response to the S0 anomaly in the bit state of the third bit group in the third written data, the processor 211 employs a more complex substitution table for that region.

[0296] After adjustment, processor 211 regenerates the write data and performs randomization verification until it finds the target write data that passes verification.

[0297] After the above adjustments, the processor 211 regenerates three new write data and performs randomization verification again. If any of the new write data passes verification, the processor 211 can store the qualified write data as the target write data into multiple target storage units.

[0298] This adaptive adjustment mechanism enables the invention to optimize randomization operations based on specific abnormal situations, which not only improves the success rate of obtaining qualified written data, but also effectively avoids the problem of uneven data distribution repeatedly occurring in specific directions or positions.

[0299] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in the processor of the storage device, the processor in the storage device performs the steps of the above-described data writing method. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0300] The data writing method and its randomized verification operation proposed in this invention have significant technical advantages in three-dimensional non-volatile memory. By performing multiple randomization operations on the written data and executing the verification process in multiple directions based on the three-dimensional circuit architecture, this method can effectively improve the uniformity of data distribution in the memory.

[0301] Specifically, this method precisely quantifies the randomization quality of data by analyzing the state proportions of multiple bit value groups in each direction and their deviations from a benchmark proportion. By comparing the maximum deviation of each bit state in multiple bit value groups in the same direction with a preset threshold, this invention can accurately determine whether the data distribution in each direction is uniform. Finally, only when the randomization quality of the written data is qualified in all three directions is the written data determined to be usable for storing the original data.

[0302] When the randomization quality in a certain direction is found to be substandard, this method records the abnormal bit state where the deviation value in that direction exceeds a preset threshold. This targeted recording mechanism provides a clear basis for subsequent randomization adjustments. If the randomization quality of all written data is substandard, this method can adjust the randomization operation based on the recorded abnormal bit states and their corresponding directions, regenerate the written data, and verify it again to store qualified written data, thereby completing the storage of the original data.

[0303] Compared to traditional methods that only focus on the overall data distribution, this invention analyzes the local distribution characteristics of bit value groups in each direction, enabling a more accurate assessment of the degree of data randomization in a three-dimensional structure. This multi-directional, multi-level verification method not only improves storage reliability but also effectively avoids the problem of uneven data distribution in specific directions or local areas.

[0304] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data writing method for a rewritable non-volatile memory module having multiple storage units, characterized in that, include: Retrieve raw data from the host system; Perform multiple randomization operations on the original data to obtain multiple write data; Based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, a randomized verification operation is performed on each written data. The randomized verification operation corresponding to each direction includes: obtaining multiple bit value groups of the written data corresponding to that direction; calculating multiple deviation values ​​based on the proportion of N states corresponding to N bit states in each bit value group and a reference proportion value; and taking the largest of the multiple deviation values ​​corresponding to the same bit state as the maximum deviation value for that same bit state, thereby obtaining N maximum deviation values ​​corresponding to the N bit states; and If none of the N maximum deviation values ​​are greater than a preset threshold, then the quality of the randomization in the corresponding direction is determined to be acceptable; and The randomized data corresponding to each direction is determined to be of qualified quality and is used as the target write data, and the target write data is stored in multiple target storage units among the multiple storage units.

2. The data writing method according to claim 1, characterized in that, Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: The XOR operation performs an XOR operation between the original data and multiple predefined different random sequences; The displacement operation performs multiple different cyclic displacements or logical displacements on the original data. The permutation operation changes the order of bits in the original data according to multiple predefined permutation tables; The dynamic random seed operation generates multiple different random seeds based on system time, data address, or other system variables, and uses the multiple random seeds and the original data to generate the multiple write data. as well as The grouping operation divides the original data into multiple sub-blocks, and applies different XOR operations, shift operations, permutation operations, and dynamic random seed operations to the multiple sub-blocks.

3. The data writing method according to claim 1, characterized in that, The step of obtaining the plurality of bit value groups corresponding to the direction of the written data includes: Obtain M bit value groups corresponding to the first direction among the plurality of directions of the written data. Multiple bit values ​​in each bit value group correspond to multiple storage cells in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of the N bit states, where N is 2. X And X is the number of bits that can be stored in each storage unit; Based on the multiple bit values ​​of each bit value group, obtain the percentage of each of the N states corresponding to the N bit states for each bit value group; and Based on the proportions of the N states, the quality of the randomization of the written data corresponding to the first direction is obtained.

4. The data writing method according to claim 3, characterized in that, The step of obtaining the quality of the randomization of the written data corresponding to the first direction based on the proportions of the N states includes: Based on the N bit states, obtain the baseline proportion value; and Based on the proportions of the N states and the baseline proportion value, the randomization quality of the written data corresponding to the first direction is obtained.

5. The data writing method according to claim 4, characterized in that, The step of obtaining the quality of the randomization of the written data corresponding to the first direction based on the N state proportions and the baseline proportion value includes: Based on each bit value group, obtain N deviation values ​​between the N state proportions of each bit value group and the baseline proportion value; Based on the M deviation values ​​corresponding to the same bit state in the M bit value groups, the largest of the M deviation values ​​is taken as the maximum deviation value corresponding to the same bit state, thereby obtaining the N maximum deviation values ​​corresponding to the N bit states. If none of the N maximum deviation values ​​are greater than the preset threshold, the quality of the randomization of the written data corresponding to the first direction is determined to be qualified; If one of the N maximum deviation values ​​is greater than the preset threshold, the quality of the randomization of the written data corresponding to the first direction is determined to be unqualified.

6. The data writing method according to claim 5, wherein the plurality of directions includes the first direction, the second direction, and the third direction, characterized in that, Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Obtain P sets of bit values ​​corresponding to the second direction of the written data and N maximum deviation values ​​of the P sets of bit values ​​corresponding to the N bit states, so as to obtain the quality of the randomization of the written data corresponding to the second direction; Obtain the Q bit value groups corresponding to the third direction of the written data and the N maximum deviation values ​​of the N bit states corresponding to the Q bit value groups, so as to obtain the quality of the randomization of the written data corresponding to the third direction; and If the quality of the randomization of the written data in the first direction, the second direction, and the third direction is all qualified, then the quality of the randomization of the written data is determined to be qualified.

7. The data writing method according to claim 1, characterized in that, After determining that the quality of the randomization corresponding to the direction of the written data is unqualified, the method further includes: Obtain one or more abnormal maximum deviation values ​​greater than the preset threshold from the N maximum deviation values, and one or more abnormal bit states corresponding to the one or more abnormal maximum deviation values ​​from the N bit states; and Record the direction and the state of one or more abnormal bits corresponding to the direction.

8. The data writing method according to claim 7, characterized in that, If the quality of the randomization of the multiple written data is all unqualified, the method further includes: Based on the one or more abnormal bit states and their corresponding directions, adjust the multiple randomization operations to regenerate multiple new write data; and The randomization verification operation is performed again for each new written data to attempt to obtain the target written data, and then the target written data is stored in the plurality of target storage units.

9. A memory controller suitable for a storage device configured with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system, characterized in that, The memory controller includes: A memory interface control circuit is provided for electrical connection to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple memory cells; and The processor is electrically connected to the memory interface control circuit. The processor is configured to: Retrieve raw data from the host system; Perform multiple randomization operations on the original data to obtain multiple write data; Based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, a randomized verification operation is performed on each written data. The randomized verification operation corresponding to each direction includes: obtaining multiple bit value groups of the written data corresponding to that direction; calculating multiple deviation values ​​based on the proportion of N states corresponding to N bit states in each bit value group and a reference proportion value; and taking the largest of the multiple deviation values ​​corresponding to the same bit state as the maximum deviation value for that same bit state, thereby obtaining N maximum deviation values ​​corresponding to the N bit states; and If none of the N maximum deviation values ​​are greater than a preset threshold, then the quality of the randomization in the corresponding direction is determined to be acceptable; and The randomized data corresponding to each direction is determined to be of qualified quality and is used as the target write data, and the target write data is stored in multiple target storage units among the multiple storage units.

10. The memory controller according to claim 9, characterized in that, Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: The XOR operation performs an XOR operation between the original data and multiple predefined different random sequences; The displacement operation performs multiple different cyclic displacements or logical displacements on the original data. The permutation operation changes the order of bits in the original data according to multiple predefined permutation tables; The dynamic random seed operation generates multiple different random seeds based on system time, data address, or other system variables, and uses the multiple random seeds and the original data to generate the multiple write data. as well as The grouping operation divides the original data into multiple sub-blocks, and applies different XOR operations, shift operations, permutation operations, and dynamic random seed operations to the multiple sub-blocks.

11. The memory controller according to claim 9, characterized in that, The step of obtaining the plurality of bit value groups corresponding to the direction of the written data includes: Obtain M bit value groups corresponding to the first direction among the plurality of directions of the written data. Multiple bit values ​​in each bit value group correspond to multiple storage cells in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of the N bit states, where N is 2. X And X is the number of bits that can be stored in each storage unit; Based on the multiple bit values ​​of each bit value group, obtain the percentage of the N states corresponding to the N bit states of each bit value group; Based on the proportions of the N states, the quality of the randomization of the written data corresponding to the first direction is obtained.

12. The memory controller according to claim 11, characterized in that, The step of obtaining the quality of the randomization of the written data corresponding to the first direction based on the proportions of the N states further includes: Based on the N bit states, obtain the baseline proportion value; and Based on the proportions of the N states and the baseline proportion value, the randomization quality of the written data corresponding to the first direction is obtained.

13. The memory controller according to claim 12, characterized in that, The step of obtaining the quality of the randomization of the written data corresponding to the first direction based on the N state proportions and the baseline proportion value includes: Based on each bit value group, obtain N deviation values ​​between the N state proportions of each bit value group and the baseline proportion value; Based on the M deviation values ​​corresponding to the same bit state in the M bit value groups, the largest of the M deviation values ​​is taken as the maximum deviation value corresponding to the same bit state, thereby obtaining the N maximum deviation values ​​corresponding to the N bit states. If none of the N maximum deviation values ​​are greater than the preset threshold, it is determined that the quality of the randomization of the written data corresponding to the first direction is qualified; If one of the N maximum deviation values ​​is greater than the preset threshold, the quality of the randomization of the written data corresponding to the first direction is determined to be unqualified.

14. The memory controller according to claim 13, wherein the plurality of directions includes the first direction, the second direction, and the third direction, characterized in that, Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Obtain P sets of bit values ​​corresponding to the second direction of the written data and N maximum deviation values ​​of the P sets of bit values ​​corresponding to the N bit states, so as to obtain the quality of the randomization of the written data corresponding to the second direction; Obtain the Q bit value groups corresponding to the third direction of the written data and the N maximum deviation values ​​of the N bit states corresponding to the Q bit value groups, so as to obtain the quality of the randomization of the written data corresponding to the third direction; and If the quality of the randomization of the written data in the first direction, the second direction, and the third direction is all qualified, then the quality of the randomization of the written data is determined to be qualified.

15. The memory controller according to claim 9, characterized in that, After determining that the quality of the randomization corresponding to the direction of the written data is unqualified, the processor is further configured to: Obtain one or more abnormal maximum deviation values ​​greater than the preset threshold from the N maximum deviation values, and one or more abnormal bit states corresponding to the one or more abnormal maximum deviation values ​​from the N bit states; and Record the direction and the state of one or more abnormal bits corresponding to the direction.

16. The memory controller according to claim 15, characterized in that, If the quality of the randomization of the plurality of written data is unsatisfactory, the processor is further configured to: Based on the one or more abnormal bit states and their corresponding directions, adjust the multiple randomization operations to regenerate multiple new write data; and The randomization verification operation is performed again for each new written data to attempt to obtain the target written data, and then the target written data is stored in the plurality of target storage units.

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