Flash memory data storage method, flash memory data reading method and flash memory

Abstract

The invention provides a flash memory data storage method, a flash memory data reading method and a flash memory. The storage method comprises the steps that original data are negated, the original data, negated data, redundant data and verification data form code words, the code words are negated, and the code words and the negated code words are written into a flash memory; the reading method comprises the steps of reading code words and negation code words from the flash memory, performing negation reduction on the negation code words, performing comparison adjustment on original code word data and reduced code word data on bits, performing extraction to obtain code words containing original data and negation data, performing negation reduction on the negation data, and obtaining the code words containing the original data and the reduced code word data. Performing comparison adjustment on the original data and the reduced data on bits to obtain the original data, and performing error correction decoding on the adjusted data after adjusting and supplementing redundant data to obtain target read data; by utilizing the characteristic that the flash memory data storage state overturning probabilities are not equal, multiple pieces of original data and negation data are subjected to backup statistical adjustment, and the probability of correctly reading the data is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of memory, and more particularly to a flash memory data storage method, a flash memory data reading method, and a flash memory. Background Art

[0002] NAND Flash is a non-volatile data storage device that does not lose data when power is off. Due to the characteristics of flash memory itself, the data stored in it may have different degrees of errors due to factors such as ambient temperature, storage time, and degree of wear. When the number of errors reaches a certain level and exceeds the error correction capability of the main control chip, the data may be lost. By adding multiple backup data, it is helpful to provide the probability of correctly obtaining key data information data. The current multi-backup method is mostly to store multiple identical backups in flash memory. The difference is mainly based on different storage space and reading time requirements, and different backup numbers are selected. By increasing the number of backups, it is expected to increase the probability of reading correct data. These backup data are the same, and the probability of errors is theoretically the same, so the improvement in the probability of correct data reading is limited. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The purpose of the present application is to solve one of the technical problems existing in the related art to at least a certain extent. The embodiments of the present application provide a flash memory data storage method, a flash memory data reading method and a flash memory, which can improve the probability of correctly reading data.

[0005] In an embodiment of a first aspect of the present application, a flash memory data storage method includes: Obtain the original data to be backed up; Inverting the original data to obtain inverted data; The original data, the inverted data, the redundant data and the check data constitute a codeword; Inverting the codeword to obtain an inverted codeword; Determine the number of code words p and the number of inverted code words q according to the storage space and reliability requirements of the flash memory; Write p copies of the codeword and q copies of the inverted codeword into the flash memory.

[0006] According to some embodiments of the first aspect of the present application, the forming of a codeword from the original data, the inverted data, the redundant data and the check data includes: Obtaining the size of the original data and the size of the user data area of ​​the codeword; Determine the maximum number of original data and inverted data according to the size of the original data and the size of the user data area of ​​the codeword; Determine the number n of the original data and the number m of the negated data according to the maximum number; The n copies of the original data, the m copies of the inverted data and the redundant data constitute a user data area of ​​the codeword; the check data constitutes a check data area of ​​the codeword; The user data area and the check data area constitute a codeword.

[0007] According to certain embodiments of the first aspect of the present application, the location areas in which the p copies of the codeword and the q copies of the inverted codeword are written in the flash memory are the same or have the same storage characteristics.

[0008] According to certain embodiments of the first aspect of the present application, writing p copies of the codeword and q copies of the inverted codeword into the flash memory includes: The p copies of the codeword and the q copies of the inverted codeword are written into the same block, the same page or the same offset within the page of the flash memory.

[0009] According to certain embodiments of the first aspect of the present application, the redundant data consists of data 0.

[0010] The second aspect of the present application is a flash memory data reading method, wherein the data in the flash memory is backed up according to the flash memory data storage method as described in the first aspect of the present application; the flash memory data reading method comprises: Obtain a first data storage address of data to be read; Read at least one codeword and at least one inverted codeword from the flash memory according to the first data storage address; Inverting the inverted codeword to obtain a restored codeword; Compare and adjust the code word and the restored code word on the bit position to obtain a valid code word; Extracting the original data and the inverted data from the user data area of ​​the valid codeword; Inverting the inverted data to obtain restored data; Compare and adjust the original data and the restored data on a bit basis to obtain first valid data; Replacing the user data area of ​​the first valid data with the first valid data and redundant data to obtain second valid data; The second valid data is subjected to error correction decoding according to the verification data in the verification data area of ​​the second valid data to obtain target read data.

[0011] According to certain embodiments of the second aspect of the present application, comparing and adjusting the codeword and the restored codeword on a bit basis to obtain a valid codeword includes: Counting a first number of data 0s and a second number of data 1s at the same bit position in the user data area of ​​the codeword and the user data area of ​​the restored codeword; When the first number is greater than the second number, determining that the first candidate data of the bit position is data 0; When the first number is less than the second number, determining that the first candidate data of the bit position is data 1; The first candidate data of each bit is combined to obtain a valid code word.

[0012] According to certain embodiments of the second aspect of the present application, comparing and adjusting the original data and the restored data on a bit basis to obtain first valid data includes: aligning the original data and the restored data; Counting a third number of data 0s and a fourth number of data 1s at the same bit position of the original data and the restored data; When the third number is greater than the fourth number, determining that the second candidate data of the bit is data 0; When the third number is less than the fourth number, determining that the second candidate data of the bit is data 1; The second candidate data of each bit is combined to obtain the first valid data.

[0013] An embodiment of the third aspect of the present application is a flash memory, which applies the flash memory data storage method described in the embodiment of the first aspect of the present application and the flash memory data reading method described in the embodiment of the second aspect of the present application; the flash memory includes a storage controller and flash memory particles, and the storage controller is connected to the flash memory particles; the storage controller includes a codeword adjustment control module and an error correction control module; the codeword adjustment control module is used to perform codeword related operations; the error correction control module is used to perform error correction decoding operations.

[0014] According to certain embodiments of the third aspect of the present application, the storage controller also includes a protocol interface control module, a system processor and a system cache, the codeword adjustment control module and the error correction control module are arranged in a flash memory read and write control module, and the protocol interface control module, the system processor and the system cache are connected to the flash memory read and write control module via an internal bus.

[0015] The above scheme has at least the following beneficial effects: the storage method includes inverting the original data, forming a codeword with the original data, inverted data, redundant data and check data, inverting the codeword, and writing the codeword and the inverted codeword into a flash memory; the reading method includes reading the codeword and the inverted codeword from the flash memory, inverting and restoring the inverted codeword, comparing and adjusting the original data and the restored data on the bit position, extracting the original data and the inverted data, inverting and restoring the inverted data, comparing and adjusting the original data and the restored data on the bit position, and performing error correction decoding on the adjusted data to obtain the target read data; utilizing the characteristic that the probability of data storage state flipping in the flash memory is unequal, multiple copies of the original data and the inverted data are backed up and statistically adjusted to improve the probability of correctly reading the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0017] Figure 1 is a step diagram of a flash memory data storage method provided by an embodiment of the present application; Figure 2 is a sub-step diagram of step S130; Figure 3 is a step diagram of a flash memory data reading method provided in an embodiment of the present application; Figure 4 is a sub-step diagram of step S240; Figure 5 is a sub-step diagram of step S270; Figure 6 It is the structural diagram of the codeword; Figure 7 It is a structural diagram of p code words and q inverted code words; Figure 8 is a schematic diagram of step S240; Fig. 9 is a schematic diagram of step S280; Fig.10 It is a structural diagram of the flash memory provided in the embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims or the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] Due to the characteristics of flash memory, the data stored in it may have different degrees of errors due to factors such as ambient temperature, storage time, and degree of wear. When the number of errors reaches a certain level and exceeds the error correction capability of the main control chip, the data may be lost. By adding multiple backup data, it is helpful to increase the probability of correctly obtaining key data information.

[0021] Flash memory data is stored in binary 0 and 1 states. During the storage process, data may flip as the environment and time change, flipping 0 to 1 or 1 to 0. Since the two states 0 and 1 correspond to two different voltage ranges in the flash memory, changes in the external environment or prolonged storage time will affect the voltage distribution inside the flash memory. Therefore, the probability of 0 flipping to 1 and 1 flipping to 0 is usually not completely equal.

[0022] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0023] In order to solve the above problems, an embodiment of the present application provides a flash memory data storage method.

[0024] Reference Figure 1 , a flash memory data storage method, comprising the following steps: Step S110, obtaining the original data to be backed up; Step S120, inverting the original data to obtain inverted data; Step S130, the original data, the inverted data, the redundant data and the check data are combined into a codeword; Step S140, inverting the codeword to obtain an inverted codeword; Step S150, determining the number of code words p and the number of inverted code words q according to the storage space and reliability requirements of the flash memory; Step S160, write p code words and q inverted code words into the flash memory.

[0025] In step S110, the original data to be backed up is obtained, and the original data is recorded as X. The original data includes user data.

[0026] For step S120, the original data X is inverted to obtain inverted data Xb. For example, data 0 is inverted to obtain data 1, and data 1 is inverted to obtain data 0. The continuous data 0011 is inverted to obtain data 1100. The inverted data can be used as a reference together with the original data to increase the security and reliability of the data.

[0027] Reference Figure 2 For step S130, the original data, the inverted data, the redundant data and the check data are used to form a codeword, including the following steps: Step S131, obtaining the size of the original data and the size of the user data area of ​​the codeword; Step S132, determining the maximum number of original data and inverted data according to the size of the original data and the size of the user data area of ​​the codeword; Step S133, determining the number n of original data and the number m of negated data according to the maximum number; Step S134, the n original data, the m inverted data and the redundant data constitute the user data area of ​​the codeword; the check data constitutes the check data area of ​​the codeword; Step S135, the user data area and the check data area form a code word.

[0028] The size of the original data refers to the size of the storage space occupied by the data to be stored. The file size can be obtained through the file operation function in the programming language, or the size of the original data can be determined by reading the length of the data buffer.

[0029] The codeword includes a user data area and a check data area. The size of the user data area refers to the size of the storage space used to store the original data, inverted data, and redundant data in the codeword. This size is usually determined by the design of the storage system. For example, the size of the user data area of ​​the codeword may be fixed to 4KB, or it may be flexibly configured according to actual application requirements and the characteristics of the storage device.

[0030] The size of the original data is Soriginal, and the size of the user data area is Suser. Then the maximum number of original data and inverted data K=Suser / Soriginal, and rounded down to the integer obtained.

[0031] It can be understood that, assuming that the size of the original data is Soriginal, the size of the user data area of ​​the codeword is Suser. Since the user data area needs to store the original data, the inverted data and the redundant data, the following relationship can be obtained: n*Soriginal+m*Sinverted+Sredundant≤Suser, where n is the number of original data, m is the number of inverted data, Sinverted is the size of the inverted data (usually the same as the size of the original data, that is, Sinverted=Soriginal), and Sredundant is the size of the redundant data. Without considering redundant data (that is, Sredundant=0), the maximum number of original data and inverted data satisfies n*Soriginal+m*Soriginal≤Suser, that is, (n+m)*Soriginal≤Suser. Therefore, the maximum number is K=n+m≤Suser / Soriginal.

[0032] For example, if the original data size is 128 bytes, the user data area size of the codeword is 1024 bytes, and redundant data is not considered, the maximum number is n+m≤1024 / 128=8. This means that a maximum of 8 combinations of original data and inverted data can be stored, such as 5 original data and 3 inverted data, or 4 original data and 4 inverted data, etc., as long as the total number does not exceed 8.

[0033] When determining the number of original data n and the number of negated data m, it is necessary to comprehensively consider factors such as storage space utilization and data reliability requirements. Generally speaking, increasing the number of original data n can increase data redundancy and thus enhance data reliability, but it will reduce storage space utilization; while increasing the number of negated data m can improve error correction capabilities to a certain extent, but it will also affect storage space utilization. Therefore, it is necessary to determine the appropriate n and m values ​​based on specific application scenarios and requirements.

[0034] Assuming that the maximum number is 8, if the data reliability requirement is high, n can be set to 5 and m can be set to 3, that is, 5 copies of the original data and 3 copies of the inverted data are stored; if the storage space utilization requirement is high, n can be set to 6 and m can be set to 2, that is, 6 copies of the original data and 2 copies of the inverted data are stored.

[0035] Combine n original data, m inverted data and redundant data in a certain order or rule to form a user data area of ​​the codeword. For example, n original data can be arranged in sequence first, and then m inverted data can be arranged in sequence after the original data, and finally the redundant data can be added after the inverted data to form a complete user data area. Redundant data can be used to improve the error correction capability of data, for example, it can be a redundant bit for parity check, or redundant data generated by other error correction coding algorithms. In this embodiment, the redundant data consists of data 0.

[0036] Verification data is additional data used to verify and correct user data, and is usually generated by an error correction coding algorithm. The verification data is separately formed into a verification data area of ​​the codeword and stored separately from the user data area. For example, in the error correction coding process, an error correction coding algorithm such as an EEC code can be used to encode user data, generate corresponding verification data, and then store the verification data in the verification data area.

[0037] ECC error correction is a key mechanism to ensure the correctness of flash memory data. It sacrifices part of the data storage space in exchange for data reliability. When writing data, the ECC algorithm is used to encode and generate check information, and the user data area is written to the flash memory together with the ECC check information.

[0038] The user data area and the check data area of ​​the codeword are combined together according to a certain format or structure to form a complete codeword.

[0039] Reference Figure 6 , generate a code word H, H includes an error correction code word user data area composed of n copies of original data, m copies of inverted data and redundant data, and an error correction code word check data area composed of check data backup C, the n copies of original data are backup data X1, backup data X2, ..., backup data Xn, and the m copies of inverted data are backup data Xb1, backup data Xb2, ..., backup data Xbn.

[0040] For step S140, the codeword is inverted to obtain an inverted codeword.

[0041] For step S150, the number p of code words and the number q of inverted code words are determined according to the storage space and reliability requirements of the flash memory.

[0042] Understand the total available storage space of the current flash memory device. For example, suppose the flash memory has a total storage space of 10GB, and the area that can be used to store the original and inverted codewords is a part of it, assuming 5GB. Calculate how many copies can be stored based on the size of the codeword and the inverted codeword. For example, if each codeword is 1qB, and the inverted data is also 1qB (the inversion operation itself does not change the storage size of the data), then in the 5GB storage area, a maximum of 5×1024=5120 copies of such data can be stored. If it is set to store p copies of the codeword and q copies of the inverted codeword, p+q≤5120 must be satisfied.

[0043] The ratio of p and q is weighed based on the expectation of data reliability. Generally speaking, higher reliability requires more redundant data. For example, if during the data storage and reading process, in order to be able to restore the original information through other data when part of the data is damaged, it is often necessary to set a certain redundancy ratio.

[0044] For example, in order to achieve higher reliability, 3 copies of the codeword and 1 copy of the inverted codeword (i.e., p=3, q=1) can be set, so that when data needs to be restored, there are multiple redundant sources for verification and repair. However, the utilization of the storage space is relatively low at this time, because the total storage unit is used more for redundant data. On average, assuming that the storage space required for each codeword is S, the total storage requirement is 3S+1S=4S. If there is a higher requirement for storage space utilization, the redundancy ratio can be reduced, such as p=2, q=1. At this time, the storage requirement is 3S, the space utilization is higher, but the data reliability is relatively reduced.

[0045] A balance needs to be found between storage space and reliability. For example, after comprehensive consideration, p=3, q=1 or a similar combination may be set to meet basic reliability requirements while minimizing excessive storage space usage.

[0046] Reference Figure 7 , p parts of code words are recorded as H1, H2, ..., Hp; q parts of opposite code words are recorded as Hb1, Hb2, ..., Hbq.

[0047] For step S160, p portions of codewords and q portions of inverted codewords are written into the flash memory.

[0048] Determine the storage location. Flash memory has multiple storage units, each with a specific address. You need to plan in advance which address areas the stored codewords and inverted codewords will be written to. For example, the first copy of the codeword is written to addresses 0x00000000 to 0x00000FFF, the second copy is written to 0x00001000 to 0x00001FFF, and so on. The inverted codewords are assigned to subsequent address segments in sequence.

[0049] Clear the storage unit. Before writing, it is usually necessary to erase the target storage area. Because the writing of flash memory depends on erasing, all bits are 1 after erasing, and then 0 can be written. If data is written directly to the unerased area, writing may fail or the data may be incomplete.

[0050] The microcontroller performs the write operation through the flash memory controller. The controller writes the codeword and the inverted codeword into the corresponding storage unit of the flash memory in sequence according to the pre-planned address and data sequence. For example, the controller first sends a write instruction to the flash memory, specifies the first address and transmits the first data of the codeword. After receiving the instruction, the flash memory writes the data to the storage unit corresponding to the address. And so on, until all n codewords and m inverted codewords are written.

[0051] It should be noted that the location area where the n copies of the codewords to be backed up and the m copies of the inverted codewords are written in the flash memory is the same or has the same storage characteristics. The factors and degrees of data flipping that affect the two types of backup data are as similar as possible. For example, they are stored in the same flash memory block, page, and page offset. These same storage areas can be determined based on the flash memory characteristic analysis data. That is, the n copies of the codewords to be backed up and the m copies of the inverted codewords are written in the same block, the same page, or the same page offset in the flash memory.

[0052] Perform data verification operations after writing is complete. For example, read back the stored data and compare it with the expected data to ensure that the written data is correct. For example, after writing is completed, the controller will read some or all of the data from the flash memory and then compare it with the codeword and the inverted codeword before sending to check if there are any differences. If a difference is found, it may be necessary to rewrite or other error correction measures to ensure the accuracy of the data.

[0053] It is understandable that flash memory write operations have specific limitations and characteristics, such as the limited erase and write life of each storage unit, and frequent erase and write operations will cause flash memory performance to degrade or even damage. Therefore, when performing multiple write operations, the flash memory controller will automatically and reasonably arrange the storage location and erase and write times to avoid excessive wear on the same storage unit.

[0054] Another embodiment of the present application provides a flash memory data reading method. The data in the flash memory is backed up according to the above flash memory data storage method.

[0055] Reference Figure 3 , a flash memory data reading method, comprising the following steps: Step S210, obtaining a first data storage address of data to be read; Step S220, reading at least one code word and at least one inverted code word from the flash memory according to the first data storage address; Step S230, inverting the inverted codeword to obtain a restored codeword; Step S240, comparing and adjusting the code word and the restored code word in terms of bits to obtain a valid code word; Step S250, extracting original data and inverted data from the user data area of ​​the valid codeword; Step S260, inverting the inverted data to obtain restored data; Step S270, comparing and adjusting the original data and the restored data in terms of bits to obtain first valid data; Step S280, replacing the user data area of ​​the first valid data with the first valid data and the redundant data to obtain the second valid data; Step S290, performing error correction decoding on the second valid data according to the verification data in the verification data area of ​​the second valid data to obtain target read data.

[0056] For step S210, the first data storage address of the data to be read is obtained. For example, the data storage address of the data to be read is obtained by querying the address mapping table maintained by the flash memory as the first data storage address. The address mapping table stores the mapping of logical addresses to physical addresses. When data needs to be read, the corresponding physical address is first searched in the mapping table according to the logical address (such as the file offset address in the file system). For example, assuming that the logical address is 0x00123456, and the physical address corresponding to the logical address is recorded in the mapping table as 0x87654321, then data is read starting from the physical address 0x87654321.

[0057] For step S220, at least one codeword and at least one inverted codeword are read from the flash memory according to the first data storage address. Specifically, the first data storage address is used as a starting point to read data from the flash memory according to a preset order or rule. For example, assuming that the first data storage address corresponds to the first unit storing the original data, the controller will start from this address and read the subsequent several units in sequence, which may include multiple codewords and inverted codewords.

[0058] For step S230, the inverted codeword is inverted to obtain the restored codeword. Specifically, in the storage stage, the inverted codeword is obtained by flipping each bit of the codeword; now, the inverted codeword is inverted again, that is, each bit of it is flipped again. For example, the inverted codeword is 10010101, and after inversion, 01101010 is obtained. At this time, the restored codeword should be the same as the corresponding codeword.

[0059] Reference Figure 4 For step S240, the code word and the restored code word are compared and adjusted in bit positions to obtain a valid code word, including the following steps: Step S241, counting a first number of data 0s and a second number of data 1s at the same bit position in the user data area of ​​the codeword and the user data area of ​​the restored codeword; Step S242, when the first number is greater than the second number, determining that the first candidate data of the bit is data 0; Step S243, when the first number is less than the second number, determining that the first candidate data of the bit is data 1; Step S244, combining the first candidate data of each bit position to obtain a valid code word.

[0060] Compare the user data area of ​​the codeword and the user data area of ​​the restored codeword bit by bit to check the difference between the two in each bit. For example, if the user data area of ​​the codeword is 0 at a certain bit, and the user data area of ​​the restored codeword is 1 at the corresponding bit, it means that there may be an error in the bit.

[0061] Reference Figure 8 , read the codeword and restore the codeword, respectively recorded as: rH1, rH2, ..., rHp; rHb1, rHb2, ..., rHbq. Invert the inverted data backup one by one according to the bit position to obtain rHbb1, rHbb2, ..., rHbbq. Statistically determine rH1, rH2, ..., rHp and rHbb1, rHbb2, ..., rHbbq according to the bit position to obtain the first candidate data R. Further, count the number of 0s and 1s at the same bit position of rH1, rH2, ..., rHp and rHbb1, rHbb2, ..., rHbbq. If 1 is more than 0, the first candidate data is determined to be 1 at the same position in R, otherwise it is 0. Combine the first candidate data of each bit position to obtain a valid codeword.

[0062] For step S250, the original data and the inverted data are extracted from the user data area of ​​the valid codeword. The user data area of ​​the valid codeword contains the original data, the inverted data and the redundant data. The original data is extracted from the user data area according to the structure and size of the user data area, the size and quantity of the original data. The inverted data is extracted from the user data area according to the structure and size of the user data area, the size and quantity of the inverted data.

[0063] The original data and restored data in the user data area are extracted and recorded as: rX1, rX2, ..., rXn; rXb0, rXb1, ..., rXbm.

[0064] For step S260, the inverted data is inverted to obtain the restored data. The m portions of rXb1, rXb2, ..., rXbm are inverted bit by bit to obtain rXbb1, rXbb2, ..., rXbbm.

[0065] Reference Figure 5 For step S270, the original data and the restored data are compared and adjusted on the bit position to obtain the first valid data, including the following steps: Step S271, aligning original data and restored data; Step S272, counting a third number of data 0s and a fourth number of data 1s at the same bit position of the original data and the restored data; Step S273, when the third number is greater than the fourth number, determining that the second candidate data of the bit is data 0; Step S274, when the third number is less than the fourth number, determining the second candidate data of the bit position is data 1; Step S275, combining the second candidate data of each bit position to obtain the first valid data.

[0066] Align all the original data and restored data on the first bit; then the original data and restored data will correspond one to one on subsequent bits.

[0067] The number of 0s and 1s at the same bit positions of rX1, rX2, ..., rXn and rXbb1, rXbb2, ..., rXbbm is counted, and if 1 is greater than 0, the second candidate data is determined to be 1, otherwise 0. The first valid data is obtained by combining the second candidate data of each bit.

[0068] For step S280, the user data area of ​​the first valid data is replaced with the first valid data and the redundant data to obtain the second valid data. Specifically, the user data area includes a copy of the first valid data, and the other positions are filled with redundant data, and the redundant data consists of data 0. The second valid data is composed of the user data area and the check data area. Fig. 9 , the user data area of ​​the code word R is replaced with the first valid data and redundant data to obtain the code word T.

[0069] For step S290, error correction decoding is performed on the second valid data according to the check data in the check data area of ​​the second valid data to obtain target read data. Specifically, the check data is ECC check information.

[0070] When reading data, both valid information and ECC check information are read from the flash memory. Through ECC decoding and error correction operations, it can be ensured that correct data can be read within the correctable error range.

[0071] The second valid data is decoded for error correction. When the decoding is correct, the target read data is obtained. When the decoding is wrong, the second data storage address of the data to be read is obtained, the second original data and the second inverted data corresponding to the data to be read are read from the second data storage address, the second inverted data is inverted to obtain the second restored data, the second original data and the second restored data are compared and adjusted on the bit position to obtain the second adjusted data, and the second adjusted data is decoded for error correction to obtain the target read data. The second data storage address is different from the first data storage address. If the decoding is incorrect, continue to search for other backups until all backups are tried.

[0072] On the basis of storing the original data, the inverted data is additionally stored, and the probability of obtaining the correct data is increased by reading the combination of the original data and the inverted data.

[0073] The following are some examples: Assume that the original data has only 1 bit, and store 2 backups, recorded as X1 and X2; the inverted data is Xb1 and Xb2; write the original data and the differentiated data into the flash memory in 4 copies. When reading data, the original data and the inverted data read from the flash memory are recorded as: Y1, Y2, Yb1, Yb2. Then, Yb1 and Yb2 are inverted to obtain Ybb1 and Ybb2. After sorting, the data read from the flash memory is: Y1, Y2, Ybb1, Ybb2. When counting the number of 0s and 1s in Y1, Y2, Ybb1, and Ybb2, if 1 is greater than 0, the final data is determined to be 1, otherwise it is 0.

[0074] First assume that the original data is 1, then X1=X2=1,Xb1=Xb2=0.

[0075] For the case where the probability of 0 flipping to 1 P0->1 is greater than the probability of 1 flipping to 0 P1->0 (i.e.: P0->1>P1->0). The read data Y1 and Y2 correspond to the written data X1 and X2, both of which are 1. Since the probability of 1 flipping to 0 is low, assuming that neither flips, then (Y1,Y2)=(1,1). The read data Yb1 and Yb2 correspond to the written data Xb1 and Xb2, both of which are 0. Since the probability of 0 flipping to 1 is high, assuming that the flip rate is 50%, then (Yb1,Yb2) can be (1,0) or (0,1). Here, (1,0) is taken, and after inversion, Ybb1 and Ybb2 are (0,1). Finally, (Y1,Y2, Ybb1,Ybb2)=(1,1,0,1), the number of 1s is 3, the number of 0s is 1, and the final data is determined to be 1.

[0076] The probability of 0 flipping to 1 P0->1 is less than the probability of 1 flipping to 0 P1->0 (i.e.: P0->1 <p1->0). The read data Y1 and Y2 correspond to the written data X1 and X2, both of which are 1. Since the probability of 1 flipping to 0 is high, assuming the flip rate is 50%, (Y1, Y2) can be (1, 0) or (0, 1), and (1, 0) is taken here. The read data Yb1 and Yb2 correspond to the written data Xb1 and Xb2, both of which are 0. Since the probability of 0 flipping to 1 is low, assuming no flipping, (Yb1, Yb2) = (0, 0), and after inversion, Ybb1 and Ybb2 are (1, 1). Finally, (Y1, Y2, Ybb1, Ybb2) = (1, 0, 1, 1), the number of 1s is 3, the number of 0s is 1, and the final data is also judged to be 1.

[0077] When P0->1=P1->0, the error probabilities are equal, and the probability of determining that the final data is 1 is 50%.

[0078] The above writing, reading, and judging process is similar when the original data is 0. It can be seen that the probability of reading the correct data can be increased by adding the inverted data backup.

[0079] Another embodiment of the present application provides a flash memory, to which the above flash memory data storage method and flash memory data reading method are applied.

[0080] Reference Fig.10 The flash memory includes a storage controller and flash memory particles, and the storage controller is connected to the flash memory particles.

[0081] The storage controller is responsible for coordinating and managing the data interaction between the flash memory particles and the external host. It receives data from the external host and writes the data into the flash memory particles for storage; at the same time, it also reads data from the flash memory particles and then transmits the data back to the external host to ensure the correct storage and reading of data.

[0082] The data is stored in the flash memory particles. The storage controller reads the data from the external host and writes the data into the flash memory particles. The storage controller reads the data from the flash memory particles and transmits the data to the external host.

[0083] The storage controller includes a codeword adjustment control module and an error correction control module; the codeword adjustment control module is used to perform codeword related operations; the error correction control module is used to perform error correction decoding operations.

[0084] The codeword adjustment control module performs the following codeword related operations: filling redundant data inside the codeword, filling multiple copies of the same data inside the codeword, and performing an inversion operation on the codeword.

[0085] The error correction control module is responsible for performing error correction decoding operations to detect and correct errors that may occur during data storage and reading. During the data reading process, if an error is detected in the data, the error correction control module will calculate the location and value of the error based on the error correction coding algorithm and correct it to ensure the accuracy and integrity of the data.

[0086] The storage controller also includes a protocol interface control module, a system processor and a system cache. The codeword adjustment control module and the error correction control module are arranged in the flash memory read-write control module. The protocol interface control module, the system processor and the system cache are connected to the flash memory read-write control module through an internal bus.

[0087] The protocol interface control module is responsible for converting and controlling the communication protocol with the external host to ensure that the flash memory system is compatible and can communicate with different types of external hosts. It usually supports multiple storage protocols, such as SATA, SAS, NVMe, etc. According to the protocol requirements of the external host, it converts and processes the commands and data sent by the host, and then passes them to the flash read and write control module for corresponding operations. At the same time, it also encapsulates and sends the data and status information returned by the flash memory system according to the protocol format of the host to achieve normal communication with the external host.

[0088] The system processor is the central processing unit of the storage controller and is responsible for the management and control of the entire flash memory system. It coordinates the work between various modules and performs various system-level tasks and operations, such as initialization, configuration, and monitoring. For example, when the system starts, the system processor will initialize each module and set the working mode and parameters of the storage controller; during the data reading and writing process, it will monitor the data transmission status, coordinate the work of the codeword adjustment control module, error correction control module, and protocol interface control module, and ensure the correct processing and transmission of data.

[0089] The system cache is used to temporarily store data and information to improve the speed and efficiency of data reading and writing. During the data writing process, the system cache can temporarily store the data received from the external host, waiting for the storage controller to write the data to the flash memory particles; during the data reading process, it can cache the data read from the flash memory particles so as to quickly transmit the data to the external host. In addition, the system cache can also be used to store some system configuration information, status information, etc., so that the system processor can quickly access and process this information.

[0090] The flash memory read and write control module also includes a bus and register module, a flash memory bus timing module, a data transmission control module and a cache.

[0091] The bus and register module is responsible for managing the bus communication and register operations within the flash read and write control module. It provides a bus interface for data transmission and communication between various sub-modules, ensuring that data can be transmitted quickly and accurately between different sub-modules. At the same time, it also contains some registers for storing various control information, status information, and data information so that other sub-modules can access and use this information.

[0092] The flash bus timing module is responsible for controlling the bus timing of the flash memory particles to ensure that data can be written or read at the correct time. It generates corresponding timing signals according to the characteristics and requirements of the flash memory particles to control the transmission and access of data. For example, during the data writing process, it controls the write timing to ensure that the data can be correctly written within the write window period of the flash memory particles; during the data reading process, it controls the read timing to ensure that the data can be read out at the correct time.

[0093] The data transfer control module is responsible for controlling the data transfer process between the flash read / write control module and the flash memory particles. It divides the data into data blocks of appropriate size according to the commands and data of the storage controller, and then writes the data blocks one by one into the flash memory particles through the flash bus timing module; during the data reading process, it reads the data blocks one by one from the flash memory particles, then combines the data blocks into complete data, and transmits the data to the storage controller through the bus and register module.

[0094] The cache is used to temporarily store data to improve the speed and efficiency of data reading and writing. During the data writing process, the cache can temporarily store the data received from the storage controller and wait for the flash memory particles to have free storage space before writing the data; during the data reading process, it can cache the data read from the flash memory particles so that the data can be quickly transferred to the storage controller. In addition, the cache can also be used to store some intermediate data and information so that the data transmission control module can perform data transmission and processing more efficiently.

[0095] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Technical personnel familiar with the field can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A flash memory data storage method, characterized in that: include: Obtain the original data to be backed up; Inverting the original data to obtain inverted data; The original data, the inverted data, the redundant data and the check data constitute a codeword; Inverting the codeword to obtain an inverted codeword; Determine the number of code words p and the number of inverted code words q according to the storage space and reliability requirements of the flash memory; Write p copies of the codeword and q copies of the inverted codeword into the flash memory.

2. The flash memory data storage method according to claim 1, characterized in that: The forming of a codeword from the original data, the inverted data, the redundant data and the check data comprises: Obtaining the size of the original data and the size of the user data area of ​​the codeword; Determine the maximum number of original data and inverted data according to the size of the original data and the size of the user data area of ​​the codeword; Determine the number n of the original data and the number m of the negated data according to the maximum number; The n copies of the original data, the m copies of the inverted data and the redundant data constitute a user data area of ​​the codeword; the check data constitutes a check data area of ​​the codeword; The user data area and the check data area constitute a codeword.

3. The flash memory data storage method according to claim 1, characterized in that: The location areas where the p copies of the codeword and the q copies of the inverted codeword are written in the flash memory are the same or have the same storage characteristics.

4. The flash memory data storage method according to claim 1, characterized in that: Writing the p copies of the codeword and the q copies of the inverted codeword into the flash memory comprises: The p copies of the codeword and the q copies of the inverted codeword are written into the same block, the same page or the same offset within the page of the flash memory.

5. The flash memory data storage method according to claim 1, characterized in that: The redundant data consists of data 0.

6. A flash memory data reading method, characterized in that: The data in the flash memory is backed up according to the flash memory data storage method according to any one of claims 1 to 5; The flash memory data reading method comprises: Obtain a first data storage address of data to be read; Read at least one codeword and at least one inverted codeword from the flash memory according to the first data storage address; Inverting the inverted codeword to obtain a restored codeword; Compare and adjust the code word and the restored code word on the bit position to obtain a valid code word; Extracting the original data and the inverted data from the user data area of ​​the valid codeword; Inverting the inverted data to obtain restored data; Compare and adjust the original data and the restored data on a bit basis to obtain first valid data; Replacing the user data area of ​​the first valid data with the first valid data and redundant data to obtain second valid data; The second valid data is subjected to error correction decoding according to the verification data in the verification data area of ​​the second valid data to obtain target read data.

7. The flash memory data reading method according to claim 6, characterized in that: The step of comparing and adjusting the code word and the restored code word on the bit position to obtain a valid code word includes: Counting a first number of data 0s and a second number of data 1s at the same bit position in the user data area of ​​the codeword and the user data area of ​​the restored codeword; When the first number is greater than the second number, determining that the first candidate data of the bit position is data 0; When the first number is less than the second number, determining that the first candidate data of the bit position is data 1; The first candidate data of each bit is combined to obtain a valid code word.

8. The flash memory data reading method according to claim 6, characterized in that: The step of comparing and adjusting the original data and the restored data on a bit basis to obtain first valid data comprises: aligning the original data and the restored data; Counting a third number of data 0s and a fourth number of data 1s at the same bit position of the original data and the restored data; When the third number is greater than the fourth number, determining that the second candidate data of the bit is data 0; When the third number is less than the fourth number, determining that the second candidate data of the bit is data 1; The second candidate data of each bit is combined to obtain the first valid data.

9. A flash memory, characterized in that: The flash memory application comprises a flash memory data storage method as described in any one of claims 1 to 5 and a flash memory data reading method as described in any one of claims 6 to 8; the flash memory comprises a storage controller and flash memory particles, and the storage controller is connected to the flash memory particles; the storage controller comprises a codeword adjustment control module and an error correction control module; the codeword adjustment control module is used to perform codeword related operations; the error correction control module is used to perform error correction decoding operations.

10. The flash memory according to claim 9, characterized in that: The storage controller also includes a protocol interface control module, a system processor and a system cache. The codeword adjustment control module and the error correction control module are arranged in a flash memory read-write control module. The protocol interface control module, the system processor and the system cache are connected to the flash memory read-write control module via an internal bus.

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