Data processing method and device, electronic equipment and storage medium
By adjusting the encoding verification parameters, the problem of redundant data in data processing in the prior art is solved, data processing efficiency is improved and redundant data storage and reading are reduced.
Patent Information
- Application Number
- CN202411987737.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-13
AI Technical Summary
In the existing data processing methods, there are a lot of redundant data in the encoding verification process of data, resulting in low processing efficiency and redundant data during reading and writing data.
By obtaining the control parameter information during data retransmission, the redundant version number and data block parameters are obtained, and the encoding verification parameters are adjusted according to different redundant version number conditions to reduce the storage and reading of redundant data.
It reduces redundant data during the encoding verification process, improves data processing efficiency, and reduces processing time and calculation amount.
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Figure CN119988086A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to computer technology, and in particular to a data processing method, device, electronic device and storage medium. Background Art
[0002] In the current data processing method, there is a lot of redundant data after the coding verification of the data, the coding verification processing time is long, and the calculation amount of the verification process is large. At the same time, when reading the data after the coding verification processing, since a lot of redundant data will also be stored and read, the current data processing method has the problem of low data processing efficiency and redundant data in the process of reading and writing data. Summary of the invention
[0003] Embodiments of the present application provide a data processing method, device, electronic device, and storage medium.
[0004] According to a first aspect of the present application, a data processing method is provided, the method comprising: obtaining control parameter information in a data retransmission process;
[0005] Performing parameter parsing on the control parameter information to obtain a redundant version number and data block parameters;
[0006] In response to the redundant version number satisfying the first condition, adjusting the coding verification parameter corresponding to the data block based on the data block parameter, and performing coding verification processing on the data block according to the adjusted coding verification parameter;
[0007] In response to the redundant version number satisfying the second condition, obtaining the adjusted coding verification parameter; reading the corresponding data block based on the adjusted coding verification parameter; merging the retransmitted data based on the read data block; the redundant version number satisfying the first condition is smaller than the redundant version number satisfying the second condition.
[0008] According to an implementation manner of the present application, adjusting the encoding check parameter corresponding to the data block based on the data block parameter includes:
[0009] The data block parameters include at least: circular buffer size, original bit length and code block quantity;
[0010] Based on the data block parameters, determining a check matrix length corresponding to the coding check processing;
[0011] The coding check parameter is adjusted based on the check matrix length to obtain the adjusted coding check parameter.
[0012] According to an implementation manner of the present application, determining the check matrix length corresponding to the coding check processing based on the data block parameters includes:
[0013] Determining a first bit position in the circular buffer based on the circular buffer size and the set expansion factor;
[0014] Determining a coded bit length corresponding to the original bit length; the coded bit length is less than the original bit length;
[0015] Performing a modulus calculation based on the first bit position, the coded bit length, and the circular buffer size to obtain a modulus value of the coded bit length within the range of the circular buffer size;
[0016] The check matrix length is determined based on the modulus value and the first bit position.
[0017] According to an implementation manner of the present application, the adjusting the coding check parameter based on the check matrix length to obtain the adjusted coding check parameter includes:
[0018] Determining the basic matrix length of the coding verification processing;
[0019] Based on the basic matrix length, the set extension factor and the check matrix length, adjusting the decoding length included in the coding check parameter to obtain an adjusted decoding length;
[0020] The adjusted decoding length is smaller than the decoding length before adjustment.
[0021] According to an embodiment of the present application, determining the first bit position in the circular buffer based on the circular buffer size and the set expansion factor includes:
[0022] Based on the data block parameters, determining a basic graph matrix corresponding to the encoding verification process;
[0023] A first bit position in the circular buffer is determined based on the base graph matrix, the circular buffer size, and a set expansion factor.
[0024] According to an embodiment of the present application, before performing coding verification processing on the data block according to the adjusted coding verification parameter, the method further includes:
[0025] Performing rate dematching on the data block to obtain rate dematching output bits;
[0026] Combining retransmitted data on the derate matching output bits to obtain a combined data block;
[0027] The merged data block and the adjusted encoding verification parameter are sent to a memory.
[0028] According to an embodiment of the present application, the reading of the corresponding data block based on the adjusted encoding verification parameter includes:
[0029] Determine the read data length based on the decoded length included in the adjusted encoding verification parameter;
[0030] Based on the read data length, the merged data block in the memory is read once; the merged data block matches the read data length.
[0031] According to a second aspect of the present application, a data processing device is provided, the data processing device comprising:
[0032] An acquisition module, used to obtain control parameter information during data retransmission;
[0033] A parsing module, used for parsing the control parameter information to obtain a redundant version number and a data block parameter;
[0034] A decoding module, configured to adjust a coding verification parameter corresponding to the data block based on the data block parameter in response to the redundant version number satisfying a first condition, and perform coding verification processing on the data block according to the adjusted coding verification parameter;
[0035] A merging module is used to obtain the adjusted coding verification parameter in response to the redundant version number satisfying the second condition; read the corresponding data block based on the adjusted coding verification parameter; and merge the retransmitted data based on the read data block; the redundant version number that satisfies the first condition is smaller than the redundant version number that satisfies the second condition.
[0036] According to a third aspect of the present application, an electronic device is provided, including:
[0037] at least one processor; and
[0038] a memory communicatively connected to the at least one processor; wherein,
[0039] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present application.
[0040] According to a fourth aspect of the present application, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method described in the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become readily understood. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, wherein:
[0042] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.
[0043] Figure 1 The processing flow diagram of the data processing method provided in the embodiment of the present application is shown in FIG. Figure 1 ;
[0044] Figure 2 The processing flow diagram of the data processing method provided in the embodiment of the present application is shown in FIG. Figure 2 ;
[0045] Figure 3 The processing flow diagram of the data processing method provided in the embodiment of the present application is shown in FIG. Figure 3 ;
[0046] Figure 4 The processing flow diagram of the data processing method provided in the embodiment of the present application is shown in FIG. Figure 4 ;
[0047] Figure 5 The processing flow diagram of the data processing method provided in the embodiment of the present application is shown in FIG. Figure 5 ;
[0048] Figure 6 The processing flow diagram of the data processing method provided in the embodiment of the present application is shown in FIG. Figure 6 ;
[0049] Figure 7 The processing flow diagram of the data processing method provided in the embodiment of the present application is shown in FIG. Figure 7 ;
[0050] Figure 8 An application scenario diagram of the data processing method provided in an embodiment of the present application is shown;
[0051] Fig. 9 An optional schematic diagram of a data processing device provided in an embodiment of the present application is shown;
[0052] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0053] In order to make the purpose, features, and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0054] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0055] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0057] The processing flow of the data processing method provided in the embodiment of the present application is described. Figure 1 , Figure 1 The processing flow diagram of the data processing method provided in the embodiment of the present application is as follows: Figure 1 , will combine Figure 1 Steps S101-S104 are shown for explanation.
[0058] Step S101, obtaining control parameter information during data retransmission.
[0059] Step S102: parse the control parameter information to obtain a redundant version number and data block parameters.
[0060] In some embodiments, in some embodiments, the control parameter information sent by the PHY (physical layer) is obtained. The redundancy version number may include: RV version number. The RV version number defines the starting position of each HARQ (hybrid automatic repeat request) subpacket in the buffer, and different RV version numbers correspond to different data segments in the coded bit stream. Specifically, the RV version number may include: RV=0, RV=2, RV=3 and RV=1. The data block parameters may include: N cb(circular buffer size), N (raw bit length) and CB (number of code blocks).
[0061] Step S103 , in response to the redundant version number satisfying the first condition, adjusting the coding verification parameters corresponding to the data block based on the data block parameters, and performing coding verification processing on the data block according to the adjusted coding verification parameters.
[0062] In this embodiment, when RV=2, it can be determined that the redundant version number satisfies the first condition. RV=2 can represent a data retransmission. The data block may include a transmission data block. The transmission data block may include multiple code blocks. The coding check processing may include: LDPC (Low-Density Parity-Check) decoding. The coding check processing in the embodiment of the present application may also include other coding check processing methods, which are not limited in the embodiment of the present application. The coding check parameters may include: the data length during the LDPC decoding process.
[0063] Step S104, in response to the redundant version number satisfying the second condition, obtaining an adjusted coding verification parameter; reading a corresponding data block based on the adjusted coding verification parameter; merging retransmitted data based on the read data block; the redundant version number satisfying the first condition is smaller than the redundant version number satisfying the second condition.
[0064] In this embodiment, when RV=3, it can be determined that the redundant version number satisfies the second condition. RV=3 can represent secondary data retransmission. The secondary data retransmission is after the first data retransmission. Retransmission data merging based on the read data block may include: merging the read data block with the data block of the initial data transmission. The data block of the initial data transmission may be a data block in the data processing process when RV=0. Retransmission data merging may include: HARQ (Hybrid Automatic Repeat reQuest). The retransmission data merging in the embodiment of the present application may also include other retransmission data merging methods, which are not limited in the embodiment of the present application. The adjusted coding check parameters may include: the data length in the adjusted LDPC processing process during a data retransmission process.
[0065] As an example, PHY first sends control parameter information, and FPGA (Field-Programmable Gate Array) parses the control parameter information to obtain the RV version number and data block parameters. The data block parameters may include: cb, N and CB. When RV=2, FPGA detects CB in the transmission data block. If CB is greater than 1, the coding check parameters of the LDPC decoding corresponding to the data block are adjusted based on the data block parameters. The corresponding data length is read according to the coding check parameters for processing, and the data corresponding to the data length is written to DDR (Double Data Rate). When RV=3, FPGA reads the data block stored when RV=2 from DDR according to the data length, and then performs HARQ merging processing.
[0066] The method of the embodiment of the present application obtains the redundant version number and data block parameters by parsing the control parameter information, and then adjusts the coding verification parameters according to different redundant version number conditions, thereby reducing the zero padding processing in the coding verification process, thereby reducing the processing time and calculation amount of the coding verification process. By dynamically adjusting the coding verification parameters, redundant data in the storage and reading process is reduced, and data processing efficiency is improved.
[0067] In some embodiments, the processing flow of the data processing method is shown as follows: Figure 2 ,like Figure 2 As shown, adjusting the encoding verification parameters corresponding to the data block based on the data block parameters in step S103 may specifically include:
[0068] Step S201: Determine the length of the check matrix corresponding to the coding check process based on the data block parameters.
[0069] In this embodiment, based on the size of the circular buffer and the set expansion factor, the first bit position (k 0 ). The first bit position can indicate the retransmission start position. Determine the coded bit length (E) corresponding to the original bit length. The coded bit length is less than the original bit length. When the FPGA processes data retransmission and identifies CB=1, obtain the k corresponding to the data block. 0 and E. Based on k 0 and E, adjust the length of the check matrix corresponding to LDPC decoding.
[0070] Step S202: adjusting the coding check parameter based on the check matrix length to obtain the adjusted coding check parameter.
[0071] In this embodiment, the basic matrix length of LDPC decoding is determined. The decoding length included in the coding check parameter is adjusted based on the basic matrix length and the check matrix length to obtain the adjusted coding check parameter. The coding check parameters of LDPC decoding may include parameters such as code rate, decoding length and number of iterations. The coding check parameters may also include other parameters, which are not limited in the embodiments of the present application. The code rate is related to the basic matrix length and the check matrix length. kb / (mb+kb)=code rate, where kb represents the basic matrix length and mb represents the check matrix length.
[0072] The method of the embodiment of the present application determines the check matrix length by including the size of the circular buffer, the original bit length and the number of code blocks, and then adjusts the coding check parameters. Based on the parameter adjustment strategy of the data block characteristics, the obtained coding check parameters are more in line with the actual data characteristics in the coding check process, reducing the zero padding operation in the coding check process, thereby reducing the processing time and calculation amount of the coding check process. By dynamically adjusting the coding check parameters, redundant data in the storage and reading process is reduced, and data processing efficiency is improved.
[0073] In some embodiments, the processing flow of the data processing method is shown as follows: Figure 3 ,like Figure 3 As shown, determining the check matrix length corresponding to the coding check processing based on the data block parameters in step S201 may specifically include:
[0074] Step S301, determining the first bit position in the circular buffer based on the circular buffer size and the set expansion factor.
[0075] Step S302, determining the coded bit length corresponding to the original bit length; the coded bit length is smaller than the original bit length.
[0076] In this embodiment, the expansion factor may include: in the LDPC decoding process, the expansion factor is used to expand the original codeword to a multiple of the longer codeword. The expansion factor can be used to expand each element (usually 0 or 1) in the basic matrix into a Z c x Z c The first bit position may include: in the circular buffer, when CB=1, the retransmission start position corresponding to the data block. The first bit position may be based on the circular buffer size and the expansion factor (Z c ) value to calculate.
[0077] Step S303, performing a modulus calculation based on the first bit position, the coded bit length and the size of the circular buffer, to obtain a modulus value of the coded bit length within the range of the size of the circular buffer.
[0078] Step S304: determine the length of the check matrix based on the modulus value and the first bit position.
[0079] As an example, the modulo calculation based on the first bit position, the coded bit length and the circular buffer size can be expressed as mod(k 0 +E,N cb ). The coding bit length can range from k 0 and mod(k 0 +E,N cb ). In the case of RV = 2, assuming that N cb The maximum value is 25344 bytes. In this case, k 0 The starting position is 12672 bytes, based on mod(k 0 +E,N cb ) and k 0 , you can determine that the mb is set to 37.
[0080] The method of the embodiment of the present application determines the corresponding check matrix length by calculating the modulus of the first bit position and the coding bit length in the circular buffer. The coding check processing can accurately match the actual length of the data block, avoiding unnecessary zero padding operations and redundant data. Thereby reducing the processing time and calculation amount of the coding check process. By dynamically adjusting the coding check parameters, the redundant data in the storage and reading process is reduced, and the data processing efficiency is improved.
[0081] In some embodiments, the processing flow of the data processing method is shown as follows: Figure 4 ,like Figure 4 As shown, the coding check parameter is adjusted based on the check matrix length in step S202 to obtain the adjusted coding check parameter, which may specifically include:
[0082] Step S401, determining the length of the basic matrix for coding verification processing.
[0083] Step S402: Based on the basic matrix length, the set extension factor and the check matrix length, the decoding length included in the coding check parameter is adjusted to obtain an adjusted decoding length.
[0084] In this embodiment, the basic matrix length of LDPC decoding is first determined according to MCS (Modulation and Coding Scheme). The value obtained by adding the basic matrix length and the check matrix length is multiplied by the expansion factor to obtain the decoding length of LDPC decoding. LDPC decoding is performed with the adjusted decoding length of LDPC decoding, which can reduce the decoding time by 10%.
[0085] As an example, determine kb of LDPC. Based on kb, Zc and mb, adjust the decoding length included in the coding verification parameters to obtain the adjusted decoding length. According to the adjusted decoding length, take (mb+kb)*Z in the LDPC input processing module c The data of the specified length is sent to the LDPC decoding module for LDPC decoding.
[0086] The method of the embodiment of the present application adjusts the decoding length by the basic matrix length and the check matrix length, and the adjusted decoding length is less than the length before adjustment. The coding check processing can accurately match the actual length of the data block, avoiding unnecessary zero padding operations and redundant data. Thus, the processing time and calculation amount of the coding check process are reduced. By dynamically adjusting the coding check parameters, redundant data in the storage and reading process is reduced, and the data processing efficiency is improved.
[0087] In some embodiments, the processing flow of the data processing method is shown as follows: Figure 5 ,like Figure 5 As shown, the data processing method may further include:
[0088] Step S501, determining a basic graph matrix corresponding to the coding verification process based on the data block parameters.
[0089] Step S502: determining the first bit position in the circular buffer based on the basic graph matrix, the circular buffer size and the set expansion factor.
[0090] In this embodiment, the data block parameters may further include: a transmission data block size and a code rate of the first transmission. According to the transmission data block size and the code rate of the first transmission, a basic graph matrix corresponding to LDPC decoding may be determined.
[0091] As an example, based on the basic graph matrix, the circular buffer size and the set expansion factor, the first bit position in the circular buffer is determined as shown in Table 1 below:
[0092] Table 1
[0093]
[0094] Among them, rv id Represents the redundant version number, and the LDPC factor graph represents the basic graph matrix corresponding to LDPC decoding. Figure 2 The scope of application needs to meet at least one of the following three conditions: (1) the transmission data block is not larger than 292 bits; (2) the size of the transmission data block is between 292 bits and 3824 bits, and the code rate of the first transmission is not higher than 2 / 3; (3) the code rate of the first transmission of the transmission data block is not higher than 1 / 4. If the above three conditions are not met, the basic graph matrix corresponding to LDPC decoding uses the LDPC factor Figure 1 .
[0095] The method of the embodiment of the present application accurately controls the starting point of the coding verification process by determining the basic graph matrix and the first bit position. The coding verification process can accurately match the actual length of the data block, avoiding unnecessary zero padding operations and redundant data. This reduces the processing time and calculation amount of the coding verification process. By dynamically adjusting the coding verification parameters, redundant data in the storage and reading process is reduced, and data processing efficiency is improved.
[0096] In some embodiments, the processing flow of the data processing method is shown as follows: Figure 6 ,like Figure 6 As shown, before performing coding verification processing on the data block according to the adjusted coding verification parameters in step S103, the data processing method may further include:
[0097] Step S601, perform rate dematching on a data block to obtain rate dematching output bits.
[0098] Step S602: Merge retransmitted data on the rate-matching output bits to obtain a merged data block.
[0099] Step S603: Send the merged data block and the adjusted encoding verification parameters to the memory.
[0100] In this embodiment, the rate matching may include: adjusting the transmission rate of the data block to adapt to the decoding capability of the receiving end. In the rate matching process, some bits may be removed or added to the data block so that the data block can be transmitted at the corresponding rate. In the case of RV=2, the rate matching output bits are subjected to HARQ merging processing to obtain a merged data block. The merged data block and the adjusted decoding length are written into the DDR.
[0101] The method of the embodiment of the present application can integrate new and old data by de-rate matching and retransmission data merging before coding verification processing, thereby reducing data redundancy caused by retransmission. By dynamically adjusting coding verification parameters, redundant data in the storage and reading process is reduced, thereby improving data processing efficiency.
[0102] In some embodiments, the processing flow of the data processing method is shown as follows: Figure 7 ,like Figure 7 As shown, the data processing method may further include:
[0103] Step S701, determining the read data length based on the decoding length included in the adjusted encoding verification parameters.
[0104] Step S702, based on the read data length, read the merged data block in the memory once; the merged data block matches the read data length.
[0105] In this embodiment, when RV=3, the DDR CTRL (memory control) module of the FPGA determines the read data length based on the decoding length included in the adjusted coding verification parameters, reads the merged data block of the corresponding length from the DDR at one time according to the determined read data length, and then performs HARQ merging processing on the read merged data block. The merged data block matches the read data length. Reading data with the decoding length included in the adjusted coding verification parameters can reduce the DDR reading time by 10%.
[0106] The method of the embodiment of the present application determines the read data length based on the decoded length in the adjusted coding verification parameter, thereby achieving an accurate match between the read length and the data length. It reduces unnecessary data transmission and processing, and improves the efficiency of memory access. By dynamically adjusting the coding verification parameters, it reduces redundant data in the storage and reading process, and improves the data processing efficiency.
[0107] refer to Figure 8 , an application scenario diagram of the data processing method provided in an embodiment of the present application, which is applied to data processing of HARQ merging and LDPC decoding based on FPGA.
[0108] The FPGA processing flow includes:
[0109] Step S1, parameter parsing. Specifically, obtain the control parameter information sent by PHY. Parse the control parameter information to obtain the redundant version number and data block parameters. The redundant version number may include: RV version number. The RV version number defines the starting position of each HARQ subpacket in the buffer. Different RV version numbers correspond to different data segments in the coded bit stream. Specifically, the RV version number may include: RV=0, RV=2, RV=3 and RV=1. The data block parameters may include: N cb , N and CB.
[0110] Step S2, parameter processing. Specifically, when RV_SW (redundancy version number selection module) determines that RV=2, FPGA detects CB in the transmission data block. If CB>1, based on the data block parameters, the coding check parameters of the LDPC decoding corresponding to the data block are adjusted. The adjusted coding check parameters are sent to the LDPC input processing.
[0111] Step S3, rate dematching: Specifically, some bits are removed or added from the data block so that the data block can be transmitted at a corresponding rate, and rate dematching output bits are obtained.
[0112] Step S4, HARQ combining. In the case of RV=2, HARQ combining is performed on the derate matching output bits to obtain a combined data block. The combined data block and the adjusted coding check parameters are sent to the DDR CTRL. The DDR CTRL writes the data corresponding to the data length into the DDR.
[0113] When RV=3, the DDR CTRL module of the FPGA determines the read data length based on the decoding length included in the adjusted coding check parameters when RV=2, reads the merged data block of the corresponding length from the DDR at one time according to the determined read data length, and then performs HARQ merging processing on the read merged data block.
[0114] Step S5, LDPC input processing. Specifically, in the case of RV=2, the adjusted coding check parameters are sent to the LDPC decoding.
[0115] Step S6, LDPC decoding: In the case of RV=2, LDPC decoding is performed according to the adjusted coding check parameters.
[0116] The following further describes an exemplary structure of the data processing device 90 provided in the embodiment of the present application implemented as a software module. In some embodiments, for example Fig. 9 As shown, the data processing device 90 may include: an acquisition module 901, used to obtain control parameter information in the data retransmission process; a parsing module 902, used to perform parameter parsing on the control parameter information to obtain a redundant version number and data block parameters; a decoding module 903, used to adjust the encoding verification parameters corresponding to the data block based on the data block parameters in response to the redundant version number satisfying the first condition, and perform encoding verification processing on the data block according to the adjusted encoding verification parameters; a merging module 904, used to obtain the adjusted encoding verification parameters in response to the redundant version number satisfying the second condition; read the corresponding data block based on the adjusted encoding verification parameters; and merge the retransmitted data based on the read data block; the redundant version number that satisfies the first condition is less than the redundant version number that satisfies the second condition.
[0117] In some embodiments, the decoding module 903 can be used for: data block parameters include at least: circular buffer size, original bit length and number of code blocks; based on the data block parameters, determine the length of the check matrix corresponding to the coding check processing; adjust the coding check parameters based on the check matrix length to obtain adjusted coding check parameters.
[0118] In some embodiments, the decoding module 903 can be used to: determine the first bit position in the circular buffer based on the circular buffer size and the set expansion factor; determine the coded bit length corresponding to the original bit length; the coded bit length is less than the original bit length; perform a modulus calculation based on the first bit position, the coded bit length and the circular buffer size to obtain the modulus value of the coded bit length within the range of the circular buffer size; determine the check matrix length based on the modulus value and the first bit position.
[0119] In some embodiments, the decoding module 903 can be used to: determine the basic matrix length of the coding check processing; adjust the decoding length included in the coding check parameters based on the basic matrix length, the set expansion factor and the check matrix length to obtain the adjusted decoding length; the adjusted decoding length is less than the decoding length before adjustment.
[0120] In some embodiments, the decoding module 903 can be used to: determine the basic graph matrix corresponding to the encoding verification processing based on the data block parameters; determine the first bit position in the circular buffer based on the basic graph matrix, the circular buffer size and the set expansion factor.
[0121] In some embodiments, the data processing device may further include a matching module, which may be used to: perform rate matching on the data block to obtain rate matching output bits; perform retransmission data merging on the rate matching output bits to obtain a merged data block; and send the merged data block and the adjusted coding check parameters to the memory.
[0122] In some embodiments, the merge module 904 can be used to: determine the read data length based on the decoding length included in the adjusted encoding verification parameters; read the merged data block in the memory once based on the read data length; and match the merged data block with the read data length.
[0123] It should be noted that the description of the device in the embodiment of the present application is similar to the description of the method embodiment described above, and has similar beneficial effects as the method embodiment, so it will not be repeated. Figures 1 to 8 The present invention can be understood by referring to the description of any one of the accompanying drawings.
[0124] According to an embodiment of the present application, the present application also provides an electronic device and a non-transitory computer-readable storage medium.
[0125] Fig.10A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.
[0126] like Fig.10 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.
[0127] Multiple components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.
[0128] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as data processing methods. For example, in some embodiments, the data processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the data processing method in any other appropriate manner (e.g., by means of firmware).
[0129] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0130] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions / operations specified in the flow chart and / or block diagram. The program code can be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.
[0131] In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0132] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).
[0133] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.
[0134] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.
[0135] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in this application can be achieved, and this document is not limited here.
[0136] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0137] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A data processing method, comprising: Obtain control parameter information during data retransmission; Performing parameter parsing on the control parameter information to obtain a redundant version number and data block parameters; In response to the redundant version number satisfying the first condition, adjusting the coding verification parameter corresponding to the data block based on the data block parameter, and performing coding verification processing on the data block according to the adjusted coding verification parameter; In response to the redundant version number satisfying a second condition, obtaining the adjusted encoding verification parameter; The corresponding data block is read based on the adjusted coding verification parameter; the retransmitted data is merged based on the read data block; the redundant version number that meets the first condition is smaller than the redundant version number that meets the second condition.
2. The method according to claim 1, wherein adjusting the encoding verification parameters corresponding to the data block based on the data block parameters comprises: The data block parameters include at least: a circular buffer size, an original bit length, and a code block quantity; Determining, based on the data block parameters, a check matrix length corresponding to the coding check processing; The coding check parameter is adjusted based on the check matrix length to obtain the adjusted coding check parameter.
3. The method according to claim 2, wherein determining the length of the check matrix corresponding to the coding check processing based on the data block parameters comprises: Determining a first bit position in the circular buffer based on the circular buffer size and the set expansion factor; Determining a coded bit length corresponding to the original bit length; the coded bit length is less than the original bit length; Performing a modulus calculation based on the first bit position, the coded bit length, and the circular buffer size to obtain a modulus value of the coded bit length within the range of the circular buffer size; The check matrix length is determined based on the modulus value and the first bit position.
4. The method according to claim 2, wherein the adjusting the coding check parameter based on the check matrix length to obtain the adjusted coding check parameter comprises: Determining the basic matrix length of the coding verification processing; Based on the basic matrix length, the set extension factor and the check matrix length, adjusting the decoding length included in the coding check parameter to obtain an adjusted decoding length; The adjusted decoding length is smaller than the decoding length before adjustment.
5. The method according to claim 3, wherein determining the first bit position in the circular buffer based on the circular buffer size and the set expansion factor comprises: Based on the data block parameters, determining a basic graph matrix corresponding to the encoding verification process; A first bit position in the circular buffer is determined based on the base graph matrix, the circular buffer size, and a set expansion factor.
6. The method according to claim 1, before performing coding verification processing on the data block according to the adjusted coding verification parameters, the method further comprises: Performing rate dematching on the data block to obtain rate dematching output bits; Combining retransmitted data on the derate matching output bits to obtain a combined data block; The merged data block and the adjusted encoding verification parameter are sent to a memory.
7. The method according to claim 6, wherein the step of reading the corresponding data block based on the adjusted encoding verification parameter comprises: Determine the read data length based on the decoded length included in the adjusted encoding verification parameter; Based on the read data length, reading the merged data block in the memory once; The merged data block matches the read data length.
8. A data processing device, comprising: An acquisition module, used to obtain control parameter information during data retransmission; A parsing module, used for parsing the control parameter information to obtain a redundant version number and a data block parameter; A decoding module, configured to adjust a coding verification parameter corresponding to the data block based on the data block parameter in response to the redundant version number satisfying a first condition, and perform coding verification processing on the data block according to the adjusted coding verification parameter; A merging module, configured to obtain the adjusted encoding verification parameter in response to the redundant version number satisfying a second condition; Reading a corresponding data block based on the adjusted encoding verification parameter; Retransmitted data is merged based on the read data blocks; the redundant version number that meets the first condition is smaller than the redundant version number that meets the second condition.
9. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method according to any one of claims 1 to 7.